arm: mvebu: increase delay after setting ddr3 training patterns

The mv78260 needs atleast 10ms after setting the ddr3 training patterns or else the cpu will hang.

This patch increases said delay to 20ms just to be safe.

---
 drivers/ddr/mvebu/ddr3_hw_training.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index a8c5e6a..c9c9272 100644
@@ -674,7 +674,7 @@ int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume)
 
 	reg_write(REG_DRAM_TRAINING_ADDR, reg);
 
-	udelay(100);
+	mdelay(20);
 
 	/* Check if Successful */
 	if (reg_read(REG_DRAM_TRAINING_ADDR) &

2.3.6

Hi Anton,

s/atleast/at least

Is this documented somewhere? Or just a value from your experiments / tests?

In general I'm fine with this patch. But I noticed that this patch breaks booting on my AXP board. I then remembered another issue I has with timer functions in SPL on MVEBU (A38x). The timer functionality is not enabled at all at this early boot time. I'll send another patch shortly. Please give it a try and let me know if this works. And if you still need this delay increasing patch here.

Thank,
Stefan

Hi Stefan,

Your timer patch fixes the booting problems for me so this delay isn't necessary anymore.

Thanks,
Anton

Hi Anton, hi Stefan,

I've pushed the two patches from you guys to marvell/master:

http://git.denx.de/?p=u-boot/u-boot-marvell.git;a=summary

I'll leave them there for some time before sending pull request.

Luka

Hi Luka,

My Patch isn't necessary anymore and as Stefan said potentially breaking on other chip versions.

Anton

Hi Anton,

I think everything is merged correctly as was intended. Please check.

Luka

Hi Luka

2015-07-15 17:04 GMT+02:00 Luka Perkov <[email protected]>:

Is correct.

Thanks, Anton

Hi Luka,

Thanks.

Could you please add the A38x SPL patch series (with the SERDES/PHY and DDR setup) as well now that the merge window has opened? Just let me know if it does not apply clean any more. I'll respin the patchset then.

Thanks,
Stefan

Hi Stefan,

Can you please respin the patchset? Thanks!

Luka