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lpc32xx: devkit3250 board update

PATCH Superseded Vladimir Zapolskiy 4 participants 21 messages Jul 17, 2015 – Aug 13, 2015

Subsystems (4)
Arm (32-bit) Memory technology devices (MTD) NAND flash Arm/LPC32XX SoC support
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Vladimir Zapolskiy

author maintainer
#0 lore raw

v2 cover lpc32xx: devkit3250 board update

This changeset improves support of Timll DevKit3250 board:
* added LPC32xx MAC and SMSC RMII phy support, this dependends on
- http://patchwork.ozlabs.org/patch/489100/
- http://patchwork.ozlabs.org/patch/489190/
- http://patchwork.ozlabs.org/patch/491419/
- http://patchwork.ozlabs.org/patch/491420/
* added GPIO, SPI, I2C support, works good, many thanks to Albert,
* added LPC32xx SLC NAND driver, testing of 50 MiB data raw reading shows 1 MiB/s speed, the same change has been sent to the mailing list separately, here it is duplicated as a build dependency:
- http://patchwork.ozlabs.org/patch/495247/
- http://patchwork.ozlabs.org/patch/495250/
* added an option to pass DTB to an operating system,
* changed serial console to commonly used as default UART5,
* boot delay is set to 1 for convenience,
* extended predefined environment variables and reserved space on NAND,
* added an option to build SPL image for the board, by default SPL downloads U-boot image from NAND (offset 0x40000, size 0x60000).

Changes from v1 to v2:
* addressed Albert's and Scott's comments to LPC32xx SLC NAND driver, see patch v2 2/4,
* added Tegra and TI maintainers to Cc list to review/ack a change 1/4 in simple NAND SPL framework, which potentially (very unlikely) may cause a regression in NAND SPL on Tegra, TI OMAP or TI DaVinci platforms.

Previous version of the change and discussion can be found here:
http://lists.denx.de/pipermail/u-boot/2015-July/219253.html

Albert, from commit logs I noticed that WORK92105 has SLC NAND chip, but it is managed by MLC controller, if you have any plans to test LPC32xx SLC NAND driver from the series, please *be aware* of different OOB layouts, I found it is quite easy to screw up the chip, if SLC and MLC are interchanged, so that only "nand scrub" helps. FWIW this SLC NAND driver uses a default OOB layout, the same one is found in Linux LPC32xx SLC NAND driver.

Vladimir Zapolskiy (4):
spl: nand: simple: replace readb() with chip specific read_buf()
nand: lpc32xx: add SLC NAND controller support
lpc32xx: devkit3250: update of board configuration
lpc32xx: devkit3250: add spl build support

 arch/arm/Kconfig                              |   1 +
 arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |   6 +
 arch/arm/include/asm/arch-lpc32xx/clk.h       |   2 +
 arch/arm/include/asm/arch-lpc32xx/sys_proto.h |   1 +
 board/timll/devkit3250/Makefile               |   1 +
 board/timll/devkit3250/devkit3250.c           |  31 ++++-
 board/timll/devkit3250/devkit3250_spl.c       |  68 ++++++++++
 configs/devkit3250_defconfig                  |   4 +
 drivers/mtd/nand/Makefile                     |   1 +
 drivers/mtd/nand/lpc32xx_nand_slc.c           | 176 ++++++++++++++++++++++++++
 drivers/mtd/nand/nand_spl_simple.c            |   7 +-
 include/configs/devkit3250.h                  | 145 ++++++++++++++++++++-
 12 files changed, 435 insertions(+), 8 deletions(-)
 create mode 100644 board/timll/devkit3250/devkit3250_spl.c
 create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c
Signature · 1 line
2.1.4
author maintainer
#1 lore raw

PATCH v2 1/4 spl: nand: simple: replace readb() with chip specific read_buf()

Some NAND controllers define custom functions to read data out, respect this in order to correctly support bad block handling in simple SPL NAND framework.

NAND controller specific read_buf() is used even to read 1 byte in case of connected 8-bit NAND device, it turns out that read_byte() may become outdated.

Signed-off-by Vladimir Zapolskiy <[email protected]>
Cc Tom Rini <[email protected]>
Cc Tom Warren <[email protected]>

---
Changes from v1 to v2:
* no changes, added Tom and Tom to Cc list for review and/or regression testing on Tegra, TI OMAP and TI DaVinci platforms

Previous discussion can be found here:
http://lists.denx.de/pipermail/u-boot/2015-July/219250.html

 drivers/mtd/nand/nand_spl_simple.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)
drivers/mtd/nand/nand_spl_simple.c +5 -2
index 700ca32..e69f662 100644
@@ -115,6 +115,7 @@ static int nand_command(int block, int page, uint32_t offs,
 static int nand_is_bad_block(int block)
 {
 	struct nand_chip *this = mtd.priv;
+	u_char bb_data[2];
 
 	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
 		NAND_CMD_READOOB);

@@ -123,10 +124,12 @@ static int nand_is_bad_block(int block)
 	 * Read one byte (or two if it's a 16 bit chip).
 	 */
 	if (this->options & NAND_BUSWIDTH_16) {
-		if (readw(this->IO_ADDR_R) != 0xffff)
+		this->read_buf(&mtd, bb_data, 2);
+		if (bb_data[0] != 0xff || bb_data[1] != 0xff)
 			return 1;
 	} else {
-		if (readb(this->IO_ADDR_R) != 0xff)
+		this->read_buf(&mtd, bb_data, 1);
+		if (bb_data[0] != 0xff)
 			return 1;
 	}
Signature · 1 line
2.1.4
#2 lore raw

PATCH v2 1/4 spl: nand: simple: replace readb() with chip specific read_buf()

Quoted 16 lines · Vladimir Zapolskiy

Some NAND controllers define custom functions to read data out, respect this in order to correctly support bad block handling in simple SPL NAND framework.

NAND controller specific read_buf() is used even to read 1 byte in case of connected 8-bit NAND device, it turns out that read_byte() may become outdated.

Signed-off-by Vladimir Zapolskiy <[email protected]>
Cc Tom Rini <[email protected]>
Cc Tom Warren <[email protected]>

---
Changes from v1 to v2:
* no changes, added Tom and Tom to Cc list for review and/or regression testing on Tegra, TI OMAP and TI DaVinci platforms

Quoted 5 lines

Previous discussion can be found here:
http://lists.denx.de/pipermail/u-boot/2015-July/219250.html

 drivers/mtd/nand/nand_spl_simple.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)
Acked-by Scott Wood <[email protected]>

-Scott

#3 lore raw

PATCH v2 1/4 spl: nand: simple: replace readb() with chip specific read_buf()

In reply to Vladimir Zapolskiy
Quoted 4 lines · Vladimir Zapolskiy

Some NAND controllers define custom functions to read data out, respect this in order to correctly support bad block handling in simple SPL NAND framework.

Quoted 8 lines

NAND controller specific read_buf() is used even to read 1 byte in case of connected 8-bit NAND device, it turns out that read_byte() may become outdated.

Signed-off-by Vladimir Zapolskiy <[email protected]>
Cc Tom Rini <[email protected]>
Cc Tom Warren <[email protected]>
Acked-by Scott Wood <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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author maintainer
#4 lore raw

PATCH v2 2/4 nand: lpc32xx: add SLC NAND controller support

In reply to Vladimir Zapolskiy

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine.

The driver can be included to an SPL image.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v1 to v2:
* addressed Albert's and Scott's comments to LPC32xx SLC NAND driver:
- removed unnecessary uint32_t casts in write_buf()/write_byte(),
- removed IO_ADDR_[RW] assignment, this is done in nand.c for SPL and generally not needed for custom defined PIO interfaces in U-boot (with exception of simple NAND SPL, addressed by 1/4),
- removed leftover declarations of HW ECC related bit fields, this should be added along with HW ECC support,
- improved description of a reason why software ECC is selected, if DMA is unavailable (explicit reference to User Manual from NXP).

Previous review can be found here:
http://lists.denx.de/pipermail/u-boot/2015-July/219095.html
http://lists.denx.de/pipermail/u-boot/2015-July/219254.html

 arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |   6 +
 arch/arm/include/asm/arch-lpc32xx/clk.h       |   2 +
 arch/arm/include/asm/arch-lpc32xx/sys_proto.h |   1 +
 drivers/mtd/nand/Makefile                     |   1 +
 drivers/mtd/nand/lpc32xx_nand_slc.c           | 176 ++++++++++++++++++++++++++
 5 files changed, 186 insertions(+)
 create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c
arch/arm/cpu/arm926ejs/lpc32xx/devices.c +6 -0
index 5a453e3..b0287be 100644
@@ -54,6 +54,12 @@ void lpc32xx_mlc_nand_init(void)
 	writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
 }
 
+void lpc32xx_slc_nand_init(void)
+{
+	/* Enable SLC NAND interface */
+	writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
+}
+
 void lpc32xx_i2c_init(unsigned int devnum)
 {
 	/* Enable I2C interface */
arch/arm/include/asm/arch-lpc32xx/clk.h +2 -0
index 9449869..010211a 100644
@@ -153,7 +153,9 @@ struct clk_pm_regs {
 #define CLK_DMA_ENABLE			(1 << 0)
 
 /* NAND Clock Control Register bits */
+#define CLK_NAND_SLC			(1 << 0)
 #define CLK_NAND_MLC			(1 << 1)
+#define CLK_NAND_SLC_SELECT		(1 << 2)
 #define CLK_NAND_MLC_INT		(1 << 5)
 
 /* SSP Clock Control Register bits */
arch/arm/include/asm/arch-lpc32xx/sys_proto.h +1 -0
index c3d890d..0845f83 100644
@@ -12,6 +12,7 @@
 void lpc32xx_uart_init(unsigned int uart_id);
 void lpc32xx_mac_init(void);
 void lpc32xx_mlc_nand_init(void);
+void lpc32xx_slc_nand_init(void);
 void lpc32xx_i2c_init(unsigned int devnum);
 void lpc32xx_ssp_init(void);
 #if defined(CONFIG_SPL_BUILD)
drivers/mtd/nand/Makefile +1 -0
index 347ea62..e2dc99a 100644
@@ -53,6 +53,7 @@ obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
 obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
 obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
+obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o
 obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
 obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand.o
drivers/mtd/nand/lpc32xx_nand_slc.c new file +176 -0

176 lines not on this page · raw message

Signature · 1 line
2.1.4
#5 lore raw

PATCH v2 2/4 nand: lpc32xx: add SLC NAND controller support

Quoted 11 lines · Vladimir Zapolskiy
drivers/mtd/nand/lpc32xx_nand_slc.c new file +11 -0
+/* TAC register bits, be aware of overflows */
+#define TAC_W_RDY(n)         (max_t(uint32_t, (n), 0xF) << 28)
+#define TAC_W_WIDTH(n)               (max_t(uint32_t, (n), 0xF) << 24)
+#define TAC_W_HOLD(n)                (max_t(uint32_t, (n), 0xF) << 20)
+#define TAC_W_SETUP(n)               (max_t(uint32_t, (n), 0xF) << 16)
+#define TAC_R_RDY(n)         (max_t(uint32_t, (n), 0xF) << 12)
+#define TAC_R_WIDTH(n)               (max_t(uint32_t, (n), 0xF) << 8)
+#define TAC_R_HOLD(n)                (max_t(uint32_t, (n), 0xF) << 4)
+#define TAC_R_SETUP(n)               (max_t(uint32_t, (n), 0xF) << 0)
+
+static struct lpc32xx_nand_slc_registers __iomem
Quoted 2 lines

*lpc32xx_nand_slc_registers
+ = (struct lpc32xx_nand_slc_registers __iomem *)SLC_NAND_BASE;

s/registers/regs/ might help the formatting here...

Quoted 8 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +8 -0
+static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd,
+                               int cmd, unsigned int ctrl)
+{
+     debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd);
+
+     if (ctrl & NAND_NCE)
+             setbits_le32(&lpc32xx_nand_slc_registers->cfg, CFG_CE_LOW);
+     else

drivers/mtd/nand/lpc32xx_nand_slc.c line 104

Quoted 10 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +10 -0
+             clrbits_le32(&lpc32xx_nand_slc_registers->cfg, CFG_CE_LOW);
+
+     if (cmd == NAND_CMD_NONE)
+             return;
+
+     if (ctrl & NAND_CLE)
+             writel(cmd & 0xFF, &lpc32xx_nand_slc_registers->cmd);
+     else /* if (ctrl & NAND_ALE) */
+             writel(cmd & 0xFF, &lpc32xx_nand_slc_registers->addr);
+}

Why is "if (ctrl & NAND_ALE())" commented out? I think it'd be better if wrong uses of this function didn't silently cause address cycles (which could hide a bug if ALE is what was desired).

drivers/mtd/nand/lpc32xx_nand_slc.c line 120

Quoted 10 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +10 -0
+static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+     while (len-- > 0)
+             *buf++ = (uint8_t)readl(&lpc32xx_nand_slc_registers->data);
+}
+
+static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
+{
+     return (uint8_t)readl(&lpc32xx_nand_slc_registers->data);
+}

You've still got a couple unneeded casts here.

Quoted 24 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +24 -0
+/*
+ * LPC32xx has only one SLC NAND controller, don't utilize
+ * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
+ * both in SPL NAND and U-boot images.
+ */
+int board_nand_init(struct nand_chip *lpc32xx_chip)
+{
+     lpc32xx_chip->cmd_ctrl  = lpc32xx_nand_cmd_ctrl;
+     lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
+
+     /*
+      * Hardware ECC calculation is not supported by the driver,
+      * because it requires DMA support, see LPC32x0 User Manual,
+      * note after SLC_ECC register description (UM10326, p.198)
+      */
+     lpc32xx_chip->ecc.mode  = NAND_ECC_SOFT;
+
+     /*
+      * The implementation of these functions is quite common, but
+      * they MUST be defined, because access to data register
+      * is strictly 32-bit aligned.
+      */
+     lpc32xx_chip->read_buf  = lpc32xx_read_buf;
+     lpc32xx_chip->read_byte = lpc32xx_read_byte;

drivers/mtd/nand/lpc32xx_nand_slc.c line 166

Quoted 10 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +10 -0
+     lpc32xx_chip->write_buf = lpc32xx_write_buf;
+     lpc32xx_chip->write_byte        = lpc32xx_write_byte;
+
+     /*
+      * Use default ECC layout, but these values are predefined
+      * for both small and large page NAND flash devices.
+      */
+     lpc32xx_chip->ecc.size  = 256;
+     lpc32xx_chip->ecc.bytes = 3;
+     lpc32xx_chip->ecc.strength      = 1;

Please use a space before '=', not a tab. This doesn't even line up right, if that's what you were trying to do...

drivers/mtd/nand/lpc32xx_nand_slc.c line 170

Quoted 4 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +4 -0
+
+#if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
+     lpc32xx_chip->bbt_options       |= NAND_BBT_USE_FLASH;
+#endif

Likewise

-Scott

author maintainer
#6 lore raw

PATCH v2 2/4 nand: lpc32xx: add SLC NAND controller support

Hello Scott,

Quoted 16 lines · Scott Wood
Quoted 11 lines · Vladimir Zapolskiy
drivers/mtd/nand/lpc32xx_nand_slc.c new file +11 -0
+/* TAC register bits, be aware of overflows */
+#define TAC_W_RDY(n)         (max_t(uint32_t, (n), 0xF) << 28)
+#define TAC_W_WIDTH(n)               (max_t(uint32_t, (n), 0xF) << 24)
+#define TAC_W_HOLD(n)                (max_t(uint32_t, (n), 0xF) << 20)
+#define TAC_W_SETUP(n)               (max_t(uint32_t, (n), 0xF) << 16)
+#define TAC_R_RDY(n)         (max_t(uint32_t, (n), 0xF) << 12)
+#define TAC_R_WIDTH(n)               (max_t(uint32_t, (n), 0xF) << 8)
+#define TAC_R_HOLD(n)                (max_t(uint32_t, (n), 0xF) << 4)
+#define TAC_R_SETUP(n)               (max_t(uint32_t, (n), 0xF) << 0)
+
+static struct lpc32xx_nand_slc_registers __iomem
Quoted 2 lines

*lpc32xx_nand_slc_registers
+ = (struct lpc32xx_nand_slc_registers __iomem *)SLC_NAND_BASE;

s/registers/regs/ might help the formatting here...

it didn't noticeably help, but I changed the name.

Quoted 14 lines
Quoted 14 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +14 -0
+static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd,
+                               int cmd, unsigned int ctrl)
+{
+     debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd);
+
+     if (ctrl & NAND_NCE)
+             setbits_le32(&lpc32xx_nand_slc_registers->cfg, CFG_CE_LOW);
+     else
+             clrbits_le32(&lpc32xx_nand_slc_registers->cfg, CFG_CE_LOW);
+
+     if (cmd == NAND_CMD_NONE)
+             return;
+
+     if (ctrl & NAND_CLE)
Quoted 8 lines

drivers/mtd/nand/lpc32xx_nand_slc.c line 104

Quoted 4 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +4 -0
+             writel(cmd & 0xFF, &lpc32xx_nand_slc_registers->cmd);
+     else /* if (ctrl & NAND_ALE) */
+             writel(cmd & 0xFF, &lpc32xx_nand_slc_registers->addr);
+}

Why is "if (ctrl & NAND_ALE())" commented out? I think it'd be better if wrong uses of this function didn't silently cause address cycles (which could hide a bug if ALE is what was desired).

well, wrong users are expected to be fixed out of this scope, but okay, for sake of clarity and sanity testing and at the acceptable cost of one more instruction let me uncomment the second condition.

Quoted 4 lines
Quoted 4 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +4 -0
+static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+     while (len-- > 0)
+             *buf++ = (uint8_t)readl(&lpc32xx_nand_slc_registers->data);
Quoted 8 lines

drivers/mtd/nand/lpc32xx_nand_slc.c line 120

Quoted 6 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +6 -0
+}
+
+static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
+{
+     return (uint8_t)readl(&lpc32xx_nand_slc_registers->data);
+}

You've still got a couple unneeded casts here.

My fault, fixed now.

Quoted 29 lines
Quoted 29 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +29 -0
+/*
+ * LPC32xx has only one SLC NAND controller, don't utilize
+ * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
+ * both in SPL NAND and U-boot images.
+ */
+int board_nand_init(struct nand_chip *lpc32xx_chip)
+{
+     lpc32xx_chip->cmd_ctrl  = lpc32xx_nand_cmd_ctrl;
+     lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
+
+     /*
+      * Hardware ECC calculation is not supported by the driver,
+      * because it requires DMA support, see LPC32x0 User Manual,
+      * note after SLC_ECC register description (UM10326, p.198)
+      */
+     lpc32xx_chip->ecc.mode  = NAND_ECC_SOFT;
+
+     /*
+      * The implementation of these functions is quite common, but
+      * they MUST be defined, because access to data register
+      * is strictly 32-bit aligned.
+      */
+     lpc32xx_chip->read_buf  = lpc32xx_read_buf;
+     lpc32xx_chip->read_byte = lpc32xx_read_byte;
+     lpc32xx_chip->write_buf = lpc32xx_write_buf;
+     lpc32xx_chip->write_byte        = lpc32xx_write_byte;
+
+     /*
+      * Use default ECC layout, but these values are predefined
Quoted 8 lines

drivers/mtd/nand/lpc32xx_nand_slc.c line 166

Quoted 5 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +5 -0
+      * for both small and large page NAND flash devices.
+      */
+     lpc32xx_chip->ecc.size  = 256;
+     lpc32xx_chip->ecc.bytes = 3;
+     lpc32xx_chip->ecc.strength      = 1;

Please use a space before '=', not a tab. This doesn't even line up right, if that's what you were trying to do...

Right, that's my intention. I have no objection to non-leading spaces.

Quoted 7 lines

drivers/mtd/nand/lpc32xx_nand_slc.c line 170

Quoted 4 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +4 -0
+
+#if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
+     lpc32xx_chip->bbt_options       |= NAND_BBT_USE_FLASH;
+#endif

Likewise

Done.

I'd like to send the updated version v3 as a reply to this email, hopefully this is fine for you, otherwise please let me know.

Thank you for momentary review.

--
With best wishes,
Vladimir

#7 lore raw

PATCH v2 2/4 nand: lpc32xx: add SLC NAND controller support

Quoted 43 lines · Vladimir Zapolskiy

Hello Scott,

Quoted 31 lines · Scott Wood
Quoted 30 lines · Vladimir Zapolskiy
drivers/mtd/nand/lpc32xx_nand_slc.c new file +30 -0
+/*
+ * LPC32xx has only one SLC NAND controller, don't utilize
+ * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
+ * both in SPL NAND and U-boot images.
+ */
+int board_nand_init(struct nand_chip *lpc32xx_chip)
+{
+     lpc32xx_chip->cmd_ctrl  = lpc32xx_nand_cmd_ctrl;
+     lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
+
+     /*
+      * Hardware ECC calculation is not supported by the driver,
+      * because it requires DMA support, see LPC32x0 User Manual,
+      * note after SLC_ECC register description (UM10326, p.198)
+      */
+     lpc32xx_chip->ecc.mode  = NAND_ECC_SOFT;
+
+     /*
+      * The implementation of these functions is quite common, but
+      * they MUST be defined, because access to data register
+      * is strictly 32-bit aligned.
+      */
+     lpc32xx_chip->read_buf  = lpc32xx_read_buf;
+     lpc32xx_chip->read_byte = lpc32xx_read_byte;
+     lpc32xx_chip->write_buf = lpc32xx_write_buf;
+     lpc32xx_chip->write_byte        = lpc32xx_write_byte;
+
+     /*
+      * Use default ECC layout, but these values are predefined
+      * for both small and large page NAND flash devices.
Quoted 8 lines

drivers/mtd/nand/lpc32xx_nand_slc.c line 166

Quoted 4 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +4 -0
+      */
+     lpc32xx_chip->ecc.size  = 256;
+     lpc32xx_chip->ecc.bytes = 3;
+     lpc32xx_chip->ecc.strength      = 1;

Please use a space before '=', not a tab. This doesn't even line up right,
if that's what you were trying to do...

Quoted 1 line

Right, that's my intention. I have no objection to non-leading spaces.

It looks the same in v3.

-Scott

#8 lore raw

PATCH v2 2/4 nand: lpc32xx: add SLC NAND controller support

Quoted 44 lines · Scott Wood
Quoted 43 lines · Vladimir Zapolskiy

Hello Scott,

Quoted 39 lines · Scott Wood
Quoted 24 lines · Vladimir Zapolskiy
drivers/mtd/nand/lpc32xx_nand_slc.c new file +24 -0
+/*
+ * LPC32xx has only one SLC NAND controller, don't utilize
+ * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
+ * both in SPL NAND and U-boot images.
+ */
+int board_nand_init(struct nand_chip *lpc32xx_chip)
+{
+     lpc32xx_chip->cmd_ctrl  = lpc32xx_nand_cmd_ctrl;
+     lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
+
+     /*
+      * Hardware ECC calculation is not supported by the driver,
+      * because it requires DMA support, see LPC32x0 User Manual,
+      * note after SLC_ECC register description (UM10326, p.198)
+      */
+     lpc32xx_chip->ecc.mode  = NAND_ECC_SOFT;
+
+     /*
+      * The implementation of these functions is quite common, but
+      * they MUST be defined, because access to data register
+      * is strictly 32-bit aligned.
+      */
+     lpc32xx_chip->read_buf  = lpc32xx_read_buf;
+     lpc32xx_chip->read_byte = lpc32xx_read_byte;

drivers/mtd/nand/lpc32xx_nand_slc.c line 166

Quoted 10 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +10 -0
+     lpc32xx_chip->write_buf = lpc32xx_write_buf;
+     lpc32xx_chip->write_byte        = lpc32xx_write_byte;
+
+     /*
+      * Use default ECC layout, but these values are predefined
+      * for both small and large page NAND flash devices.
+      */
+     lpc32xx_chip->ecc.size  = 256;
+     lpc32xx_chip->ecc.bytes = 3;
+     lpc32xx_chip->ecc.strength      = 1;

Please use a space before '=', not a tab. This doesn't even line up right,
if that's what you were trying to do...

Quoted 3 lines
Quoted 1 line

Right, that's my intention. I have no objection to non-leading spaces.

It looks the same in v3.

Actually, v3 looks just like v2 except for the revision log...

-Scott

author maintainer
#9 lore raw

PATCH v2 2/4 nand: lpc32xx: add SLC NAND controller support

In reply to Scott Wood
Quoted 44 lines · Scott Wood
Quoted 43 lines · Vladimir Zapolskiy

Hello Scott,

Quoted 39 lines · Scott Wood
Quoted 24 lines · Vladimir Zapolskiy
drivers/mtd/nand/lpc32xx_nand_slc.c new file +24 -0
+/*
+ * LPC32xx has only one SLC NAND controller, don't utilize
+ * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
+ * both in SPL NAND and U-boot images.
+ */
+int board_nand_init(struct nand_chip *lpc32xx_chip)
+{
+     lpc32xx_chip->cmd_ctrl  = lpc32xx_nand_cmd_ctrl;
+     lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
+
+     /*
+      * Hardware ECC calculation is not supported by the driver,
+      * because it requires DMA support, see LPC32x0 User Manual,
+      * note after SLC_ECC register description (UM10326, p.198)
+      */
+     lpc32xx_chip->ecc.mode  = NAND_ECC_SOFT;
+
+     /*
+      * The implementation of these functions is quite common, but
+      * they MUST be defined, because access to data register
+      * is strictly 32-bit aligned.
+      */
+     lpc32xx_chip->read_buf  = lpc32xx_read_buf;
+     lpc32xx_chip->read_byte = lpc32xx_read_byte;

drivers/mtd/nand/lpc32xx_nand_slc.c line 166

Quoted 10 lines
drivers/mtd/nand/lpc32xx_nand_slc.c new file +10 -0
+     lpc32xx_chip->write_buf = lpc32xx_write_buf;
+     lpc32xx_chip->write_byte        = lpc32xx_write_byte;
+
+     /*
+      * Use default ECC layout, but these values are predefined
+      * for both small and large page NAND flash devices.
+      */
+     lpc32xx_chip->ecc.size  = 256;
+     lpc32xx_chip->ecc.bytes = 3;
+     lpc32xx_chip->ecc.strength      = 1;

Please use a space before '=', not a tab. This doesn't even line up right,
if that's what you were trying to do...

Quoted 4 lines
Quoted 1 line

Right, that's my intention. I have no objection to non-leading spaces.

It looks the same in v3.

I'm so sorry for confusion. Seems that "git format-patch" produces an old change, if it is called in the middle of "git rebase"...

--
With best wishes,
Vladimir

author maintainer
#10 lore raw

PATCH v3 2/4 nand: lpc32xx: add SLC NAND controller support

In reply to Scott Wood

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine.

The driver can be included to an SPL image.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v2 to v3:
* renamed "lpc32xx_nand_slc_registers" to "lpc32xx_nand_slc_regs",
* replaced non-leading tabs with spaces to get columned assignments,
* removed leftover redundant type casts,
* lpc32xx_nand_cmd_ctrl() sets address register iff (ctrl & NAND_ALE).

Changes from v1 to v2:
* addressed Albert's and Scott's comments to LPC32xx SLC NAND driver:
- removed unnecessary uint32_t casts in write_buf()/write_byte(),
- removed IO_ADDR_[RW] assignment, this is done in nand.c for SPL and generally not needed for custom defined PIO interfaces in U-boot (with exception of simple NAND SPL, addressed by 1/4),
- removed leftover declarations of HW ECC related bit fields, this should be added along with HW ECC support,
- improved description of a reason why software ECC is selected, if DMA is unavailable (explicit reference to User Manual from NXP).

Previous review can be found here:

v1:

    http://lists.denx.de/pipermail/u-boot/2015-July/219095.html
    http://lists.denx.de/pipermail/u-boot/2015-July/219254.html

v2:

    http://lists.denx.de/pipermail/u-boot/2015-July/219422.html
 arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |   6 +
 arch/arm/include/asm/arch-lpc32xx/clk.h       |   2 +
 arch/arm/include/asm/arch-lpc32xx/sys_proto.h |   1 +
 drivers/mtd/nand/Makefile                     |   1 +
 drivers/mtd/nand/lpc32xx_nand_slc.c           | 176 ++++++++++++++++++++++++++
 5 files changed, 186 insertions(+)
 create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c
arch/arm/cpu/arm926ejs/lpc32xx/devices.c +6 -0
index 5a453e3..b0287be 100644
@@ -54,6 +54,12 @@ void lpc32xx_mlc_nand_init(void)
 	writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
 }
 
+void lpc32xx_slc_nand_init(void)
+{
+	/* Enable SLC NAND interface */
+	writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
+}
+
 void lpc32xx_i2c_init(unsigned int devnum)
 {
 	/* Enable I2C interface */
arch/arm/include/asm/arch-lpc32xx/clk.h +2 -0
index 9449869..010211a 100644
@@ -153,7 +153,9 @@ struct clk_pm_regs {
 #define CLK_DMA_ENABLE			(1 << 0)
 
 /* NAND Clock Control Register bits */
+#define CLK_NAND_SLC			(1 << 0)
 #define CLK_NAND_MLC			(1 << 1)
+#define CLK_NAND_SLC_SELECT		(1 << 2)
 #define CLK_NAND_MLC_INT		(1 << 5)
 
 /* SSP Clock Control Register bits */
arch/arm/include/asm/arch-lpc32xx/sys_proto.h +1 -0
index c3d890d..0845f83 100644
@@ -12,6 +12,7 @@
 void lpc32xx_uart_init(unsigned int uart_id);
 void lpc32xx_mac_init(void);
 void lpc32xx_mlc_nand_init(void);
+void lpc32xx_slc_nand_init(void);
 void lpc32xx_i2c_init(unsigned int devnum);
 void lpc32xx_ssp_init(void);
 #if defined(CONFIG_SPL_BUILD)
drivers/mtd/nand/Makefile +1 -0
index 347ea62..e2dc99a 100644
@@ -53,6 +53,7 @@ obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
 obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
 obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
+obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o
 obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
 obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand.o
drivers/mtd/nand/lpc32xx_nand_slc.c new file +176 -0

176 lines not on this page · raw message

Signature · 1 line
2.1.4
author maintainer
#11 lore raw

PATCH v4 2/4 nand: lpc32xx: add SLC NAND controller support

In reply to Vladimir Zapolskiy

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine.

The driver can be included to an SPL image.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v3 to v4:
* renamed "lpc32xx_nand_slc_registers" to "lpc32xx_nand_slc_regs",
* replaced non-leading tabs with spaces to get columned assignments,
* removed leftover redundant type casts,
* lpc32xx_nand_cmd_ctrl() sets address register iff (ctrl & NAND_ALE).

Changes from v2 to v3:
* no changes, sent a non-rebased version by mistake.

Changes from v1 to v2:
* addressed Albert's and Scott's comments to LPC32xx SLC NAND driver:
- removed unnecessary uint32_t casts in write_buf()/write_byte(),
- removed IO_ADDR_[RW] assignment, this is done in nand.c for SPL and generally not needed for custom defined PIO interfaces in U-boot (with exception of simple NAND SPL, addressed by 1/4),
- removed leftover declarations of HW ECC related bit fields, this should be added along with HW ECC support,
- improved description of a reason why software ECC is selected, if DMA is unavailable (explicit reference to User Manual from NXP).

Previous review can be found here:
v3:

    http://lists.denx.de/pipermail/u-boot/2015-July/219431.html

v2:

    http://lists.denx.de/pipermail/u-boot/2015-July/219422.html

v1:

    http://lists.denx.de/pipermail/u-boot/2015-July/219095.html
    http://lists.denx.de/pipermail/u-boot/2015-July/219254.html
 arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |   6 +
 arch/arm/include/asm/arch-lpc32xx/clk.h       |   2 +
 arch/arm/include/asm/arch-lpc32xx/sys_proto.h |   1 +
 drivers/mtd/nand/Makefile                     |   1 +
 drivers/mtd/nand/lpc32xx_nand_slc.c           | 176 ++++++++++++++++++++++++++
 5 files changed, 186 insertions(+)
 create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c
arch/arm/cpu/arm926ejs/lpc32xx/devices.c +6 -0
index 5a453e3..b0287be 100644
@@ -54,6 +54,12 @@ void lpc32xx_mlc_nand_init(void)
 	writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
 }
 
+void lpc32xx_slc_nand_init(void)
+{
+	/* Enable SLC NAND interface */
+	writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
+}
+
 void lpc32xx_i2c_init(unsigned int devnum)
 {
 	/* Enable I2C interface */
arch/arm/include/asm/arch-lpc32xx/clk.h +2 -0
index 9449869..010211a 100644
@@ -153,7 +153,9 @@ struct clk_pm_regs {
 #define CLK_DMA_ENABLE			(1 << 0)
 
 /* NAND Clock Control Register bits */
+#define CLK_NAND_SLC			(1 << 0)
 #define CLK_NAND_MLC			(1 << 1)
+#define CLK_NAND_SLC_SELECT		(1 << 2)
 #define CLK_NAND_MLC_INT		(1 << 5)
 
 /* SSP Clock Control Register bits */
arch/arm/include/asm/arch-lpc32xx/sys_proto.h +1 -0
index c3d890d..0845f83 100644
@@ -12,6 +12,7 @@
 void lpc32xx_uart_init(unsigned int uart_id);
 void lpc32xx_mac_init(void);
 void lpc32xx_mlc_nand_init(void);
+void lpc32xx_slc_nand_init(void);
 void lpc32xx_i2c_init(unsigned int devnum);
 void lpc32xx_ssp_init(void);
 #if defined(CONFIG_SPL_BUILD)
drivers/mtd/nand/Makefile +1 -0
index 347ea62..e2dc99a 100644
@@ -53,6 +53,7 @@ obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
 obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
 obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
+obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o
 obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
 obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand.o
drivers/mtd/nand/lpc32xx_nand_slc.c new file +176 -0

176 lines not on this page · raw message

Signature · 1 line
2.1.4
author maintainer
#12 lore raw

PATCH v4 2/4 nand: lpc32xx: add SLC NAND controller support

Hello Scott,

Quoted 48 lines · Vladimir Zapolskiy

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine.

The driver can be included to an SPL image.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v3 to v4:
* renamed "lpc32xx_nand_slc_registers" to "lpc32xx_nand_slc_regs",
* replaced non-leading tabs with spaces to get columned assignments,
* removed leftover redundant type casts,
* lpc32xx_nand_cmd_ctrl() sets address register iff (ctrl & NAND_ALE).

Changes from v2 to v3:
* no changes, sent a non-rebased version by mistake.

Changes from v1 to v2:
* addressed Albert's and Scott's comments to LPC32xx SLC NAND driver:
- removed unnecessary uint32_t casts in write_buf()/write_byte(),
- removed IO_ADDR_[RW] assignment, this is done in nand.c for SPL and generally not needed for custom defined PIO interfaces in U-boot (with exception of simple NAND SPL, addressed by 1/4),
- removed leftover declarations of HW ECC related bit fields, this should be added along with HW ECC support,
- improved description of a reason why software ECC is selected, if DMA is unavailable (explicit reference to User Manual from NXP).

Previous review can be found here:
v3:

    http://lists.denx.de/pipermail/u-boot/2015-July/219431.html

v2:

    http://lists.denx.de/pipermail/u-boot/2015-July/219422.html

v1:

    http://lists.denx.de/pipermail/u-boot/2015-July/219095.html
    http://lists.denx.de/pipermail/u-boot/2015-July/219254.html
Quoted 8 lines
 arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |   6 +
 arch/arm/include/asm/arch-lpc32xx/clk.h       |   2 +
 arch/arm/include/asm/arch-lpc32xx/sys_proto.h |   1 +
 drivers/mtd/nand/Makefile                     |   1 +
 drivers/mtd/nand/lpc32xx_nand_slc.c           | 176 ++++++++++++++++++++++++++
 5 files changed, 186 insertions(+)
 create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c

please let me know, if this change is ready for inclusion to the next U-boot release. The following changes from the series to a board file (NAND and SPL build) depend on this one, if this SLC NAND change is accepted I hope Albert may find time to include board specific changes as well.

Thank you in advance.

--
With best wishes,
Vladimir

#13 lore raw

PATCH v4 2/4 nand: lpc32xx: add SLC NAND controller support

In reply to Vladimir Zapolskiy
Quoted 48 lines · Vladimir Zapolskiy

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine.

The driver can be included to an SPL image.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v3 to v4:
* renamed "lpc32xx_nand_slc_registers" to "lpc32xx_nand_slc_regs",
* replaced non-leading tabs with spaces to get columned assignments,
* removed leftover redundant type casts,
* lpc32xx_nand_cmd_ctrl() sets address register iff (ctrl & NAND_ALE).

Changes from v2 to v3:
* no changes, sent a non-rebased version by mistake.

Changes from v1 to v2:
* addressed Albert's and Scott's comments to LPC32xx SLC NAND driver:
- removed unnecessary uint32_t casts in write_buf()/write_byte(),
- removed IO_ADDR_[RW] assignment, this is done in nand.c for SPL and generally not needed for custom defined PIO interfaces in U-boot (with exception of simple NAND SPL, addressed by 1/4),
- removed leftover declarations of HW ECC related bit fields, this should be added along with HW ECC support,
- improved description of a reason why software ECC is selected, if DMA is unavailable (explicit reference to User Manual from NXP).

Previous review can be found here:
v3:

    http://lists.denx.de/pipermail/u-boot/2015-July/219431.html

v2:

    http://lists.denx.de/pipermail/u-boot/2015-July/219422.html

v1:

    http://lists.denx.de/pipermail/u-boot/2015-July/219095.html
    http://lists.denx.de/pipermail/u-boot/2015-July/219254.html
Quoted 8 lines
 arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |   6 +
 arch/arm/include/asm/arch-lpc32xx/clk.h       |   2 +
 arch/arm/include/asm/arch-lpc32xx/sys_proto.h |   1 +
 drivers/mtd/nand/Makefile                     |   1 +
 drivers/mtd/nand/lpc32xx_nand_slc.c           | 176 
++++++++++++++++++++++++++
 5 files changed, 186 insertions(+)
 create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c
Acked-by Scott Wood <[email protected]>

-Scott

#14 lore raw

PATCH v4 2/4 nand: lpc32xx: add SLC NAND controller support

Quoted 61 lines

From: Scott Wood [mailto:scottwood at freescale.com]
Sent: 27-Jul-15 9:24 PM

Quoted 48 lines · Vladimir Zapolskiy

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine.

The driver can be included to an SPL image.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v3 to v4:
* renamed "lpc32xx_nand_slc_registers" to "lpc32xx_nand_slc_regs",
* replaced non-leading tabs with spaces to get columned assignments,
* removed leftover redundant type casts,
* lpc32xx_nand_cmd_ctrl() sets address register iff (ctrl & NAND_ALE).

Changes from v2 to v3:
* no changes, sent a non-rebased version by mistake.

Changes from v1 to v2:
* addressed Albert's and Scott's comments to LPC32xx SLC NAND driver:
- removed unnecessary uint32_t casts in write_buf()/write_byte(),
- removed IO_ADDR_[RW] assignment, this is done in nand.c for SPL and generally not needed for custom defined PIO interfaces in U-boot (with exception of simple NAND SPL, addressed by 1/4),
- removed leftover declarations of HW ECC related bit fields, this should be added along with HW ECC support,
- improved description of a reason why software ECC is selected, if DMA is unavailable (explicit reference to User Manual from NXP).

Previous review can be found here:
v3:

    http://lists.denx.de/pipermail/u-boot/2015-July/219431.html

v2:

    http://lists.denx.de/pipermail/u-boot/2015-July/219422.html

v1:

    http://lists.denx.de/pipermail/u-boot/2015-July/219095.html
    http://lists.denx.de/pipermail/u-boot/2015-July/219254.html
Quoted 8 lines
 arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |   6 +
 arch/arm/include/asm/arch-lpc32xx/clk.h       |   2 +
 arch/arm/include/asm/arch-lpc32xx/sys_proto.h |   1 +
 drivers/mtd/nand/Makefile                     |   1 +
 drivers/mtd/nand/lpc32xx_nand_slc.c           | 176
++++++++++++++++++++++++++
 5 files changed, 186 insertions(+)
 create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c
Quoted 3 lines
Acked-by Scott Wood <[email protected]>

-Scott

Tested for large page NAND.

Tested-by Sylvain Lemieux <[email protected]>

________________________________

This e-mail contains privileged and confidential information intended for the use of the addressees named above. If you are not the intended recipient of this e-mail, you are hereby notified that you must not disseminate, copy or take any action in respect of any information contained in it. If you have received this e-mail in error, please notify the sender immediately by e-mail and immediately destroy this e-mail and its attachments.

#15 lore raw

PATCH v4 2/4 nand: lpc32xx: add SLC NAND controller support

In reply to Vladimir Zapolskiy
Quoted 13 lines · Vladimir Zapolskiy

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine.

Quoted 5 lines

The driver can be included to an SPL image.

Signed-off-by Vladimir Zapolskiy <[email protected]>
Acked-by Scott Wood <[email protected]>
Tested-by Sylvain Lemieux <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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author maintainer
#16 lore raw

PATCH v2 3/4 lpc32xx: devkit3250: update of board configuration

In reply to Vladimir Zapolskiy

This change adds more peripherals to Timll DevKit3250 board, namely MAC and SMSC phy, SLC NAND, GPIO, SPI and I2C.

Also the default serial console is changed to UART5, added an option to pass device tree blob by means of bootm, predefined environment variables are slightly extended and reserved space on NAND to store user defined U-boot environment.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v1 to v2:
* no changes

Previous review and discussion can be found here:
http://lists.denx.de/pipermail/u-boot/2015-July/219252.html

 board/timll/devkit3250/devkit3250.c | 31 ++++++++++++-
 configs/devkit3250_defconfig        |  3 ++
 include/configs/devkit3250.h        | 92 +++++++++++++++++++++++++++++++++++--
 3 files changed, 120 insertions(+), 6 deletions(-)
board/timll/devkit3250/devkit3250.c +30 -1
index 6acc416..4b3c94e 100644
@@ -1,23 +1,52 @@
 /*
  * Embest/Timll DevKit3250 board support
  *
- * Copyright (C) 2011 Vladimir Zapolskiy <[email protected]>
+ * Copyright (C) 2011-2015 Vladimir Zapolskiy <[email protected]>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/emc.h>
+#include <asm/arch/wdt.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
+
+void reset_periph(void)
+{
+	/* This function resets peripherals by triggering RESOUT_N */
+	setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
+	writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
+	udelay(300);
+
+	writel(0, &wdt->mctrl);
+	clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
+
+	/* Such a long delay is needed to initialize SMSC phy */
+	udelay(10000);
+}
 
 int board_early_init_f(void)
 {
 	lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+	lpc32xx_i2c_init(1);
+	lpc32xx_i2c_init(2);
+	lpc32xx_ssp_init();
+	lpc32xx_mac_init();
+
+	/*
+	 * nWP may be controlled by GPO19, but unpopulated by default R23
+	 * makes no sense to configure this GPIO level, nWP is always high
+	 */
+	lpc32xx_slc_nand_init();
 
 	return 0;
 }
configs/devkit3250_defconfig +3 -0
index f0c4ee1..56d719f 100644
@@ -1,3 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_DEVKIT3250=y
+# CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
include/configs/devkit3250.h +87 -5

128 lines not on this page · raw message

Signature · 1 line
2.1.4
#17 lore raw

PATCH v2 3/4 lpc32xx: devkit3250: update of board configuration

Quoted 10 lines · Vladimir Zapolskiy

This change adds more peripherals to Timll DevKit3250 board, namely

MAC and SMSC phy, SLC NAND, GPIO, SPI and I2C.

Also the default serial console is changed to UART5, added an option to pass device tree blob by means of bootm, predefined environment variables are slightly extended and reserved space on NAND to store user defined U-boot environment.

Signed-off-by Vladimir Zapolskiy <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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author maintainer
#18 lore raw

PATCH v2 4/4 lpc32xx: devkit3250: add spl build support

In reply to Vladimir Zapolskiy

The change adds SPL build support to Timll DevKit3250 board, the generated SPL image can be uploaded over UART5, JTAG or stored on NAND. SPL is designed to load U-boot image from NAND.

All new NAND chip defines in board configuration are needed by SPL NAND "simple" framework, the framework is used to reduce potentially duplicated code from LPC32xx SLC NAND driver.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v1 to v2:
* no changes

The same version of the change can be found here
http://lists.denx.de/pipermail/u-boot/2015-July/219251.html

 arch/arm/Kconfig                        |  1 +
 board/timll/devkit3250/Makefile         |  1 +
 board/timll/devkit3250/devkit3250_spl.c | 68 +++++++++++++++++++++++++++++++++
 configs/devkit3250_defconfig            |  1 +
 include/configs/devkit3250.h            | 53 +++++++++++++++++++++++++
 5 files changed, 124 insertions(+)
 create mode 100644 board/timll/devkit3250/devkit3250_spl.c
arch/arm/Kconfig +1 -0
index 506463c..95b15bc 100644
@@ -121,6 +121,7 @@ config TARGET_MAXBCM
 config TARGET_DEVKIT3250
 	bool "Support devkit3250"
 	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_WORK_92105
 	bool "Support work_92105"
board/timll/devkit3250/Makefile +1 -0
index 4722986..74d5cd3 100644
@@ -6,3 +6,4 @@
 #
 
 obj-y	:= devkit3250.o
+obj-$(CONFIG_SPL_BUILD) += devkit3250_spl.o
board/timll/devkit3250/devkit3250_spl.c new file +68 -0

68 lines not on this page · raw message

configs/devkit3250_defconfig +1 -0
index 56d719f..7246da5 100644
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_DEVKIT3250=y
+CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_DM=y
include/configs/devkit3250.h +53 -0

66 lines not on this page · raw message

Signature · 1 line
2.1.4
#19 lore raw

PATCH v2 4/4 lpc32xx: devkit3250: add spl build support

Quoted 9 lines · Vladimir Zapolskiy

The change adds SPL build support to Timll DevKit3250 board, the generated SPL image can be uploaded over UART5, JTAG or stored on NAND. SPL is designed to load U-boot image from NAND.

All new NAND chip defines in board configuration are needed by SPL NAND "simple" framework, the framework is used to reduce potentially duplicated code from LPC32xx SLC NAND driver.

Signed-off-by Vladimir Zapolskiy <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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author maintainer
#20 lore raw

v2 cover lpc32xx: devkit3250 board update

In reply to Vladimir Zapolskiy

Hello Albert,

Quoted 38 lines · Vladimir Zapolskiy

This changeset improves support of Timll DevKit3250 board:
* added LPC32xx MAC and SMSC RMII phy support, this dependends on
- http://patchwork.ozlabs.org/patch/489100/
- http://patchwork.ozlabs.org/patch/489190/
- http://patchwork.ozlabs.org/patch/491419/
- http://patchwork.ozlabs.org/patch/491420/
* added GPIO, SPI, I2C support, works good, many thanks to Albert,
* added LPC32xx SLC NAND driver, testing of 50 MiB data raw reading shows 1 MiB/s speed, the same change has been sent to the mailing list separately, here it is duplicated as a build dependency:
- http://patchwork.ozlabs.org/patch/495247/
- http://patchwork.ozlabs.org/patch/495250/
* added an option to pass DTB to an operating system,
* changed serial console to commonly used as default UART5,
* boot delay is set to 1 for convenience,
* extended predefined environment variables and reserved space on NAND,
* added an option to build SPL image for the board, by default SPL downloads U-boot image from NAND (offset 0x40000, size 0x60000).

Changes from v1 to v2:
* addressed Albert's and Scott's comments to LPC32xx SLC NAND driver, see patch v2 2/4,
* added Tegra and TI maintainers to Cc list to review/ack a change 1/4 in simple NAND SPL framework, which potentially (very unlikely) may cause a regression in NAND SPL on Tegra, TI OMAP or TI DaVinci platforms.

Previous version of the change and discussion can be found here:
http://lists.denx.de/pipermail/u-boot/2015-July/219253.html

Albert, from commit logs I noticed that WORK92105 has SLC NAND chip, but it is managed by MLC controller, if you have any plans to test LPC32xx SLC NAND driver from the series, please *be aware* of different OOB layouts, I found it is quite easy to screw up the chip, if SLC and MLC are interchanged, so that only "nand scrub" helps. FWIW this SLC NAND driver uses a default OOB layout, the same one is found in Linux LPC32xx SLC NAND driver.

Quoted 5 lines

Vladimir Zapolskiy (4):
spl: nand: simple: replace readb() with chip specific read_buf()
nand: lpc32xx: add SLC NAND controller support
lpc32xx: devkit3250: update of board configuration
lpc32xx: devkit3250: add spl build support

do you see any left issues in this series or in MAC series mentioned on top? If no, please could you apply these 8 patches?

Thank you in advance.

--
With best wishes,
Vladimir