imx: imximage: add new CHECK/CLR BIT command

* Add pmic pfuze300 support for imx7 and iMX6 DL/SL/SX SoC's
* Implement power_pfuze300_init to be used in power_init_board callback function.

Signed-off-by Adrian Alonso <[email protected]>

Signed-off-by Peng Fan <[email protected]>

---
 drivers/power/pmic/Makefile        |  1 +
 drivers/power/pmic/pmic_pfuze300.c | 32 ++++++++++++++++
 include/power/pfuze300_pmic.h      | 78 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 111 insertions(+)
 create mode 100644 drivers/power/pmic/pmic_pfuze300.c
 create mode 100644 include/power/pfuze300_pmic.h

drivers/power/pmic/Makefile +1 -0

index ae86f04..43040ff 100644
@@ -14,6 +14,7 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
 obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
 obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
 obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
+obj-$(CONFIG_POWER_PFUZE300) += pmic_pfuze300.o
 obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o
 obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o
 obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o

drivers/power/pmic/pmic_pfuze300.c new file +32 -0

new file mode 100644
index 0000000..4304ddd
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Peng Fan <[email protected]>
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze300_pmic.h>
+
+int power_pfuze300_init(unsigned char bus)
+{
+	static const char name[] = "PFUZE300";
+	struct pmic *p = pmic_alloc();
+
+	if (!p) {
+		printf("%s: POWER allocation error!\n", __func__);
+		return -ENOMEM;
+	}
+
+	p->name = name;
+	p->interface = PMIC_I2C;
+	p->number_of_regs = PMIC_NUM_OF_REGS;
+	p->hw.i2c.addr = CONFIG_POWER_PFUZE300_I2C_ADDR;
+	p->hw.i2c.tx_num = 1;
+	p->bus = bus;
+
+	return 0;
+}

include/power/pfuze300_pmic.h new file +68 -0

new file mode 100644
index 0000000..c7ec5ce
@@ -0,0 +1,78 @@
+/*
+ *  Copyright (C) 2015 Freescale Semiconductor, Inc
+ *  Peng Fan <[email protected]>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef __PFUZE300_PMIC_H_
+#define __PFUZE300_PMIC_H_
+
+/* PFUZE300 registers */
+enum {
+	PFUZE300_DEVICEID	= 0x00,
+
+	PFUZE300_REVID		= 0x03,
+	PFUZE300_FABID		= 0x04,
+	PFUZE300_INTSTAT0	= 0x05,
+	PFUZE300_INTMASK0	= 0x06,
+	PFUZE300_INTSENSE0	= 0x07,
+	PFUZE300_INTSTAT1	= 0x08,
+	PFUZE300_INTMASK1	= 0x09,
+	PFUZE300_INTSENSE1	= 0x0A,
+
+	PFUZE300_INTSTAT3	= 0x0E,
+	PFUZE300_INTMASK3	= 0x0F,
+	PFUZE300_INTSENSE3	= 0x10,
+	PFUZE300_INTSTAT4	= 0x11,
+	PFUZE300_INTMASK4	= 0x12,
+	PFUZE300_INTSENSE4	= 0x13,
+
+	PFUZE300_COINCTL	= 0x1A,
+	PFUZE300_PWRCTL		= 0x1B,
+	PFUZE300_MEMA		= 0x1C,
+	PFUZE300_MEMB		= 0x1D,
+	PFUZE300_MEMC		= 0x1E,
+	PFUZE300_MEMD		= 0x1F,
+
+	PFUZE300_SW1AVOLT	= 0x20,
+	PFUZE300_SW1ASTBY	= 0x21,
+	PFUZE300_SW1AOFF	= 0x22,
+	PFUZE300_SW1AMODE	= 0x23,
+	PFUZE300_SW1ACONF	= 0x24,
+
+	PFUZE300_SW1BVOLT	= 0x2E,
+	PFUZE300_SW1BSTBY	= 0x2F,
+	PFUZE300_SW1BOFF	= 0x30,
+	PFUZE300_SW1BMODE	= 0x31,
+	PFUZE300_SW1BCONF	= 0x32,
+
+	PFUZE300_SW2VOLT	= 0x35,
+	PFUZE300_SW2STBY	= 0x36,
+	PFUZE300_SW2OFF		= 0x37,
+	PFUZE300_SW2MODE	= 0x38,
+	PFUZE300_SW2CONF	= 0x39,
+
+	PFUZE300_SW3VOLT	= 0x3C,
+	PFUZE300_SW3STBY	= 0x3D,
+	PFUZE300_SW3OFF		= 0x3E,
+	PFUZE300_SW3MODE	= 0x3F,
+	PFUZE300_SW3CONF	= 0x40,
+
+	PFUZE300_SWBSTCTL	= 0x66,
+
+	PFUZE300_LDOGCTL	= 0x69,
+	PFUZE300_VREFDDRCTL	= 0x6A,
+	PFUZE300_VSNVSCTL	= 0x6B,
+	PFUZE300_VLDO1CTL	= 0x6C,
+	PFUZE300_VLDO2CTL	= 0x6D,
+	PFUZE300_VCC_SDCTL	= 0x6E,

* Add pmic pfuze300 support for imx7 and iMX6 DL/SL/SX SoC's

* Add support for usb driver for i.MX7D SoC

Signed-off-by Adrian Alonso <[email protected]>

Signed-off-by Ye.Li <[email protected]>

Signed-off-by Peng Fan <[email protected]>

-----Original Message-----
From: Fabio Estevam [mailto:festevam at gmail.com]
Sent: Thursday, July 16, 2015 9:15 AM
To: Alonso Lazcano Adrian-B38018
Cc: U-Boot-Denx; Stefano Babic; Estevam Fabio-R49496; Otavio Salvador
Subject: Re: [U-Boot] [PATCH 08/11] imx: mx7 dm thermal driver support

Hi Adrian,

Quoted 8 lines · Adrian Alonso

include/configs/mx6cuboxi.h +0 -0

index 3d5bba7..d42b7f0 100644
@@ -14,7 +14,7 @@
 #define CONFIG_SPL_MMC_SUPPORT
 #include "imx6_spl.h"
 

include/configs/mx6cuboxi.h line 17

Quoted 2 lines

include/configs/mx6cuboxi.h +1 -1

-#define CONFIG_IMX6_THERMAL
+#define CONFIG_IMX_THERMAL

This would cause a conflict with Peter Robinson's series that centralizas CONFIG_IMX6_THERMAL

[Adrian] So far Peter Robinson patch's have been Acked but not yet committed into u-boot master.
I will wait into patch's are committed to rework and send and new patch series for imx7 support addressing All the comment and suggestion.

* The system counter driver for imx7d abd mx6ul, move this timer driver to imx-common and rename it as syscounter.c

For mx6ul and mx7, configurations are used for choose the GPT timer or system counter timer (default).

GPT timer: CONFIG_GPT_TIMER
System counter timer: CONFIG_SYSCOUNTER_TIMER

For mx6dqp GPT timer is the default setting.

Signed-off-by Adrian Alonso <[email protected]>

Signed-off-by Ye.Li <[email protected]>

---
  arch/arm/imx-common/syscounter.c             | 126 +++++++++++++++++++++++++++
  arch/arm/include/asm/imx-common/syscounter.h |  29 ++++++
  include/configs/mx6_common.h                 |   1 +
  3 files changed, 156 insertions(+)

create mode 100644 arch/arm/imx-common/syscounter.c create mode 100644 arch/arm/include/asm/imx-common/syscounter.h

arch/arm/imx-common/syscounter.c new file +47 -0

new file mode 100644
index 0000000..f5e5cdc
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * The file use ls102xa/timer.c as a reference.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/syscounter.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long usec)
+{
+	ulong ticks;
+
+	if (usec < 1000)
+		ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+	else
+		ticks = ((usec / 10) * (get_tbclk() / 100000));
+
+	return ticks;
+}
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	unsigned long freq;
+
+	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, freq);
+
+	return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)

arch/arm/imx-common/syscounter.c new file +69 -0

+
+int timer_init(void)
+{
+	struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
+	unsigned long val, freq;
+
+	freq = CONFIG_SC_TIMER_CLK;
+	asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+	writel(freq, &sctr->cntfid0);
+
+	/* Enable system counter */
+	val = readl(&sctr->cntcr);
+	val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
+	val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
+	writel(val, &sctr->cntcr);
+
+	gd->arch.tbl = 0;
+	gd->arch.tbu = 0;
+
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	unsigned long long now;
+
+	asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
+
+	gd->arch.tbl = (unsigned long)(now & 0xffffffff);
+	gd->arch.tbu = (unsigned long)(now >> 32);
+
+	return now;
+}
+
+ulong get_timer_masked(void)
+{
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	unsigned long freq;
+
+	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+	return freq;
+}

arch/arm/include/asm/imx-common/syscounter.h new file +29 -0

new file mode 100644
index 0000000..ddb412e
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SYSTEM_COUNTER_H
+#define _ASM_ARCH_SYSTEM_COUNTER_H
+
+/* System Counter */
+struct sctr_regs {
+	u32 cntcr;
+	u32 cntsr;
+	u32 cntcv1;
+	u32 cntcv2;
+	u32 resv1[4];
+	u32 cntfid0;
+	u32 cntfid1;
+	u32 cntfid2;
+	u32 resv2[1001];
+	u32 counterid[1];
+};
+
+#define SC_CNTCR_ENABLE		(1 << 0)
+#define SC_CNTCR_HDBG		(1 << 1)
+#define SC_CNTCR_FREQ0		(1 << 8)
+#define SC_CNTCR_FREQ1		(1 << 9)
+
+#endif

include/configs/mx6_common.h +0 -0

index 86d7b16..690038d 100644

-----Original Message-----
From: Nikolay Dimitrov [mailto:picmaster at mail.bg]
Sent: Monday, July 20, 2015 3:43 PM
To: Alonso Lazcano Adrian-B38018
Cc: u-boot at lists.denx.de; sbabic at denx.de; Estevam Fabio-R49496; otavio at ossystems.com.br
Subject: Re: [U-Boot] [PATCH 09/11] imx: system counter driver for imx7d and mx6ul

Hi Adrian,

Quoted 9 lines · Adrian Alonso

* The system counter driver for imx7d abd mx6ul, move this timer driver to imx-common and rename it as syscounter.c

For mx6ul and mx7, configurations are used for choose the GPT timer or system counter timer (default).

GPT timer: CONFIG_GPT_TIMER
System counter timer: CONFIG_SYSCOUNTER_TIMER

Quoted 6 lines

For mx6dqp GPT timer is the default setting.

Signed-off-by Adrian Alonso <[email protected]>

Signed-off-by Ye.Li <[email protected]>

---
  arch/arm/imx-common/syscounter.c             | 126

+++++++++++++++++++++++++++

Quoted 65 lines

  arch/arm/include/asm/imx-common/syscounter.h |  29 ++++++
  include/configs/mx6_common.h                 |   1 +
  3 files changed, 156 insertions(+)

create mode 100644 arch/arm/imx-common/syscounter.c create mode 100644 arch/arm/include/asm/imx-common/syscounter.h

arch/arm/imx-common/syscounter.c new file +52 -0

new file mode 100644
index 0000000..f5e5cdc
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * The file use ls102xa/timer.c as a reference.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/syscounter.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long usec) {
+	ulong ticks;
+
+	if (usec < 1000)
+		ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+	else
+		ticks = ((usec / 10) * (get_tbclk() / 100000));
+
+	return ticks;
+}
+
+static inline unsigned long long tick_to_time(unsigned long long
+tick) {
+	unsigned long freq;
+
+	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, freq);
+
+	return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+	unsigned long freq;
+
+	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+	usec = usec * freq  + 999999;

arch/arm/imx-common/syscounter.c line 57

Quoted 4 lines

arch/arm/imx-common/syscounter.c new file +4 -0

+	do_div(usec, 1000000);
+
+	return usec;
+}

Is it possible to use the same naming convention for usec2ticks(), tick_to_time() and us_to_tick() (e.g. choose either "2" or "_to_")? Thanks.

Quoted 112 lines

arch/arm/imx-common/syscounter.c new file +69 -0

+
+int timer_init(void)
+{
+	struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
+	unsigned long val, freq;
+
+	freq = CONFIG_SC_TIMER_CLK;
+	asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+	writel(freq, &sctr->cntfid0);
+
+	/* Enable system counter */
+	val = readl(&sctr->cntcr);
+	val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
+	val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
+	writel(val, &sctr->cntcr);
+
+	gd->arch.tbl = 0;
+	gd->arch.tbu = 0;
+
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	unsigned long long now;
+
+	asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
+
+	gd->arch.tbl = (unsigned long)(now & 0xffffffff);
+	gd->arch.tbu = (unsigned long)(now >> 32);
+
+	return now;
+}
+
+ulong get_timer_masked(void)
+{
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	unsigned long freq;
+
+	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+	return freq;
+}

arch/arm/include/asm/imx-common/syscounter.h new file +29 -0

new file mode 100644
index 0000000..ddb412e
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SYSTEM_COUNTER_H
+#define _ASM_ARCH_SYSTEM_COUNTER_H
+
+/* System Counter */
+struct sctr_regs {
+	u32 cntcr;
+	u32 cntsr;
+	u32 cntcv1;
+	u32 cntcv2;
+	u32 resv1[4];
+	u32 cntfid0;
+	u32 cntfid1;
+	u32 cntfid2;
+	u32 resv2[1001];
+	u32 counterid[1];
+};
+
+#define SC_CNTCR_ENABLE		(1 << 0)
+#define SC_CNTCR_HDBG		(1 << 1)
+#define SC_CNTCR_FREQ0		(1 << 8)
+#define SC_CNTCR_FREQ1		(1 << 9)
+
+#endif

(quoted diff) +0 -0

b/include/configs/mx6_common.h index 86d7b16..690038d 100644

include/configs/mx6_common.h line 36

Quoted 7 lines

include/configs/mx6_common.h +1 -0

@@ -30,6 +30,7 @@
 
  #define CONFIG_MP
  #define CONFIG_MXC_GPT_HCLK
+#define CONFIG_GPT_TIMER
 
  #define CONFIG_SYS_NO_FLASH
 

Regards,
Nikolay

Hi Nikolay,

Quoted 93 lines

-----Original Message-----
From: Nikolay Dimitrov [mailto:picmaster at mail.bg]
Sent: Monday, July 20, 2015 3:43 PM
To: Alonso Lazcano Adrian-B38018
Cc: u-boot at lists.denx.de; sbabic at denx.de; Estevam Fabio-R49496; otavio at ossystems.com.br
Subject: Re: [U-Boot] [PATCH 09/11] imx: system counter driver for imx7d and mx6ul

Hi Adrian,

Quoted 9 lines · Adrian Alonso

* The system counter driver for imx7d abd mx6ul, move this timer driver to imx-common and rename it as syscounter.c

For mx6ul and mx7, configurations are used for choose the GPT timer or system counter timer (default).

GPT timer: CONFIG_GPT_TIMER
System counter timer: CONFIG_SYSCOUNTER_TIMER

Quoted 6 lines

For mx6dqp GPT timer is the default setting.

Signed-off-by Adrian Alonso <[email protected]>

Signed-off-by Ye.Li <[email protected]>

---
   arch/arm/imx-common/syscounter.c             | 126

+++++++++++++++++++++++++++

Quoted 65 lines

   arch/arm/include/asm/imx-common/syscounter.h |  29 ++++++
   include/configs/mx6_common.h                 |   1 +
   3 files changed, 156 insertions(+)

create mode 100644 arch/arm/imx-common/syscounter.c create mode 100644 arch/arm/include/asm/imx-common/syscounter.h

arch/arm/imx-common/syscounter.c new file +52 -0

new file mode 100644
index 0000000..f5e5cdc
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * The file use ls102xa/timer.c as a reference.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/syscounter.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long usec) {
+	ulong ticks;
+
+	if (usec < 1000)
+		ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+	else
+		ticks = ((usec / 10) * (get_tbclk() / 100000));
+
+	return ticks;
+}
+
+static inline unsigned long long tick_to_time(unsigned long long
+tick) {
+	unsigned long freq;
+
+	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, freq);
+
+	return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+	unsigned long freq;
+
+	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+	usec = usec * freq  + 999999;

Quoted 8 lines

arch/arm/imx-common/syscounter.c line 57

Quoted 4 lines

arch/arm/imx-common/syscounter.c new file +4 -0

+	do_div(usec, 1000000);
+
+	return usec;
+}

Is it possible to use the same naming convention for usec2ticks(), tick_to_time() and us_to_tick() (e.g. choose either "2" or "_to_")? Thanks.

[Adrian] usec2ticks follows the definition of prototype function in header file "include/common.h"
the comment in the header /* arch/$(ARCH)/lib/time.c */ implies that each platform should provide that function; For iMX SoC's case usec2ticks is only used in drivers/crypto/fsl/jr.c and drivers/i2c/fsl_i2c.c IMHO we should keep the same naming convention defined in the "include/common.h" file.

Quoted 117 lines

Quoted 117 lines

arch/arm/imx-common/syscounter.c new file +69 -0

+
+int timer_init(void)
+{
+	struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
+	unsigned long val, freq;
+
+	freq = CONFIG_SC_TIMER_CLK;
+	asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+	writel(freq, &sctr->cntfid0);
+
+	/* Enable system counter */
+	val = readl(&sctr->cntcr);
+	val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
+	val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
+	writel(val, &sctr->cntcr);
+
+	gd->arch.tbl = 0;
+	gd->arch.tbu = 0;
+
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	unsigned long long now;
+
+	asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
+
+	gd->arch.tbl = (unsigned long)(now & 0xffffffff);
+	gd->arch.tbu = (unsigned long)(now >> 32);
+
+	return now;
+}
+
+ulong get_timer_masked(void)
+{
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	unsigned long freq;
+
+	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+	return freq;
+}

arch/arm/include/asm/imx-common/syscounter.h new file +29 -0

new file mode 100644
index 0000000..ddb412e
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SYSTEM_COUNTER_H
+#define _ASM_ARCH_SYSTEM_COUNTER_H
+
+/* System Counter */
+struct sctr_regs {
+	u32 cntcr;
+	u32 cntsr;
+	u32 cntcv1;
+	u32 cntcv2;
+	u32 resv1[4];
+	u32 cntfid0;
+	u32 cntfid1;
+	u32 cntfid2;
+	u32 resv2[1001];
+	u32 counterid[1];
+};
+
+#define SC_CNTCR_ENABLE		(1 << 0)
+#define SC_CNTCR_HDBG		(1 << 1)
+#define SC_CNTCR_FREQ0		(1 << 8)
+#define SC_CNTCR_FREQ1		(1 << 9)
+
+#endif

(quoted diff) +0 -0

b/include/configs/mx6_common.h index 86d7b16..690038d 100644

include/configs/mx6_common.h +1 -0

@@ -30,6 +30,7 @@
 
   #define CONFIG_MP
   #define CONFIG_MXC_GPT_HCLK
+#define CONFIG_GPT_TIMER
 

Quoted 6 lines

include/configs/mx6_common.h line 36

Quoted 3 lines

include/configs/mx6_common.h +0 -0

   #define CONFIG_SYS_NO_FLASH
 

Regards,
Nikolay

* Introduce a new cpu type MXC_CPU_MX7D and relevant functions for mx7d. Implement the soc.c for various system level functions like:
temperature check, arch init, get mac fuse, boot mode get/apply, etc.
* Additional, enable building imx common platform files for mx7d.

Signed-off-by Adrian Alonso <[email protected]>

Signed-off-by Peng Fan <[email protected]>

Signed-off-by Ye.Li <[email protected]>

---
 arch/arm/Kconfig                            |    7 +
 arch/arm/Makefile                           |    4 +-
 arch/arm/cpu/armv7/Makefile                 |    3 +-
 arch/arm/cpu/armv7/mx7/Makefile             |    9 +
 arch/arm/cpu/armv7/mx7/clock.c              | 1130 +++++++++++
 arch/arm/cpu/armv7/mx7/clock_slice.c        |  757 +++++++
 arch/arm/cpu/armv7/mx7/hab.c                |  277 +++
 arch/arm/cpu/armv7/mx7/soc.c                |  409 ++++
 arch/arm/imx-common/Makefile                |   17 +-
 arch/arm/imx-common/cpu.c                   |   17 +
 arch/arm/imx-common/timer.c                 |    9 +-
 arch/arm/include/asm/arch-imx/cpu.h         |    1 +
 arch/arm/include/asm/arch-mx7/clock.h       |  348 ++++
 arch/arm/include/asm/arch-mx7/clock_slice.h |  116 ++
 arch/arm/include/asm/arch-mx7/crm_regs.h    | 2813 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx7/gpio.h        |   12 +

 arch/arm/include/asm/arch-mx7/hab.h         |   69 +
 arch/arm/include/asm/arch-mx7/imx-regs.h    | 1303 +++++++++++++
 arch/arm/include/asm/arch-mx7/mx7-pins.h    |   19 +
 arch/arm/include/asm/arch-mx7/mx7d_pins.h   | 1308 +++++++++++++
 arch/arm/include/asm/arch-mx7/sys_proto.h   |   45 +
 arch/arm/include/asm/imx-common/boot_mode.h |   21 +
 drivers/watchdog/Makefile                   |    2 +-
 23 files changed, 8688 insertions(+), 8 deletions(-)

 create mode 100644 arch/arm/cpu/armv7/mx7/Makefile
 create mode 100644 arch/arm/cpu/armv7/mx7/clock.c
 create mode 100644 arch/arm/cpu/armv7/mx7/clock_slice.c
 create mode 100644 arch/arm/cpu/armv7/mx7/hab.c
 create mode 100644 arch/arm/cpu/armv7/mx7/soc.c
 create mode 100644 arch/arm/include/asm/arch-mx7/clock.h
 create mode 100644 arch/arm/include/asm/arch-mx7/clock_slice.h
 create mode 100644 arch/arm/include/asm/arch-mx7/crm_regs.h
 create mode 100644 arch/arm/include/asm/arch-mx7/gpio.h
 create mode 100644 arch/arm/include/asm/arch-mx7/hab.h
 create mode 100644 arch/arm/include/asm/arch-mx7/imx-regs.h
 create mode 100644 arch/arm/include/asm/arch-mx7/mx7-pins.h
 create mode 100644 arch/arm/include/asm/arch-mx7/mx7d_pins.h
 create mode 100644 arch/arm/include/asm/arch-mx7/sys_proto.h

arch/arm/Kconfig +0 -0

index 506463c..40aabb6 100644

* Add i.MX7D SABRESD board BSP codes, with enabled modules:

UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX.

Build target: mx7dsabresd_config

Signed-off-by Peng Fan <[email protected]>

Signed-off-by Fugang Duan <[email protected]>

Signed-off-by Ye.Li <[email protected]>

Signed-off-by Adrian Alonso <[email protected]>

---
 board/freescale/mx7dsabresd/Kconfig       |  15 +
 board/freescale/mx7dsabresd/Makefile      |   6 +
 board/freescale/mx7dsabresd/imximage.cfg  | 110 +++++
 board/freescale/mx7dsabresd/mx7dsabresd.c | 656 ++++++++++++++++++++++++++++++
 configs/mx7dsabresd_defconfig             |  10 +
 include/configs/mx7_common.h              |  22 +
 include/configs/mx7dsabresd.h             | 382 +++++++++++++++++
 7 files changed, 1201 insertions(+)
 create mode 100644 board/freescale/mx7dsabresd/Kconfig
 create mode 100644 board/freescale/mx7dsabresd/Makefile
 create mode 100644 board/freescale/mx7dsabresd/imximage.cfg
 create mode 100644 board/freescale/mx7dsabresd/mx7dsabresd.c
 create mode 100644 configs/mx7dsabresd_defconfig
 create mode 100644 include/configs/mx7_common.h
 create mode 100644 include/configs/mx7dsabresd.h

board/freescale/mx7dsabresd/imximage.cfg new file +22 -0

@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */

board/freescale/mx7dsabresd/imximage.cfg new file +15 -0

+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx7dsabresd/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
 
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/io.h>

board/freescale/mx7dsabresd/imximage.cfg new file +8 -0

+{
+       struct bootrom_sw_info **p =
+               (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
+
+       u8 boot_type = (*p)->boot_dev_type;
+       u8 dev_no = (*p)->boot_dev_instance;
+
+       /* If not boot from sd/mmc, use default value */

board/freescale/mx7dsabresd/imximage.cfg new file +49 -0

+{
+       if (1 == dev_no)
+               dev_no++;
+
+       return dev_no;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+       int ret = 0;
+
+       switch (cfg->esdhc_base) {
+       case USDHC1_BASE_ADDR:
+               ret = !gpio_get_value(USDHC1_CD_GPIO);
+               break;
+       case USDHC3_BASE_ADDR:
+               ret = 1; /* Assume uSDHC3 emmc is always present */
+               break;
+       }
+
+       return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+       int i, ret;
+       /*
+        * According to the board_mmc_init() the following map is done:
+        * (U-boot device node)    (Physical Port)
+        * mmc0                    USDHC1
+        * mmc2                    USDHC3 (eMMC)
+        */
+       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+               switch (i) {
+               case 0:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+                       gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
+                       gpio_direction_input(USDHC1_CD_GPIO);
+                       gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
+                       gpio_direction_output(USDHC1_PWR_GPIO, 0);
+                       udelay(500);
+                       gpio_direction_output(USDHC1_PWR_GPIO, 1);
+                       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+                       break;
+               case 1:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));

board/freescale/mx7dsabresd/imximage.cfg new file +65 -0

+                       }
+
+                       ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+                       if (ret)
+                               return ret;
+       }
+
+       return 0;
+}
+
+int check_mmc_autodetect(void)
+{
+       char *autodetect_str = getenv("mmcautodetect");
+
+       if ((autodetect_str != NULL) &&
+               (strcmp(autodetect_str, "yes") == 0)) {
+               return 1;
+       }
+
+       return 0;
+}
+
+void board_late_mmc_init(void)
+{
+       char cmd[32];
+       char mmcblk[32];
+       u32 dev_no = mmc_get_env_devno();
+
+       if (!check_mmc_autodetect())
+               return;
+
+       setenv_ulong("mmcdev", dev_no);
+
+       /* Set mmcblk env */
+       sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
+               mmc_map_to_kernel_blk(dev_no));
+       setenv("mmcroot", mmcblk);
+
+       sprintf(cmd, "mmc dev %d", dev_no);
+       run_command(cmd, 0);
+}
+
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(bd_t *bis)
+{
+       int ret;
+
+       setup_iomux_fec();
+
+       ret = fecmxc_initialize_multi(bis, 0,
+               CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+       if (ret)
+               printf("FEC1 MXC: %s:failed\n", __func__);
+
+       return ret;
+}
+
+static int setup_fec(void)
+{
+       struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+               = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+       int ret;
+

board/freescale/mx7dsabresd/imximage.cfg new file +13 -0

+#ifdef CONFIG_USB_EHCI_MX7
+iomux_v3_cfg_t const usb_otg1_pads[] = {
+       MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usb_otg2_pads[] = {
+       MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+       switch (port) {
+       case 0:

board/freescale/mx7dsabresd/imximage.cfg new file +1 -0

+#endif /*CONFIG_IMX_UDC*/

configs/mx7dsabresd_defconfig new file +10 -0

new file mode 100644
index 0000000..879847c
@@ -0,0 +1,10 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D"
+CONFIG_ARM=y
+CONFIG_TARGET_MX7DSABRESD=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set

include/configs/mx7_common.h new file +22 -0

new file mode 100644
index 0000000..25f79f3
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX7.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+
+#ifndef __MX7_COMMON_H
+#define __MX7_COMMON_H
+
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_MXC_GPT_HCLK
+
+#define CONFIG_SYSCOUNTER_TIMER
+#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
+
+#define CONFIG_IOMUX_LPSR
+#define CONFIG_IMX_FIXED_IVT_OFFSET
+
+#endif

include/configs/mx7dsabresd.h new file +111 -0

new file mode 100644
index 0000000..4119646
@@ -0,0 +1,382 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX7D SABRESD board.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __MX7D_SABRESD_CONFIG_H
+#define __MX7D_SABRESD_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx7_common.h"
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_MX7
+#define CONFIG_ROM_UNIFIED_SECTIONS
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_DBG_MONITOR
+/* uncomment for PLUGIN mode support */
+/* #define CONFIG_USE_PLUGIN */
+
+/* uncomment for SECURE mode support */
+/* #define CONFIG_SECURE_BOOT */
+
+#ifdef CONFIG_SECURE_BOOT
+#ifndef CONFIG_CSF_SIZE
+#define CONFIG_CSF_SIZE 0x4000
+#endif
+#endif
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (32 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE           UART1_IPS_BASE_ADDR
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_BAUDRATE                        115200
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+
+#define PHYS_SDRAM_SIZE                        SZ_1G
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_ETHPRIME                 "FEC"
+#define CONFIG_FEC_MXC_PHYADDR          0
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_BROADCOM
+#define CONFIG_FEC_DMA_MINALIGN                64
+
+/* ENET1 */
+#define IMX_FEC_BASE                   ENET_IPS_BASE_ADDR
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE300
+#define CONFIG_POWER_PFUZE300_I2C_ADDR 0x08
+
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+
+/* I2C configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_SPEED           100000
+
+#undef CONFIG_CMD_IMLS

* Extend imximage DCD version 2 to support DCD commands CMD_WRITE_CLR_BIT 4 [address] [mask bit] means:

    while ((*address & ~mask) != 0);
  CMD_CHECK_BITS_SET 4 [address] [mask bit] means:
    while ((*address & mask) != mask);
  CMD_CHECK_BITS_CLR 4 [address] [mask bit] means:
    *address = *address & ~mask;

* Add set_dcd_param_v2 helper function to set DCD
command parameters

Signed-off-by Adrian Alonso <[email protected]>

Signed-off-by Peng Fan <[email protected]>

---
Changes for V2
- Add set_dcd_param_v2 helper function to set DCD command tag and parameters

 tools/imximage.c | 99 ++++++++++++++++++++++++++++++++++++++++++++------------
 tools/imximage.h | 25 ++++++++++----
 2 files changed, 97 insertions(+), 27 deletions(-)

tools/imximage.c +6 -2

index 6f469ae..cc0392f 100644
@@ -21,7 +21,10 @@
 static table_entry_t imximage_cmds[] = {
 	{CMD_BOOT_FROM,         "BOOT_FROM",            "boot command",	  },
 	{CMD_BOOT_OFFSET,       "BOOT_OFFSET",          "Boot offset",	  },
-	{CMD_DATA,              "DATA",                 "Reg Write Data", },
+	{CMD_WRITE_DATA,        "DATA",                 "Reg Write Data", },
+	{CMD_WRITE_CLR_BIT,     "CLR_BIT",              "Reg clear bit",  },
+	{CMD_CHECK_BITS_SET,    "CHECK_BITS_SET",   "Reg Check bits set", },
+	{CMD_CHECK_BITS_CLR,    "CHECK_BITS_CLR",   "Reg Check bits clr", },
 	{CMD_CSF,               "CSF",           "Command Sequence File", },
 	{CMD_IMAGE_VERSION,     "IMAGE_VERSION",        "image version",  },
 	{-1,                    "",                     "",	          },

@@ -62,7 +65,7 @@ static table_entry_t imximage_boot_loadsize[] = {
  */
 static table_entry_t imximage_versions[] = {
 	{IMXIMAGE_V1,	"",	" (i.MX25/35/51 compatible)", },
-	{IMXIMAGE_V2,	"",	" (i.MX53/6 compatible)",     },
+	{IMXIMAGE_V2,	"",	" (i.MX53/6/7 compatible)",   },
 	{-1,            "",     " (Invalid)",                 },
 };
 

@@ -79,6 +82,7 @@ static uint32_t imximage_csf_size = UNDEFINED;
 static uint32_t imximage_init_loadsize;
 
 static set_dcd_val_t set_dcd_val;
+static set_dcd_param_t set_dcd_param;
 static set_dcd_rst_t set_dcd_rst;
 static set_imx_hdr_t set_imx_hdr;
 static uint32_t max_dcd_entries;

tools/imximage.c +15 -0

+
 static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
 					int fld, uint32_t value, uint32_t off)
 {

@@ -156,6 +166,43 @@ static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
 	}
 }
 
+static void set_dcd_param_v2(struct imx_header *imxhdr, uint32_t dcd_len,
+		int32_t cmd)
+{
+	dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
+
+	switch (cmd) {
+	case CMD_WRITE_DATA:
+		dcd_v2->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
+		dcd_v2->write_dcd_command.length = cpu_to_be16(
+				dcd_len * sizeof(dcd_addr_data_t) + 4);
+		dcd_v2->write_dcd_command.param = DCD_WRITE_DATA_PARAM;
+		break;
+	case CMD_WRITE_CLR_BIT:
+		dcd_v2->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;

tools/imximage.c +21 -16

+		dcd_v2->write_dcd_command.length = cpu_to_be16(0xC);
+		dcd_v2->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
+		break;
+	case CMD_CHECK_BITS_CLR:
+		dcd_v2->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
+		dcd_v2->write_dcd_command.length = cpu_to_be16(0xC);
+		dcd_v2->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
+		break;
+	default:
+		break;
+	}
+}
+
 static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
 					int fld, uint32_t value, uint32_t off)
 {

@@ -200,10 +247,7 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
 	dcd_v2->header.length = cpu_to_be16(
 			dcd_len * sizeof(dcd_addr_data_t) + 8);
 	dcd_v2->header.version = DCD_VERSION;
-	dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG;
-	dcd_v2->write_dcd_command.length = cpu_to_be16(
-			dcd_len * sizeof(dcd_addr_data_t) + 4);
-	dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
+	set_dcd_param_v2(imxhdr, dcd_len, CMD_WRITE_DATA);
 }
 
 static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,

@@ -266,12 +310,14 @@ static void set_hdr_func(void)
 	switch (imximage_version) {
 	case IMXIMAGE_V1:
 		set_dcd_val = set_dcd_val_v1;
+		set_dcd_param = set_dcd_param_v1;
 		set_dcd_rst = set_dcd_rst_v1;
 		set_imx_hdr = set_imx_hdr_v1;
 		max_dcd_entries = MAX_HW_CFG_SIZE_V1;
 		break;
 	case IMXIMAGE_V2:
 		set_dcd_val = set_dcd_val_v2;
+		set_dcd_param = set_dcd_param_v2;
 		set_dcd_rst = set_dcd_rst_v2;
 		set_imx_hdr = set_imx_hdr_v2;
 		max_dcd_entries = MAX_HW_CFG_SIZE_V2;

@@ -396,8 +442,12 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
 		if (unlikely(cmd_ver_first != 1))
 			cmd_ver_first = 0;
 		break;
-	case CMD_DATA:
+	case CMD_WRITE_DATA:
+	case CMD_WRITE_CLR_BIT:
+	case CMD_CHECK_BITS_SET:
+	case CMD_CHECK_BITS_CLR:
 		value = get_cfg_value(token, name, lineno);
+		(*set_dcd_param)(imxhdr, dcd_len, cmd);
 		(*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len);
 		if (unlikely(cmd_ver_first != 1))
 			cmd_ver_first = 0;

@@ -436,20 +486,29 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
 		break;
 	case CFG_REG_ADDRESS:
 	case CFG_REG_VALUE:
-		if (*cmd != CMD_DATA)
-			return;
-
-		value = get_cfg_value(token, name, lineno);
-		(*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
-
-		if (fld == CFG_REG_VALUE) {
-			(*dcd_len)++;
-			if (*dcd_len > max_dcd_entries) {
-				fprintf(stderr, "Error: %s[%d] -"
-					"DCD table exceeds maximum size(%d)\n",

tools/imximage.c +14 -0

+			(*set_dcd_val)(imxhdr, name, lineno, fld, value,
+					*dcd_len);
+
+			if (fld == CFG_REG_VALUE) {
+				(*dcd_len)++;
+				if (*dcd_len > max_dcd_entries) {
+					fprintf(stderr, "Error: %s[%d] -"
+						"DCD table exceeds maximum size(%d)\n",
+						name, lineno, max_dcd_entries);
+					exit(EXIT_FAILURE);
+				}
 			}
+			break;
+		default:
+			break;
 		}
 		break;
 	default:

tools/imximage.h +15 -7

index 36fe095..c199814 100644
@@ -42,19 +42,27 @@
 #define FLASH_LOADSIZE_SATA		FLASH_LOADSIZE_STANDARD
 #define FLASH_LOADSIZE_QSPI		0x0 /* entire image */
 
-#define IVT_HEADER_TAG 0xD1
-#define IVT_VERSION 0x40
-#define DCD_HEADER_TAG 0xD2
-#define DCD_COMMAND_TAG 0xCC
-#define DCD_VERSION 0x40
-#define DCD_COMMAND_PARAM 0x4
+/* Command tags and parameters */
+#define IVT_HEADER_TAG			0xD1
+#define IVT_VERSION			0x40
+#define DCD_HEADER_TAG			0xD2
+#define DCD_VERSION			0x40
+#define DCD_WRITE_DATA_COMMAND_TAG	0xCC
+#define DCD_WRITE_DATA_PARAM		0x4
+#define DCD_WRITE_CLR_BIT_PARAM	0xC
+#define DCD_CHECK_DATA_COMMAND_TAG	0xCF
+#define DCD_CHECK_BITS_SET_PARAM	0x14
+#define DCD_CHECK_BITS_CLR_PARAM	0x04
 
 enum imximage_cmd {
 	CMD_INVALID,
 	CMD_IMAGE_VERSION,
 	CMD_BOOT_FROM,
 	CMD_BOOT_OFFSET,
-	CMD_DATA,
+	CMD_WRITE_DATA,
+	CMD_WRITE_CLR_BIT,
+	CMD_CHECK_BITS_SET,
+	CMD_CHECK_BITS_CLR,
 	CMD_CSF,
 };