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armv8: Fix TCR macros for shareability attribute

PATCH New Alison Wang 2 participants 2 messages Jun 29, 2015 – Jul 20, 2015 Arm (32-bit)

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Alison Wang

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PATCH 1/2 armv8: Fix TCR macros for shareability attribute

From: Zhichun Hua <[email protected]>

For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit position [13:12] of TCR_ELx register.

Signed-off-by Zhichun Hua <[email protected]>
Signed-off-by York Sun <[email protected]>
---
 arch/arm/include/asm/armv8/mmu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/armv8/mmu.h +2 -2
index 4b9cb52..04fa0be 100644
@@ -93,8 +93,8 @@
 #define TCR_ORGN_WBNWA		(3 << 10)
 #define TCR_ORGN_MASK		(3 << 10)
 #define TCR_SHARED_NON		(0 << 12)
-#define TCR_SHARED_OUTER	(1 << 12)
-#define TCR_SHARED_INNER	(2 << 12)
+#define TCR_SHARED_OUTER	(2 << 12)
+#define TCR_SHARED_INNER	(3 << 12)
 #define TCR_TG0_4K		(0 << 14)
 #define TCR_TG0_64K		(1 << 14)
 #define TCR_TG0_16K		(2 << 14)
Signature · 1 line
2.1.0.27.g96db324