u-boot: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit

This patch addresses a problem mentioned recently on this mailing list: [1].

In that posting a LS1021 based system was locking up at about 5 minutes after boot, but the problem was mysteriously related to the toolchain used for building u-boot. Debugging the problem reveals a stuck interrupt 29 on the GIC.

It appears Freescale's LS1021 support in u-boot erroneously sets the 64-bit ARM generic PL1 physical time CompareValue register to all-ones with a 32-bit value. This causes the timer compare to fire 344 seconds after u-boot configures it. Depending on how fast u-boot gets the kernel booted, this amounts to about 5-minutes of Linux uptime before locking up.

Apparently the bug is masked by some toolchains. Perhaps this is explained by default compiler options, word sizes, or binutils versions. At any rate this patch makes the manipulation explicitly 64-bit which alleviates the issue.

[1] https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html

This patch addresses a problem mentioned recently on this mailing list: [1].

In that posting a LS1021 based system was locking up at about 5 minutes after boot, but the problem was mysteriously related to the toolchain used for building u-boot. Debugging the problem reveals a stuck interrupt 29 on the GIC.

It appears Freescale's LS1021 support in u-boot erroneously sets the 64-bit ARM generic PL1 physical time CompareValue register to all-ones with a 32-bit value. This causes the timer compare to fire 344 seconds after u-boot configures it. Depending on how fast u-boot gets the kernel booted, this amounts to about 5-minutes of Linux uptime before locking up.

Apparently the bug is masked by some toolchains. Perhaps this is explained by default compiler options, word sizes, or binutils versions. At any rate this patch makes the manipulation explicitly 64-bit which alleviates the issue.

[1] https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html

Index: u-boot-2015.04/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
===================================================================

arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +1 -1

@@ -28,7 +28,7 @@
  #define RCWSR4_SRDS1_PRTCL_SHIFT	24
  #define RCWSR4_SRDS1_PRTCL_MASK		0xff000000
 
-#define TIMER_COMP_VAL			0xffffffff
+#define TIMER_COMP_VAL			0xffffffffffffffffull
  #define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
  #define SYS_COUNTER_CTRL_ENABLE		(1 << 24)
 

Index: u-boot-2015.04/arch/arm/cpu/armv7/ls102xa/timer.c
===================================================================

arch/arm/cpu/armv7/ls102xa/timer.c +4 -3

@@ -58,7 +58,8 @@ int timer_init(void)
  	struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
 
          if (!readl( &sctr->cntcr )) {
-                unsigned long ctrl, val, freq;
+                unsigned long ctrl, freq;
+		unsigned long long val64;
 
                  /* Enable System Counter */
                  writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);

@@ -71,8 +72,8 @@ int timer_init(void)
                  asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
 
                  /* Set PL1 Physical Comp Value */
-                val = TIMER_COMP_VAL;
-                asm("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val));
+                val64 = TIMER_COMP_VAL;
+                asm("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val64));
 
                  gd->arch.tbl = 0;
                  gd->arch.tbu = 0;