assortment of tegra fixes/enhancements

index 287460c..645d965 100644
@@ -15,9 +15,15 @@
 #define CONFIG_CI_UDC
 #define CONFIG_CI_UDC_HAS_HOSTPC
 #define CONFIG_USB_GADGET_DUALSPEED
+#ifndef CONFIG_G_DNL_VENDOR_NUM
 #define CONFIG_G_DNL_VENDOR_NUM 0x0955
+#endif
+#ifndef CONFIG_G_DNL_PRODUCT_NUM
 #define CONFIG_G_DNL_PRODUCT_NUM 0x701A
+#endif
+#ifndef CONFIG_G_DNL_MANUFACTURER
 #define CONFIG_G_DNL_MANUFACTURER "NVIDIA"
+#endif
 #define CONFIG_USBDOWNLOAD_GADGET
 /* USB mass storage protocol */
 #define CONFIG_USB_GADGET_MASS_STORAGE

index d63af0e..9ff0831 100644
@@ -56,6 +56,8 @@ struct timerus {
 /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
 #define NV_WB_RUN_ADDRESS	0x40020000
 
+#define NVBOOTTYPE_RECOVERY	2	/* BR entered RCM */
+#define NVBOOTINFOTABLE_BOOTTYPE 0xC	/* Boot type in BIT in IRAM */
 #define NVBOOTINFOTABLE_BCTSIZE	0x38	/* BCT size in BIT in IRAM */
 #define NVBOOTINFOTABLE_BCTPTR	0x3C	/* BCT pointer in BIT in IRAM */
 

index 6244214..b7a2219 100644
@@ -9,7 +9,10 @@
 #include <dm.h>
 #include <asm/arch/gp_padctrl.h>
 #include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/tegra.h>
 #include <asm/gpio.h>
+#include <asm/io.h>
 #include <i2c.h>
 #include <netdev.h>
 

@@ -18,6 +21,15 @@
 #define PMU_I2C_ADDRESS		0x2D
 #define MAX_I2C_RETRY		3
 
+int arch_misc_init(void)
+{
+	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
+	    NVBOOTTYPE_RECOVERY)
+		printf("USB recovery mode\n");
+
+	return 0;
+}
+
 /*
  * Routine: pinmux_init
  * Description: Do individual peripheral pinmux configs

index 8ae9ccf..7210a8a 100644
@@ -8,8 +8,20 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/tegra.h>
 #include <asm/gpio.h>
+#include <asm/io.h>
+
+int arch_misc_init(void)
+{
+	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
+	    NVBOOTTYPE_RECOVERY)
+		printf("USB recovery mode\n");
+
+	return 0;
+}
 
 #ifdef CONFIG_TEGRA_MMC
 /*

index f4bc7d8..7ca79eb 100644
@@ -8,10 +8,22 @@
 #include <common.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/gp_padctrl.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/tegra.h>
+#include <asm/io.h>
 #include "pinmux-config-colibri_t30.h"
 #include <i2c.h>
 #include <asm/gpio.h>
 
+int arch_misc_init(void)
+{
+	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
+	    NVBOOTTYPE_RECOVERY)
+		printf("USB recovery mode\n");
+
+	return 0;
+}
+
 /*
  * Routine: pinmux_init
  * Description: Do individual peripheral pinmux configs

index aba9ba6..283b002 100644
@@ -11,6 +11,8 @@
 
 #include "tegra30-common.h"
 
+#define CONFIG_ARCH_MISC_INIT
+
 /* High-level configuration options */
 #define V_PROMPT			"Apalis T30 # "
 #define CONFIG_TEGRA_BOARD_STRING	"Toradex Apalis T30"

index 8228e42..d80d352 100644
@@ -9,6 +9,8 @@
 
 #include "tegra20-common.h"
 
+#define CONFIG_ARCH_MISC_INIT
+
 /* High-level configuration options */
 #define V_PROMPT			"Colibri T20 # "
 #define CONFIG_TEGRA_BOARD_STRING	"Toradex Colibri T20"

index 4655668..249b5c0 100644
@@ -11,6 +11,8 @@
 
 #include "tegra30-common.h"
 
+#define CONFIG_ARCH_MISC_INIT
+
 /* High-level configuration options */
 #define V_PROMPT			"Colibri T30 # "
 #define CONFIG_TEGRA_BOARD_STRING	"Toradex Colibri T30"

index 7210a8a..81d344c 100644
@@ -75,3 +75,21 @@ void pin_mux_usb(void)
 	pinmux_tristate_disable(PMUX_PINGRP_SPIG);
 }
 #endif
+
+#ifdef CONFIG_VIDEO_TEGRA
+/*
+ * Routine: pin_mux_display
+ * Description: setup the pin muxes/tristate values for the LCD interface)
+ */
+void pin_mux_display(void)
+{
+	/*
+	 * Manually untristate BL_ON (PT4 - SODIMM 71) as specified through
+	 * device-tree
+	 */
+	pinmux_tristate_disable(PMUX_PINGRP_DTA);
+
+	pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
+	pinmux_tristate_disable(PMUX_PINGRP_SDC);
+}
+#endif

index d80d352..82a887b 100644
@@ -45,6 +45,16 @@
 /* General networking support */
 #define CONFIG_CMD_DHCP
 
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP				LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES	10
+#define CONFIG_CMD_BMP
+#define CONFIG_LCD_LOGO
+
 /* NAND support */
 #define CONFIG_CMD_NAND
 #define CONFIG_TEGRA_NAND

index 82a887b..24880c3 100644
@@ -23,6 +23,10 @@
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_COLIBRI_T20
 
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_CMD_I2C
+
 /* SD/MMC support */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC

index 81d344c..42b293d 100644
@@ -13,9 +13,44 @@
 #include <asm/arch-tegra/tegra.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
+#include <i2c.h>
+
+#define PMU_I2C_ADDRESS		0x34
+#define MAX_I2C_RETRY		3
+#define PMU_SUPPLYENE		0x14
+#define PMU_SUPPLYENE_SYSINEN	(1<<5)
+#define PMU_SUPPLYENE_EXITSLREQ	(1<<1)
 
 int arch_misc_init(void)
 {
+	/* Disable PMIC sleep mode on low supply voltage */
+	struct udevice *dev;
+	u8 addr, data[1];
+	int err;
+
+	err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
+	if (err) {
+		debug("%s: Cannot find PMIC I2C chip\n", __func__);
+		return err;
+	}
+
+	addr = PMU_SUPPLYENE;
+
+	err = dm_i2c_read(dev, addr, data, 1);
+	if (err) {
+		debug("failed to get PMU_SUPPLYENE\n");
+		return err;
+	}
+
+	data[0] &= ~PMU_SUPPLYENE_SYSINEN;
+	data[0] |= PMU_SUPPLYENE_EXITSLREQ;
+
+	err = dm_i2c_write(dev, addr, data, 1);
+	if (err) {
+		debug("failed to set PMU_SUPPLYENE\n");
+		return err;
+	}
+
 	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
 	    NVBOOTTYPE_RECOVERY)
 		printf("USB recovery mode\n");

index b660f3b..9c90634 100644
@@ -86,16 +86,6 @@ struct fdt_nand {
 
 struct nand_drv {
 	struct nand_ctlr *reg;
-
-	/*
-	* When running in PIO mode to get READ ID bytes from register
-	* RESP_0, we need this variable as an index to know which byte in
-	* register RESP_0 should be read.
-	* Because common code in nand_base.c invokes read_byte function two
-	* times for NAND_CMD_READID.
-	* And our controller returns 4 bytes at once in register RESP_0.
-	*/
-	int pio_byte_index;
 	struct fdt_nand config;
 };
 

@@ -181,25 +171,16 @@ static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
 static uint8_t read_byte(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;
-	u32 dword_read;
 	struct nand_drv *info;
 
 	info = (struct nand_drv *)chip->priv;
 
-	/* In PIO mode, only 4 bytes can be transferred with single CMD_GO. */
-	if (info->pio_byte_index > 3) {
-		info->pio_byte_index = 0;
-		writel(CMD_GO | CMD_PIO
-			| CMD_RX | CMD_CE0,
-			&info->reg->command);
-		if (!nand_waitfor_cmd_completion(info->reg))
-			printf("Command timeout\n");
-	}
+	writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
+	       &info->reg->command);
+	if (!nand_waitfor_cmd_completion(info->reg))
+		printf("Command timeout\n");
 
-	dword_read = readl(&info->reg->resp);
-	dword_read = dword_read >> (8 * info->pio_byte_index);
-	info->pio_byte_index++;
-	return (uint8_t)dword_read;
+	return (uint8_t)readl(&info->reg->resp);
 }
 
 /**

@@ -314,6 +295,9 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
 	if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
 		column >>= 1;
 
+	/* Disable subpage writes as we do not provide ecc->hwctl */
+	chip->options |= NAND_NO_SUBPAGE_WRITE;
+
 	nand_clear_interrupt_status(info->reg);
 
 	/* Stop DMA engine, clear DMA completion status */

@@ -330,12 +314,8 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
 	case NAND_CMD_READID:
 		writel(NAND_CMD_READID, &info->reg->cmd_reg1);
 		writel(column & 0xFF, &info->reg->addr_reg1);
-		writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO
-			| CMD_RX |
-			((4 - 1) << CMD_TRANS_SIZE_SHIFT)
-			| CMD_CE0,
-			&info->reg->command);
+		writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
+		       &info->reg->command);
-		info->pio_byte_index = 0;
 		break;
 	case NAND_CMD_PARAM:
 		writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);

@@ -376,7 +356,6 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
 			| ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
 			| CMD_CE0,
 			&info->reg->command);
-		info->pio_byte_index = 0;
 		break;
 	case NAND_CMD_RESET:
 		writel(NAND_CMD_RESET, &info->reg->cmd_reg1);

index 9f90683..02d8aed 100644
@@ -16,6 +16,7 @@
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <fdtdec.h>
+#include <bouncebuf.h>
 #include "tegra_nand.h"
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -93,35 +94,6 @@ static struct nand_drv nand_ctrl;
 static struct mtd_info *our_mtd;
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
-#ifdef CONFIG_SYS_DCACHE_OFF
-static inline void dma_prepare(void *start, unsigned long length,
-			       int is_writing)
-{
-}
-#else
-/**
- * Prepare for a DMA transaction
- *
- * For a write we flush out our data. For a read we invalidate, since we
- * need to do this before we read from the buffer after the DMA has
- * completed, so may as well do it now.
- *
- * @param start		Start address for DMA buffer (should be cache-aligned)
- * @param length	Length of DMA buffer in bytes
- * @param is_writing	0 if reading, non-zero if writing
- */
-static void dma_prepare(void *start, unsigned long length, int is_writing)
-{
-	unsigned long addr = (unsigned long)start;
-
-	length = ALIGN(length, ARCH_DMA_MINALIGN);
-	if (is_writing)
-		flush_dcache_range(addr, addr + length);
-	else
-		invalidate_dcache_range(addr, addr + length);
-}
-#endif
-
 /**
  * Wait for command completion
  *

@@ -534,6 +506,8 @@ static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
 	char *tag_ptr;
 	struct nand_drv *info;
 	struct fdt_nand *config;
+	unsigned int bbflags;
+	struct bounce_buffer bbstate, bbstate_oob;
 
 	if ((uintptr_t)buf & 0x03) {
 		printf("buf %p has to be 4-byte aligned\n", buf);

@@ -550,21 +524,21 @@ static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
 
 	stop_command(info->reg);
 
+	if (is_writing)
+		bbflags = GEN_BB_READ;
+	else
+		bbflags = GEN_BB_WRITE;
+
+	bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift,
+			    bbflags);
 	writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
-	writel(virt_to_phys(buf), &info->reg->data_block_ptr);
+	writel((u32)bbstate.bounce_buffer, &info->reg->data_block_ptr);
 
+	/* Set ECC selection, configure ECC settings */
 	if (with_ecc) {
-		writel(virt_to_phys(tag_ptr), &info->reg->tag_ptr);
 		if (is_writing)
 			memcpy(tag_ptr, chip->oob_poi + free->offset,
-				chip->ecc.layout->oobavail +
-				TAG_ECC_BYTES);
-	} else {
-		writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
-	}
-
-	/* Set ECC selection, configure ECC settings */
-	if (with_ecc) {
+			       chip->ecc.layout->oobavail + TAG_ECC_BYTES);
 		tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
 		reg_val |= (CFG_SKIP_SPARE_SEL_4
 			| CFG_SKIP_SPARE_ENABLE

@@ -577,7 +551,8 @@ static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
 
 		if (!is_writing)
 			tag_size += SKIPPED_SPARE_BYTES;
-		dma_prepare(tag_ptr, tag_size, is_writing);
+		bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
+				    bbflags);
 	} else {
 		tag_size = mtd->oobsize;
 		reg_val |= (CFG_SKIP_SPARE_DISABLE

@@ -585,14 +560,12 @@ static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
 			| CFG_ECC_EN_TAG_DISABLE
 			| CFG_HW_ECC_DISABLE
 			| (tag_size - 1));
-		dma_prepare(chip->oob_poi, tag_size, is_writing);
+		bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi,
+				    tag_size, bbflags);
 	}
 	writel(reg_val, &info->reg->config);
-
-	dma_prepare(buf, 1 << chip->page_shift, is_writing);
-
+	writel((u32)bbstate_oob.bounce_buffer, &info->reg->tag_ptr);
 	writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
-
 	writel(tag_size - 1, &info->reg->dma_cfg_b);
 
 	nand_clear_interrupt_status(info->reg);

@@ -638,6 +611,9 @@ static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
 		return -EIO;
 	}
 
+	bounce_buffer_stop(&bbstate_oob);
+	bounce_buffer_stop(&bbstate);
+
 	if (with_ecc && !is_writing) {
 		memcpy(chip->oob_poi, tag_ptr,
 			SKIPPED_SPARE_BYTES);

@@ -755,6 +731,8 @@ static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
 	int tag_size;
 	struct nand_oobfree *free = chip->ecc.layout->oobfree;
 	struct nand_drv *info;
+	unsigned int bbflags;
+	struct bounce_buffer bbstate_oob;
 
 	if (((int)chip->oob_poi) & 0x03)
 		return -EINVAL;

@@ -764,8 +742,6 @@ static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
 
 	stop_command(info->reg);
 
-	writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
-
 	/* Set ECC selection */
 	tag_size = mtd->oobsize;
 	if (with_ecc)

@@ -779,13 +755,20 @@ static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
 		CFG_HW_ECC_DISABLE);
 	writel(reg_val, &info->reg->config);
 
-	dma_prepare(chip->oob_poi, tag_size, is_writing);
-
-	writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
-
 	if (is_writing && with_ecc)
 		tag_size -= TAG_ECC_BYTES;
 
+	if (is_writing)
+		bbflags = GEN_BB_READ;
+	else
+		bbflags = GEN_BB_WRITE;
+
+	bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size,
+			    bbflags);
+	writel((u32)bbstate_oob.bounce_buffer, &info->reg->tag_ptr);
+
+	writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
+
 	writel(tag_size - 1, &info->reg->dma_cfg_b);
 
 	nand_clear_interrupt_status(info->reg);

@@ -822,6 +805,8 @@ static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
 		return -EIO;
 	}
 
+	bounce_buffer_stop(&bbstate_oob);
+
 	if (with_ecc && !is_writing) {
 		reg_val = (u32)check_ecc_error(info->reg, 0, 0,
 			(u8 *)(chip->oob_poi + free->offset),

index 24880c3..a5f0a35 100644
@@ -64,6 +64,17 @@
 #define CONFIG_TEGRA_NAND
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 
+/* Dynamic MTD partition support */
+#define CONFIG_CMD_MTDPARTS	/* Enable 'mtdparts' command line support */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT		"nand0=tegra_nand"
+#define MTDPARTS_DEFAULT	"mtdparts=tegra_nand:"		\
+				"2m(u-boot)ro,"			\
+				"1m(u-boot-env),"		\
+				"1m(cfgblock)ro,"		\
+				"-(ubi)"
+
 /* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET              (SZ_2M)

@@ -76,6 +87,9 @@
 /* Miscellaneous commands */
 #define CONFIG_FAT_WRITE
 
+#define BOARD_EXTRA_ENV_SETTINGS \
+	"mtdparts=" MTDPARTS_DEFAULT "\0"
+
 /* Increase console I/O buffer size */
 #undef CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_CBSIZE		1024

index a5f0a35..72a328f 100644
@@ -81,6 +81,14 @@
 #undef  CONFIG_ENV_SIZE /* undef size from tegra20-common.h */
 #define CONFIG_ENV_SIZE                (SZ_64K)
 
+/* UBI */
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS	/* increases size by almost 60 KB */
+#define CONFIG_LZO
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_RBTREE
+
 /* Debug commands */
 #define CONFIG_CMD_CACHE
 

index 283b002..898ccdf 100644
@@ -79,6 +79,9 @@
 #undef CONFIG_SYS_MAXARGS
 #define CONFIG_SYS_MAXARGS		32
 
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 

index 72a328f..4c45ef8 100644
@@ -113,6 +113,9 @@
 #undef CONFIG_SYS_MAXARGS
 #define CONFIG_SYS_MAXARGS		32
 
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 

index 249b5c0..3ef4778 100644
@@ -72,6 +72,9 @@
 #undef CONFIG_SYS_MAXARGS
 #define CONFIG_SYS_MAXARGS		32
 
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 

index 898ccdf..8f7f833 100644
@@ -60,6 +60,9 @@
 
 /* General networking support */
 #define CONFIG_CMD_DHCP
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE		16384
+#define CONFIG_TFTP_TSIZE
 
 /* Miscellaneous commands */
 #define CONFIG_FAT_WRITE

index 4c45ef8..65c4bee 100644
@@ -48,6 +48,9 @@
 
 /* General networking support */
 #define CONFIG_CMD_DHCP
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE		1536
+#define CONFIG_TFTP_TSIZE
 
 /* LCD support */
 #define CONFIG_LCD

index 3ef4778..f91c2e2 100644
@@ -53,6 +53,9 @@
 
 /* General networking support */
 #define CONFIG_CMD_DHCP
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE		16384
+#define CONFIG_TFTP_TSIZE
 
 /* Miscellaneous commands */
 #define CONFIG_FAT_WRITE

index b7a2219..879006f 100644
@@ -6,13 +6,13 @@
  */
 
 #include <common.h>
-#include <dm.h>
 #include <asm/arch/gp_padctrl.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/tegra.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
+#include <dm.h>
 #include <i2c.h>
 #include <netdev.h>
 

@@ -59,6 +59,7 @@ int tegra_pcie_board_init(void)
 		debug("%s: Cannot find PMIC I2C chip\n", __func__);
 		return err;
 	}
+
 	/* TPS659110: VDD2_OP_REG = 1.05V */
 	data[0] = 0x27;
 	addr = 0x25;

index 7ca79eb..44b5beb 100644
@@ -6,14 +6,14 @@
  */
 
 #include <common.h>
-#include <asm/arch/pinmux.h>
 #include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/tegra.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
-#include "pinmux-config-colibri_t30.h"
 #include <i2c.h>
-#include <asm/gpio.h>
+#include "pinmux-config-colibri_t30.h"
 
 int arch_misc_init(void)
 {

index 8f7f833..7fc4bd9 100644
@@ -1,6 +1,8 @@
 /*
  * Copyright (c) 2014-2015 Marcel Ziswiler
  *
+ * Configuration settings for the Toradex Apalis T30 modules.
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 

@@ -28,7 +30,7 @@
 #define CONFIG_SYS_I2C_TEGRA
 #define CONFIG_CMD_I2C
 
-/* SD/MMC */
+/* SD/MMC support */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC

@@ -40,10 +42,10 @@
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_SYS_MMC_ENV_PART		2
 
-/* USB Host support */
+/* USB host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	3
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_USB
 

index 65c4bee..f068cfa 100644
@@ -1,6 +1,8 @@
 /*
  * Copyright (C) 2012 Lucas Stach
  *
+ * Configuration settings for the Toradex Colibri T20 modules.
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 

@@ -38,7 +40,7 @@
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_ULPI
 #define CONFIG_USB_ULPI_VIEWPORT
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	3
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_USB
 

@@ -65,7 +67,7 @@
 /* NAND support */
 #define CONFIG_CMD_NAND
 #define CONFIG_TEGRA_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
 
 /* Dynamic MTD partition support */
 #define CONFIG_CMD_MTDPARTS	/* Enable 'mtdparts' command line support */

@@ -80,9 +82,9 @@
 
 /* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
 #define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET              (SZ_2M)
-#undef  CONFIG_ENV_SIZE /* undef size from tegra20-common.h */
-#define CONFIG_ENV_SIZE                (SZ_64K)
+#define CONFIG_ENV_OFFSET		(SZ_2M)
+#undef CONFIG_ENV_SIZE		/* undef size from tegra20-common.h */
+#define CONFIG_ENV_SIZE			(SZ_64K)
 
 /* UBI */
 #define CONFIG_CMD_BOOTZ

index f91c2e2..04fdc48 100644
@@ -1,6 +1,8 @@
 /*
  * Copyright (c) 2013-2015 Stefan Agner
  *
+ * Configuration settings for the Toradex Colibri T30 modules.
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 

@@ -28,7 +30,7 @@
 #define CONFIG_SYS_I2C_TEGRA
 #define CONFIG_CMD_I2C
 
-/* SD/MMC */
+/* SD/MMC support */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC

@@ -40,10 +42,10 @@
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_SYS_MMC_ENV_PART		2
 
-/* USB Host support */
+/* USB host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	3
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_USB
 

index 42b293d..83e1ddc 100644
@@ -51,6 +51,9 @@ int arch_misc_init(void)
 		return err;
 	}
 
+	/* make sure SODIMM pin 87 nRESET_OUT is released properly */
+	pinmux_set_func(PMUX_PINGRP_ATA, PMUX_FUNC_GMI);
+
 	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
 	    NVBOOTTYPE_RECOVERY)
 		printf("USB recovery mode\n");