socfpga: SPL and DDR init
Subsystems (5)
cover socfpga: SPL and DDR init
This series fixes the SPL support on SoCFPGA and cleans up the DDR init code such that it is becoming remotely mainlinable. After this series, the SPL is capable of booting from both SD/MMC and QSPI NOR.
There is still work to be done, but I'd like to start picking it up so it can land in 2015.10 . Reviews and comments are welcome.
Dinh Nguyen (3):
driver/ddr/altera: Add DDR driver for Altera's SDRAM controller driver/ddr/altera: Add the sdram calibration portion
arm: socfpga: enable the Altera SDRAM controller driver
Marek Vasut (169):
arm: socfpga: Move sdram_config.h to board dir
ddr: altera: Move struct sdram_prot_rule prototype
ddr: altera: Fix typo in mp_threshold1 programming
ddr: altera: Fix debug message format in sequencer
arm: socfpga: reset: Add missing reset manager regs
arm: socfpga: reset: Start reworking the SoCFPGA reset manager
arm: socfpga: reset: Implement unified function to toggle reset
arm: socfpga: reset: Replace ad-hoc reset functions
arm: socfpga: reset: Repair bridge reset handling
arm: socfpga: reset: Add function to reset add peripherals
arm: socfpga: reset: Add SDMMC, QSPI and DMA defines
arm: socfpga: clock: Get rid of cm_config_t typedef
arm: socfpga: clock: Clean up pll_config.h
arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg()
arm: socfpga: scan: Zap redundant params in
scan_mgr_io_scan_chain_prg()
arm: socfpga: scan: Zap iocsr_scan_chain*_table()
arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio()
arm: socfpga: system: Clean up pinmux_config.c
arm: socfpga: spl: Toggle warm reset config I/O bit
arm: socfpga: spl: Configure SCU and NIC-301 early
arm: socfpga: spl: Add missing reset logic
arm: socfpga: spl: Merge spl_board_init() into board_init_f()
arm: socfpga: spl: Remove custom linker script
arm: socfpga: spl: Add support for booting from SD/MMC
arm: socfpga: spl: Add support for booting from QSPI
arm: socfpga: spl: Add support for selecting boot device from BSEL
arm: socfpga: misc: Fix warm reset
arm: socfpga: misc: Add support for printing boot mode
arm: socfpga: misc: Export bootmode into environment variable
arm: socfpga: misc: Probe ethernet GMAC from OF
arm: socfpga: misc: Reset ethernet from OF
arm: socfpga: config: Move SPL GD and malloc to RAM
arm: socfpga: config: Zap incorrect config options
arm: socfpga: config: Exclude CONFIG_SPI_FLASH_MTD from SPL build
arm: socfpga: config: Enable CONFIG_SPI_FLASH_BAR
arm: socfpga: config: Fix LOADADDR
arm: socfpga: config: Make CONFIG_SPI_FLASH_MTD useful
Makefile: Add target for building bootable SPL image for SoCFPGA
ddr: altera: Minor indent fix in set_rank_and_odt_mask()
ddr: altera: Clean up ugly casts in sdram_calibration_full()
ddr: altera: Zap invocation of sdr_get_addr((u32 *)BASE_RW_MGR)"
ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_reg_file->.*)
ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_scc_mgr->.*)
ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_rw_load.*->.*)
ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_mgr_.*->.*)
ddr: altera: Pluck out remaining sdr_get_addr() calls
ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS
ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly
ddr: altera: Massage addr into I/O accessors
ddr: altera: Clean up hc_initialize_rom_data()
ddr: altera: Clean up initialize_reg_file()
ddr: altera: Clean up initialize_hps_phy()
ddr: altera: Clean up reg_file_set*()
ddr: altera: Clean up scc manager function args
ddr: altera: Reorder scc manager functions
ddr: altera: Implement universal scc manager config function
ddr: altera: Clean up scc_mgr_initialize()
ddr: altera: Shuffle around scc_mgr_set_*all_ranks()
ddr: altera: Implement universal scc_mgr_set_all_ranks()
ddr: altera: Clean up scc_mgr_load_dqs_for_write_group()
ddr: altera: Clean up scc_set_bypass_mode()
ddr: altera: Clean up scc_mgr_set_oct_out1_delay()
ddr: altera: Clean up scc_mgr_apply_group_dq_out1_delay()
ddr: altera: Clean up scc_mgr_*_delay() args
ddr: altera: Clean up scc_mgr_set_hhp_extras()
ddr: altera: Extract scc_mgr_set_hhp_extras()
ddr: altera: Clean up scc_mgr_zero_all()
ddr: altera: Clean up scc_mgr_zero_group()
FIXME: ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add()
cleanup part 1
ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup
part 2
ddr: altera: Clean up
scc_mgr_apply_group_all_out_delay_add_all_ranks()
ddr: altera: Factor out instruction loading from
rw_mgr_mem_initialize()
ddr: altera: Factor out common code
ddr: altera: Minor clean up of set_jump_as_return()
ddr: altera: Fix ad-hoc iterative division implementation
ddr: altera: Rework initialize_tracking()
ddr: altera: Init my_param and my_gbl
ddr: altera: Rename initialize() to phy_mgr_initialize()
ddr: altera: Clean up run_mem_calibrate()
ddr: altera: Clean up phy_mgr_initialize()
ddr: altera: Clean up mem_config()
ddr: altera: Clean up mem_precharge_and_activate()
ddr: altera: Clean up set_rank_and_odt_mask() part 1
ddr: altera: Clean up set_rank_and_odt_mask() part 2
ddr: altera: Clean up set_rank_and_odt_mask() part 3
ddr: altera: Minor clean up of mem_skip_calibrate()
ddr: altera: Trivial mem_calibrate() indent cleanup
ddr: altera: Internal mem_calibrate() cleanup part 1
ddr: altera: Internal mem_calibrate() cleanup part 2
ddr: altera: Internal mem_calibrate() cleanup part 3
ddr: altera: Internal mem_calibrate() cleanup part 4
ddr: altera: Internal mem_calibrate() cleanup part 5
ddr: altera: Internal mem_calibrate() cleanup part 6
ddr: altera: Minor clean up of rw_mgr_mem_initialize()
ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 1
ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 2
ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 3
ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 4
ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 5
ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 6
ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 7
ddr: altera: Extract guaranteed write from
rw_mgr_mem_calibrate_vfifo()
ddr: altera: Extract DQS enable calibration from
rw_mgr_mem_calibrate_vfifo()
ddr: altera: Extract Centering DQ/DQS from
rw_mgr_mem_calibrate_vfifo()
ddr: altera: Minor rw_mgr_mem_calibrate_read_load_patterns() cleanup
ddr: altera: Zap rw_mgr_mem_calibrate_read_test_patterns_all_ranks()
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_patterns()
ddr: altera: Clean up
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 1
ddr: altera: Clean up
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 2
ddr: altera: Clean up
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 3
ddr: altera: Clean up
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 4
ddr: altera: Clean up sdr_find_window_centre() part 1
ddr: altera: Clean up sdr_find_window_centre() part 2
ddr: altera: Clean up sdr_find_window_centre() part 3
ddr: altera: Clean up sdr_*_phase() part 1
ddr: altera: Clean up sdr_*_phase() part 2
ddr: altera: Clean up sdr_*_phase() part 3
ddr: altera: Clean up sdr_*_phase() part 4
ddr: altera: Clean up sdr_*_phase() part 5
ddr: altera: Clean up sdr_*_phase() part 6
ddr: altera: Clean up sdr_*_phase() part 7
ddr: altera: Clean up sdr_*_phase() part 8
ddr: altera: Clean up sdr_*_phase() part 9
ddr: altera: Clean up sdr_*_phase() part 10
ddr: altera: Clean up rw_mgr_*_vfifo() part 1
ddr: altera: Clean up rw_mgr_*_vfifo() part 2
ddr: altera: Clean up find_vfifo_read()
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
part 1
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
part 2
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
part 3
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
part 4
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
part 5
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
part 6
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
part 7
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_all_ranks()
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 1
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 2
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 3
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 4
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 5
ddr: altera: Clean up rw_mgr_mem_calibrate_writes()
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 3
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 4
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 5
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 7
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 8
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 9
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue()
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end()
ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo()
ddr: altera: Minor clean up of rw_mgr_mem_handoff()
ddr: altera: Clean up of delay_for_n_mem_clocks() part 1
ddr: altera: Clean up of delay_for_n_mem_clocks() part 2
ddr: altera: Clean up of delay_for_n_mem_clocks() part 3
ddr: altera: Clean up of delay_for_n_mem_clocks() part 4
ddr: altera: Clean up of delay_for_n_mem_clocks() part 5
Makefile | 13 + arch/arm/mach-socfpga/clock_manager.c | 28 +- arch/arm/mach-socfpga/include/mach/clock_manager.h | 12 +- arch/arm/mach-socfpga/include/mach/reset_manager.h | 60 +- arch/arm/mach-socfpga/include/mach/scan_manager.h | 23 +- arch/arm/mach-socfpga/include/mach/sdram.h | 298 +- .../arm/mach-socfpga/include/mach/system_manager.h | 7 +- arch/arm/mach-socfpga/misc.c | 115 +- arch/arm/mach-socfpga/reset_manager.c | 99 +- arch/arm/mach-socfpga/scan_manager.c | 31 +- arch/arm/mach-socfpga/spl.c | 220 +- arch/arm/mach-socfpga/system_manager.c | 16 +- arch/arm/mach-socfpga/u-boot-spl.lds | 45 - board/altera/socfpga/Makefile | 4 +- board/altera/socfpga/qts/Makefile | 7 - board/altera/socfpga/qts/sdram_config.h | 100 + board/altera/socfpga/wrap_iocsr_config.c | 41 + board/altera/socfpga/wrap_pinmux_config.c | 35 + board/altera/socfpga/wrap_pll_config.c | 144 + configs/socfpga_arria5_defconfig | 9 + configs/socfpga_cyclone5_defconfig | 10 + configs/socfpga_socrates_defconfig | 11 +- drivers/ddr/altera/Makefile | 11 + drivers/ddr/altera/sdram.c | 817 +++++ drivers/ddr/altera/sequencer.c | 3806 ++++++++++++++++++++ drivers/ddr/altera/sequencer.h | 299 ++ drivers/ddr/altera/sequencer_auto.h | 128 + drivers/ddr/altera/sequencer_auto_ac_init.h | 84 + drivers/ddr/altera/sequencer_auto_inst_init.h | 268 ++ drivers/ddr/altera/sequencer_defines.h | 121 + include/configs/socfpga_arria5.h | 7 +- include/configs/socfpga_common.h | 63 +- include/configs/socfpga_cyclone5.h | 7 +- include/fdtdec.h | 1 + lib/fdtdec.c | 1 + scripts/Makefile.spl | 11 + 36 files changed, 6566 insertions(+), 386 deletions(-) delete mode 100644 arch/arm/mach-socfpga/u-boot-spl.lds delete mode 100644 board/altera/socfpga/qts/Makefile create mode 100644 board/altera/socfpga/qts/sdram_config.h create mode 100644 board/altera/socfpga/wrap_iocsr_config.c create mode 100644 board/altera/socfpga/wrap_pinmux_config.c create mode 100644 board/altera/socfpga/wrap_pll_config.c create mode 100644 drivers/ddr/altera/Makefile create mode 100644 drivers/ddr/altera/sdram.c create mode 100644 drivers/ddr/altera/sequencer.c create mode 100644 drivers/ddr/altera/sequencer.h create mode 100644 drivers/ddr/altera/sequencer_auto.h create mode 100644 drivers/ddr/altera/sequencer_auto_ac_init.h create mode 100644 drivers/ddr/altera/sequencer_auto_inst_init.h create mode 100644 drivers/ddr/altera/sequencer_defines.h
Signature · 1 line
2.1.4
PATCH 1/172 driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
From: Dinh Nguyen <[email protected]>
This patch enables the SDRAM controller that is used on Altera's SoCFPGA family. This patch configures the SDRAM controller based on a configuration file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by Dinh Nguyen <[email protected]>
--- Makefile | 1 + arch/arm/mach-socfpga/include/mach/sdram.h | 311 ++++++++- arch/arm/mach-socfpga/include/mach/sdram_config.h | 100 +++ drivers/ddr/altera/sdram.c | 799 ++++++++++++++++++++++ scripts/Makefile.spl | 1 + 5 files changed, 1200 insertions(+), 12 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_config.h create mode 100644 drivers/ddr/altera/sdram.c
Makefile +1 -0
@@ -651,6 +651,7 @@ libs-y += drivers/power/ \ libs-y += drivers/spi/ libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/ libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ +libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/ libs-y += drivers/serial/ libs-y += drivers/usb/dwc3/ libs-y += drivers/usb/emul/
arch/arm/mach-socfpga/include/mach/sdram.h +299 -12
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arch/arm/mach-socfpga/include/mach/sdram_config.h new file +100 -0
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drivers/ddr/altera/sdram.c new file +799 -0
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scripts/Makefile.spl +1 -0
@@ -62,6 +62,7 @@ libs-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/ libs-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/ libs-$(CONFIG_SYS_MVEBU_DDR_A38X) += drivers/ddr/marvell/a38x/ libs-$(CONFIG_SYS_MVEBU_DDR_AXP) += drivers/ddr/marvell/axp/ +libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/ libs-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/ libs-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/ libs-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/
Signature · 1 line
2.1.4
PATCH 2/172 driver/ddr/altera: Add the sdram calibration portion
In reply to Marek VasutFrom: Dinh Nguyen <[email protected]>
This patch adds the DDR calibration portion of the Altera SDRAM driver.
Signed-off-by Dinh Nguyen <[email protected]>
--- drivers/ddr/altera/Makefile | 11 + drivers/ddr/altera/sequencer.c | 4051 +++++++++++++++++++++++++ drivers/ddr/altera/sequencer.h | 322 ++ drivers/ddr/altera/sequencer_auto.h | 128 + drivers/ddr/altera/sequencer_auto_ac_init.h | 84 + drivers/ddr/altera/sequencer_auto_inst_init.h | 268 ++ drivers/ddr/altera/sequencer_defines.h | 121 + 7 files changed, 4985 insertions(+) create mode 100644 drivers/ddr/altera/Makefile create mode 100644 drivers/ddr/altera/sequencer.c create mode 100644 drivers/ddr/altera/sequencer.h create mode 100644 drivers/ddr/altera/sequencer_auto.h create mode 100644 drivers/ddr/altera/sequencer_auto_ac_init.h create mode 100644 drivers/ddr/altera/sequencer_auto_inst_init.h create mode 100644 drivers/ddr/altera/sequencer_defines.h
drivers/ddr/altera/Makefile new file +11 -0
@@ -0,0 +1,11 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# (C) Copyright 2010, Thomas Chou <[email protected]> +# Copyright (C) 2014 Altera Corporation <www.altera.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ALTERA_SDRAM) += sdram.o sequencer.o
drivers/ddr/altera/sequencer.c new file +4051 -0
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drivers/ddr/altera/sequencer.h new file +322 -0
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drivers/ddr/altera/sequencer_auto.h new file +128 -0
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drivers/ddr/altera/sequencer_auto_ac_init.h new file +84 -0
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drivers/ddr/altera/sequencer_auto_inst_init.h new file +268 -0
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drivers/ddr/altera/sequencer_defines.h new file +121 -0
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Signature · 1 line
2.1.4
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PATCH 3/172 arm: socfpga: enable the Altera SDRAM controller driver
In reply to Marek VasutFrom: Dinh Nguyen <[email protected]>
Enable the Altera SDRAM driver for the SoCFPGA platform.
Signed-off-by Dinh Nguyen <[email protected]>
Acked-by Marek Vasut <[email protected]>
--- include/configs/socfpga_common.h | 5 +++++ 1 file changed, 5 insertions(+)
include/configs/socfpga_common.h +5 -0
@@ -75,6 +75,11 @@#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS/* +* SDRAM controller +*/ +#define CONFIG_ALTERA_SDRAM + +/* * EPCS/EPCQx1 Serial Flash Controller */ #ifdef CONFIG_ALTERA_SPI
Signature · 1 line
2.1.4
PATCH 4/172 arm: socfpga: Move sdram_config.h to board dir
In reply to Marek VasutThis file is absolutelly positively board specific, so move it into the correct place.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/include/mach/sdram_config.h | 100 ---------------------- board/altera/socfpga/qts/sdram_config.h | 100 ++++++++++++++++++++++ drivers/ddr/altera/sdram.c | 7 +- 3 files changed, 106 insertions(+), 101 deletions(-) delete mode 100644 arch/arm/mach-socfpga/include/mach/sdram_config.h create mode 100644 board/altera/socfpga/qts/sdram_config.h
arch/arm/mach-socfpga/include/mach/sdram_config.h deleted +0 -100
@@ -1,100 +0,0 @@ -/* -* Copyright Altera Corporation (C) 2012-2015 -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/* This file is autogenerated from tools provided by Altera.*/ -#ifndef __SDRAM_CONFIG_H -#define __SDRAM_CONFIG_H - -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#ifdef CONFIG_SOCFPGA_ARRIA5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26 -#else -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 - -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \ -0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \ -0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \ -0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 - -#endif /*#ifndef__SDRAM_CONFIG_H*/
board/altera/socfpga/qts/sdram_config.h new file +100 -0
100 lines not on this page · raw message
drivers/ddr/altera/sdram.c +6 -1
@@ -8,10 +8,15 @@#include <watchdog.h> #include <asm/arch/fpga_manager.h> #include <asm/arch/sdram.h> -#include <asm/arch/sdram_config.h> #include <asm/arch/system_manager.h> #include <asm/io.h> +/* +* FIXME: This path is temporary until the SDRAM driver gets +* a proper thorough cleanup. +*/ +#include "../../../board/altera/socfpga/qts/sdram_config.h" +/* define constant for 4G memory - used for SDRAM errata workaround */ #define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
Signature · 1 line
2.1.4
PATCH 5/172 ddr: altera: Move struct sdram_prot_rule prototype
In reply to Marek VasutMove the structure prototype from sdram.h header file into sdram.c source file, since it is used only there and for local purpose only. There is no point in having it global.
While at this move, fix the data types in the structure from uintNN_t to uNN and fix the coding style a bit.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/include/mach/sdram.h | 13 ------------- drivers/ddr/altera/sdram.c | 13 +++++++++++++ 2 files changed, 13 insertions(+), 13 deletions(-)
arch/arm/mach-socfpga/include/mach/sdram.h +0 -13
@@ -73,19 +73,6 @@ struct socfpga_sdr_ctrl {u32 phy_ctrl2; }; -struct sdram_prot_rule { -uint64_t sdram_start;/* SDRAM start address */ -uint64_t sdram_end;/* SDRAM end address */ -uint32_t rule;/* SDRAM protection rule number: 0-19 */ -int valid;/* Rule valid or not? 1 - valid, 0 not*/ - -uint32_t security; -uint32_t portmask; -uint32_t result; -uint32_t lo_prot_id; -uint32_t hi_prot_id; -}; -#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
drivers/ddr/altera/sdram.c +13 -0
@@ -22,6 +22,19 @@DECLARE_GLOBAL_DATA_PTR ; +struct sdram_prot_rule { +u64 sdram_start;/* SDRAM start address */ +u64 sdram_end;/* SDRAM end address */ +u32 rule;/* SDRAM protection rule number: 0-19 */ +int valid;/* Rule valid or not? 1 - valid, 0 not*/ + +u32 security; +u32 portmask; +u32 result; +u32 lo_prot_id; +u32 hi_prot_id; +}; +static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ; static struct socfpga_sdr_ctrl *sdr_ctrl =
Signature · 1 line
2.1.4
PATCH 6/172 ddr: altera: Fix typo in mp_threshold1 programming
In reply to Marek VasutIt is the configuration data that should go into the register, not the register mask, just like the surrounding code does it. Fix this typo.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Tom Rini <[email protected]>
--- drivers/ddr/altera/sdram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/ddr/altera/sdram.c +1 -1
@@ -539,7 +539,7 @@ static void set_sdr_mp_threshold(void)clrsetbits_le32 (&sdr_ctrl->mp_threshold1,SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK , -SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK << +CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB ); clrsetbits_le32(&sdr_ctrl->mp_threshold2,
Signature · 1 line
2.1.4
PATCH 7/172 ddr: altera: Fix debug message format in sequencer
In reply to Marek VasutThe debug messages missed proper newlines and/or spaces in them. Fix the formatting.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Tom Rini <[email protected]>
--- drivers/ddr/altera/sequencer.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)
drivers/ddr/altera/sequencer.c +7 -7
@@ -332,7 +332,7 @@ static void scc_mgr_initialize(void)*/ uint32_t i;for (i =0 ; i <16 ; i++) { -debug_cond (DLEVEL ==1 ,"%s:%d: Clearing SCC RFILE index %u" , +debug_cond (DLEVEL ==1 ,"%s:%d: Clearing SCC RFILE index %u\n" , __func__, __LINE__, i);writel (0 ,SOCFPGA_SDR_ADDRESS + addr + (i <<2 )); }
@@ -2386,7 +2386,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,uint32_t write_group, write_test_bgn;uint32_t failed_substage; -debug ("%s:%d: %u %u" , __func__, __LINE__, read_group, test_bgn); +debug ("%s:%d: %u %u\n" , __func__, __LINE__, read_group, test_bgn);/* update info for sims */ reg_file_set_stage (CAL_STAGE_VFIFO );
@@ -3994,14 +3994,14 @@ int sdram_calibration_full(void)printf ("%s: Preparing to start memory calibration\n" , __FILE__);debug ("%s:%d\n" , __func__, __LINE__); -debug_cond (DLEVEL ==1 ,"DDR3 FULL_RATE ranks=%lu cs/dimm=%lu dq/dqs=%lu,%lu vg/dqs=%lu,%lu" , +debug_cond (DLEVEL ==1 ,"DDR3 FULL_RATE ranks=%lu cs/dimm=%lu dq/dqs=%lu,%lu vg/dqs=%lu,%lu " , (long unsigned int )RW_MGR_MEM_NUMBER_OF_RANKS , (long unsigned int )RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM , (long unsigned int )RW_MGR_MEM_DQ_PER_READ_DQS , (long unsigned int )RW_MGR_MEM_DQ_PER_WRITE_DQS , (long unsigned int )RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS , (long unsigned int )RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS ); - debug_cond(DLEVEL == 1, "dqs=%lu,%lu dq=%lu dm=%lu ptap_delay=%lu dtap_delay=%lu", + debug_cond(DLEVEL == 1, "dqs=%lu,%lu dq=%lu dm=%lu ptap_delay=%lu dtap_delay=%lu ", (long unsigned int)RW_MGR_MEM_IF_READ_DQS_WIDTH, (long unsigned int)RW_MGR_MEM_IF_WRITE_DQS_WIDTH, (long unsigned int)RW_MGR_MEM_DATA_WIDTH,
@@ -4011,16 +4011,16 @@ int sdram_calibration_full(void)debug_cond (DLEVEL ==1 ,"dtap_dqsen_delay=%lu, dll=%lu" , (long unsigned int )IO_DELAY_PER_DQS_EN_DCHAIN_TAP , (long unsigned int )IO_DLL_CHAIN_LENGTH ); -debug_cond (DLEVEL ==1 ,"max values: en_p=%lu dqdqs_p=%lu en_d=%lu dqs_in_d=%lu" , +debug_cond (DLEVEL ==1 ,"max values: en_p=%lu dqdqs_p=%lu en_d=%lu dqs_in_d=%lu " , (long unsigned int )IO_DQS_EN_PHASE_MAX , (long unsigned int )IO_DQDQS_OUT_PHASE_MAX , (long unsigned int )IO_DQS_EN_DELAY_MAX , (long unsigned int )IO_DQS_IN_DELAY_MAX ); -debug_cond (DLEVEL ==1 ,"io_in_d=%lu io_out1_d=%lu io_out2_d=%lu" , +debug_cond (DLEVEL ==1 ,"io_in_d=%lu io_out1_d=%lu io_out2_d=%lu " , (long unsigned int )IO_IO_IN_DELAY_MAX , (long unsigned int )IO_IO_OUT1_DELAY_MAX , (long unsigned int )IO_IO_OUT2_DELAY_MAX ); -debug_cond (DLEVEL ==1 ,"dqs_in_reserve=%lu dqs_out_reserve=%lu" , +debug_cond (DLEVEL ==1 ,"dqs_in_reserve=%lu dqs_out_reserve=%lu\n" , (long unsigned int )IO_DQS_IN_RESERVE , (long unsigned int )IO_DQS_OUT_RESERVE );
Signature · 1 line
2.1.4
PATCH 8/172 arm: socfpga: reset: Add missing reset manager regs
In reply to Marek VasutDefine two missing reset manager registers, which are in the SoCFPGA CV datasheet.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/mach-socfpga/include/mach/reset_manager.h +2 -0
@@ -28,6 +28,8 @@ struct socfpga_reset_manager {u32 per_mod_reset;u32 per2_mod_reset;u32 brg_mod_reset; +u32 misc_mod_reset; +u32 tstscratch; };#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET )
Signature · 1 line
2.1.4
PATCH 9/172 arm: socfpga: reset: Start reworking the SoCFPGA reset manager
In reply to Marek VasutImplement macro SOCFPGA_RESET(name), which produces an abstract reset number. Implement macros which allow extracting the reset offset in permodrstN register and which permodrstN register the reset is located in from this abstract reset number. Use these macros throughout the reset manager.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/include/mach/reset_manager.h | 47 ++++++++++++++++++---- arch/arm/mach-socfpga/reset_manager.c | 22 +++++----- 2 files changed, 50 insertions(+), 19 deletions(-)
arch/arm/mach-socfpga/include/mach/reset_manager.h +39 -8
@@ -38,13 +38,44 @@ struct socfpga_reset_manager {#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1#endif -#define RSTMGR_PERMODRST_EMAC0_LSB 0 -#define RSTMGR_PERMODRST_EMAC1_LSB 1 -#define RSTMGR_PERMODRST_L4WD0_LSB 6 -#define RSTMGR_PERMODRST_OSC1TIMER0_LSB 8 -#define RSTMGR_PERMODRST_UART0_LSB 16 -#define RSTMGR_PERMODRST_SPIM0_LSB 18 -#define RSTMGR_PERMODRST_SPIM1_LSB 19 -#define RSTMGR_PERMODRST_SDR_LSB 29 +/* +* Define a reset identifier, from which a permodrst bank ID +* and reset ID can be extracted using the subsequent macros +* RSTMGR_RESET() and RSTMGR_BANK(). +*/ +#define RSTMGR_BANK_OFFSET 8 +#define RSTMGR_BANK_MASK 0x7 +#define RSTMGR_RESET_OFFSET 0 +#define RSTMGR_RESET_MASK 0x1f +#define RSTMGR_DEFINE (_bank, _offset) \ + ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) + +/* Extract reset ID from the reset identifier. */ +#define RSTMGR_RESET (_reset) \ + (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) + +/* Extract bank ID from the reset identifier. */ +#define RSTMGR_BANK (_reset) \ + (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) + +/* +* SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: +* 0 ... mpumodrst +* 1 ... permodrst +* 2 ... per2modrst +* 3 ... brgmodrst +* 4 ... miscmodrst +*/ +#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) +#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) +#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) +#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) +#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) +#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) +#define RSTMGR_SDR RSTMGR_DEFINE(1, 29) + +/* Create a human-readable reference to SoCFPGA reset. */ +#define SOCFPGA_RESET (_name) RSTMGR_##_name#endif /* _RESET_MANAGER_H_ */
arch/arm/mach-socfpga/reset_manager.c +11 -11
@@ -20,11 +20,11 @@ void socfpga_watchdog_reset(void) {/* assert reset for watchdog */ setbits_le32 (&reset_manager_base->per_mod_reset, -1 <<RSTMGR_PERMODRST_L4WD0_LSB ); +1 <<RSTMGR_RESET (SOCFPGA_RESET (L4WD0 )));/* deassert watchdog from reset (watchdog in not running state) */ clrbits_le32 (&reset_manager_base->per_mod_reset, -1 <<RSTMGR_PERMODRST_L4WD0_LSB ); +1 <<RSTMGR_RESET (SOCFPGA_RESET (L4WD0 ))); }/*
@@ -94,13 +94,13 @@ void socfpga_emac_reset(int enable)const void *reset = &reset_manager_base->per_mod_reset;if (enable) { -setbits_le32 (reset,1 <<RSTMGR_PERMODRST_EMAC0_LSB ); -setbits_le32 (reset,1 <<RSTMGR_PERMODRST_EMAC1_LSB ); +setbits_le32 (reset,1 <<RSTMGR_RESET (SOCFPGA_RESET (EMAC0 ))); +setbits_le32 (reset,1 <<RSTMGR_RESET (SOCFPGA_RESET (EMAC1 ))); }else {#if (CONFIG_EMAC_BASE ==SOCFPGA_EMAC0_ADDRESS ) -clrbits_le32 (reset,1 <<RSTMGR_PERMODRST_EMAC0_LSB ); +clrbits_le32 (reset,1 <<RSTMGR_RESET (SOCFPGA_RESET (EMAC0 )));#elif (CONFIG_EMAC_BASE ==SOCFPGA_EMAC1_ADDRESS ) -clrbits_le32 (reset,1 <<RSTMGR_PERMODRST_EMAC1_LSB ); +clrbits_le32 (reset,1 <<RSTMGR_RESET (SOCFPGA_RESET (EMAC1 )));#endif } }
@@ -110,8 +110,8 @@ void socfpga_spim_enable(void) {const void *reset = &reset_manager_base->per_mod_reset; -clrbits_le32 (reset, (1 <<RSTMGR_PERMODRST_SPIM0_LSB ) | - (1 <<RSTMGR_PERMODRST_SPIM1_LSB )); +clrbits_le32 (reset, (1 <<RSTMGR_RESET (SOCFPGA_RESET (SPIM0 ))) | + (1 <<RSTMGR_RESET (SOCFPGA_RESET (SPIM1 )))); }/* Bring UART0 out of reset. */
@@ -119,7 +119,7 @@ void socfpga_uart0_enable(void) {const void *reset = &reset_manager_base->per_mod_reset; -clrbits_le32 (reset,1 <<RSTMGR_PERMODRST_UART0_LSB ); +clrbits_le32 (reset,1 <<RSTMGR_RESET (SOCFPGA_RESET (UART0 ))); }/* Bring SDRAM controller out of reset. */
@@ -127,7 +127,7 @@ void socfpga_sdram_enable(void) {const void *reset = &reset_manager_base->per_mod_reset; -clrbits_le32 (reset,1 <<RSTMGR_PERMODRST_SDR_LSB ); +clrbits_le32 (reset,1 <<RSTMGR_RESET (SOCFPGA_RESET (SDR ))); }/* Bring OSC1 timer out of reset. */
@@ -135,5 +135,5 @@ void socfpga_osc1timer_enable(void) {const void *reset = &reset_manager_base->per_mod_reset; -clrbits_le32 (reset,1 <<RSTMGR_PERMODRST_OSC1TIMER0_LSB ); +clrbits_le32 (reset,1 <<RSTMGR_RESET (SOCFPGA_RESET (OSC1TIMER0 ))); }
Signature · 1 line
2.1.4
PATCH 10/172 arm: socfpga: reset: Implement unified function to toggle reset
In reply to Marek VasutImplement function socfpga_per_reset(), which allows asserting or de-asserting reset of each reset manager peripheral in a unified manner. Use this function throughout reset manager.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 + arch/arm/mach-socfpga/reset_manager.c | 58 +++++++++++++--------- 2 files changed, 37 insertions(+), 23 deletions(-)
arch/arm/mach-socfpga/include/mach/reset_manager.h +2 -0
@@ -12,6 +12,8 @@ void reset_deassert_peripherals_handoff(void);void socfpga_bridges_reset (int enable); +void socfpga_per_reset (u32 reset,int set); +void socfpga_emac_reset (int enable);void socfpga_watchdog_reset (void );void socfpga_spim_enable (void );
arch/arm/mach-socfpga/reset_manager.c +35 -23
99 lines not on this page · raw message
Signature · 1 line
2.1.4
PATCH 11/172 arm: socfpga: reset: Replace ad-hoc reset functions
In reply to Marek VasutReplace all those ad-hoc reset functions, which were all copies of the same invocation of clrbits_le32() anyway, with one single unified function, socfpga_per_reset(), with necessary parameters.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/include/mach/reset_manager.h | 7 --- arch/arm/mach-socfpga/misc.c | 14 ++++-- arch/arm/mach-socfpga/reset_manager.c | 50 ---------------------- arch/arm/mach-socfpga/spl.c | 6 +-- 4 files changed, 13 insertions(+), 64 deletions(-)
arch/arm/mach-socfpga/include/mach/reset_manager.h +0 -7
@@ -14,13 +14,6 @@ void socfpga_bridges_reset(int enable);void socfpga_per_reset (u32 reset,int set); -void socfpga_emac_reset (int enable); -void socfpga_watchdog_reset (void ); -void socfpga_spim_enable (void ); -void socfpga_uart0_enable (void ); -void socfpga_sdram_enable (void ); -void socfpga_osc1timer_enable (void ); -struct socfpga_reset_manager {u32 status;u32 ctrl;
arch/arm/mach-socfpga/misc.c +10 -4
@@ -54,8 +54,10 @@ int cpu_eth_init(bd_t *bis) {#if CONFIG_EMAC_BASE ==SOCFPGA_EMAC0_ADDRESS const int physhift =SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB ; +const u32 reset =SOCFPGA_RESET (EMAC0 );#elif CONFIG_EMAC_BASE ==SOCFPGA_EMAC1_ADDRESS const int physhift =SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB ; +const u32 reset =SOCFPGA_RESET (EMAC1 );#else #error "Incorrect CONFIG_EMAC_BASE value!"#endif
@@ -66,7 +68,8 @@ int cpu_eth_init(bd_t *bis)* Putting the EMAC controller to reset when configuring the PHY * interface select at System Manager */ -socfpga_emac_reset (1 ); +socfpga_per_reset (SOCFPGA_RESET (EMAC0 ),1 ); +socfpga_per_reset (SOCFPGA_RESET (EMAC1 ),1 );/* Clearing emac0 PHY interface select to 0 */ clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
@@ -77,7 +80,7 @@ int cpu_eth_init(bd_t *bis) SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);/* Release the EMAC controller from reset */ -socfpga_emac_reset (0 ); +socfpga_per_reset (reset,0 );/* initialize and register the emac */ return designware_initialize(CONFIG_EMAC_BASE,
@@ -163,8 +166,10 @@ int arch_cpu_init(void)* If the HW watchdog is NOT enabled, make sure it is not running, * for example because it was enabled in the preloader. This might * trigger a watchdog-triggered reboot of Linux kernel later. +* Toggle watchdog reset, so watchdog in not running state. */ -socfpga_watchdog_reset (); +socfpga_per_reset (SOCFPGA_RESET (L4WD0 ),1 ); +socfpga_per_reset (SOCFPGA_RESET (L4WD0 ),0 );#endif return 0 ;
@@ -214,7 +219,8 @@ int arch_early_init_r(void)#ifdef CONFIG_DESIGNWARE_SPI /* Get Designware SPI controller out of reset */ -socfpga_spim_enable (); +socfpga_per_reset (SOCFPGA_RESET (SPIM0 ),0 ); +socfpga_per_reset (SOCFPGA_RESET (SPIM1 ),0 );#endif return 0 ;
arch/arm/mach-socfpga/reset_manager.c +0 -50
59 lines not on this page · raw message
arch/arm/mach-socfpga/spl.c +3 -3
@@ -175,9 +175,9 @@ void spl_board_init(void)/* freeze all IO banks */ sys_mgr_frzctrl_freeze_req (); -socfpga_sdram_enable (); -socfpga_uart0_enable (); -socfpga_osc1timer_enable (); +socfpga_per_reset (SOCFPGA_RESET (SDR ),0 ); +socfpga_per_reset (SOCFPGA_RESET (UART0 ),0 ); +socfpga_per_reset (SOCFPGA_RESET (OSC1TIMER0 ),0 );timer_init ();
Signature · 1 line
2.1.4
PATCH 11/172 arm: socfpga: reset: Replace ad-hoc reset functions
Quoted 46 lines · Marek Vasut
Replace all those ad-hoc reset functions, which were all copies of the same invocation of
clrbits_le32()anyway, with one single unified function,socfpga_per_reset(), with necessary parameters.Signed-off-by Marek Vasut <[email protected]>--- arch/arm/mach-socfpga/include/mach/reset_manager.h | 7 --- arch/arm/mach-socfpga/misc.c | 14 ++++-- arch/arm/mach-socfpga/reset_manager.c | 50 ---------------------- arch/arm/mach-socfpga/spl.c | 6 +-- 4 files changed, 13 insertions(+), 64 deletions(-)arch/arm/mach-socfpga/include/mach/reset_manager.h +0
-7@@ -14,13 +14,6 @@ void socfpga_bridges_reset(int enable);void socfpga_per_reset (u32 reset,int set); -void socfpga_emac_reset (int enable); -void socfpga_watchdog_reset (void ); -void socfpga_spim_enable (void ); -void socfpga_uart0_enable (void ); -void socfpga_sdram_enable (void ); -void socfpga_osc1timer_enable (void ); -struct socfpga_reset_manager {u32 status;u32 ctrl;arch/arm/mach-socfpga/misc.c +2
-0@@ -54,8 +54,10 @@ int cpu_eth_init(bd_t *bis) {#if CONFIG_EMAC_BASE ==SOCFPGA_EMAC0_ADDRESS const int physhift =SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB ; +const u32 reset =SOCFPGA_RESET (EMAC0 );#elif CONFIG_EMAC_BASE ==SOCFPGA_EMAC1_ADDRESS const int physhift =SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB ; +const u32 reset =SOCFPGA_RESET (EMAC1 );#else #error "Incorrect CONFIG_EMAC_BASE value!"#endif
arch/arm/mach-socfpga/misc.c int cpu_eth_init(bd_t *bis) · line 72
Quoted 6 lines
arch/arm/mach-socfpga/misc.c +2
-1@@ -66,7 +68,8 @@ int cpu_eth_init(bd_t *bis)* Putting the EMAC controller to reset when configuring the PHY * interface select at System Manager */ -socfpga_emac_reset (1 ); +socfpga_per_reset (SOCFPGA_RESET (EMAC0 ),1 ); +socfpga_per_reset (SOCFPGA_RESET (EMAC1 ),1 );
Couldn't you just use the 'reset' variable here?
This my only comment on this patch, no need to resend if it's the only one.
Thanks,
Dinh
PATCH 11/172 arm: socfpga: reset: Replace ad-hoc reset functions
On Tuesday, July 28, 2015 at 09:12:50 PM, Dinh Nguyen wrote:
Hi!
Quoted 11 lines
arch/arm/mach-socfpga/misc.c int cpu_eth_init(bd_t *bis) · line 74
Quoted 9 lines
arch/arm/mach-socfpga/misc.c +2
-1@@ -66,7 +68,8 @@ int cpu_eth_init(bd_t *bis)* Putting the EMAC controller to reset when configuring the PHY * interface select at System Manager */ -socfpga_emac_reset (1 ); +socfpga_per_reset (SOCFPGA_RESET (EMAC0 ),1 ); +socfpga_per_reset (SOCFPGA_RESET (EMAC1 ),1 );Couldn't you just use the 'reset' variable here?
Actually, the answer is no. The logic here is such, that you put both GMAC into reset state, but release from reset only the GMAC which is useful to you. The rest remains in reset indefinitelly, so it doesn't consume power etc.
Best regards,
Marek Vasut
PATCH 12/172 arm: socfpga: reset: Repair bridge reset handling
In reply to Marek VasutThe current bridge reset code, which de-asserted the bridge reset, was activelly polling whether the FPGA is programmed and ready and in case it was (!), the code called hang(). This makes no sense at all. Repair it such that the code instead checks whether the FPGA is programmed, but without any polling involved, and only if it is programmed, it de-asserts the reset.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/reset_manager.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm/mach-socfpga/reset_manager.c +4 -4
@@ -85,10 +85,10 @@ void socfpga_bridges_reset(int enable)writel (0xffffffff , &reset_manager_base->brg_mod_reset); }else {/* Check signal from FPGA. */ -if (fpgamgr_poll_fpga_ready ()) { -/* FPGA not ready. Wait for watchdog timeout. */ -printf ("%s: fpga not ready, hanging.\n" , __func__); -hang (); +if (!fpgamgr_test_fpga_ready ()) { +/* FPGA not ready, do nothing. */ +printf ("%s: FPGA not ready, aborting.\n" , __func__); +return ; }/* brdmodrst */
Signature · 1 line
2.1.4
PATCH 12/172 arm: socfpga: reset: Repair bridge reset handling
Quoted 2 lines · Marek Vasut
The current bridge reset code, which de-asserted the bridge reset, was activelly polling whether the FPGA is programmed and ready and
s/activelly/actively
Again...only comment for this patch, no need to resend.
Dinh
PATCH 12/172 arm: socfpga: reset: Repair bridge reset handling
Quoted 7 lines · Dinh Nguyen
Quoted 2 lines · Marek Vasut
The current bridge reset code, which de-asserted the bridge reset, was activelly polling whether the FPGA is programmed and ready and
s/activelly/actively
Again...only comment for this patch, no need to resend.
Fixed, thanks!
Sorry about the blast of patches . How far are you with the review please? :)
Best regards,
Marek Vasut
PATCH 13/172 arm: socfpga: reset: Add function to reset add peripherals
In reply to Marek VasutAdd socfpga_per_reset_all() function to reset all peripherals but the L4 watchdog. This is needed in the SPL.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/include/mach/reset_manager.h | 1 + arch/arm/mach-socfpga/reset_manager.c | 13 +++++++++++++ 2 files changed, 14 insertions(+)
arch/arm/mach-socfpga/include/mach/reset_manager.h +1 -0
@@ -13,6 +13,7 @@ void reset_deassert_peripherals_handoff(void);void socfpga_bridges_reset (int enable);void socfpga_per_reset (u32 reset,int set); +void socfpga_per_reset_all (void );struct socfpga_reset_manager {u32 status;
arch/arm/mach-socfpga/reset_manager.c +13 -0
@@ -40,6 +40,19 @@ void socfpga_per_reset(u32 reset, int set) }/* +* Assert reset on every peripheral but L4WD0. +* Watchdog must be kept intact to prevent glitches +* and/or hangs. +*/ +void socfpga_per_reset_all (void ) +{ +const u32 l4wd0 =1 <<RSTMGR_RESET (SOCFPGA_RESET (L4WD0 )); + +writel (~l4wd0, &reset_manager_base->per_mod_reset); +writel (0xffffffff , &reset_manager_base->per2_mod_reset); +} + +/* * Write the reset manager register to cause reset */ void reset_cpu (ulong addr)
Signature · 1 line
2.1.4
PATCH 14/172 arm: socfpga: reset: Add SDMMC, QSPI and DMA defines
In reply to Marek VasutAdd SDMMC, QSPI and DMA reset defines. These are needed by SPL so that we can boot from SD card and QSPI.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +++ 1 file changed, 3 insertions(+)
arch/arm/mach-socfpga/include/mach/reset_manager.h +3 -0
@@ -69,6 +69,9 @@ struct socfpga_reset_manager {#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16)#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18)#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) +#define RSTMGR_QSPI RSTMGR_DEFINE(0, 5) +#define RSTMGR_SDMMC RSTMGR_DEFINE(0, 22) +#define RSTMGR_DMA RSTMGR_DEFINE(0, 28)#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)/* Create a human-readable reference to SoCFPGA reset. */
Signature · 1 line
2.1.4
PATCH 15/172 arm: socfpga: clock: Get rid of cm_config_t typedef
In reply to Marek VasutGet rid of this cryptic typedef and replace it with explicit struct cm_config.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/clock_manager.c | 2 +- arch/arm/mach-socfpga/include/mach/clock_manager.h | 6 +++--- arch/arm/mach-socfpga/spl.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-)
arch/arm/mach-socfpga/clock_manager.c +1 -1
@@ -88,7 +88,7 @@ static void cm_write_with_phase(uint32_t value,* Ungate clocks */ -void cm_basic_init (const cm_config_t *cfg) +void cm_basic_init (const struct cm_config *cfg) {uint32_t start, timeout;
arch/arm/mach-socfpga/include/mach/clock_manager.h +3 -3
@@ -17,7 +17,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);unsigned int cm_get_spi_controller_clk_hz (void );#endif -typedef struct { +struct cm_config {/* main group */ uint32_t main_vco_base;uint32_t mpuclk;
@@ -49,9 +49,9 @@ typedef struct {uint32_t ddr2xdqsclk;uint32_t ddrdqclk;uint32_t s2fuser2clk; -} cm_config_t; +}; -extern void cm_basic_init (const cm_config_t *cfg); +extern void cm_basic_init (const struct cm_config *cfg);struct socfpga_clock_manager_main_pll {u32 vco;
arch/arm/mach-socfpga/spl.c +1 -1
@@ -85,7 +85,7 @@ void spl_board_init(void) { unsigned long sdram_size; #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET - cm_config_t cm_default_cfg = { + struct cm_config cm_default_cfg = { /* main group */ MAIN_VCO_BASE, (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
Signature · 1 line
2.1.4
PATCH 16/172 arm: socfpga: clock: Clean up pll_config.h
In reply to Marek VasutExtract the clock configuration horribleness caused by pll_config.h in the following manner.
First of all, introduce a few new accessors which return values of various clocks used in clock_manager.c and use them in clock_manager.c . These accessors replace those few macros which came from pll_config.h originally. Also introduce an accessor which returns the struct cm_config default configuration for the clock manager used in SPL.
The accessors are implemented in a board-specific wrap_pll_config.c file, whose sole purpose is to include the qts-generated pll_config.h and provide only the necessary values to the clock manager.
The purpose of this design is to limit the scope of inclusion for the pll_config.h , which thus far was included build-wide and poluted the namespace. With this change, the inclusion is limited to just the new wrap_pll_config.c file, which in turn provides three simple functions for the clock_manager.c to use.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/clock_manager.c | 28 ++-- arch/arm/mach-socfpga/include/mach/clock_manager.h | 8 +- arch/arm/mach-socfpga/spl.c | 114 +--------------- board/altera/socfpga/Makefile | 2 +- board/altera/socfpga/wrap_pll_config.c | 144 +++++++++++++++++++++ include/configs/socfpga_arria5.h | 1 - include/configs/socfpga_cyclone5.h | 1 - 7 files changed, 169 insertions(+), 129 deletions(-) create mode 100644 board/altera/socfpga/wrap_pll_config.c
arch/arm/mach-socfpga/clock_manager.c +14 -14
@@ -88,7 +88,7 @@ static void cm_write_with_phase(uint32_t value,* Ungate clocks */ -void cm_basic_init (const struct cm_config *cfg) +void cm_basic_init (const struct cm_config *const cfg) {uint32_t start, timeout;
@@ -336,7 +336,7 @@ static unsigned int cm_get_main_vco_clk_hz(void)/* get the main VCO clock */ reg =readl (&clock_manager_base->main_pll.vco); - clock =CONFIG_HPS_CLK_OSC1_HZ ; + clock =cm_get_osc_clk_hz (1 ); clock /= ((reg &CLKMGR_MAINPLLGRP_VCO_DENOM_MASK ) >>CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET ) +1 ; clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
@@ -354,11 +354,11 @@ static unsigned int cm_get_per_vco_clk_hz(void) reg = (reg &CLKMGR_PERPLLGRP_VCO_SSRC_MASK ) >>CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET ;if (reg ==CLKMGR_VCO_SSRC_EOSC1 ) - clock =CONFIG_HPS_CLK_OSC1_HZ ; + clock =cm_get_osc_clk_hz (1 );else if (reg ==CLKMGR_VCO_SSRC_EOSC2 ) - clock =CONFIG_HPS_CLK_OSC2_HZ ; + clock =cm_get_osc_clk_hz (2 );else if (reg ==CLKMGR_VCO_SSRC_F2S ) - clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ; + clock =cm_get_f2s_per_ref_clk_hz ();/* get the PER VCO clock */ reg =readl (&clock_manager_base->per_pll.vco);
@@ -393,11 +393,11 @@ unsigned long cm_get_sdram_clk_hz(void) reg = (reg &CLKMGR_SDRPLLGRP_VCO_SSRC_MASK ) >>CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET ;if (reg ==CLKMGR_VCO_SSRC_EOSC1 ) - clock =CONFIG_HPS_CLK_OSC1_HZ ; + clock =cm_get_osc_clk_hz (1 );else if (reg ==CLKMGR_VCO_SSRC_EOSC2 ) - clock =CONFIG_HPS_CLK_OSC2_HZ ; + clock =cm_get_osc_clk_hz (2 );else if (reg ==CLKMGR_VCO_SSRC_F2S ) - clock =CONFIG_HPS_CLK_F2S_SDR_REF_HZ ; + clock =cm_get_f2s_sdr_ref_clk_hz ();/* get the SDRAM VCO clock */ reg =readl (&clock_manager_base->sdr_pll.vco);
@@ -459,7 +459,7 @@ unsigned int cm_get_mmc_controller_clk_hz(void)CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET ;if (reg ==CLKMGR_SDMMC_CLK_SRC_F2S ) { - clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ; + clock =cm_get_f2s_per_ref_clk_hz (); }else if (reg ==CLKMGR_SDMMC_CLK_SRC_MAIN ) { clock =cm_get_main_vco_clk_hz ();
@@ -489,7 +489,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void)CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET ;if (reg ==CLKMGR_QSPI_CLK_SRC_F2S ) { - clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ; + clock =cm_get_f2s_per_ref_clk_hz (); }else if (reg ==CLKMGR_QSPI_CLK_SRC_MAIN ) { clock =cm_get_main_vco_clk_hz ();
@@ -524,10 +524,10 @@ static void cm_print_clock_quick_summary(void) {printf ("MPU %10ld kHz\n" ,cm_get_mpu_clk_hz () /1000 );printf ("DDR %10ld kHz\n" ,cm_get_sdram_clk_hz () /1000 ); -printf ("EOSC1 %8d kHz\n" ,CONFIG_HPS_CLK_OSC1_HZ /1000 ); -printf ("EOSC2 %8d kHz\n" ,CONFIG_HPS_CLK_OSC2_HZ /1000 ); -printf ("F2S_SDR_REF %8d kHz\n" ,CONFIG_HPS_CLK_F2S_SDR_REF_HZ /1000 ); -printf ("F2S_PER_REF %8d kHz\n" ,CONFIG_HPS_CLK_F2S_PER_REF_HZ /1000 ); +printf ("EOSC1 %8d kHz\n" ,cm_get_osc_clk_hz (1 ) /1000 ); +printf ("EOSC2 %8d kHz\n" ,cm_get_osc_clk_hz (2 ) /1000 ); +printf ("F2S_SDR_REF %8d kHz\n" ,cm_get_f2s_sdr_ref_clk_hz () /1000 ); +printf ("F2S_PER_REF %8d kHz\n" ,cm_get_f2s_per_ref_clk_hz () /1000 );printf ("MMC %8d kHz\n" ,cm_get_mmc_controller_clk_hz () /1000 );printf ("QSPI %8d kHz\n" ,cm_get_qspi_controller_clk_hz () /1000 );printf ("UART %8d kHz\n" ,cm_get_l4_sp_clk_hz () /1000 );
arch/arm/mach-socfpga/include/mach/clock_manager.h +7 -1
@@ -15,6 +15,12 @@ unsigned int cm_get_l4_sp_clk_hz(void);unsigned int cm_get_mmc_controller_clk_hz (void );unsigned int cm_get_qspi_controller_clk_hz (void );unsigned int cm_get_spi_controller_clk_hz (void ); +const unsigned int cm_get_osc_clk_hz (const int osc); +const unsigned int cm_get_f2s_per_ref_clk_hz (void ); +const unsigned int cm_get_f2s_sdr_ref_clk_hz (void ); + +/* Clock configuration accessors */ +const struct cm_config *const cm_get_default_config (void );#endif struct cm_config {
@@ -51,7 +57,7 @@ struct cm_config {uint32_t s2fuser2clk; }; -extern void cm_basic_init (const struct cm_config *cfg); +void cm_basic_init (const struct cm_config *const cfg);struct socfpga_clock_manager_main_pll {u32 vco;
arch/arm/mach-socfpga/spl.c +3 -111
132 lines not on this page · raw message
board/altera/socfpga/Makefile +1 -1
@@ -6,5 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := socfpga.o +obj-y := socfpga.o wrap_pll_config.o obj-$(CONFIG_SPL_BUILD) += qts/
board/altera/socfpga/wrap_pll_config.c new file +144 -0
144 lines not on this page · raw message
include/configs/socfpga_arria5.h +0 -1
@@ -9,7 +9,6 @@#include <asm/arch/socfpga_base_addrs.h> #include "../../board/altera/socfpga/qts/pinmux_config.h" #include "../../board/altera/socfpga/qts/iocsr_config.h" -#include "../../board/altera/socfpga/qts/pll_config.h" /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH
include/configs/socfpga_cyclone5.h +0 -1
@@ -9,7 +9,6 @@#include <asm/arch/socfpga_base_addrs.h> #include "../../board/altera/socfpga/qts/pinmux_config.h" #include "../../board/altera/socfpga/qts/iocsr_config.h" -#include "../../board/altera/socfpga/qts/pll_config.h" /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH
Signature · 1 line
2.1.4
PATCH 17/172 arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg()
In reply to Marek VasutThis function is never used outside of scan_manager.c , so make it static. Zap the prototype in scan_manager.h and move the documentation above the function. Make the documentation kerneldoc compliant.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/include/mach/scan_manager.h | 11 ----------- arch/arm/mach-socfpga/scan_manager.c | 14 +++++++++----- 2 files changed, 9 insertions(+), 16 deletions(-)
arch/arm/mach-socfpga/include/mach/scan_manager.h +0 -11
@@ -68,17 +68,6 @@ struct socfpga_scan_manager {#define SCANMGR_STAT_ACTIVE_GET (x) (((x) & 0x80000000) >> 31)#define SCANMGR_STAT_WFIFOCNT_GET (x) (((x) & 0x70000000) >> 28) -/* -* Program HPS IO Scan Chain -* io_scan_chain_id - IO scan chain ID -* io_scan_chain_len_in_bits - IO scan chain length in bits -* iocsr_scan_chain - IO scan chain table -*/ -uint32_t scan_mgr_io_scan_chain_prg ( -uint32_t io_scan_chain_id, -uint32_t io_scan_chain_len_in_bits, -const uint32_t *iocsr_scan_chain); -extern const uint32_t iocsr_scan_chain0_table[ ((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH /32 ) +1 )]; extern const uint32_t iocsr_scan_chain1_table[
arch/arm/mach-socfpga/scan_manager.c +9 -5
@@ -38,11 +38,15 @@ static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter)return 1 ; } -/* Program HPS IO Scan Chain */ -uint32_t scan_mgr_io_scan_chain_prg ( -uint32_t io_scan_chain_id, -uint32_t io_scan_chain_len_in_bits, -const uint32_t *iocsr_scan_chain) +/** +* scan_mgr_io_scan_chain_prg() - Program HPS IO Scan Chain +* @io_scan_chain_id: IO scan chain ID +* @io_scan_chain_len_in_bits: IO scan chain length in bits +* @iocsr_scan_chain: IO scan chain table +*/ +static int scan_mgr_io_scan_chain_prg (const unsigned int io_scan_chain_id, +uint32_t io_scan_chain_len_in_bits, +const uint32_t *iocsr_scan_chain) {uint16_t tdi_tdo_header;uint32_t io_program_iter;
Signature · 1 line
2.1.4
PATCH 18/172 arm: socfpga: scan: Zap redundant params in scan_mgr_io_scan_chain_prg()
In reply to Marek VasutIt is sufficient to pass in the scan chain ID into the function to determine the remaining two parameters, so drop those params and determine them locally in the function. The big-ish switch in the function is temporary and will be replaced by a proper function call in subsequent patch.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/scan_manager.c | 39 ++++++++++++++++++++++++------------ 1 file changed, 26 insertions(+), 13 deletions(-)
arch/arm/mach-socfpga/scan_manager.c +26 -13
@@ -41,12 +41,8 @@ static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter)/** * scan_mgr_io_scan_chain_prg() - Program HPS IO Scan Chain * @io_scan_chain_id: IO scan chain ID -* @io_scan_chain_len_in_bits: IO scan chain length in bits -* @iocsr_scan_chain: IO scan chain table */ -static int scan_mgr_io_scan_chain_prg (const unsigned int io_scan_chain_id, -uint32_t io_scan_chain_len_in_bits, -const uint32_t *iocsr_scan_chain) +static int scan_mgr_io_scan_chain_prg (const unsigned int io_scan_chain_id) {uint16_t tdi_tdo_header;uint32_t io_program_iter;
@@ -54,6 +50,27 @@ static int scan_mgr_io_scan_chain_prg(const unsigned int io_scan_chain_id,uint32_t residual;uint32_t i;uint32_t index =0 ; +uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain; + +switch (io_scan_chain_id) { +case 0 : + io_scan_chain_len_in_bits =CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH ; + iocsr_scan_chain = iocsr_scan_chain0_table; +break ; +case 1 : + io_scan_chain_len_in_bits =CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH ; + iocsr_scan_chain = iocsr_scan_chain1_table; +break ; +case 2 : + io_scan_chain_len_in_bits =CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH ; + iocsr_scan_chain = iocsr_scan_chain2_table; +break ; +case 3 : + io_scan_chain_len_in_bits =CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH ; + iocsr_scan_chain = iocsr_scan_chain3_table; +break ; + }/* * De-assert reinit if the IO scan chain is intended for HIO. In
@@ -201,13 +218,9 @@ int scan_mgr_configure_iocsr(void)int status =0 ;/* configure the IOCSR through scan chain */ - status |=scan_mgr_io_scan_chain_prg (0 , -CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH , iocsr_scan_chain0_table); - status |=scan_mgr_io_scan_chain_prg (1 , -CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH , iocsr_scan_chain1_table); - status |=scan_mgr_io_scan_chain_prg (2 , -CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH , iocsr_scan_chain2_table); - status |=scan_mgr_io_scan_chain_prg (3 , -CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH , iocsr_scan_chain3_table); + status |=scan_mgr_io_scan_chain_prg (0 ); + status |=scan_mgr_io_scan_chain_prg (1 ); + status |=scan_mgr_io_scan_chain_prg (2 ); + status |=scan_mgr_io_scan_chain_prg (3 );return status; }
Signature · 1 line
2.1.4
PATCH 19/172 arm: socfpga: scan: Zap iocsr_scan_chain*_table()
In reply to Marek VasutIntroduce accessor iocsr_get_config_table() for retrieving IOCSR config tables. This patch is again trimming down the namespace polution.
The IOCSR config tables are used only by scan manager, they are generated by qts and are board specific. Before this patch, the approach to use these tables in scan manager was to define an extern variable to silence the compiler and compile board-specific iocsr_config.c into U-Boot which defined those extern variables. Furthermore, since these are tables and the scan manager needs to know the size of those tables, iocsr_config.h is included build-wide.
This patch wraps all this into a single accessor which takes the scan chain ID and returns pointer to the table and it's size. All this is wrapped in wrap_iocsr_config.c board-specific file. The file includes the iocsr_config.c (!) to access the original tables and transitively iocsr_config.h . It is thus no longer necessary to include iocsr_config.h build-wide and the namespace polution is trimmed some more.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/include/mach/scan_manager.h | 12 ++----- arch/arm/mach-socfpga/scan_manager.c | 30 +++++------------ board/altera/socfpga/Makefile | 2 +- board/altera/socfpga/qts/Makefile | 2 +- board/altera/socfpga/wrap_iocsr_config.c | 41 +++++++++++++++++++++++ include/configs/socfpga_arria5.h | 1 - include/configs/socfpga_cyclone5.h | 1 - 7 files changed, 54 insertions(+), 35 deletions(-) create mode 100644 board/altera/socfpga/wrap_iocsr_config.c
arch/arm/mach-socfpga/include/mach/scan_manager.h +3 -9
@@ -68,15 +68,9 @@ struct socfpga_scan_manager {#define SCANMGR_STAT_ACTIVE_GET (x) (((x) & 0x80000000) >> 31)#define SCANMGR_STAT_WFIFOCNT_GET (x) (((x) & 0x70000000) >> 28) -extern const uint32_t iocsr_scan_chain0_table[ - ((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH /32 ) +1 )]; -extern const uint32_t iocsr_scan_chain1_table[ - ((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH /32 ) +1 )]; -extern const uint32_t iocsr_scan_chain2_table[ - ((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH /32 ) +1 )]; -extern const uint32_t iocsr_scan_chain3_table[ - ((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH /32 ) +1 )]; -int scan_mgr_configure_iocsr (void ); +int iocsr_get_config_table (const unsigned int chain_id, +const unsigned long **table, +unsigned int *table_len);#endif /* _SCAN_MANAGER_H_ */
arch/arm/mach-socfpga/scan_manager.c +8 -22
@@ -48,29 +48,15 @@ static int scan_mgr_io_scan_chain_prg(const unsigned int io_scan_chain_id)uint32_t io_program_iter;uint32_t io_scan_chain_data_residual;uint32_t residual; -uint32_t i; +uint32_t i, ret;uint32_t index =0 ; -uint32_t io_scan_chain_len_in_bits, - const uint32_t *iocsr_scan_chain; - -switch (io_scan_chain_id) { -case 0 : - io_scan_chain_len_in_bits =CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH ; - iocsr_scan_chain = iocsr_scan_chain0_table; -break ; -case 1 : - io_scan_chain_len_in_bits =CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH ; - iocsr_scan_chain = iocsr_scan_chain1_table; -break ; -case 2 : - io_scan_chain_len_in_bits =CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH ; - iocsr_scan_chain = iocsr_scan_chain2_table; -break ; -case 3 : - io_scan_chain_len_in_bits =CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH ; - iocsr_scan_chain = iocsr_scan_chain3_table; -break ; - } +uint32_t io_scan_chain_len_in_bits; +const unsigned long *iocsr_scan_chain; + + ret =iocsr_get_config_table (io_scan_chain_id, &iocsr_scan_chain, + &io_scan_chain_len_in_bits); +if (ret) +return 1 ;/* * De-assert reinit if the IO scan chain is intended for HIO. In
board/altera/socfpga/Makefile +1 -1
@@ -7,4 +7,4 @@ # obj-y := socfpga.o wrap_pll_config.o -obj-$(CONFIG_SPL_BUILD) += qts/ +obj-$(CONFIG_SPL_BUILD) += qts/ wrap_iocsr_config.o
board/altera/socfpga/qts/Makefile +1 -1
@@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += pinmux_config.o iocsr_config.o +obj-y += pinmux_config.o
board/altera/socfpga/wrap_iocsr_config.c new file +41 -0
41 lines not on this page · raw message
include/configs/socfpga_arria5.h +0 -1
@@ -8,7 +8,6 @@#include <asm/arch/socfpga_base_addrs.h> #include "../../board/altera/socfpga/qts/pinmux_config.h" -#include "../../board/altera/socfpga/qts/iocsr_config.h" /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH
include/configs/socfpga_cyclone5.h +0 -1
@@ -8,7 +8,6 @@#include <asm/arch/socfpga_base_addrs.h> #include "../../board/altera/socfpga/qts/pinmux_config.h" -#include "../../board/altera/socfpga/qts/iocsr_config.h" /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH
Signature · 1 line
2.1.4
PATCH 20/172 arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio()
In reply to Marek VasutRework sysmgr_enable_warmrstcfgio() into sysmgr_config_warmrstcfgio(), which allows both enabling and disabling the warm reset config I/O functionality.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/include/mach/system_manager.h | 2 +- arch/arm/mach-socfpga/spl.c | 2 +- arch/arm/mach-socfpga/system_manager.c | 10 +++++++--- 3 files changed, 9 insertions(+), 5 deletions(-)
arch/arm/mach-socfpga/include/mach/system_manager.h +1 -1
@@ -10,7 +10,7 @@#ifndef __ASSEMBLY__void sysmgr_pinmux_init (void ); -void sysmgr_enable_warmrstcfgio (void ); +void sysmgr_config_warmrstcfgio (int enable);/* declaration for handoff table type */ extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM ];
arch/arm/mach-socfpga/spl.c +1 -1
@@ -78,7 +78,7 @@ void spl_board_init(void)cm_basic_init (cm_default_cfg);/* Enable bootrom to configure IOs. */ -sysmgr_enable_warmrstcfgio (); +sysmgr_config_warmrstcfgio (1 );/* configure the IOCSR / IO buffer settings */ if (scan_mgr_configure_iocsr ())
arch/arm/mach-socfpga/system_manager.c +7 -3
@@ -70,8 +70,12 @@ void sysmgr_pinmux_init(void)/* * This bit allows the bootrom to configure the IOs after a warm reset. */ -void sysmgr_enable_warmrstcfgio (void ) +void sysmgr_config_warmrstcfgio (int enable) { -setbits_le32 (&sysmgr_regs->romcodegrp_ctrl, -SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO ); +if (enable) +setbits_le32 (&sysmgr_regs->romcodegrp_ctrl, +SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO ); +else +clrbits_le32 (&sysmgr_regs->romcodegrp_ctrl, +SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO ); }
Signature · 1 line
2.1.4
PATCH 21/172 arm: socfpga: system: Clean up pinmux_config.c
In reply to Marek VasutImplement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux table and it's size from the QTS-generated pinmux_config.c. The target here is again to get rid of poluting global namespace by including the pinmux_config.h into it.
Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros, which are explicitly useless to us in U-Boot. Instead, U-Boot does use DT to detect exactly these configuration options. This patch makes sure that while this QTS-generated file can stay in the tree, these obscure macros do not ooze into the namespace anymore.
Signed-off-by Marek Vasut <[email protected]>
--- .../arm/mach-socfpga/include/mach/system_manager.h | 5 ++-- arch/arm/mach-socfpga/system_manager.c | 6 +++- board/altera/socfpga/Makefile | 2 +- board/altera/socfpga/qts/Makefile | 7 ----- board/altera/socfpga/wrap_pinmux_config.c | 35 ++++++++++++++++++++++ include/configs/socfpga_arria5.h | 1 - include/configs/socfpga_cyclone5.h | 1 - 7 files changed, 43 insertions(+), 14 deletions(-) delete mode 100644 board/altera/socfpga/qts/Makefile create mode 100644 board/altera/socfpga/wrap_pinmux_config.c
arch/arm/mach-socfpga/include/mach/system_manager.h +2 -3
@@ -12,9 +12,8 @@void sysmgr_pinmux_init (void );void sysmgr_config_warmrstcfgio (int enable); -/* declaration for handoff table type */ -extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM ]; - +void sysmgr_get_pinmux_table (const unsigned long **table, +unsigned int *table_len);#endif struct socfpga_system_manager {
arch/arm/mach-socfpga/system_manager.c +5 -1
@@ -57,9 +57,13 @@ static void populate_sysmgr_fpgaintf_module(void)void sysmgr_pinmux_init (void ) {uint32_t regs = (uint32_t )&sysmgr_regs->emacio[0 ]; +const unsigned long *sys_mgr_init_table; +unsigned int len;int i; -for (i =0 ; i <ARRAY_SIZE (sys_mgr_init_table); i++) { +sysmgr_get_pinmux_table (&sys_mgr_init_table, &len); + +for (i =0 ; i < len; i++) {writel (sys_mgr_init_table[i], regs); regs +=sizeof (regs); }
board/altera/socfpga/Makefile +1 -1
@@ -7,4 +7,4 @@ # obj-y := socfpga.o wrap_pll_config.o -obj-$(CONFIG_SPL_BUILD) += qts/ wrap_iocsr_config.o +obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o
board/altera/socfpga/qts/Makefile deleted +0 -7
@@ -1,7 +0,0 @@ -# -# (C) Copyright 2015 Marek Vasut <[email protected]> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += pinmux_config.o
board/altera/socfpga/wrap_pinmux_config.c new file +35 -0
@@ -0,0 +1,35 @@ +/* +* Copyright (C) 2015 Marek Vasut <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <errno.h> +/* +* Yes, dear reader, we're including a C file here, this is no mistake. +* But this time around, we do even more perverse hacking here to be +* compatible with QTS headers and obtain reasonably nice results too. +* +* First, we define _PRELOADER_PINMUX_CONFIG_H_, which will neutralise +* the pinmux_config.h inclusion in pinmux_config.c . Since we are +* probing everything from DT, we do NOT want those macros from the +* pinmux_config.h to ooze into our build system, anywhere, ever. So +* we nip it at the bud. +* +* Next, pinmux_config.c needs CONFIG_HPS_PINMUX_NUM and uses it to +* specify sized array explicitly. Instead, we want to use ARRAY_SIZE +* to figure out the size of the array, so define this macro as an +* empty one, so that the preprocessor optimizes things such that the +* arrays are not sized by default. +*/ +#define _PRELOADER_PINMUX_CONFIG_H_ +#define CONFIG_HPS_PINMUX_NUM +#include "qts/pinmux_config.c" + +void sysmgr_get_pinmux_table (const unsigned long **table, +unsigned int *table_len) +{ + *table = sys_mgr_init_table; + *table_len =ARRAY_SIZE (sys_mgr_init_table); +}
include/configs/socfpga_arria5.h +0 -1
@@ -7,7 +7,6 @@#define __CONFIG_SOCFPGA_ARRIA5_H__#include <asm/arch/socfpga_base_addrs.h> -#include "../../board/altera/socfpga/qts/pinmux_config.h" /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH
include/configs/socfpga_cyclone5.h +0 -1
@@ -7,7 +7,6 @@#define __CONFIG_SOCFPGA_CYCLONE5_H__#include <asm/arch/socfpga_base_addrs.h> -#include "../../board/altera/socfpga/qts/pinmux_config.h" /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH
Signature · 1 line
2.1.4
PATCH 22/172 arm: socfpga: spl: Toggle warm reset config I/O bit
In reply to Marek VasutSynchronise the SPL behavior with the original Altera code and toggle the Warm Reset Config I/O bit accordingly.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/spl.c | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm/mach-socfpga/spl.c +5 -0
@@ -84,8 +84,13 @@ void spl_board_init(void)if (scan_mgr_configure_iocsr ())hang (); +sysmgr_config_warmrstcfgio (0 ); +/* configure the pin muxing through system manager */ +sysmgr_config_warmrstcfgio (1 );sysmgr_pinmux_init (); +sysmgr_config_warmrstcfgio (0 ); +#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ /* de-assert reset for peripherals and bridges based on handoff */
Signature · 1 line
2.1.4
PATCH 23/172 arm: socfpga: spl: Configure SCU and NIC-301 early
In reply to Marek VasutConfigure the ARM SCU and NIC301 very early. The ARM SCU SNSAC register must be configured, so we can access all peripherals. The NIC-301 must be configured so that the BootROM is not mapped into the SDRAM address space.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/spl.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
arch/arm/mach-socfpga/spl.c +22 -0
@@ -17,11 +17,27 @@#include <asm/arch/clock_manager.h> #include <asm/arch/scan_manager.h> #include <asm/arch/sdram.h> +#include <asm/arch/scu.h> +#include <asm/arch/nic301.h> DECLARE_GLOBAL_DATA_PTR ;static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE ; +static struct scu_registers *scu_regs = + (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS ; +static struct nic301_registers *nic301_regs = + (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS ; + +static void socfpga_nic301_slave_ns (void ) +{ +writel (0x1 , &nic301_regs->lwhps2fpgaregs); +writel (0x1 , &nic301_regs->hps2fpgaregs); +writel (0x1 , &nic301_regs->acp); +writel (0x1 , &nic301_regs->rom); +writel (0x1 , &nic301_regs->ocram); +writel (0x1 , &nic301_regs->sdrdata); +}void board_init_f (ulong dummy) {
@@ -42,7 +58,13 @@ void board_init_f(ulong dummy)memset (__bss_start,0 , __bss_end - __bss_start); +socfpga_nic301_slave_ns (); + +/* Configure ARM MPU SNSAC register. */ +setbits_le32 (&scu_regs->sacr,0xfff ); +/* Remap SDRAM to 0x0 */ +writel (0x1 , &nic301_regs->remap);/* remap.mpuzero */ writel (0x1 , &pl310->pl310_addr_filter_start);board_init_r (NULL ,0 );
Signature · 1 line
2.1.4
PATCH 24/172 arm: socfpga: spl: Add missing reset logic
In reply to Marek VasutMake sure that all the peripherals are correctly reset and then brought out of reset in the SPL. Not going through proper reset cycle might leave the IP blocks in inconsistent state.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/spl.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
arch/arm/mach-socfpga/spl.c +9 -1
@@ -89,6 +89,11 @@ void spl_board_init(void)/* freeze all IO banks */ sys_mgr_frzctrl_freeze_req (); +/* Put everything into reset but L4WD0. */ +socfpga_per_reset_all (); +/* Put FPGA bridges into reset too. */ +socfpga_bridges_reset (1 ); +socfpga_per_reset (SOCFPGA_RESET (SDR ),0 );socfpga_per_reset (SOCFPGA_RESET (UART0 ),0 );socfpga_per_reset (SOCFPGA_RESET (OSC1TIMER0 ),0 );
@@ -115,8 +120,9 @@ void spl_board_init(void)#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ -/* de-assert reset for peripherals and bridges based on handoff */ +/* De-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff (); +socfpga_bridges_reset (0 );debug ("Unfreezing/Thaw all I/O banks\n" );/* unfreeze / thaw all IO banks */
@@ -145,4 +151,6 @@ void spl_board_init(void)puts ("SDRAM size check failed!\n" );hang (); } + +socfpga_bridges_reset (1 ); }
Signature · 1 line
2.1.4
PATCH 25/172 arm: socfpga: spl: Merge spl_board_init() into board_init_f()
In reply to Marek VasutThe code in spl_board_init() should have been in board_init_f() from the beginning, since it is code which configures system and then starts DRAM. Thus, it cannot be in spl_board_init(), which is called from board_init_r() , which already expects a working DRAM.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/spl.c | 29 ++++++++++++----------------- include/configs/socfpga_common.h | 1 - 2 files changed, 12 insertions(+), 18 deletions(-)
arch/arm/mach-socfpga/spl.c +12 -17
@@ -29,6 +29,11 @@ static struct scu_registers *scu_regs =static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS ; +u32 spl_boot_device (void ) +{ +return BOOT_DEVICE_RAM ; +} +static void socfpga_nic301_slave_ns (void ) {writel (0x1 , &nic301_regs->lwhps2fpgaregs);
@@ -41,9 +46,14 @@ static void socfpga_nic301_slave_ns(void)void board_init_f (ulong dummy) { +#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET +const struct cm_config *cm_default_cfg =cm_get_default_config (); +#endif struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ; +unsigned long sdram_size;unsigned long reg; +/* * First C code to run. Clear fake OCRAM ECC first as SBE * and DBE might triggered during power on
@@ -67,24 +77,7 @@ void board_init_f(ulong dummy)writel (0x1 , &nic301_regs->remap);/* remap.mpuzero */ writel (0x1 , &pl310->pl310_addr_filter_start); -board_init_r (NULL ,0 ); -} - -u32 spl_boot_device (void ) -{ -return BOOT_DEVICE_RAM ; -} - -/* -* Board initialization after bss clearance -*/ -void spl_board_init (void ) -{ -unsigned long sdram_size;#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET -const struct cm_config *cm_default_cfg =cm_get_default_config (); -#endif -debug ("Freezing all I/O banks\n" );/* freeze all IO banks */ sys_mgr_frzctrl_freeze_req ();
@@ -153,4 +146,6 @@ void spl_board_init(void) }socfpga_bridges_reset (1 ); + +board_init_r (NULL ,0 ); }
include/configs/socfpga_common.h +0 -1
@@ -293,7 +293,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);* 0xFFFF_FF00 ...... End of SRAM */ #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_RAM_DEVICE #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR
Signature · 1 line
2.1.4
PATCH 26/172 arm: socfpga: spl: Remove custom linker script
In reply to Marek VasutRemove the custom SPL linker script, use the generic one instead. The custom script doesn't bring in anything new and is only burden to maintain.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/u-boot-spl.lds | 45 ------------------------------------ include/configs/socfpga_common.h | 3 --- 2 files changed, 48 deletions(-) delete mode 100644 arch/arm/mach-socfpga/u-boot-spl.lds
arch/arm/mach-socfpga/u-boot-spl.lds deleted +0 -45
@@ -1,45 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) } - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.vectors) - arch/arm/cpu/armv7/start.o (.text*) - *(.text*) - } >.sdram - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram - - . = ALIGN(4); - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram - - . = ALIGN(4); - __image_copy_end = .; - - .end : - { - *(.__end) - } - - .bss : { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } >.sdram -}
include/configs/socfpga_common.h +0 -3
@@ -302,9 +302,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);#define CHUNKSZ_CRC32 (1 * 1024)/* FIXME: ewww */ #define CONFIG_CRC32_VERIFY -/* Linker script for SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-socfpga/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_WATCHDOG_SUPPORT
Signature · 1 line
2.1.4
PATCH 27/172 arm: socfpga: spl: Add support for booting from SD/MMC
In reply to Marek VasutAdd code and configuration options to support booting from RAW SD/MMC card as well as for ext4/vfat filesystems. Enable support for booting from SD/MMC card, but don't enable the filesystem support just yet to retain compatibility with old SoCFPGA card format.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/spl.c | 17 +++++++++++++++++ configs/socfpga_arria5_defconfig | 2 ++ configs/socfpga_cyclone5_defconfig | 2 ++ configs/socfpga_socrates_defconfig | 3 ++- include/configs/socfpga_common.h | 14 ++++++++++++++ 5 files changed, 37 insertions(+), 1 deletion(-)
arch/arm/mach-socfpga/spl.c +17 -0
@@ -31,8 +31,25 @@ static struct nic301_registers *nic301_regs =u32 spl_boot_device (void ) { +#ifdef CONFIG_SPL_MMC_SUPPORT +socfpga_per_reset (SOCFPGA_RESET (SDMMC ),0 ); +socfpga_per_reset (SOCFPGA_RESET (DMA ),0 ); +return BOOT_DEVICE_MMC1 ; +#else return BOOT_DEVICE_RAM ; +#endif +} + +#ifdef CONFIG_SPL_MMC_SUPPORT +u32 spl_boot_mode (void ) +{ +#if defined(CONFIG_SPL_FAT_SUPPORT ) || defined(CONFIG_SPL_EXT_SUPPORT ) +return MMCSD_MODE_FS ; +#else +return MMCSD_MODE_RAW ; +#endif } +#endif static void socfpga_nic301_slave_ns (void ) {
configs/socfpga_arria5_defconfig +2 -0
@@ -7,3 +7,5 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set CONFIG_OF_CONTROL=y CONFIG_SPI_FLASH=y +CONFIG_SPL_DM=y +CONFIG_SPL_MMC_SUPPORT=y
configs/socfpga_cyclone5_defconfig +2 -0
@@ -9,3 +9,5 @@ CONFIG_OF_CONTROL=y CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SPL_DM=y +CONFIG_SPL_MMC_SUPPORT=y
configs/socfpga_socrates_defconfig +2 -1
@@ -6,7 +6,8 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_OF_CONTROL=y -CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SPL_DM=y +CONFIG_SPL_MMC_SUPPORT=y
include/configs/socfpga_common.h +14 -0
@@ -306,6 +306,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT + +/* SPL SDMMC boot support */ +#ifdef CONFIG_SPL_MMC_SUPPORT +#if defined(CONFIG_SPL_FAT_SUPPORT ) || defined(CONFIG_SPL_EXT_SUPPORT ) +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +#define CONFIG_SPL_LIBDISK_SUPPORT +#else +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00/* offset 2560 sect (1M+256k) */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800/* 400 KB */ +#endif +#endif /* * Stack setup
Signature · 1 line
2.1.4
PATCH 28/172 arm: socfpga: spl: Add support for booting from QSPI
In reply to Marek VasutAdd code and configuration options to support booting from QSPI NOR. Enable support for booting from QSPI NOR.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/spl.c | 5 ++++- configs/socfpga_arria5_defconfig | 4 ++++ configs/socfpga_cyclone5_defconfig | 4 ++++ configs/socfpga_socrates_defconfig | 4 ++++ include/configs/socfpga_common.h | 9 +++++++++ 5 files changed, 25 insertions(+), 1 deletion(-)
arch/arm/mach-socfpga/spl.c +4 -1
@@ -31,7 +31,10 @@ static struct nic301_registers *nic301_regs =u32 spl_boot_device (void ) { -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_SPI_SUPPORT +socfpga_per_reset (SOCFPGA_RESET (QSPI ),0 ); +return BOOT_DEVICE_SPI ; +#elif CONFIG_SPL_MMC_SUPPORT socfpga_per_reset (SOCFPGA_RESET (SDMMC ),0 );socfpga_per_reset (SOCFPGA_RESET (DMA ),0 );return BOOT_DEVICE_MMC1 ;
configs/socfpga_arria5_defconfig +4 -0
@@ -9,3 +9,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPI_FLASH=y CONFIG_SPL_DM=y CONFIG_SPL_MMC_SUPPORT=y +CONFIG_DM_SEQ_ALIAS=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPL_SPI_SUPPORT=y
configs/socfpga_cyclone5_defconfig +4 -0
@@ -11,3 +11,7 @@ CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y CONFIG_SPL_DM=y CONFIG_SPL_MMC_SUPPORT=y +CONFIG_DM_SEQ_ALIAS=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPL_SPI_SUPPORT=y
configs/socfpga_socrates_defconfig +4 -0
@@ -11,3 +11,7 @@ CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y CONFIG_SPL_DM=y CONFIG_SPL_MMC_SUPPORT=y +CONFIG_DM_SEQ_ALIAS=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPL_SPI_SUPPORT=y
include/configs/socfpga_common.h +9 -0
@@ -307,6 +307,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);#define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT
@@ -321,6 +322,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);#endif #endif +/* SPL QSPI boot support */ +#ifdef CONFIG_SPL_SPI_SUPPORT +#define CONFIG_DM_SEQ_ALIAS 1 +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 +#endif +/* * Stack setup */
Signature · 1 line
2.1.4
PATCH 29/172 arm: socfpga: spl: Add support for selecting boot device from BSEL
In reply to Marek VasutRework spl_boot_device() such that it reads the BSEL settings from system manager and decides from where to load U-Boot based on this information.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/spl.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-)
arch/arm/mach-socfpga/spl.c +23 -12
@@ -28,19 +28,32 @@ static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS ;static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS ; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ;u32 spl_boot_device (void ) { -#ifdef CONFIG_SPL_SPI_SUPPORT -socfpga_per_reset (SOCFPGA_RESET (QSPI ),0 ); -return BOOT_DEVICE_SPI ; -#elif CONFIG_SPL_MMC_SUPPORT -socfpga_per_reset (SOCFPGA_RESET (SDMMC ),0 ); -socfpga_per_reset (SOCFPGA_RESET (DMA ),0 ); -return BOOT_DEVICE_MMC1 ; -#else -return BOOT_DEVICE_RAM ; -#endif +const u32 bsel =readl (&sysmgr_regs->bootinfo); + +switch (bsel &0x7 ) { +case 0x1 :/* FPGA (HPS2FPGA Bridge) */ +return BOOT_DEVICE_RAM ; +case 0x2 :/* NAND Flash (1.8V) */ +case 0x3 :/* NAND Flash (3.0V) */ +return BOOT_DEVICE_NAND ; +case 0x4 :/* SD/MMC External Transceiver (1.8V) */ +case 0x5 :/* SD/MMC Internal Transceiver (3.0V) */ +socfpga_per_reset (SOCFPGA_RESET (SDMMC ),0 ); +socfpga_per_reset (SOCFPGA_RESET (DMA ),0 ); +return BOOT_DEVICE_MMC1 ; +case 0x6 :/* QSPI Flash (1.8V) */ +case 0x7 :/* QSPI Flash (3.0V) */ +socfpga_per_reset (SOCFPGA_RESET (QSPI ),0 ); +return BOOT_DEVICE_SPI ; +default : +printf ("Invalid boot device (bsel=%08x)!\n" , bsel); +hang (); + } }#ifdef CONFIG_SPL_MMC_SUPPORT
@@ -69,8 +82,6 @@ void board_init_f(ulong dummy)#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET const struct cm_config *cm_default_cfg =cm_get_default_config ();#endif -struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ;unsigned long sdram_size;unsigned long reg;
Signature · 1 line
2.1.4
PATCH 30/172 arm: socfpga: misc: Fix warm reset
In reply to Marek VasutWrite necessary magic value into the Warm Boot from ON-Chip RAM group Enable register to enable Warm reset support. Instead of doing this in the reset_cpu() function, we do it in arch early init to avoid breaking old kernel code which expects this magic value to be already written into this register.
This magic is originally excavated from common/spl/spl.c in the u-boot port from altera, where this value was written just before the SPL jumped to actual U-Boot in the RAM.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/misc.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm/mach-socfpga/misc.c +10 -0
@@ -193,6 +193,16 @@ static uint32_t iswgrp_handoff[8];int arch_early_init_r (void ) {int i; + +/* +* Write magic value into magic register to unlock support for +* issuing warm reset. The ancient kernel code expects this +* value to be written into the register by the bootloader, so +* to support that old code, we write it here instead of in the +* reset_cpu() function just before reseting the CPU. +*/ +writel (0xae9efebc , &sysmgr_regs->romcodegrp_warmramgrp_enable); +for (i =0 ; i <8 ; i++)/* Cache initial SW setting regs */ iswgrp_handoff[i] =readl (&sysmgr_regs->iswgrp_handoff[i]);
Signature · 1 line
2.1.4
PATCH 31/172 arm: socfpga: misc: Add support for printing boot mode
In reply to Marek VasutAdd support for printing from which device the SoCFPGA board booted. This decodes the BSEL settings and prints it in human readable form.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/misc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
arch/arm/mach-socfpga/misc.c +13 -0
@@ -100,12 +100,25 @@ int cpu_mmc_init(bd_t *bis)#endif #if defined(CONFIG_DISPLAY_CPUINFO ) +const char *const bsel_str[] = { +"Reserved" , +"FPGA (HPS2FPGA Bridge)" , +"NAND Flash (1.8V)" , +"NAND Flash (3.0V)" , +"SD/MMC External Transceiver (1.8V)" , +"SD/MMC Internal Transceiver (3.0V)" , +"QSPI Flash (1.8V)" , +"QSPI Flash (3.0V)" , +}; +/* * Print CPU information */ int print_cpuinfo (void ) { +const u32 bsel =readl (&sysmgr_regs->bootinfo) &0x7 ;puts ("CPU: Altera SoCFPGA Platform\n" ); +printf ("BOOT: %s\n" , bsel_str[bsel]);return 0 ; }#endif
Signature · 1 line
2.1.4
PATCH 32/172 arm: socfpga: misc: Export bootmode into environment variable
In reply to Marek Vasutsetenv an environment variable called "bootmode" , which contains the board boot mode. This can be in turn used in scripts to determine from where to load kernel and such.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/misc.c | 34 +++++++++++++++++++++++----------- include/configs/socfpga_common.h | 1 + 2 files changed, 24 insertions(+), 11 deletions(-)
arch/arm/mach-socfpga/misc.c +23 -11
@@ -99,26 +99,38 @@ int cpu_mmc_init(bd_t *bis) }#endif -#if defined(CONFIG_DISPLAY_CPUINFO ) -const char *const bsel_str[] = { -"Reserved" , -"FPGA (HPS2FPGA Bridge)" , -"NAND Flash (1.8V)" , -"NAND Flash (3.0V)" , -"SD/MMC External Transceiver (1.8V)" , -"SD/MMC Internal Transceiver (3.0V)" , -"QSPI Flash (1.8V)" , -"QSPI Flash (3.0V)" , +struct { +const char *mode; +const char *name; +} bsel_str[] = { + {"rsvd" ,"Reserved" , }, + {"fpga" ,"FPGA (HPS2FPGA Bridge)" , }, + {"nand" ,"NAND Flash (1.8V)" , }, + {"nand" ,"NAND Flash (3.0V)" , }, + {"sd" ,"SD/MMC External Transceiver (1.8V)" , }, + {"sd" ,"SD/MMC Internal Transceiver (3.0V)" , }, + {"qspi" ,"QSPI Flash (1.8V)" , }, + {"qspi" ,"QSPI Flash (3.0V)" , }, };/* * Print CPU information */ +#if defined(CONFIG_DISPLAY_CPUINFO )int print_cpuinfo (void ) {const u32 bsel =readl (&sysmgr_regs->bootinfo) &0x7 ;puts ("CPU: Altera SoCFPGA Platform\n" ); -printf ("BOOT: %s\n" , bsel_str[bsel]); +printf ("BOOT: %s\n" , bsel_str[bsel].name); +return 0 ; +} +#endif + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init (void ) +{ +const u32 bsel =readl (&sysmgr_regs->bootinfo) &0x7 ; +setenv ("bootmode" , bsel_str[bsel].mode);return 0 ; }#endif
include/configs/socfpga_common.h +1 -0
@@ -18,6 +18,7 @@*/ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_ARCH_MISC_INIT #define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_SYS_NO_FLASH #define CONFIG_CLOCKS
Signature · 1 line
2.1.4
PATCH 33/172 arm: socfpga: misc: Probe ethernet GMAC from OF
In reply to Marek VasutThe GMAC can now be probed from OF, so enable DM ethernet and remove the old ad-hoc designware_initialize() invocation.
Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Joe Hershberger <[email protected]>
--- arch/arm/mach-socfpga/misc.c | 4 +--- configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + include/configs/socfpga_arria5.h | 1 - include/configs/socfpga_cyclone5.h | 1 - 5 files changed, 3 insertions(+), 5 deletions(-)
arch/arm/mach-socfpga/misc.c +1 -3
@@ -82,9 +82,7 @@ int cpu_eth_init(bd_t *bis)/* Release the EMAC controller from reset */ socfpga_per_reset (reset,0 ); -/* initialize and register the emac */ -return designware_initialize (CONFIG_EMAC_BASE , - CONFIG_PHY_INTERFACE_MODE); + return 0; }#endif
configs/socfpga_cyclone5_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set CONFIG_OF_CONTROL=y CONFIG_SPI_FLASH=y +CONFIG_DM_ETH=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y CONFIG_SPL_DM=y
configs/socfpga_socrates_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set CONFIG_OF_CONTROL=y CONFIG_SPI_FLASH=y +CONFIG_DM_ETH=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y CONFIG_SPL_DM=y
include/configs/socfpga_arria5.h +0 -1
@@ -49,7 +49,6 @@/* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET )#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS -#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII/* PHY */ #define CONFIG_PHY_MICREL
include/configs/socfpga_cyclone5.h +0 -1
@@ -49,7 +49,6 @@/* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET )#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS -#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII/* PHY */ #define CONFIG_PHY_MICREL
Signature · 1 line
2.1.4
PATCH 34/172 arm: socfpga: misc: Reset ethernet from OF
In reply to Marek VasutReset the GMAC ethernets based on the "resets" OF node instead of ad-hoc hardcoded values in the U-Boot code. Since we don't have a proper reset framework in place yet, we have to do this slightly ad-hoc parsing of the OF tree instead.
Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Joe Hershberger <[email protected]>
--- arch/arm/mach-socfpga/misc.c | 68 +++++++++++++++++++++++++++----------- include/configs/socfpga_arria5.h | 1 - include/configs/socfpga_cyclone5.h | 1 - include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 5 files changed, 51 insertions(+), 21 deletions(-)
arch/arm/mach-socfpga/misc.c +49 -19
@@ -6,6 +6,8 @@#include <common.h> #include <asm/io.h> +#include <fdtdec.h> +#include <libfdt.h> #include <altera.h> #include <miiphy.h> #include <netdev.h>
@@ -17,6 +19,8 @@#include <asm/arch/scu.h> #include <asm/pl310.h> +#include <dt-bindings/reset/altr,rst-mgr.h> +DECLARE_GLOBAL_DATA_PTR ; static struct pl310_regs *const pl310 =
@@ -50,26 +54,20 @@ void enable_caches(void)* DesignWare Ethernet initialization */ #ifdef CONFIG_ETH_DESIGNWARE -int cpu_eth_init (bd_t *bis) +static void dwmac_deassert_reset (const unsigned int of_reset_id) { -#if CONFIG_EMAC_BASE ==SOCFPGA_EMAC0_ADDRESS -const int physhift =SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB ; -const u32 reset =SOCFPGA_RESET (EMAC0 ); -#elif CONFIG_EMAC_BASE ==SOCFPGA_EMAC1_ADDRESS -const int physhift =SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB ; -const u32 reset =SOCFPGA_RESET (EMAC1 ); -#else -#error "Incorrect CONFIG_EMAC_BASE value!" -#endif - -/* Initialize EMAC. This needs to be done at least once per boot. */ - -/* -* Putting the EMAC controller to reset when configuring the PHY -* interface select at System Manager -*/ -socfpga_per_reset (SOCFPGA_RESET (EMAC0 ),1 ); -socfpga_per_reset (SOCFPGA_RESET (EMAC1 ),1 ); +u32 physhift, reset; + +if (of_reset_id ==EMAC0_RESET ) { + physhift =SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB ; + reset =SOCFPGA_RESET (EMAC0 ); + }else if (of_reset_id ==EMAC1_RESET ) { + physhift =SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB ; + reset =SOCFPGA_RESET (EMAC1 ); + }else { +printf ("GMAC: Invalid reset ID (%i)!\n" , of_reset_id); +return ; + }/* Clearing emac0 PHY interface select to 0 */ clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
@@ -81,6 +79,38 @@ int cpu_eth_init(bd_t *bis)/* Release the EMAC controller from reset */ socfpga_per_reset (reset,0 ); +} + +int cpu_eth_init (bd_t *bis) +{ +const void *fdt = gd->fdt_blob; +struct fdtdec_phandle_args args; +int nodes[2 ];/* Max. two GMACs */ +int ret, count; +int i, node; + +/* Put both GMACs into RESET state. */ +socfpga_per_reset (SOCFPGA_RESET (EMAC0 ),1 ); +socfpga_per_reset (SOCFPGA_RESET (EMAC1 ),1 ); + + count =fdtdec_find_aliases_for_id (fdt,"ethernet" , +COMPAT_ALTERA_SOCFPGA_DWMAC , + nodes,ARRAY_SIZE (nodes)); +for (i =0 ; i < count; i++) { + node = nodes[i]; +if (node <=0 ) +continue ; + + ret =fdtdec_parse_phandle_with_args (fdt, node,"resets" , +"#reset-cells" ,1 ,0 , + &args); +if (ret || (args.args_count !=1 )) { +debug ("GMAC%i: Failed to parse DT 'resets'!\n" , i); +continue ; + } + +dwmac_deassert_reset (args.args[0 ]); + }return 0 ; }
include/configs/socfpga_arria5.h +0 -1
@@ -48,7 +48,6 @@/* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET ) -#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS/* PHY */ #define CONFIG_PHY_MICREL
include/configs/socfpga_cyclone5.h +0 -1
@@ -48,7 +48,6 @@/* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET ) -#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS/* PHY */ #define CONFIG_PHY_MICREL
include/fdtdec.h +1 -0
@@ -184,6 +184,7 @@ enum fdt_compat_id {COMPAT_INTEL_PCH ,/* Intel PCH */ COMPAT_INTEL_IRQ_ROUTER ,/* Intel Interrupt Router */ COMPAT_ALTERA_SOCFPGA_DWMMC ,/* SoCFPGA DWMMC controller */ +COMPAT_ALTERA_SOCFPGA_DWMAC ,/* SoCFPGA Ethernet controller */ COMPAT_COUNT, };
lib/fdtdec.c +1 -0
@@ -77,6 +77,7 @@ static const char * const compat_names[COMPAT_COUNT] = {COMPAT (COMPAT_INTEL_PCH ,"intel,bd82x6x" ),COMPAT (COMPAT_INTEL_IRQ_ROUTER ,"intel,irq-router" ),COMPAT (ALTERA_SOCFPGA_DWMMC ,"altr,socfpga-dw-mshc" ), + COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"), };const char *fdtdec_get_compatible (enum fdt_compat_id id)
Signature · 1 line
2.1.4
PATCH 35/172 arm: socfpga: config: Move SPL GD and malloc to RAM
In reply to Marek VasutNow that the SPL structure is organised such that it matches the U-Boot's SPL design, it is possible to use the option of relocating GD to RAM. And since we have GD in RAM, move malloc area to RAM as well. We point the malloc base pointer 1 MiB past U-Boot's load address. We use simple malloc for SPL because it is 3kiB smaller in terms of code size than regular malloc which was used thus far.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/spl.c | 3 +++ configs/socfpga_arria5_defconfig | 3 +++ configs/socfpga_cyclone5_defconfig | 3 +++ configs/socfpga_socrates_defconfig | 3 +++ include/configs/socfpga_common.h | 14 ++++++++------ 5 files changed, 20 insertions(+), 6 deletions(-)
arch/arm/mach-socfpga/spl.c +3 -0
@@ -178,5 +178,8 @@ void board_init_f(ulong dummy)socfpga_bridges_reset (1 ); +/* Configure simple malloc base pointer into RAM. */ + gd->malloc_base =CONFIG_SYS_TEXT_BASE + (1024 *1024 ); +board_init_r (NULL ,0 ); }
configs/socfpga_arria5_defconfig +3 -0
@@ -13,3 +13,6 @@ CONFIG_DM_SEQ_ALIAS=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x00800000 +CONFIG_SYS_MALLOC_F_LEN=0x2000
configs/socfpga_cyclone5_defconfig +3 -0
@@ -16,3 +16,6 @@ CONFIG_DM_SEQ_ALIAS=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x00800000 +CONFIG_SYS_MALLOC_F_LEN=0x2000
configs/socfpga_socrates_defconfig +3 -0
@@ -16,3 +16,6 @@ CONFIG_DM_SEQ_ALIAS=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x00800000 +CONFIG_SYS_MALLOC_F_LEN=0x2000
include/configs/socfpga_common.h +8 -6
@@ -39,10 +39,11 @@#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
@@ -296,9 +297,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_RAM_DEVICE #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024)#define CONFIG_SPL_MAX_SIZE (64 * 1024) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif #define CHUNKSZ_CRC32 (1 * 1024)/* FIXME: ewww */ #define CONFIG_CRC32_VERIFY
Signature · 1 line
2.1.4
PATCH 36/172 arm: socfpga: config: Zap incorrect config options
In reply to Marek VasutThere is no need to disable support for partitions in the SPL, we can support partitions in SPL perfectly well. This is likely some remnant from old times, so just remove this configuration option.
Moreover, the CRC32 chunk size doesn't have to be adjusted anymore, since both the GD and malloc area are in RAM by the time this CRC check can be used and there's plenty of space. Zap this abomination as well.
Signed-off-by Marek Vasut <[email protected]>
--- include/configs/socfpga_common.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-)
include/configs/socfpga_common.h +2 -7
@@ -23,6 +23,8 @@#define CONFIG_SYS_NO_FLASH #define CONFIG_CLOCKS +#define CONFIG_CRC32_VERIFY +#define CONFIG_FIT #define CONFIG_OF_LIBFDT #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
@@ -302,9 +304,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);#define CONFIG_SYS_MALLOC_SIMPLE #endif -#define CHUNKSZ_CRC32 (1 * 1024)/* FIXME: ewww */ -#define CONFIG_CRC32_VERIFY -#define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_WATCHDOG_SUPPORT
@@ -338,8 +337,4 @@ unsigned int cm_get_qspi_controller_clk_hz(void);*/ #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_PARTITIONS -#endif -#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
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2.1.4
PATCH 37/172 arm: socfpga: config: Exclude CONFIG_SPI_FLASH_MTD from SPL build
In reply to Marek VasutWe do not need full MTD support in the SPL build, it only adds size and is not usable in any way. Exclude it.
Signed-off-by Marek Vasut <[email protected]>
--- include/configs/socfpga_common.h | 2 ++ 1 file changed, 2 insertions(+)
include/configs/socfpga_common.h +2 -0
@@ -203,7 +203,9 @@ unsigned int cm_get_l4_sp_clk_hz(void);/* Enable multiple SPI NOR flash manufacturers */ #define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ #define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_SPI_FLASH_MTD +#endif /* QSPI reference clock */ #ifndef __ASSEMBLY__unsigned int cm_get_qspi_controller_clk_hz (void );
Signature · 1 line
2.1.4
PATCH 38/172 arm: socfpga: config: Enable CONFIG_SPI_FLASH_BAR
In reply to Marek VasutThis is needed to access broken (read: Micron) SPI flashes which are larger than 16 MiB and don't correctly support 4-byte addressing.
Signed-off-by Marek Vasut <[email protected]>
--- include/configs/socfpga_common.h | 1 + 1 file changed, 1 insertion(+)
include/configs/socfpga_common.h +1 -0
@@ -213,6 +213,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);#endif #define CONFIG_CQSPI_DECODER 0#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_BAR #endif #ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */
Signature · 1 line
2.1.4
PATCH 39/172 arm: socfpga: config: Fix LOADADDR
In reply to Marek VasutSetting LOADADDR to 0x8000 is a bad idea, it is very likely that some kind of overlap will happen. Move the LOADADDR 0x01000000 (16MiB from start of RAM) to make sure no overlap happens when loading kernel for example.
Signed-off-by Marek Vasut <[email protected]>
--- include/configs/socfpga_arria5.h | 2 +- include/configs/socfpga_cyclone5.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
include/configs/socfpga_arria5.h +1 -1
@@ -43,7 +43,7 @@#else #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"#endif -#define CONFIG_LOADADDR 0x8000 +#define CONFIG_LOADADDR 0x01000000#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR/* Ethernet on SoC (EMAC) */
include/configs/socfpga_cyclone5.h +1 -1
@@ -43,7 +43,7 @@#else #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"#endif -#define CONFIG_LOADADDR 0x8000 +#define CONFIG_LOADADDR 0x01000000#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR/* Ethernet on SoC (EMAC) */
Signature · 1 line
2.1.4
PATCH 40/172 arm: socfpga: config: Make CONFIG_SPI_FLASH_MTD useful
In reply to Marek VasutEnable the mtdparts command and related options to make support for SPI NOR MTD useful in any way. With the mtdparts command in place, it is possible to use partition of the SPI NOR in U-Boot.
Signed-off-by Marek Vasut <[email protected]>
--- include/configs/socfpga_common.h | 4 ++++ 1 file changed, 4 insertions(+)
include/configs/socfpga_common.h +4 -0
@@ -205,6 +205,10 @@ unsigned int cm_get_l4_sp_clk_hz(void);#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */ #ifndef CONFIG_SPL_BUILD #define CONFIG_SPI_FLASH_MTD +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nor0=ff705000.spi"#endif /* QSPI reference clock */ #ifndef __ASSEMBLY__
Signature · 1 line
2.1.4
PATCH 41/172 Makefile: Add target for building bootable SPL image for SoCFPGA
In reply to Marek VasutAdd build target for generating boot partition images recognised by the SoCFPGA BootROM. The SoCFPGA BootROM expects four copies of the u-boot-spl-dtb.sfp at the beginning of boot partition. Those are u-boot-spl-dtb.bin augmented by a header with which the BootROM can work. The u-boot-dtb.img uImage is appended to this to produce a full boot partition image, the u-boot-with-spl-dtb.sfp . This is the name of the final target.
Signed-off-by Marek Vasut <[email protected]>
--- Makefile | 12 ++++++++++++ scripts/Makefile.spl | 10 ++++++++++ 2 files changed, 22 insertions(+)
Makefile +12 -0
@@ -1007,6 +1007,15 @@ u-boot-nand.gph: u-boot.bin FORCE $(call if_changed,mkimage) @dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@ +ifneq ($(CONFIG_ARCH_SOCFPGA),) +quiet_cmd_socboot = SOCBOOT $@ +cmd_socboot = cat spl/u-boot-spl-dtb.sfp spl/u-boot-spl-dtb.sfp \ + spl/u-boot-spl-dtb.sfp spl/u-boot-spl-dtb.sfp \ + u-boot-dtb.img > $@ || rm -f $@ +u-boot-with-spl-dtb.sfp: spl/u-boot-spl-dtb.sfp u-boot-dtb.img FORCE + $(call if_changed,socboot) +endif + # x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including # reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in # the middle.
@@ -1266,6 +1275,9 @@ spl/u-boot-spl: tools prepare $(if $(CONFIG_OF_SEPARATE),dts/dt.dtb) spl/sunxi-spl.bin: spl/u-boot-spl @: +spl/u-boot-spl-dtb.sfp: spl/u-boot-spl + @: + tpl/u-boot-tpl.bin: tools prepare $(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all
scripts/Makefile.spl +10 -0
@@ -163,6 +163,10 @@ ifdef CONFIG_SAMSUNG ALL-y += $(obj)/$(BOARD)-spl.bin endif +ifdef CONFIG_ARCH_SOCFPGA +ALL-y += $(obj)/$(SPL_BIN)-dtb.sfp +endif + ifdef CONFIG_SUNXI ALL-y += $(obj)/sunxi-spl.bin endif
@@ -231,6 +235,12 @@ ifneq ($(CONFIG_SPL_TEXT_BASE),) LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE) endif +ifdef CONFIG_ARCH_SOCFPGA +MKIMAGEFLAGS_$(SPL_BIN)-dtb.sfp = -T socfpgaimage +$(obj)/$(SPL_BIN)-dtb.sfp: $(obj)/$(SPL_BIN)-dtb.bin FORCE + $(call if_changed,mkimage) +endif + ifdef CONFIG_SUNXI quiet_cmd_mksunxiboot = MKSUNXI $@ cmd_mksunxiboot = $(objtree)/tools/mksunxiboot $< $@
Signature · 1 line
2.1.4
PATCH 42/172 ddr: altera: Minor indent fix in set_rank_and_odt_mask()
In reply to Marek VasutFix the position of the } else { statement to make it correctly indented.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/ddr/altera/sequencer.c +1 -1
@@ -260,7 +260,7 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode) odt_mask_0 =0x0 ; odt_mask_1 =0x3 & (1 << rank); } - }else { + }else {/* 4 Ranks * Read: * ----------+-----------------------+
Signature · 1 line
2.1.4
PATCH 43/172 ddr: altera: Clean up ugly casts in sdram_calibration_full()
In reply to Marek VasutUse the correct formating string in those debug_cond() invocations and zap those unnecessary ugly casts.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 50 ++++++++++++++++++------------------------ 1 file changed, 21 insertions(+), 29 deletions(-)
drivers/ddr/altera/sequencer.c +21 -29
@@ -3994,35 +3994,27 @@ int sdram_calibration_full(void)printf ("%s: Preparing to start memory calibration\n" , __FILE__);debug ("%s:%d\n" , __func__, __LINE__); -debug_cond (DLEVEL ==1 ,"DDR3 FULL_RATE ranks=%lu cs/dimm=%lu dq/dqs=%lu,%lu vg/dqs=%lu,%lu " , - (long unsigned int )RW_MGR_MEM_NUMBER_OF_RANKS , - (long unsigned int )RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM , - (long unsigned int )RW_MGR_MEM_DQ_PER_READ_DQS , - (long unsigned int )RW_MGR_MEM_DQ_PER_WRITE_DQS , - (long unsigned int )RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS , - (long unsigned int )RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS ); -debug_cond (DLEVEL ==1 ,"dqs=%lu,%lu dq=%lu dm=%lu ptap_delay=%lu dtap_delay=%lu " , - (long unsigned int )RW_MGR_MEM_IF_READ_DQS_WIDTH , - (long unsigned int )RW_MGR_MEM_IF_WRITE_DQS_WIDTH , - (long unsigned int )RW_MGR_MEM_DATA_WIDTH , - (long unsigned int )RW_MGR_MEM_DATA_MASK_WIDTH , - (long unsigned int )IO_DELAY_PER_OPA_TAP , - (long unsigned int )IO_DELAY_PER_DCHAIN_TAP ); -debug_cond (DLEVEL ==1 ,"dtap_dqsen_delay=%lu, dll=%lu" , - (long unsigned int )IO_DELAY_PER_DQS_EN_DCHAIN_TAP , - (long unsigned int )IO_DLL_CHAIN_LENGTH ); -debug_cond (DLEVEL ==1 ,"max values: en_p=%lu dqdqs_p=%lu en_d=%lu dqs_in_d=%lu " , - (long unsigned int )IO_DQS_EN_PHASE_MAX , - (long unsigned int )IO_DQDQS_OUT_PHASE_MAX , - (long unsigned int )IO_DQS_EN_DELAY_MAX , - (long unsigned int )IO_DQS_IN_DELAY_MAX ); -debug_cond (DLEVEL ==1 ,"io_in_d=%lu io_out1_d=%lu io_out2_d=%lu " , - (long unsigned int )IO_IO_IN_DELAY_MAX , - (long unsigned int )IO_IO_OUT1_DELAY_MAX , - (long unsigned int )IO_IO_OUT2_DELAY_MAX ); -debug_cond (DLEVEL ==1 ,"dqs_in_reserve=%lu dqs_out_reserve=%lu\n" , - (long unsigned int )IO_DQS_IN_RESERVE , - (long unsigned int )IO_DQS_OUT_RESERVE ); +debug_cond (DLEVEL ==1 , +"DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u " , +RW_MGR_MEM_NUMBER_OF_RANKS ,RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM , +RW_MGR_MEM_DQ_PER_READ_DQS ,RW_MGR_MEM_DQ_PER_WRITE_DQS , +RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS , +RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS ); +debug_cond (DLEVEL ==1 , +"dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u " , +RW_MGR_MEM_IF_READ_DQS_WIDTH ,RW_MGR_MEM_IF_WRITE_DQS_WIDTH , +RW_MGR_MEM_DATA_WIDTH ,RW_MGR_MEM_DATA_MASK_WIDTH , +IO_DELAY_PER_OPA_TAP ,IO_DELAY_PER_DCHAIN_TAP ); +debug_cond (DLEVEL ==1 ,"dtap_dqsen_delay=%u, dll=%u" , +IO_DELAY_PER_DQS_EN_DCHAIN_TAP ,IO_DLL_CHAIN_LENGTH ); +debug_cond (DLEVEL ==1 ,"max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u " , +IO_DQS_EN_PHASE_MAX ,IO_DQDQS_OUT_PHASE_MAX , +IO_DQS_EN_DELAY_MAX ,IO_DQS_IN_DELAY_MAX ); +debug_cond (DLEVEL ==1 ,"io_in_d=%u io_out1_d=%u io_out2_d=%u " , +IO_IO_IN_DELAY_MAX ,IO_IO_OUT1_DELAY_MAX , +IO_IO_OUT2_DELAY_MAX ); +debug_cond (DLEVEL ==1 ,"dqs_in_reserve=%u dqs_out_reserve=%u\n" , +IO_DQS_IN_RESERVE ,IO_DQS_OUT_RESERVE );hc_initialize_rom_data ();
Signature · 1 line
2.1.4
PATCH 44/172 ddr: altera: Zap invocation of sdr_get_addr((u32 *)BASE_RW_MGR)"
In reply to Marek VasutInstead of this indirection, just adjust the register pointer and directly use the register base address.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/ddr/altera/sequencer.c +3 -3
@@ -1248,7 +1248,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn, ((group *RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS + vg) << 2)); - addr =sdr_get_addr ((u32 *)BASE_RW_MGR ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS ; base_rw_mgr =readl (SOCFPGA_SDR_ADDRESS + addr); tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
@@ -1406,7 +1406,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group ((group *RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS + vg) << 2)); - addr =sdr_get_addr ((u32 *)BASE_RW_MGR ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS ; base_rw_mgr =readl (SOCFPGA_SDR_ADDRESS + addr); tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
@@ -2789,7 +2789,7 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn, tmp_bit_chk =0 ; addr =sdr_get_addr (&phy_mgr_cmd->fifo_reset); - addr_rw_mgr =sdr_get_addr ((u32 *)BASE_RW_MGR ); + addr_rw_mgr =SDR_PHYGRP_RWMGRGRP_ADDRESS ;for (vg =RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS -1 ; ; vg--) {/* reset the fifos to get pointers to known state */ writel (0 ,SOCFPGA_SDR_ADDRESS + addr);
Signature · 1 line
2.1.4
PATCH 45/172 ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_reg_file->.*)
In reply to Marek VasutInstead of this indirection, just adjust the register pointer and directly use the register base address.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 46 ++++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 22 deletions(-)
drivers/ddr/altera/sequencer.c +24 -22
@@ -22,7 +22,7 @@ static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs = (struct socfpga_sdr_rw_load_jump_manager *)(BASE_RW_MGR +0xC00 );static struct socfpga_sdr_reg_file *sdr_reg_file = - (struct socfpga_sdr_reg_file *)(BASE_REG_FILE ); + (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS ;static struct socfpga_sdr_scc_mgr *sdr_scc_mgr = (struct socfpga_sdr_scc_mgr *)(BASE_SCC_MGR +0x0E00 );
@@ -130,7 +130,7 @@ static void set_failing_group_stage(uint32_t group, uint32_t stage,static void reg_file_set_group (uint32_t set_group) { -u32 addr =sdr_get_addr (&sdr_reg_file->cur_stage); +u32 addr = (u32)&sdr_reg_file->cur_stage;/* Read the current group and stage */ uint32_t cur_stage_group =readl (SOCFPGA_SDR_ADDRESS + addr);
@@ -147,7 +147,8 @@ static void reg_file_set_group(uint32_t set_group)static void reg_file_set_stage (uint32_t set_stage) { -u32 addr =sdr_get_addr (&sdr_reg_file->cur_stage); +u32 addr = (u32)&sdr_reg_file->cur_stage; +/* Read the current group and stage */ uint32_t cur_stage_group =readl (SOCFPGA_SDR_ADDRESS + addr);
@@ -163,7 +164,8 @@ static void reg_file_set_stage(uint32_t set_stage)static void reg_file_set_sub_stage (uint32_t set_sub_stage) { -u32 addr =sdr_get_addr (&sdr_reg_file->cur_stage); +u32 addr = (u32)&sdr_reg_file->cur_stage; +/* Read the current group and stage */ uint32_t cur_stage_group =readl (SOCFPGA_SDR_ADDRESS + addr);
@@ -1911,7 +1913,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)if (found_passing_read && found_failing_read) dtaps_per_ptap = d - initial_failing_dtap; - addr =sdr_get_addr (&sdr_reg_file->dtaps_per_ptap); + addr = (u32)&sdr_reg_file->dtaps_per_ptap;writel (dtaps_per_ptap,SOCFPGA_SDR_ADDRESS + addr); debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \ - %u = %u", __func__, __LINE__, d,
@@ -3754,7 +3756,7 @@ static uint32_t run_mem_calibrate(void)/* Update the FOM in the register file */ debug_info = gbl->fom_in; debug_info |= gbl->fom_out <<8 ; - addr =sdr_get_addr (&sdr_reg_file->fom); + addr = (u32)&sdr_reg_file->fom;writel (debug_info,SOCFPGA_SDR_ADDRESS + addr); addr =sdr_get_addr (&phy_mgr_cfg->cal_debug_info);
@@ -3768,7 +3770,7 @@ static uint32_t run_mem_calibrate(void) debug_info |= gbl->error_substage <<8 ; debug_info |= gbl->error_group <<16 ; - addr =sdr_get_addr (&sdr_reg_file->failing_stage); + addr = (u32)&sdr_reg_file->failing_stage;writel (debug_info,SOCFPGA_SDR_ADDRESS + addr); addr =sdr_get_addr (&phy_mgr_cfg->cal_debug_info);writel (debug_info,SOCFPGA_SDR_ADDRESS + addr);
@@ -3779,7 +3781,7 @@ static uint32_t run_mem_calibrate(void) debug_info = gbl->error_stage; debug_info |= gbl->error_substage <<8 ; debug_info |= gbl->error_group <<16 ; - addr =sdr_get_addr (&sdr_reg_file->failing_stage); + addr = (u32)&sdr_reg_file->failing_stage;writel (debug_info,SOCFPGA_SDR_ADDRESS + addr); }
@@ -3809,25 +3811,25 @@ static void initialize_reg_file(void)uint32_t addr;/* Initialize the register file with the correct data */ - addr =sdr_get_addr (&sdr_reg_file->signature); + addr = (u32)&sdr_reg_file->signature;writel (REG_FILE_INIT_SEQ_SIGNATURE ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_reg_file->debug_data_addr); + addr = (u32)&sdr_reg_file->debug_data_addr;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_reg_file->cur_stage); + addr = (u32)&sdr_reg_file->cur_stage;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_reg_file->fom); + addr = (u32)&sdr_reg_file->fom;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_reg_file->failing_stage); + addr = (u32)&sdr_reg_file->failing_stage;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_reg_file->debug1); + addr = (u32)&sdr_reg_file->debug1;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_reg_file->debug2); + addr = (u32)&sdr_reg_file->debug2;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); }
@@ -3931,25 +3933,25 @@ static void initialize_tracking(void) concatenated_refresh = concatenated_refresh ^1000 ;/* trefi */ /* Initialize the register file with the correct data */ - addr =sdr_get_addr (&sdr_reg_file->dtaps_per_ptap); + addr = (u32)&sdr_reg_file->dtaps_per_ptap;writel (dtaps_per_ptap,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_reg_file->trk_sample_count); + addr = (u32)&sdr_reg_file->trk_sample_count;writel (trk_sample_count,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_reg_file->trk_longidle); + addr = (u32)&sdr_reg_file->trk_longidle;writel (concatenated_longidle,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_reg_file->delays); + addr = (u32)&sdr_reg_file->delays;writel (concatenated_delays,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_reg_file->trk_rw_mgr_addr); + addr = (u32)&sdr_reg_file->trk_rw_mgr_addr;writel (concatenated_rw_addr,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_reg_file->trk_read_dqs_width); + addr = (u32)&sdr_reg_file->trk_read_dqs_width;writel (RW_MGR_MEM_IF_READ_DQS_WIDTH ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_reg_file->trk_rfsh); + addr = (u32)&sdr_reg_file->trk_rfsh;writel (concatenated_refresh,SOCFPGA_SDR_ADDRESS + addr); }
Signature · 1 line
2.1.4
PATCH 46/172 ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_scc_mgr->.*)
In reply to Marek VasutInstead of this indirection, just adjust the register pointer and directly use the register base address.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 90 +++++++++++++++++++++--------------------- 1 file changed, 45 insertions(+), 45 deletions(-)
drivers/ddr/altera/sequencer.c +45 -45
@@ -25,7 +25,7 @@ static struct socfpga_sdr_reg_file *sdr_reg_file = (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS ;static struct socfpga_sdr_scc_mgr *sdr_scc_mgr = - (struct socfpga_sdr_scc_mgr *)(BASE_SCC_MGR +0x0E00 ); + (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS |0xe00 );static struct socfpga_phy_mgr_cmd *phy_mgr_cmd = (struct socfpga_phy_mgr_cmd *)(BASE_PHY_MGR );
@@ -387,10 +387,10 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,scc_mgr_set_dqs_en_phase (read_group, phase);if (update_scan_chains) { - addr =sdr_get_addr (&sdr_scc_mgr->dqs_ena); + addr = (u32)&sdr_scc_mgr->dqs_ena;writel (read_group,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); } }
@@ -427,10 +427,10 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,scc_mgr_set_dqdqs_output_phase (write_group, phase);if (update_scan_chains) { - addr =sdr_get_addr (&sdr_scc_mgr->dqs_ena); + addr = (u32)&sdr_scc_mgr->dqs_ena;writel (write_group,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); } }
@@ -455,7 +455,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group, r += NUM_RANKS_PER_SHADOW_REG) {scc_mgr_set_dqs_en_delay (read_group, delay); - addr =sdr_get_addr (&sdr_scc_mgr->dqs_ena); + addr = (u32)&sdr_scc_mgr->dqs_ena;writel (read_group,SOCFPGA_SDR_ADDRESS + addr);/* * In shadow register mode, the T11 settings are stored in
@@ -465,7 +465,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,* select_shadow_regs_for_update with update_scan_chains * set to 0. */ - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); }/*
@@ -476,7 +476,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,* select_shadow_regs_for_update with update_scan_chains * set to 0. */ - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); }
@@ -587,10 +587,10 @@ static void scc_mgr_zero_all(void) }/* multicast to all DQS group enables */ - addr =sdr_get_addr (&sdr_scc_mgr->dqs_ena); + addr = (u32)&sdr_scc_mgr->dqs_ena;writel (0xff ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); }
@@ -609,22 +609,22 @@ static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode) __func__, __LINE__); }/* multicast to all DQ enables */ - addr =sdr_get_addr (&sdr_scc_mgr->dq_ena); + addr = (u32)&sdr_scc_mgr->dq_ena;writel (0xff ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_scc_mgr->dm_ena); + addr = (u32)&sdr_scc_mgr->dm_ena;writel (0xff ,SOCFPGA_SDR_ADDRESS + addr);/* update current DQS IO enable */ - addr =sdr_get_addr (&sdr_scc_mgr->dqs_io_ena); + addr = (u32)&sdr_scc_mgr->dqs_io_ena;writel (0 ,SOCFPGA_SDR_ADDRESS + addr);/* update the DQS logic */ - addr =sdr_get_addr (&sdr_scc_mgr->dqs_ena); + addr = (u32)&sdr_scc_mgr->dqs_ena;writel (write_group,SOCFPGA_SDR_ADDRESS + addr);/* hit update */ - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); }
@@ -644,7 +644,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin, }/* multicast to all DQ enables */ - addr =sdr_get_addr (&sdr_scc_mgr->dq_ena); + addr = (u32)&sdr_scc_mgr->dq_ena;writel (0xff ,SOCFPGA_SDR_ADDRESS + addr);/* Zero all DM config settings */
@@ -653,7 +653,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin, }/* multicast to all DM enables */ - addr =sdr_get_addr (&sdr_scc_mgr->dm_ena); + addr = (u32)&sdr_scc_mgr->dm_ena;writel (0xff ,SOCFPGA_SDR_ADDRESS + addr);/* zero all DQS io settings */
@@ -665,11 +665,11 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,scc_mgr_load_dqs_for_write_group (write_group);/* multicast to all DQS IO enables (only 1) */ - addr =sdr_get_addr (&sdr_scc_mgr->dqs_io_ena); + addr = (u32)&sdr_scc_mgr->dqs_io_ena;writel (0 ,SOCFPGA_SDR_ADDRESS + addr);/* hit update to zero everything */ - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); } }
@@ -677,7 +677,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,/* load up dqs config settings */ static void scc_mgr_load_dqs (uint32_t dqs) { -uint32_t addr =sdr_get_addr (&sdr_scc_mgr->dqs_ena); +uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;writel (dqs,SOCFPGA_SDR_ADDRESS + addr); }
@@ -685,7 +685,7 @@ static void scc_mgr_load_dqs(uint32_t dqs)static void scc_mgr_load_dqs_for_write_group (uint32_t write_group) {uint32_t read_group; -uint32_t addr =sdr_get_addr (&sdr_scc_mgr->dqs_ena); +uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;/* * Although OCT affects only write data, the OCT delay is controlled * by the DQS logic block which is instantiated once per read group.
@@ -702,7 +702,7 @@ static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)/* load up dqs io config settings */ static void scc_mgr_load_dqs_io (void ) { -uint32_t addr =sdr_get_addr (&sdr_scc_mgr->dqs_io_ena); +uint32_t addr = (u32)&sdr_scc_mgr->dqs_io_ena;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); }
@@ -710,7 +710,7 @@ static void scc_mgr_load_dqs_io(void)/* load up dq config settings */ static void scc_mgr_load_dq (uint32_t dq_in_group) { -uint32_t addr =sdr_get_addr (&sdr_scc_mgr->dq_ena); +uint32_t addr = (u32)&sdr_scc_mgr->dq_ena;writel (dq_in_group,SOCFPGA_SDR_ADDRESS + addr); }
@@ -718,7 +718,7 @@ static void scc_mgr_load_dq(uint32_t dq_in_group)/* load up dm config settings */ static void scc_mgr_load_dm (uint32_t dm) { -uint32_t addr =sdr_get_addr (&sdr_scc_mgr->dm_ena); +uint32_t addr = (u32)&sdr_scc_mgr->dm_ena;writel (dm,SOCFPGA_SDR_ADDRESS + addr); }
@@ -859,7 +859,7 @@ static void scc_mgr_apply_group_all_out_delay_add_all_ranks( uint32_t write_group, uint32_t group_bgn, uint32_t delay) { uint32_t r; -uint32_t addr =sdr_get_addr (&sdr_scc_mgr->update); +uint32_t addr = (u32)&sdr_scc_mgr->update;for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) {
@@ -1967,7 +1967,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delayscc_mgr_set_dq_in_delay (write_group, p, d);scc_mgr_load_dq (p); } - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); }
@@ -1985,7 +1985,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delayscc_mgr_set_dq_in_delay (write_group, p,0 );scc_mgr_load_dq (p); } - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); }
@@ -2032,7 +2032,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, right_edge[i] =IO_IO_IN_DELAY_MAX +1 ; } - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;/* Search for the left edge of the window for each bit */ for (d =0 ; d <=IO_IO_IN_DELAY_MAX ; d++) {scc_mgr_apply_group_dq_in_delay (write_group, test_bgn, d);
@@ -2121,7 +2121,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,break ; } - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;/* Search for the right edge of the window for each bit */ for (d =0 ; d <=IO_DQS_IN_DELAY_MAX - start_dqs; d++) {scc_mgr_set_dqs_bus_in_delay (read_group, d + start_dqs);
@@ -2214,7 +2214,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, }/* Check that all bits have a window */ - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;for (i =0 ; i <RW_MGR_MEM_DQ_PER_READ_DQS ; i++) { debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \ %d right_edge[%u]: %d", __func__, __LINE__,
@@ -2364,7 +2364,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,* Do not remove this line as it makes sure all of our decisions * have been applied. Apply the update bit. */ - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr);return (dq_margin >=0 ) && (dqs_margin >=0 );
@@ -2875,7 +2875,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, }/* Search for the left edge of the window for each bit */ - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;for (d =0 ; d <=IO_IO_OUT1_DELAY_MAX ; d++) {scc_mgr_apply_group_dq_out1_delay (write_group, test_bgn, d);
@@ -2959,7 +2959,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, }/* Search for the right edge of the window for each bit */ - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;for (d =0 ; d <=IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, d + start_dqs);
@@ -3133,7 +3133,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,/* Move DQS */ scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, new_dqs); - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr);/* Centre DM */
@@ -3152,7 +3152,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,int32_t win_best =0 ;/* Search for the/part of the window with DM shift */ - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;for (d =IO_IO_OUT1_DELAY_MAX ; d >=0 ; d -=DELTA_D ) {scc_mgr_apply_group_dm_out1_delay (write_group, d);writel (0 ,SOCFPGA_SDR_ADDRESS + addr);
@@ -3199,7 +3199,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, }/* Search for the/part of the window with DQS shifts */ - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;for (d =0 ; d <=IO_IO_OUT1_DELAY_MAX - new_dqs; d +=DELTA_D ) {/* * Note: This only shifts DQS, so are we limiting ourselve to
@@ -3271,7 +3271,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, dm_margin = left_edge[0 ] - mid;scc_mgr_apply_group_dm_out1_delay (write_group, mid); - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
@@ -3288,7 +3288,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,* Do not remove this line as it makes sure all of our * decisions have been applied. */ - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr);return (dq_margin >=0 ) && (dqs_margin >=0 ) && (dm_margin >=0 ); }
@@ -3458,20 +3458,20 @@ static void mem_skip_calibrate(void)scc_mgr_set_dqdqs_output_phase (i, (1.25 *IO_DLL_CHAIN_LENGTH -2 )); } - addr =sdr_get_addr (&sdr_scc_mgr->dqs_ena); + addr = (u32)&sdr_scc_mgr->dqs_ena;writel (0xff ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_scc_mgr->dqs_io_ena); + addr = (u32)&sdr_scc_mgr->dqs_io_ena;writel (0xff ,SOCFPGA_SDR_ADDRESS + addr); addr =sdr_get_addr ((u32 *)SCC_MGR_GROUP_COUNTER );for (i =0 ; i <RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; i++) {writel (i,SOCFPGA_SDR_ADDRESS + addr); } - addr =sdr_get_addr (&sdr_scc_mgr->dq_ena); + addr = (u32)&sdr_scc_mgr->dq_ena;writel (0xff ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_scc_mgr->dm_ena); + addr = (u32)&sdr_scc_mgr->dm_ena;writel (0xff ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); }
@@ -3480,7 +3480,7 @@ static void mem_skip_calibrate(void)scc_mgr_set_dqs_bus_in_delay (i,10 );scc_mgr_load_dqs (i); } - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr);/*
@@ -3690,7 +3690,7 @@ static uint32_t mem_calibrate(void)* Do not remove this line as it makes sure all of our decisions * have been applied. */ - addr =sdr_get_addr (&sdr_scc_mgr->update); + addr = (u32)&sdr_scc_mgr->update;writel (0 ,SOCFPGA_SDR_ADDRESS + addr);return 1 ; }
Signature · 1 line
2.1.4
PATCH 47/172 ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_rw_load.*->.*)
In reply to Marek VasutInstead of this indirection, just adjust the register pointer and directly use the register base address.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 126 ++++++++++++++++++++--------------------- 1 file changed, 63 insertions(+), 63 deletions(-)
drivers/ddr/altera/sequencer.c +63 -63
@@ -16,10 +16,10 @@static void scc_mgr_load_dqs_for_write_group (uint32_t write_group);static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs = - (struct socfpga_sdr_rw_load_manager *)(BASE_RW_MGR +0x800 ); + (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS |0x800 );static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs = - (struct socfpga_sdr_rw_load_jump_manager *)(BASE_RW_MGR +0xC00 ); + (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS |0xC00 );static struct socfpga_sdr_reg_file *sdr_reg_file = (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS ;
@@ -873,7 +873,7 @@ static void scc_mgr_apply_group_all_out_delay_add_all_ranks(/* could be applied to other protocols if we wanted to */ static void set_jump_as_return (void ) { -uint32_t addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr0); +uint32_t addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;/* * to save space, we replace return with jump to special shared
@@ -881,7 +881,7 @@ static void set_jump_as_return(void)* we always jump */ writel (0xff ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add0); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;writel (RW_MGR_RETURN ,SOCFPGA_SDR_ADDRESS + addr); }
@@ -944,25 +944,25 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)* overhead */ if (afi_clocks <=0x100 ) { - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr1); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (inner),SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add1); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;writel (RW_MGR_IDLE_LOOP1 ,SOCFPGA_SDR_ADDRESS + addr); addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP );writel (RW_MGR_IDLE_LOOP1 ,SOCFPGA_SDR_ADDRESS + addr); }else { - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr0); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (inner),SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr1); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (outer),SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add0); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;writel (RW_MGR_IDLE_LOOP2 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add1); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;writel (RW_MGR_IDLE_LOOP2 ,SOCFPGA_SDR_ADDRESS + addr);/* hack to get around compiler not being smart enough */
@@ -1016,24 +1016,24 @@ static void rw_mgr_mem_initialize(void)*/ /* Load counters */ - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr0); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TINIT_CNTR0_VAL ),SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr1); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TINIT_CNTR1_VAL ),SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr2); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TINIT_CNTR2_VAL ),SOCFPGA_SDR_ADDRESS + addr);/* Load jump address */ - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add0); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;writel (RW_MGR_INIT_RESET_0_CKE_0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add1); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;writel (RW_MGR_INIT_RESET_0_CKE_0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add2); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;writel (RW_MGR_INIT_RESET_0_CKE_0 ,SOCFPGA_SDR_ADDRESS + addr);/* Execute count instruction */
@@ -1060,22 +1060,22 @@ static void rw_mgr_mem_initialize(void)*/ /* Load counters */ - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr0); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TRESET_CNTR0_VAL ),SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr1); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TRESET_CNTR1_VAL ),SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr2); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TRESET_CNTR2_VAL ),SOCFPGA_SDR_ADDRESS + addr);/* Load jump address */ - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add0); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;writel (RW_MGR_INIT_RESET_1_CKE_0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add1); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;writel (RW_MGR_INIT_RESET_1_CKE_0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add2); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;writel (RW_MGR_INIT_RESET_1_CKE_0 ,SOCFPGA_SDR_ADDRESS + addr); addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP );
@@ -1223,14 +1223,14 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_READ_WRITE );/* Load up a constant bursts of read commands */ - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr0); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;writel (0x20 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add0); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;writel (RW_MGR_GUARANTEED_READ ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr1); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;writel (0x20 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add1); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;writel (RW_MGR_GUARANTEED_READ_CONT ,SOCFPGA_SDR_ADDRESS + addr); tmp_bit_chk =0 ;
@@ -1296,28 +1296,28 @@ static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_READ_WRITE );/* Load up a constant bursts */ - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr0); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;writel (0x20 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add0); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;writel (RW_MGR_GUARANTEED_WRITE_WAIT0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr1); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;writel (0x20 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add1); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;writel (RW_MGR_GUARANTEED_WRITE_WAIT1 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr2); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;writel (0x04 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add2); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;writel (RW_MGR_GUARANTEED_WRITE_WAIT2 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr3); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;writel (0x04 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add3); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;writel (RW_MGR_GUARANTEED_WRITE_WAIT3 ,SOCFPGA_SDR_ADDRESS + addr); addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP );
@@ -1358,18 +1358,18 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group/* set rank */ set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_READ_WRITE ); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr1); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;writel (0x10 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add1); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;writel (RW_MGR_READ_B2B_WAIT1 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr2); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;writel (0x10 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add2); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;writel (RW_MGR_READ_B2B_WAIT2 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr0); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;if (quick_read_mode)writel (0x1 ,SOCFPGA_SDR_ADDRESS + addr);/* need at least two (1+1) reads to capture failures */
@@ -1378,9 +1378,9 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t groupelse writel (0x32 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add0); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;writel (RW_MGR_READ_B2B ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr3); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;if (all_groups) writel(RW_MGR_MEM_IF_READ_DQS_WIDTH * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
@@ -1388,7 +1388,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t groupelse writel (0x0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add3); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;writel (RW_MGR_READ_B2B ,SOCFPGA_SDR_ADDRESS + addr); tmp_bit_chk =0 ;
@@ -2665,23 +2665,23 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,* instruction that sends out the data. We set the counter to a * large number so that the jump is always taken. */ - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr2); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;writel (0xFF ,SOCFPGA_SDR_ADDRESS + addr);/* CNTR 3 - Not used */ if (test_dm) { mcc_instruction =RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 ; - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add2); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;writel (RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add3); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;writel (RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP ,SOCFPGA_SDR_ADDRESS + addr); }else { mcc_instruction =RW_MGR_LFSR_WR_RD_BANK_0_WL_1 ; - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add2); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;writel (RW_MGR_LFSR_WR_RD_BANK_0_DATA ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add3); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;writel (RW_MGR_LFSR_WR_RD_BANK_0_NOP ,SOCFPGA_SDR_ADDRESS + addr); } }else if (rw_wl_nop_cycles ==0 ) {
@@ -2690,18 +2690,18 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,* to the DQS enable instruction. We set the counter to a large * number so that the jump is always taken. */ - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr2); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;writel (0xFF ,SOCFPGA_SDR_ADDRESS + addr);/* CNTR 3 - Not used */ if (test_dm) { mcc_instruction =RW_MGR_LFSR_WR_RD_DM_BANK_0 ; - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add2); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;writel (RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS ,SOCFPGA_SDR_ADDRESS + addr); }else { mcc_instruction =RW_MGR_LFSR_WR_RD_BANK_0 ; - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add2); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;writel (RW_MGR_LFSR_WR_RD_BANK_0_DQS ,SOCFPGA_SDR_ADDRESS + addr); } }else {
@@ -2710,24 +2710,24 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,* and NOT take the jump. So we set the counter to 0. The jump * address doesn't count. */ - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr2); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;writel (0x0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add2); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;writel (0x0 ,SOCFPGA_SDR_ADDRESS + addr);/* * CNTR 3 - Set the nop counter to the number of cycles we * need to loop for, minus 1. */ - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr3); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;writel (rw_wl_nop_cycles -1 ,SOCFPGA_SDR_ADDRESS + addr);if (test_dm) { mcc_instruction =RW_MGR_LFSR_WR_RD_DM_BANK_0 ; - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add3); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;writel (RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP ,SOCFPGA_SDR_ADDRESS + addr); }else { mcc_instruction =RW_MGR_LFSR_WR_RD_BANK_0 ; - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add3); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;writel (RW_MGR_LFSR_WR_RD_BANK_0_NOP ,SOCFPGA_SDR_ADDRESS + addr); } }
@@ -2735,23 +2735,23 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group, addr =sdr_get_addr ((u32 *)RW_MGR_RESET_READ_DATAPATH );writel (0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr0); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;if (quick_write_mode)writel (0x08 ,SOCFPGA_SDR_ADDRESS + addr);else writel (0x40 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add0); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;writel (mcc_instruction,SOCFPGA_SDR_ADDRESS + addr);/* * CNTR 1 - This is used to ensure enough time elapses * for read data to come back. */ - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr1); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;writel (0x30 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add1); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;if (test_dm) {writel (RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT ,SOCFPGA_SDR_ADDRESS + addr); }else {
@@ -3333,14 +3333,14 @@ static void mem_precharge_and_activate(void) addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP );writel (RW_MGR_PRECHARGE_ALL ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr0); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;writel (0x0F ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add0); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;writel (RW_MGR_ACTIVATE_0_AND_1_WAIT1 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_mgr_regs->load_cntr1); + addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;writel (0x0F ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&sdr_rw_load_jump_mgr_regs->load_jump_add1); + addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;writel (RW_MGR_ACTIVATE_0_AND_1_WAIT2 ,SOCFPGA_SDR_ADDRESS + addr);/* activate rows */
Signature · 1 line
2.1.4
PATCH 48/172 ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_mgr_.*->.*)
In reply to Marek VasutInstead of this indirection, just adjust the register pointer and directly use the register base address.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 52 +++++++++++++++++++++--------------------- 1 file changed, 26 insertions(+), 26 deletions(-)
drivers/ddr/altera/sequencer.c +26 -26
@@ -28,10 +28,10 @@ static struct socfpga_sdr_scc_mgr *sdr_scc_mgr = (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS |0xe00 );static struct socfpga_phy_mgr_cmd *phy_mgr_cmd = - (struct socfpga_phy_mgr_cmd *)(BASE_PHY_MGR ); + (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS ;static struct socfpga_phy_mgr_cfg *phy_mgr_cfg = - (struct socfpga_phy_mgr_cfg *)(BASE_PHY_MGR +0x4000 ); + (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS |0x40 );static struct socfpga_data_mgr *data_mgr = (struct socfpga_data_mgr *)(BASE_DATA_MGR );
@@ -181,7 +181,7 @@ static void reg_file_set_sub_stage(uint32_t set_sub_stage)static void initialize (void ) { -u32 addr =sdr_get_addr (&phy_mgr_cfg->mux_sel); +u32 addr = (u32)&phy_mgr_cfg->mux_sel;debug ("%s:%d\n" , __func__, __LINE__);/* USER calibration has control over path to memory */
@@ -193,14 +193,14 @@ static void initialize(void)writel (0x3 ,SOCFPGA_SDR_ADDRESS + addr);/* USER memory clock is not stable we begin initialization */ - addr =sdr_get_addr (&phy_mgr_cfg->reset_mem_stbl); + addr = (u32)&phy_mgr_cfg->reset_mem_stbl;writel (0 ,SOCFPGA_SDR_ADDRESS + addr);/* USER calibration status all set to zero */ - addr =sdr_get_addr (&phy_mgr_cfg->cal_status); + addr = (u32)&phy_mgr_cfg->cal_status;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&phy_mgr_cfg->cal_debug_info); + addr = (u32)&phy_mgr_cfg->cal_debug_info;writel (0 ,SOCFPGA_SDR_ADDRESS + addr);if ((dyn_calib_steps &CALIB_SKIP_ALL ) !=CALIB_SKIP_ALL ) {
@@ -1041,7 +1041,7 @@ static void rw_mgr_mem_initialize(void)writel (RW_MGR_INIT_RESET_0_CKE_0 ,SOCFPGA_SDR_ADDRESS + addr);/* indicate that memory is stable */ - addr =sdr_get_addr (&phy_mgr_cfg->reset_mem_stbl); + addr = (u32)&phy_mgr_cfg->reset_mem_stbl;writel (1 ,SOCFPGA_SDR_ADDRESS + addr);/*
@@ -1237,7 +1237,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,for (vg =RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS -1 ; ; vg--) {/* reset the fifos to get pointers to known state */ - addr =sdr_get_addr (&phy_mgr_cmd->fifo_reset); + addr = (u32)&phy_mgr_cmd->fifo_reset;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); addr =sdr_get_addr ((u32 *)RW_MGR_RESET_READ_DATAPATH );writel (0 ,SOCFPGA_SDR_ADDRESS + addr);
@@ -1394,7 +1394,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group tmp_bit_chk =0 ;for (vg =RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS -1 ; ; vg--) {/* reset the fifos to get pointers to known state */ - addr =sdr_get_addr (&phy_mgr_cmd->fifo_reset); + addr = (u32)&phy_mgr_cmd->fifo_reset;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); addr =sdr_get_addr ((u32 *)RW_MGR_RESET_READ_DATAPATH );writel (0 ,SOCFPGA_SDR_ADDRESS + addr);
@@ -1449,7 +1449,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,static void rw_mgr_incr_vfifo (uint32_t grp,uint32_t *v) { -uint32_t addr =sdr_get_addr (&phy_mgr_cmd->inc_vfifo_hard_phy); +uint32_t addr = (u32)&phy_mgr_cmd->inc_vfifo_hard_phy;writel (grp,SOCFPGA_SDR_ADDRESS + addr); (*v)++;
@@ -2572,7 +2572,7 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void)rw_mgr_mem_calibrate_read_load_patterns (0 ,1 ); found_one =0 ; - addr =sdr_get_addr (&phy_mgr_cfg->phy_rlat); + addr = (u32)&phy_mgr_cfg->phy_rlat; do { writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr); debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
@@ -2593,13 +2593,13 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void)/* reset the fifos to get pointers to known state */ - addr =sdr_get_addr (&phy_mgr_cmd->fifo_reset); + addr = (u32)&phy_mgr_cmd->fifo_reset;writel (0 ,SOCFPGA_SDR_ADDRESS + addr);if (found_one) {/* add a fudge factor to the read latency that was determined */ gbl->curr_read_lat +=2 ; - addr =sdr_get_addr (&phy_mgr_cfg->phy_rlat); + addr = (u32)&phy_mgr_cfg->phy_rlat;writel (gbl->curr_read_lat,SOCFPGA_SDR_ADDRESS + addr); debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \ read_lat=%u\n", __func__, __LINE__,
@@ -2790,7 +2790,7 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_READ_WRITE ); tmp_bit_chk =0 ; - addr =sdr_get_addr (&phy_mgr_cmd->fifo_reset); + addr = (u32)&phy_mgr_cmd->fifo_reset; addr_rw_mgr =SDR_PHYGRP_RWMGRGRP_ADDRESS ;for (vg =RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS -1 ; ; vg--) {/* reset the fifos to get pointers to known state */
@@ -3396,12 +3396,12 @@ static void mem_config(void)if (gbl->curr_read_lat > max_latency) gbl->curr_read_lat = max_latency; - addr =sdr_get_addr (&phy_mgr_cfg->phy_rlat); + addr = (u32)&phy_mgr_cfg->phy_rlat;writel (gbl->curr_read_lat,SOCFPGA_SDR_ADDRESS + addr);/* advertise write latency */ gbl->curr_write_lat = wlat; - addr =sdr_get_addr (&phy_mgr_cfg->afi_wlat); + addr = (u32)&phy_mgr_cfg->afi_wlat;writel (wlat -2 ,SOCFPGA_SDR_ADDRESS + addr);/* initialize bit slips */
@@ -3488,11 +3488,11 @@ static void mem_skip_calibrate(void)* in sequencer. */ vfifo_offset =CALIB_VFIFO_OFFSET ; - addr =sdr_get_addr (&phy_mgr_cmd->inc_vfifo_hard_phy); + addr = (u32)&phy_mgr_cmd->inc_vfifo_hard_phy;for (j =0 ; j < vfifo_offset; j++) {writel (0xff ,SOCFPGA_SDR_ADDRESS + addr); } - addr =sdr_get_addr (&phy_mgr_cmd->fifo_reset); + addr = (u32)&phy_mgr_cmd->fifo_reset;writel (0 ,SOCFPGA_SDR_ADDRESS + addr);/*
@@ -3500,7 +3500,7 @@ static void mem_skip_calibrate(void)* generation-time constant. */ gbl->curr_read_lat =CALIB_LFIFO_OFFSET ; - addr =sdr_get_addr (&phy_mgr_cfg->phy_rlat); + addr = (u32)&phy_mgr_cfg->phy_rlat;writel (gbl->curr_read_lat,SOCFPGA_SDR_ADDRESS + addr); }
@@ -3704,7 +3704,7 @@ static uint32_t run_mem_calibrate(void)debug ("%s:%d\n" , __func__, __LINE__);/* Reset pass/fail status shown on afi_cal_success/fail */ - addr =sdr_get_addr (&phy_mgr_cfg->cal_status); + addr = (u32)&phy_mgr_cfg->cal_status;writel (PHY_MGR_CAL_RESET ,SOCFPGA_SDR_ADDRESS + addr); addr =sdr_get_addr ((u32 *)BASE_MMR );
@@ -3720,7 +3720,7 @@ static uint32_t run_mem_calibrate(void) pass =mem_calibrate ();mem_precharge_and_activate (); - addr =sdr_get_addr (&phy_mgr_cmd->fifo_reset); + addr = (u32)&phy_mgr_cmd->fifo_reset;writel (0 ,SOCFPGA_SDR_ADDRESS + addr);/*
@@ -3734,7 +3734,7 @@ static uint32_t run_mem_calibrate(void)* 0: AFI Mux Select * 1: DDIO Mux Select */ - addr =sdr_get_addr (&phy_mgr_cfg->mux_sel); + addr = (u32)&phy_mgr_cfg->mux_sel;writel (0x2 ,SOCFPGA_SDR_ADDRESS + addr); }
@@ -3759,9 +3759,9 @@ static uint32_t run_mem_calibrate(void) addr = (u32)&sdr_reg_file->fom;writel (debug_info,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&phy_mgr_cfg->cal_debug_info); + addr = (u32)&phy_mgr_cfg->cal_debug_info;writel (debug_info,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&phy_mgr_cfg->cal_status); + addr = (u32)&phy_mgr_cfg->cal_status;writel (PHY_MGR_CAL_SUCCESS ,SOCFPGA_SDR_ADDRESS + addr); }else {printf ("%s: CALIBRATION FAILED\n" , __FILE__);
@@ -3772,9 +3772,9 @@ static uint32_t run_mem_calibrate(void) addr = (u32)&sdr_reg_file->failing_stage;writel (debug_info,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&phy_mgr_cfg->cal_debug_info); + addr = (u32)&phy_mgr_cfg->cal_debug_info;writel (debug_info,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&phy_mgr_cfg->cal_status); + addr = (u32)&phy_mgr_cfg->cal_status;writel (PHY_MGR_CAL_FAIL ,SOCFPGA_SDR_ADDRESS + addr);/* Update the failing group/stage in the register file */
Signature · 1 line
2.1.4
PATCH 49/172 ddr: altera: Pluck out remaining sdr_get_addr() calls
In reply to Marek VasutRemove the remaining invocations of sdr_get_addr() and the function itself. This makes the code a bit less cryptic.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 141 ++++++++++++++++------------------------- drivers/ddr/altera/sequencer.h | 53 ++++++---------- 2 files changed, 75 insertions(+), 119 deletions(-)
drivers/ddr/altera/sequencer.c +56 -85
@@ -34,10 +34,9 @@ static struct socfpga_phy_mgr_cfg *phy_mgr_cfg = (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS |0x40 );static struct socfpga_data_mgr *data_mgr = - (struct socfpga_data_mgr *)(BASE_DATA_MGR ); + (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS ;#define DELTA_D 1 -#define MGR_SELECT_MASK 0xf8000/* * In order to reduce ROM size, most of the selectable calibration steps are
@@ -83,37 +82,6 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn, uint32_t write_group, uint32_t use_dm, uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks); -static u32 sdr_get_addr (u32 *base) -{ -u32 addr = (u32 )base &MGR_SELECT_MASK ; - -switch (addr) { -case BASE_PHY_MGR : - addr = (((u32 )base >>8 ) & (1 <<6 )) | ((u32 )base &0x3f ) | -SDR_PHYGRP_PHYMGRGRP_ADDRESS ; -break ; -case BASE_RW_MGR : - addr = ((u32 )base &0x1fff ) |SDR_PHYGRP_RWMGRGRP_ADDRESS ; -break ; -case BASE_DATA_MGR : - addr = ((u32 )base &0x7ff ) |SDR_PHYGRP_DATAMGRGRP_ADDRESS ; -break ; -case BASE_SCC_MGR : - addr = ((u32 )base &0xfff ) |SDR_PHYGRP_SCCGRP_ADDRESS ; -break ; -case BASE_REG_FILE : - addr = ((u32 )base &0x7ff ) |SDR_PHYGRP_REGFILEGRP_ADDRESS ; -break ; -case BASE_MMR : - addr = ((u32 )base &0xfff ) |SDR_CTRLGRP_ADDRESS ; -break ; -default : -return -1 ; - } - -return addr; -} -static void set_failing_group_stage (uint32_t group,uint32_t stage,uint32_t substage) {
@@ -318,13 +286,13 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode) (0xFF & ~(1 << rank)) | ((0xFF & odt_mask_0) <<8 ) | ((0xFF & odt_mask_1) <<16 ); - addr =sdr_get_addr ((u32 *)RW_MGR_SET_CS_AND_ODT_MASK ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_SET_CS_AND_ODT_MASK_OFFSET ;writel (cs_and_odt_mask,SOCFPGA_SDR_ADDRESS + addr); }static void scc_mgr_initialize (void ) { -u32 addr =sdr_get_addr ((u32 *)SCC_MGR_HHP_RFILE ); +u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_HHP_RFILE_OFFSET ;/* * Clear register file for HPS
@@ -343,7 +311,7 @@ static void scc_mgr_initialize(void)static void scc_mgr_set_dqs_bus_in_delay (uint32_t read_group,uint32_t delay) { -u32 addr =sdr_get_addr ((u32 *)SCC_MGR_DQS_IN_DELAY ); +u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQS_IN_DELAY_OFFSET ;/* Load the setting in the SCC manager */ writel (delay,SOCFPGA_SDR_ADDRESS + addr + (read_group <<2 ));
@@ -352,14 +320,14 @@ static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group,static void scc_mgr_set_dqs_io_in_delay (uint32_t write_group,uint32_t delay) { -u32 addr =sdr_get_addr ((u32 *)SCC_MGR_IO_IN_DELAY ); +u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_IN_DELAY_OFFSET ;writel (delay,SOCFPGA_SDR_ADDRESS + addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS <<2 )); }static void scc_mgr_set_dqs_en_phase (uint32_t read_group,uint32_t phase) { -u32 addr =sdr_get_addr ((u32 *)SCC_MGR_DQS_EN_PHASE ); +u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQS_EN_PHASE_OFFSET ;/* Load the setting in the SCC manager */ writel (phase,SOCFPGA_SDR_ADDRESS + addr + (read_group <<2 ));
@@ -399,7 +367,7 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,static void scc_mgr_set_dqdqs_output_phase (uint32_t write_group,uint32_t phase) { -u32 addr =sdr_get_addr ((u32 *)SCC_MGR_DQDQS_OUT_PHASE ); +u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQDQS_OUT_PHASE_OFFSET ;/* Load the setting in the SCC manager */ writel (phase,SOCFPGA_SDR_ADDRESS + addr + (write_group <<2 ));
@@ -438,7 +406,7 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,static void scc_mgr_set_dqs_en_delay (uint32_t read_group,uint32_t delay) { -uint32_t addr =sdr_get_addr ((u32 *)SCC_MGR_DQS_EN_DELAY ); +uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQS_EN_DELAY_OFFSET ;/* Load the setting in the SCC manager */ writel(delay + IO_DQS_EN_DELAY_OFFSET, SOCFPGA_SDR_ADDRESS + addr +
@@ -483,7 +451,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,static void scc_mgr_set_oct_out1_delay (uint32_t write_group,uint32_t delay) {uint32_t read_group; -uint32_t addr =sdr_get_addr ((u32 *)SCC_MGR_OCT_OUT1_DELAY ); +uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_OCT_OUT1_DELAY_OFFSET ;/* * Load the setting in the SCC manager
@@ -502,7 +470,7 @@ static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)static void scc_mgr_set_dq_out1_delay (uint32_t write_group,uint32_t dq_in_group,uint32_t delay) { -uint32_t addr =sdr_get_addr ((u32 *)SCC_MGR_IO_OUT1_DELAY ); +uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ;/* Load the setting in the SCC manager */ writel (delay,SOCFPGA_SDR_ADDRESS + addr + (dq_in_group <<2 ));
@@ -511,7 +479,7 @@ static void scc_mgr_set_dq_out1_delay(uint32_t write_group,static void scc_mgr_set_dq_in_delay (uint32_t write_group,uint32_t dq_in_group,uint32_t delay) { -uint32_t addr =sdr_get_addr ((u32 *)SCC_MGR_IO_IN_DELAY ); +uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_IN_DELAY_OFFSET ;/* Load the setting in the SCC manager */ writel (delay,SOCFPGA_SDR_ADDRESS + addr + (dq_in_group <<2 ));
@@ -529,7 +497,7 @@ static void scc_mgr_set_hhp_extras(void)* bits: 8:8 = 1'b0 - separate OE from Output delay setting */ uint32_t value = (0 <<8 ) | (0 <<7 ) | (1 <<5 ) | (1 <<2 ) | (1 <<1 ) | (1 <<0 ); -uint32_t addr =sdr_get_addr ((u32 *)SCC_MGR_HHP_GLOBALS ); +uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_HHP_GLOBALS_OFFSET ;writel (value,SOCFPGA_SDR_ADDRESS + addr +SCC_MGR_HHP_EXTRAS_OFFSET ); }
@@ -537,7 +505,7 @@ static void scc_mgr_set_hhp_extras(void)static void scc_mgr_set_dqs_out1_delay (uint32_t write_group,uint32_t delay) { -uint32_t addr =sdr_get_addr ((u32 *)SCC_MGR_IO_OUT1_DELAY ); +uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ;/* Load the setting in the SCC manager */ writel (delay,SOCFPGA_SDR_ADDRESS + addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS <<2 ));
@@ -546,7 +514,7 @@ static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,static void scc_mgr_set_dm_out1_delay (uint32_t write_group,uint32_t dm,uint32_t delay) { -uint32_t addr =sdr_get_addr ((u32 *)SCC_MGR_IO_OUT1_DELAY ); +uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ;/* Load the setting in the SCC manager */ writel(delay, SOCFPGA_SDR_ADDRESS + addr +
@@ -950,7 +918,7 @@ static void delay_for_n_mem_clocks(const uint32_t clocks) addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;writel (RW_MGR_IDLE_LOOP1 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_IDLE_LOOP1 ,SOCFPGA_SDR_ADDRESS + addr); }else { addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
@@ -968,11 +936,11 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)/* hack to get around compiler not being smart enough */ if (afi_clocks <=0x10000 ) {/* only need to run once */ - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_IDLE_LOOP2 ,SOCFPGA_SDR_ADDRESS + addr); }else {do { - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_IDLE_LOOP2 ,SOCFPGA_SDR_ADDRESS + addr); }while (c_loop-- !=0 ); }
@@ -988,7 +956,7 @@ static void rw_mgr_mem_initialize(void)debug ("%s:%d\n" , __func__, __LINE__);/* The reset / cke part of initialization is broadcasted to all ranks */ - addr =sdr_get_addr ((u32 *)RW_MGR_SET_CS_AND_ODT_MASK ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_SET_CS_AND_ODT_MASK_OFFSET ;writel (RW_MGR_RANK_ALL ,SOCFPGA_SDR_ADDRESS + addr);/*
@@ -1037,7 +1005,7 @@ static void rw_mgr_mem_initialize(void)writel (RW_MGR_INIT_RESET_0_CKE_0 ,SOCFPGA_SDR_ADDRESS + addr);/* Execute count instruction */ - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_INIT_RESET_0_CKE_0 ,SOCFPGA_SDR_ADDRESS + addr);/* indicate that memory is stable */
@@ -1078,7 +1046,7 @@ static void rw_mgr_mem_initialize(void) addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;writel (RW_MGR_INIT_RESET_1_CKE_0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_INIT_RESET_1_CKE_0 ,SOCFPGA_SDR_ADDRESS + addr);/* bring up clock enable */
@@ -1101,7 +1069,7 @@ static void rw_mgr_mem_initialize(void)*/ if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) &0x1 ) {set_jump_as_return (); - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_MRS2_MIRR ,SOCFPGA_SDR_ADDRESS + addr);delay_for_n_mem_clocks (4 );set_jump_as_return ();
@@ -1114,7 +1082,7 @@ static void rw_mgr_mem_initialize(void)writel (RW_MGR_MRS0_DLL_RESET_MIRR ,SOCFPGA_SDR_ADDRESS + addr); }else {set_jump_as_return (); - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_MRS2 ,SOCFPGA_SDR_ADDRESS + addr);delay_for_n_mem_clocks (4 );set_jump_as_return ();
@@ -1126,7 +1094,7 @@ static void rw_mgr_mem_initialize(void)writel (RW_MGR_MRS0_DLL_RESET ,SOCFPGA_SDR_ADDRESS + addr); }set_jump_as_return (); - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_ZQCL ,SOCFPGA_SDR_ADDRESS + addr);/* tZQinit = tDLLK = 512 ck cycles */
@@ -1152,7 +1120,7 @@ static void rw_mgr_mem_handoff(void)set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_OFF );/* precharge all banks ... */ - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_PRECHARGE_ALL ,SOCFPGA_SDR_ADDRESS + addr);/* load up MR settings specified by user */
@@ -1161,7 +1129,7 @@ static void rw_mgr_mem_handoff(void)* Use Mirror-ed commands for odd ranks if address * mirrorring is on */ - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) &0x1 ) {set_jump_as_return ();writel (RW_MGR_MRS2_MIRR ,SOCFPGA_SDR_ADDRESS + addr);
@@ -1239,13 +1207,13 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn, addr = (u32)&phy_mgr_cmd->fifo_reset;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr ((u32 *)RW_MGR_RESET_READ_DATAPATH ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RESET_READ_DATAPATH_OFFSET ;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS /RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS ); - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_GUARANTEED_READ ,SOCFPGA_SDR_ADDRESS + addr + ((group *RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS + vg) <<2 ));
@@ -1260,7 +1228,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn, *bit_chk &= tmp_bit_chk; } - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_CLEAR_DQS_ENABLE ,SOCFPGA_SDR_ADDRESS + addr + (group <<2 ));set_rank_and_odt_mask (0 ,RW_MGR_ODT_MODE_OFF );
@@ -1320,7 +1288,7 @@ static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn, addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;writel (RW_MGR_GUARANTEED_WRITE_WAIT3 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_GUARANTEED_WRITE ,SOCFPGA_SDR_ADDRESS + addr); }
@@ -1396,14 +1364,17 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group/* reset the fifos to get pointers to known state */ addr = (u32)&phy_mgr_cmd->fifo_reset;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr ((u32 *)RW_MGR_RESET_READ_DATAPATH ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RESET_READ_DATAPATH_OFFSET ;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS /RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS ); - addr =sdr_get_addr ((u32 *)(all_groups ?RW_MGR_RUN_ALL_GROUPS : -RW_MGR_RUN_SINGLE_GROUP )); +if (all_groups) + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_ALL_GROUPS_OFFSET ; +else + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ; +writel (RW_MGR_READ_B2B ,SOCFPGA_SDR_ADDRESS + addr + ((group *RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS + vg) <<2 ));
@@ -1418,7 +1389,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group *bit_chk &= tmp_bit_chk; } - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_CLEAR_DQS_ENABLE ,SOCFPGA_SDR_ADDRESS + addr + (group <<2 ));if (all_correct) {
@@ -2018,7 +1989,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,debug ("%s:%d: %u %u" , __func__, __LINE__, read_group, test_bgn); - addr =sdr_get_addr ((u32 *)SCC_MGR_DQS_IN_DELAY ); + addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQS_IN_DELAY_OFFSET ; start_dqs =readl (SOCFPGA_SDR_ADDRESS + addr + (read_group <<2 ));if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ) start_dqs_en = readl(SOCFPGA_SDR_ADDRESS + addr + ((read_group << 2)
@@ -2306,7 +2277,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, dqs_margin =IO_IO_IN_DELAY_MAX +1 ; dq_margin =IO_IO_IN_DELAY_MAX +1 ; - addr =sdr_get_addr ((u32 *)SCC_MGR_IO_IN_DELAY ); + addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_IN_DELAY_OFFSET ;/* add delay to bring centre of all DQ windows to the same "level" */ for (i =0 , p = test_bgn; i <RW_MGR_MEM_DQ_PER_READ_DQS ; i++, p++) {/* Use values before divide by 2 to reduce round off error */
@@ -2732,7 +2703,7 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group, } } - addr =sdr_get_addr ((u32 *)RW_MGR_RESET_READ_DATAPATH ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RESET_READ_DATAPATH_OFFSET ;writel (0 ,SOCFPGA_SDR_ADDRESS + addr); addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
@@ -2758,7 +2729,7 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,writel (RW_MGR_LFSR_WR_RD_BANK_0_WAIT ,SOCFPGA_SDR_ADDRESS + addr); } - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (mcc_instruction,SOCFPGA_SDR_ADDRESS + addr + (group <<2 )); }
@@ -2858,7 +2829,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, dm_margin =0 ; - addr =sdr_get_addr ((u32 *)SCC_MGR_IO_OUT1_DELAY ); + addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ; start_dqs =readl (SOCFPGA_SDR_ADDRESS + addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS <<2 ));
@@ -3097,7 +3068,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, dq_margin =IO_IO_OUT1_DELAY_MAX +1 ;/* add delay to bring centre of all DQ windows to the same "level" */ - addr =sdr_get_addr ((u32 *)SCC_MGR_IO_OUT1_DELAY ); + addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ;for (i =0 , p = test_bgn; i <RW_MGR_MEM_DQ_PER_WRITE_DQS ; i++, p++) {/* Use values before divide by 2 to reduce round off error */ shift_dq = (left_edge[i] - right_edge[i] -
@@ -3330,7 +3301,7 @@ static void mem_precharge_and_activate(void)set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_OFF );/* precharge all banks ... */ - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_PRECHARGE_ALL ,SOCFPGA_SDR_ADDRESS + addr); addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
@@ -3344,7 +3315,7 @@ static void mem_precharge_and_activate(void)writel (RW_MGR_ACTIVATE_0_AND_1_WAIT2 ,SOCFPGA_SDR_ADDRESS + addr);/* activate rows */ - addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_ACTIVATE_0_AND_1 ,SOCFPGA_SDR_ADDRESS + addr); } }
@@ -3359,10 +3330,10 @@ static void mem_config(void)debug ("%s:%d\n" , __func__, __LINE__);/* read in write and read latency */ - addr =sdr_get_addr (&data_mgr->t_wl_add); + addr = (u32)&data_mgr->t_wl_add; wlat =readl (SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr (&data_mgr->mem_t_add); + addr = (u32)&data_mgr->mem_t_add; wlat +=readl (SOCFPGA_SDR_ADDRESS + addr);/* WL for hard phy does not include additive latency */
@@ -3373,7 +3344,7 @@ static void mem_config(void)*/ wlat = wlat +1 ; - addr =sdr_get_addr (&data_mgr->t_rl_add); + addr = (u32)&data_mgr->t_rl_add; rlat =readl (SOCFPGA_SDR_ADDRESS + addr); rw_wl_nop_cycles = wlat -2 ;
@@ -3463,7 +3434,7 @@ static void mem_skip_calibrate(void) addr = (u32)&sdr_scc_mgr->dqs_io_ena;writel (0xff ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr ((u32 *)SCC_MGR_GROUP_COUNTER ); + addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_GROUP_COUNTER_OFFSET ;for (i =0 ; i <RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; i++) {writel (i,SOCFPGA_SDR_ADDRESS + addr); }
@@ -3529,7 +3500,7 @@ static uint32_t mem_calibrate(void)mem_config ();uint32_t bypass_mode =0x1 ; - addr =sdr_get_addr ((u32 *)SCC_MGR_GROUP_COUNTER ); + addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_GROUP_COUNTER_OFFSET ;for (i =0 ; i <RW_MGR_MEM_IF_READ_DQS_WIDTH ; i++) {writel (i,SOCFPGA_SDR_ADDRESS + addr);scc_set_bypass_mode (i, bypass_mode);
@@ -3565,7 +3536,7 @@ static uint32_t mem_calibrate(void)if (current_run ==0 )continue ; - addr =sdr_get_addr ((u32 *)SCC_MGR_GROUP_COUNTER ); + addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_GROUP_COUNTER_OFFSET ;writel (write_group,SOCFPGA_SDR_ADDRESS + addr);scc_mgr_zero_group (write_group, write_test_bgn,0 );
@@ -3707,11 +3678,11 @@ static uint32_t run_mem_calibrate(void) addr = (u32)&phy_mgr_cfg->cal_status;writel (PHY_MGR_CAL_RESET ,SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr ((u32 *)BASE_MMR ); + addr =SDR_CTRLGRP_ADDRESS ;/* stop tracking manger */ uint32_t ctrlcfg =readl (SOCFPGA_SDR_ADDRESS + addr); - addr =sdr_get_addr ((u32 *)BASE_MMR ); + addr =SDR_CTRLGRP_ADDRESS ;writel (ctrlcfg &0xFFBFFFFF ,SOCFPGA_SDR_ADDRESS + addr);initialize ();
@@ -3738,7 +3709,7 @@ static uint32_t run_mem_calibrate(void)writel (0x2 ,SOCFPGA_SDR_ADDRESS + addr); } - addr =sdr_get_addr ((u32 *)BASE_MMR ); + addr =SDR_CTRLGRP_ADDRESS ;writel (ctrlcfg,SOCFPGA_SDR_ADDRESS + addr);if (pass) {
@@ -3793,13 +3764,13 @@ static void hc_initialize_rom_data(void)uint32_t i;uint32_t addr; - addr =sdr_get_addr ((u32 *)(RW_MGR_INST_ROM_WRITE )); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_INST_ROM_WRITE_OFFSET ;for (i =0 ; i <ARRAY_SIZE (inst_rom_init); i++) {uint32_t data = inst_rom_init[i];writel (data,SOCFPGA_SDR_ADDRESS + addr + (i <<2 )); } - addr =sdr_get_addr ((u32 *)(RW_MGR_AC_ROM_WRITE )); + addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_AC_ROM_WRITE_OFFSET ;for (i =0 ; i <ARRAY_SIZE (ac_rom_init); i++) {uint32_t data = ac_rom_init[i];writel (data,SOCFPGA_SDR_ADDRESS + addr + (i <<2 ));
@@ -3862,7 +3833,7 @@ static void initialize_hps_phy(void) reg |=SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET (0 ); reg |=SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET ( trk_sample_count); - addr =sdr_get_addr ((u32 *)BASE_MMR ); + addr =SDR_CTRLGRP_ADDRESS ;writel (reg,SOCFPGA_SDR_ADDRESS + addr +SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET ); reg =0 ;
drivers/ddr/altera/sequencer.h +19 -34
77 lines not on this page · raw message
Signature · 1 line
2.1.4
PATCH 50/172 ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS
In reply to Marek VasutJust trim down the constant SOCFPGA_SDR_ADDRESS + SDR_PHYGRP.*ADDRESS in the code.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/include/mach/sdram.h | 2 +- drivers/ddr/altera/sdram.c | 2 +- drivers/ddr/altera/sequencer.c | 458 ++++++++++++++--------------- drivers/ddr/altera/sequencer.h | 10 +- 4 files changed, 236 insertions(+), 236 deletions(-)
arch/arm/mach-socfpga/include/mach/sdram.h +1 -1
@@ -14,7 +14,7 @@ int sdram_calibration_full(void);extern int sdram_calibration (void ); -#define SDR_CTRLGRP_ADDRESS 0x5000 +#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)struct socfpga_sdr_ctrl {u32 ctrl_cfg;
drivers/ddr/altera/sdram.c +1 -1
@@ -38,7 +38,7 @@ struct sdram_prot_rule {static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ;static struct socfpga_sdr_ctrl *sdr_ctrl = - (struct socfpga_sdr_ctrl *)(SOCFPGA_SDR_ADDRESS +SDR_CTRLGRP_ADDRESS ); + (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS ;static int compute_errata_rows (unsigned long long memsize,int cs,int width,int rows,int banks,int cols)
drivers/ddr/altera/sequencer.c +229 -229
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drivers/ddr/altera/sequencer.h +5 -5
@@ -93,11 +93,11 @@#define SCC_MGR_HHP_RFILE_OFFSET 0x0B00#define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00 -#define SDR_PHYGRP_SCCGRP_ADDRESS 0x0 -#define SDR_PHYGRP_PHYMGRGRP_ADDRESS 0x1000 -#define SDR_PHYGRP_RWMGRGRP_ADDRESS 0x2000 -#define SDR_PHYGRP_DATAMGRGRP_ADDRESS 0x4000 -#define SDR_PHYGRP_REGFILEGRP_ADDRESS 0x4800 +#define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0) +#define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000) +#define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000) +#define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000) +#define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800)#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154
Signature · 1 line
2.1.4
PATCH 51/172 ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly
In reply to Marek VasutUse the proper structure which describes these registers, especially since this is already in place.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 20 +++++++++----------- drivers/ddr/altera/sequencer.h | 4 ---- 2 files changed, 9 insertions(+), 15 deletions(-)
drivers/ddr/altera/sequencer.c +9 -11
@@ -36,6 +36,9 @@ static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =static struct socfpga_data_mgr *data_mgr = (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS ; +static struct socfpga_sdr_ctrl *sdr_ctrl = + (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS ; +#define DELTA_D 1/*
@@ -3678,12 +3681,10 @@ static uint32_t run_mem_calibrate(void) addr = (u32)&phy_mgr_cfg->cal_status;writel (PHY_MGR_CAL_RESET , addr); - addr =SDR_CTRLGRP_ADDRESS ;/* stop tracking manger */ -uint32_t ctrlcfg =readl (addr); +uint32_t ctrlcfg =readl (&sdr_ctrl->ctrl_cfg); - addr =SDR_CTRLGRP_ADDRESS ; -writel (ctrlcfg &0xFFBFFFFF , addr); +writel (ctrlcfg &0xFFBFFFFF , &sdr_ctrl->ctrl_cfg);initialize ();rw_mgr_mem_initialize ();
@@ -3709,8 +3710,7 @@ static uint32_t run_mem_calibrate(void)writel (0x2 , addr); } - addr =SDR_CTRLGRP_ADDRESS ; -writel (ctrlcfg, addr); +writel (ctrlcfg, &sdr_ctrl->ctrl_cfg);if (pass) {printf ("%s: CALIBRATION PASSED\n" , __FILE__);
@@ -3807,7 +3807,6 @@ static void initialize_reg_file(void)static void initialize_hps_phy (void ) {uint32_t reg; -uint32_t addr;/* * Tracking also gets configured here because it's in the * same register.
@@ -3833,8 +3832,7 @@ static void initialize_hps_phy(void) reg |=SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET (0 ); reg |=SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET ( trk_sample_count); - addr =SDR_CTRLGRP_ADDRESS ; -writel (reg, addr +SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET ); +writel (reg, &sdr_ctrl->phy_ctrl0); reg =0 ; reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
@@ -3842,13 +3840,13 @@ static void initialize_hps_phy(void) SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH); reg |=SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET ( trk_long_idle_sample_count); -writel (reg, addr +SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET ); +writel (reg, &sdr_ctrl->phy_ctrl1); reg =0 ; reg |=SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET ( trk_long_idle_sample_count >>SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH ); -writel (reg, addr +SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET ); +writel (reg, &sdr_ctrl->phy_ctrl2); }static void initialize_tracking (void )
drivers/ddr/altera/sequencer.h +0 -4
@@ -99,10 +99,6 @@#define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000)#define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150 -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154 -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158 -#define PHY_MGR_CAL_RESET (0)#define PHY_MGR_CAL_SUCCESS (1)#define PHY_MGR_CAL_FAIL (2)
Signature · 1 line
2.1.4
PATCH 52/172 ddr: altera: Massage addr into I/O accessors
In reply to Marek VasutGet rid of invocations of this sort:
addr = (u32)&base->reg;
writel(val, addr);
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 672 +++++++++++++++-------------------------- 1 file changed, 248 insertions(+), 424 deletions(-)
drivers/ddr/altera/sequencer.c +248 -424
@@ -101,10 +101,8 @@ static void set_failing_group_stage(uint32_t group, uint32_t stage,static void reg_file_set_group (uint32_t set_group) { -u32 addr = (u32)&sdr_reg_file->cur_stage; -/* Read the current group and stage */ -uint32_t cur_stage_group =readl (addr); +uint32_t cur_stage_group =readl (&sdr_reg_file->cur_stage);/* Clear the group */ cur_stage_group &=0x0000FFFF ;
@@ -113,15 +111,13 @@ static void reg_file_set_group(uint32_t set_group) cur_stage_group |= (set_group <<16 );/* Write the data back */ -writel (cur_stage_group, addr); +writel (cur_stage_group, &sdr_reg_file->cur_stage); }static void reg_file_set_stage (uint32_t set_stage) { -u32 addr = (u32)&sdr_reg_file->cur_stage; -/* Read the current group and stage */ -uint32_t cur_stage_group =readl (addr); +uint32_t cur_stage_group =readl (&sdr_reg_file->cur_stage);/* Clear the stage and substage */ cur_stage_group &=0xFFFF0000 ;
@@ -130,15 +126,13 @@ static void reg_file_set_stage(uint32_t set_stage) cur_stage_group |= (set_stage &0x000000FF );/* Write the data back */ -writel (cur_stage_group, addr); +writel (cur_stage_group, &sdr_reg_file->cur_stage); }static void reg_file_set_sub_stage (uint32_t set_sub_stage) { -u32 addr = (u32)&sdr_reg_file->cur_stage; -/* Read the current group and stage */ -uint32_t cur_stage_group =readl (addr); +uint32_t cur_stage_group =readl (&sdr_reg_file->cur_stage);/* Clear the substage */ cur_stage_group &=0xFFFF00FF ;
@@ -147,13 +141,11 @@ static void reg_file_set_sub_stage(uint32_t set_sub_stage) cur_stage_group |= ((set_sub_stage <<8 ) &0x0000FF00 );/* Write the data back */ -writel (cur_stage_group, addr); +writel (cur_stage_group, &sdr_reg_file->cur_stage); }static void initialize (void ) { -u32 addr = (u32)&phy_mgr_cfg->mux_sel; -debug ("%s:%d\n" , __func__, __LINE__);/* USER calibration has control over path to memory */ /*
@@ -161,18 +153,15 @@ static void initialize(void)* 0: AFI Mux Select * 1: DDIO Mux Select */ -writel (0x3 , addr); +writel (0x3 , &phy_mgr_cfg->mux_sel);/* USER memory clock is not stable we begin initialization */ - addr = (u32)&phy_mgr_cfg->reset_mem_stbl; -writel (0 , addr); +writel (0 , &phy_mgr_cfg->reset_mem_stbl);/* USER calibration status all set to zero */ - addr = (u32)&phy_mgr_cfg->cal_status; -writel (0 , addr); +writel (0 , &phy_mgr_cfg->cal_status); - addr = (u32)&phy_mgr_cfg->cal_debug_info; -writel (0 , addr); +writel (0 , &phy_mgr_cfg->cal_debug_info);if ((dyn_calib_steps &CALIB_SKIP_ALL ) !=CALIB_SKIP_ALL ) { param->read_correct_mask_vg = ((uint32_t)1 <<
@@ -196,7 +185,6 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)uint32_t odt_mask_0 =0 ;uint32_t odt_mask_1 =0 ;uint32_t cs_and_odt_mask; -uint32_t addr;if (odt_mode ==RW_MGR_ODT_MODE_READ_WRITE ) {if (RW_MGR_MEM_NUMBER_OF_RANKS ==1 ) {
@@ -289,8 +277,8 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode) (0xFF & ~(1 << rank)) | ((0xFF & odt_mask_0) <<8 ) | ((0xFF & odt_mask_1) <<16 ); - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_SET_CS_AND_ODT_MASK_OFFSET ; -writel (cs_and_odt_mask, addr); +writel (cs_and_odt_mask,SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_SET_CS_AND_ODT_MASK_OFFSET ); }static void scc_mgr_initialize (void )
@@ -341,7 +329,6 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group, {uint32_t r;uint32_t update_scan_chains; -uint32_t addr;for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) {
@@ -358,11 +345,8 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,scc_mgr_set_dqs_en_phase (read_group, phase);if (update_scan_chains) { - addr = (u32)&sdr_scc_mgr->dqs_ena; -writel (read_group, addr); - - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (read_group, &sdr_scc_mgr->dqs_ena); +writel (0 , &sdr_scc_mgr->update); } } }
@@ -381,7 +365,6 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group, {uint32_t r;uint32_t update_scan_chains; -uint32_t addr;for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) {
@@ -398,11 +381,8 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,scc_mgr_set_dqdqs_output_phase (write_group, phase);if (update_scan_chains) { - addr = (u32)&sdr_scc_mgr->dqs_ena; -writel (write_group, addr); - - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (write_group, &sdr_scc_mgr->dqs_ena); +writel (0 , &sdr_scc_mgr->update); } } }
@@ -420,14 +400,12 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group, uint32_t delay) {uint32_t r; -uint32_t addr;for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) {scc_mgr_set_dqs_en_delay (read_group, delay); - addr = (u32)&sdr_scc_mgr->dqs_ena; -writel (read_group, addr); +writel (read_group, &sdr_scc_mgr->dqs_ena);/* * In shadow register mode, the T11 settings are stored in * registers in the core, which are updated by the DQS_ENA
@@ -436,8 +414,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,* select_shadow_regs_for_update with update_scan_chains * set to 0. */ - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update); }/* * In shadow register mode, the T11 settings are stored in
@@ -447,8 +424,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,* select_shadow_regs_for_update with update_scan_chains * set to 0. */ - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update); }static void scc_mgr_set_oct_out1_delay (uint32_t write_group,uint32_t delay)
@@ -531,7 +507,6 @@ static void scc_mgr_set_dm_out1_delay(uint32_t write_group,static void scc_mgr_zero_all (void ) {uint32_t i, r; -uint32_t addr;/* * USER Zero all DQS config settings, across all groups and all
@@ -558,16 +533,12 @@ static void scc_mgr_zero_all(void) }/* multicast to all DQS group enables */ - addr = (u32)&sdr_scc_mgr->dqs_ena; -writel (0xff , addr); - - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (0xff , &sdr_scc_mgr->dqs_ena); +writel (0 , &sdr_scc_mgr->update); }static void scc_set_bypass_mode (uint32_t write_group,uint32_t mode) { -uint32_t addr;/* mode = 0 : Do NOT bypass - Half Rate Mode */ /* mode = 1 : Bypass - Full Rate Mode */
@@ -580,30 +551,23 @@ static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode) __func__, __LINE__); }/* multicast to all DQ enables */ - addr = (u32)&sdr_scc_mgr->dq_ena; -writel (0xff , addr); - - addr = (u32)&sdr_scc_mgr->dm_ena; -writel (0xff , addr); +writel (0xff , &sdr_scc_mgr->dq_ena); +writel (0xff , &sdr_scc_mgr->dm_ena);/* update current DQS IO enable */ - addr = (u32)&sdr_scc_mgr->dqs_io_ena; -writel (0 , addr); +writel (0 , &sdr_scc_mgr->dqs_io_ena);/* update the DQS logic */ - addr = (u32)&sdr_scc_mgr->dqs_ena; -writel (write_group, addr); +writel (write_group, &sdr_scc_mgr->dqs_ena);/* hit update */ - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update); }static void scc_mgr_zero_group (uint32_t write_group,uint32_t test_begin,int32_t out_only) {uint32_t i, r; -uint32_t addr;for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) {
@@ -615,8 +579,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin, }/* multicast to all DQ enables */ - addr = (u32)&sdr_scc_mgr->dq_ena; -writel (0xff , addr); +writel (0xff , &sdr_scc_mgr->dq_ena);/* Zero all DM config settings */ for (i =0 ; i <RW_MGR_NUM_DM_PER_WRITE_GROUP ; i++) {
@@ -624,8 +587,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin, }/* multicast to all DM enables */ - addr = (u32)&sdr_scc_mgr->dm_ena; -writel (0xff , addr); +writel (0xff , &sdr_scc_mgr->dm_ena);/* zero all DQS io settings */ if (!out_only)
@@ -636,21 +598,17 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,scc_mgr_load_dqs_for_write_group (write_group);/* multicast to all DQS IO enables (only 1) */ - addr = (u32)&sdr_scc_mgr->dqs_io_ena; -writel (0 , addr); +writel (0 , &sdr_scc_mgr->dqs_io_ena);/* hit update to zero everything */ - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update); } }/* load up dqs config settings */ static void scc_mgr_load_dqs (uint32_t dqs) { -uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena; - -writel (dqs, addr); +writel (dqs, &sdr_scc_mgr->dqs_ena); }static void scc_mgr_load_dqs_for_write_group (uint32_t write_group)
@@ -673,25 +631,19 @@ static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)/* load up dqs io config settings */ static void scc_mgr_load_dqs_io (void ) { -uint32_t addr = (u32)&sdr_scc_mgr->dqs_io_ena; - -writel (0 , addr); +writel (0 , &sdr_scc_mgr->dqs_io_ena); }/* load up dq config settings */ static void scc_mgr_load_dq (uint32_t dq_in_group) { -uint32_t addr = (u32)&sdr_scc_mgr->dq_ena; - -writel (dq_in_group, addr); +writel (dq_in_group, &sdr_scc_mgr->dq_ena); }/* load up dm config settings */ static void scc_mgr_load_dm (uint32_t dm) { -uint32_t addr = (u32)&sdr_scc_mgr->dm_ena; - -writel (dm, addr); +writel (dm, &sdr_scc_mgr->dm_ena); }/*
@@ -830,13 +782,12 @@ static void scc_mgr_apply_group_all_out_delay_add_all_ranks( uint32_t write_group, uint32_t group_bgn, uint32_t delay) { uint32_t r; -uint32_t addr = (u32)&sdr_scc_mgr->update;for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) {scc_mgr_apply_group_all_out_delay_add (write_group, group_bgn, delay); -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update); } }
@@ -844,16 +795,13 @@ static void scc_mgr_apply_group_all_out_delay_add_all_ranks(/* could be applied to other protocols if we wanted to */ static void set_jump_as_return (void ) { -uint32_t addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0; -/* * to save space, we replace return with jump to special shared * RETURN instruction so we set the counter to large value so that * we always jump */ -writel (0xff , addr); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0; -writel (RW_MGR_RETURN , addr); +writel (0xff , &sdr_rw_load_mgr_regs->load_cntr0); +writel (RW_MGR_RETURN , &sdr_rw_load_jump_mgr_regs->load_jump_add0); }/*
@@ -866,7 +814,6 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)uint8_t inner =0 ;uint8_t outer =0 ;uint16_t c_loop =0 ; -uint32_t addr;debug ("%s:%d: clocks=%u ... start\n" , __func__, __LINE__, clocks);
@@ -915,36 +862,37 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)* overhead */ if (afi_clocks <=0x100 ) { - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1; -writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (inner), addr); +writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (inner), + &sdr_rw_load_mgr_regs->load_cntr1); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1; -writel (RW_MGR_IDLE_LOOP1 , addr); +writel (RW_MGR_IDLE_LOOP1 , + &sdr_rw_load_jump_mgr_regs->load_jump_add1); - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ; -writel (RW_MGR_IDLE_LOOP1 , addr); +writel (RW_MGR_IDLE_LOOP1 ,SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_RUN_SINGLE_GROUP_OFFSET ); }else { - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0; -writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (inner), addr); +writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (inner), + &sdr_rw_load_mgr_regs->load_cntr0); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1; -writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (outer), addr); +writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (outer), + &sdr_rw_load_mgr_regs->load_cntr1); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0; -writel (RW_MGR_IDLE_LOOP2 , addr); +writel (RW_MGR_IDLE_LOOP2 , + &sdr_rw_load_jump_mgr_regs->load_jump_add0); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1; -writel (RW_MGR_IDLE_LOOP2 , addr); +writel (RW_MGR_IDLE_LOOP2 , + &sdr_rw_load_jump_mgr_regs->load_jump_add1);/* hack to get around compiler not being smart enough */ if (afi_clocks <=0x10000 ) {/* only need to run once */ - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ; -writel (RW_MGR_IDLE_LOOP2 , addr); +writel (RW_MGR_IDLE_LOOP2 ,SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_RUN_SINGLE_GROUP_OFFSET ); }else {do { - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ; -writel (RW_MGR_IDLE_LOOP2 , addr); +writel (RW_MGR_IDLE_LOOP2 , +SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_RUN_SINGLE_GROUP_OFFSET ); }while (c_loop-- !=0 ); } }
@@ -954,13 +902,14 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)static void rw_mgr_mem_initialize (void ) {uint32_t r; -uint32_t addr; +uint32_t grpaddr =SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_RUN_SINGLE_GROUP_OFFSET ;debug ("%s:%d\n" , __func__, __LINE__);/* The reset / cke part of initialization is broadcasted to all ranks */ - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_SET_CS_AND_ODT_MASK_OFFSET ; -writel (RW_MGR_RANK_ALL , addr); +writel (RW_MGR_RANK_ALL ,SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_SET_CS_AND_ODT_MASK_OFFSET );/* * Here's how you load register for a loop
@@ -987,33 +936,26 @@ static void rw_mgr_mem_initialize(void)*/ /* Load counters */ - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TINIT_CNTR0_VAL ), - addr); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1; + &sdr_rw_load_mgr_regs->load_cntr0);writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TINIT_CNTR1_VAL ), - addr); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2; + &sdr_rw_load_mgr_regs->load_cntr1);writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TINIT_CNTR2_VAL ), - addr); + &sdr_rw_load_mgr_regs->load_cntr2);/* Load jump address */ - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0; -writel (RW_MGR_INIT_RESET_0_CKE_0 , addr); - - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1; -writel (RW_MGR_INIT_RESET_0_CKE_0 , addr); - - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2; -writel (RW_MGR_INIT_RESET_0_CKE_0 , addr); +writel (RW_MGR_INIT_RESET_0_CKE_0 , + &sdr_rw_load_jump_mgr_regs->load_jump_add0); +writel (RW_MGR_INIT_RESET_0_CKE_0 , + &sdr_rw_load_jump_mgr_regs->load_jump_add1); +writel (RW_MGR_INIT_RESET_0_CKE_0 , + &sdr_rw_load_jump_mgr_regs->load_jump_add2);/* Execute count instruction */ - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ; -writel (RW_MGR_INIT_RESET_0_CKE_0 , addr); +writel (RW_MGR_INIT_RESET_0_CKE_0 , grpaddr);/* indicate that memory is stable */ - addr = (u32)&phy_mgr_cfg->reset_mem_stbl; -writel (1 , addr); +writel (1 , &phy_mgr_cfg->reset_mem_stbl);/* * transition the RESET to high
@@ -1031,26 +973,22 @@ static void rw_mgr_mem_initialize(void)*/ /* Load counters */ - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TRESET_CNTR0_VAL ), - addr); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1; + &sdr_rw_load_mgr_regs->load_cntr0);writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TRESET_CNTR1_VAL ), - addr); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2; + &sdr_rw_load_mgr_regs->load_cntr1);writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TRESET_CNTR2_VAL ), - addr); + &sdr_rw_load_mgr_regs->load_cntr2);/* Load jump address */ - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0; -writel (RW_MGR_INIT_RESET_1_CKE_0 , addr); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1; -writel (RW_MGR_INIT_RESET_1_CKE_0 , addr); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2; -writel (RW_MGR_INIT_RESET_1_CKE_0 , addr); +writel (RW_MGR_INIT_RESET_1_CKE_0 , + &sdr_rw_load_jump_mgr_regs->load_jump_add0); +writel (RW_MGR_INIT_RESET_1_CKE_0 , + &sdr_rw_load_jump_mgr_regs->load_jump_add1); +writel (RW_MGR_INIT_RESET_1_CKE_0 , + &sdr_rw_load_jump_mgr_regs->load_jump_add2); - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ; -writel (RW_MGR_INIT_RESET_1_CKE_0 , addr); +writel (RW_MGR_INIT_RESET_1_CKE_0 , grpaddr);/* bring up clock enable */
@@ -1072,33 +1010,30 @@ static void rw_mgr_mem_initialize(void)*/ if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) &0x1 ) {set_jump_as_return (); - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ; -writel (RW_MGR_MRS2_MIRR , addr); +writel (RW_MGR_MRS2_MIRR , grpaddr);delay_for_n_mem_clocks (4 );set_jump_as_return (); -writel (RW_MGR_MRS3_MIRR , addr); +writel (RW_MGR_MRS3_MIRR , grpaddr);delay_for_n_mem_clocks (4 );set_jump_as_return (); -writel (RW_MGR_MRS1_MIRR , addr); +writel (RW_MGR_MRS1_MIRR , grpaddr);delay_for_n_mem_clocks (4 );set_jump_as_return (); -writel (RW_MGR_MRS0_DLL_RESET_MIRR , addr); +writel (RW_MGR_MRS0_DLL_RESET_MIRR , grpaddr); }else {set_jump_as_return (); - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ; -writel (RW_MGR_MRS2 , addr); +writel (RW_MGR_MRS2 , grpaddr);delay_for_n_mem_clocks (4 );set_jump_as_return (); -writel (RW_MGR_MRS3 , addr); +writel (RW_MGR_MRS3 , grpaddr);delay_for_n_mem_clocks (4 );set_jump_as_return (); -writel (RW_MGR_MRS1 , addr); +writel (RW_MGR_MRS1 , grpaddr);set_jump_as_return (); -writel (RW_MGR_MRS0_DLL_RESET , addr); +writel (RW_MGR_MRS0_DLL_RESET , grpaddr); }set_jump_as_return (); - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ; -writel (RW_MGR_ZQCL , addr); +writel (RW_MGR_ZQCL , grpaddr);/* tZQinit = tDLLK = 512 ck cycles */ delay_for_n_mem_clocks (512 );
@@ -1112,7 +1047,8 @@ static void rw_mgr_mem_initialize(void)static void rw_mgr_mem_handoff (void ) {uint32_t r; -uint32_t addr; +uint32_t grpaddr =SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_RUN_SINGLE_GROUP_OFFSET ;debug ("%s:%d\n" , __func__, __LINE__);for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r++) {
@@ -1123,8 +1059,7 @@ static void rw_mgr_mem_handoff(void)set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_OFF );/* precharge all banks ... */ - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ; -writel (RW_MGR_PRECHARGE_ALL , addr); +writel (RW_MGR_PRECHARGE_ALL , grpaddr);/* load up MR settings specified by user */
@@ -1132,31 +1067,30 @@ static void rw_mgr_mem_handoff(void)* Use Mirror-ed commands for odd ranks if address * mirrorring is on */ - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) &0x1 ) {set_jump_as_return (); -writel (RW_MGR_MRS2_MIRR , addr); +writel (RW_MGR_MRS2_MIRR , grpaddr);delay_for_n_mem_clocks (4 );set_jump_as_return (); -writel (RW_MGR_MRS3_MIRR , addr); +writel (RW_MGR_MRS3_MIRR , grpaddr);delay_for_n_mem_clocks (4 );set_jump_as_return (); -writel (RW_MGR_MRS1_MIRR , addr); +writel (RW_MGR_MRS1_MIRR , grpaddr);delay_for_n_mem_clocks (4 );set_jump_as_return (); -writel (RW_MGR_MRS0_USER_MIRR , addr); +writel (RW_MGR_MRS0_USER_MIRR , grpaddr); }else {set_jump_as_return (); -writel (RW_MGR_MRS2 , addr); +writel (RW_MGR_MRS2 , grpaddr);delay_for_n_mem_clocks (4 );set_jump_as_return (); -writel (RW_MGR_MRS3 , addr); +writel (RW_MGR_MRS3 , grpaddr);delay_for_n_mem_clocks (4 );set_jump_as_return (); -writel (RW_MGR_MRS1 , addr); +writel (RW_MGR_MRS1 , grpaddr);delay_for_n_mem_clocks (4 );set_jump_as_return (); -writel (RW_MGR_MRS0_USER , addr); +writel (RW_MGR_MRS0_USER , grpaddr); }/* * USER need to wait tMOD (12CK or 15ns) time before issuing
@@ -1194,24 +1128,21 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_READ_WRITE );/* Load up a constant bursts of read commands */ - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0; -writel (0x20 , addr); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0; -writel (RW_MGR_GUARANTEED_READ , addr); +writel (0x20 , &sdr_rw_load_mgr_regs->load_cntr0); +writel (RW_MGR_GUARANTEED_READ , + &sdr_rw_load_jump_mgr_regs->load_jump_add0); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1; -writel (0x20 , addr); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1; -writel (RW_MGR_GUARANTEED_READ_CONT , addr); +writel (0x20 , &sdr_rw_load_mgr_regs->load_cntr1); +writel (RW_MGR_GUARANTEED_READ_CONT , + &sdr_rw_load_jump_mgr_regs->load_jump_add1); tmp_bit_chk =0 ;for (vg =RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS -1 ; ; vg--) {/* reset the fifos to get pointers to known state */ - addr = (u32)&phy_mgr_cmd->fifo_reset; -writel (0 , addr); - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RESET_READ_DATAPATH_OFFSET ; -writel (0 , addr); +writel (0 , &phy_mgr_cmd->fifo_reset); +writel (0 ,SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_RESET_READ_DATAPATH_OFFSET ); tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS /RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS );
@@ -1221,8 +1152,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn, ((group *RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS + vg) << 2)); - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS ; - base_rw_mgr =readl (addr); + base_rw_mgr =readl (SDR_PHYGRP_RWMGRGRP_ADDRESS ); tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));if (vg ==0 )
@@ -1253,7 +1183,6 @@ static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn, uint32_t all_ranks) {uint32_t r; -uint32_t addr;uint32_t rank_end = all_ranks ?RW_MGR_MEM_NUMBER_OF_RANKS : (rank_bgn +NUM_RANKS_PER_SHADOW_REG );
@@ -1267,32 +1196,28 @@ static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_READ_WRITE );/* Load up a constant bursts */ - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0; -writel (0x20 , addr); +writel (0x20 , &sdr_rw_load_mgr_regs->load_cntr0); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0; -writel (RW_MGR_GUARANTEED_WRITE_WAIT0 , addr); +writel (RW_MGR_GUARANTEED_WRITE_WAIT0 , + &sdr_rw_load_jump_mgr_regs->load_jump_add0); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1; -writel (0x20 , addr); +writel (0x20 , &sdr_rw_load_mgr_regs->load_cntr1); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1; -writel (RW_MGR_GUARANTEED_WRITE_WAIT1 , addr); +writel (RW_MGR_GUARANTEED_WRITE_WAIT1 , + &sdr_rw_load_jump_mgr_regs->load_jump_add1); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2; -writel (0x04 , addr); +writel (0x04 , &sdr_rw_load_mgr_regs->load_cntr2); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2; -writel (RW_MGR_GUARANTEED_WRITE_WAIT2 , addr); +writel (RW_MGR_GUARANTEED_WRITE_WAIT2 , + &sdr_rw_load_jump_mgr_regs->load_jump_add2); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3; -writel (0x04 , addr); +writel (0x04 , &sdr_rw_load_mgr_regs->load_cntr3); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3; -writel (RW_MGR_GUARANTEED_WRITE_WAIT3 , addr); +writel (RW_MGR_GUARANTEED_WRITE_WAIT3 , + &sdr_rw_load_jump_mgr_regs->load_jump_add3); - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ; -writel (RW_MGR_GUARANTEED_WRITE , addr); +writel (RW_MGR_GUARANTEED_WRITE ,SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_RUN_SINGLE_GROUP_OFFSET ); }set_rank_and_odt_mask (0 ,RW_MGR_ODT_MODE_OFF );
@@ -1329,46 +1254,41 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group/* set rank */ set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_READ_WRITE ); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1; -writel (0x10 , addr); +writel (0x10 , &sdr_rw_load_mgr_regs->load_cntr1); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1; -writel (RW_MGR_READ_B2B_WAIT1 , addr); +writel (RW_MGR_READ_B2B_WAIT1 , + &sdr_rw_load_jump_mgr_regs->load_jump_add1); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2; -writel (0x10 , addr); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2; -writel (RW_MGR_READ_B2B_WAIT2 , addr); +writel (0x10 , &sdr_rw_load_mgr_regs->load_cntr2); +writel (RW_MGR_READ_B2B_WAIT2 , + &sdr_rw_load_jump_mgr_regs->load_jump_add2); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;if (quick_read_mode) -writel (0x1 , addr); +writel (0x1 , &sdr_rw_load_mgr_regs->load_cntr0);/* need at least two (1+1) reads to capture failures */ else if (all_groups) -writel (0x06 , addr); +writel (0x06 , &sdr_rw_load_mgr_regs->load_cntr0);else -writel (0x32 , addr); +writel (0x32 , &sdr_rw_load_mgr_regs->load_cntr0); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0; -writel (RW_MGR_READ_B2B , addr); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3; +writel (RW_MGR_READ_B2B , + &sdr_rw_load_jump_mgr_regs->load_jump_add0);if (all_groups)writel (RW_MGR_MEM_IF_READ_DQS_WIDTH *RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS -1 , - addr); + &sdr_rw_load_mgr_regs->load_cntr3);else -writel (0x0 , addr); +writel (0x0 , &sdr_rw_load_mgr_regs->load_cntr3); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3; -writel (RW_MGR_READ_B2B , addr); +writel (RW_MGR_READ_B2B , + &sdr_rw_load_jump_mgr_regs->load_jump_add3); tmp_bit_chk =0 ;for (vg =RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS -1 ; ; vg--) {/* reset the fifos to get pointers to known state */ - addr = (u32)&phy_mgr_cmd->fifo_reset; -writel (0 , addr); - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RESET_READ_DATAPATH_OFFSET ; -writel (0 , addr); +writel (0 , &phy_mgr_cmd->fifo_reset); +writel (0 ,SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_RESET_READ_DATAPATH_OFFSET ); tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS /RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS );
@@ -1382,8 +1302,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group ((group *RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS + vg) << 2)); - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS ; - base_rw_mgr =readl (addr); + base_rw_mgr =readl (SDR_PHYGRP_RWMGRGRP_ADDRESS ); tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));if (vg ==0 )
@@ -1423,9 +1342,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,static void rw_mgr_incr_vfifo (uint32_t grp,uint32_t *v) { -uint32_t addr = (u32)&phy_mgr_cmd->inc_vfifo_hard_phy; - -writel (grp, addr); +writel (grp, &phy_mgr_cmd->inc_vfifo_hard_phy); (*v)++; }
@@ -1687,7 +1604,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)uint32_t dtaps_per_ptap;uint32_t work_bgn, work_mid, work_end;uint32_t found_passing_read, found_failing_read, initial_failing_dtap; -uint32_t addr;debug ("%s:%d %u\n" , __func__, __LINE__, grp);
@@ -1887,8 +1803,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)if (found_passing_read && found_failing_read) dtaps_per_ptap = d - initial_failing_dtap; - addr = (u32)&sdr_reg_file->dtaps_per_ptap; -writel (dtaps_per_ptap, addr); +writel (dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);debug_cond (DLEVEL ==2 ,"%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \ - %u = %u" , __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
@@ -1918,7 +1833,6 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delayuint32_t p;uint32_t d;uint32_t r; -uint32_t addr;const uint32_t delay_step =IO_IO_IN_DELAY_MAX / (RW_MGR_MEM_DQ_PER_READ_DQS -1 );
@@ -1941,8 +1855,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delayscc_mgr_set_dq_in_delay (write_group, p, d);scc_mgr_load_dq (p); } - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update); } found =rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase (read_group);
@@ -1959,8 +1872,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delayscc_mgr_set_dq_in_delay (write_group, p,0 );scc_mgr_load_dq (p); } - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update); }return found;
@@ -2006,12 +1918,11 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, right_edge[i] =IO_IO_IN_DELAY_MAX +1 ; } - addr = (u32)&sdr_scc_mgr->update;/* Search for the left edge of the window for each bit */ for (d =0 ; d <=IO_IO_IN_DELAY_MAX ; d++) {scc_mgr_apply_group_dq_in_delay (write_group, test_bgn, d); -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update);/* * Stop searching when the read test doesn't pass AND when
@@ -2095,7 +2006,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,break ; } - addr = (u32)&sdr_scc_mgr->update;/* Search for the right edge of the window for each bit */ for (d =0 ; d <=IO_DQS_IN_DELAY_MAX - start_dqs; d++) {scc_mgr_set_dqs_bus_in_delay (read_group, d + start_dqs);
@@ -2107,7 +2017,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, }scc_mgr_load_dqs (read_group); -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update);/* * Stop searching when the read test doesn't pass AND when
@@ -2188,7 +2098,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, }/* Check that all bits have a window */ - addr = (u32)&sdr_scc_mgr->update;for (i =0 ; i <RW_MGR_MEM_DQ_PER_READ_DQS ; i++) { debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \ %d right_edge[%u]: %d", __func__, __LINE__,
@@ -2206,7 +2115,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, start_dqs_en); }scc_mgr_load_dqs (read_group); -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update); debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \ find edge [%u]: %d %d", __func__, __LINE__,
@@ -2280,7 +2189,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, dqs_margin =IO_IO_IN_DELAY_MAX +1 ; dq_margin =IO_IO_IN_DELAY_MAX +1 ; - addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_IN_DELAY_OFFSET ;/* add delay to bring centre of all DQ windows to the same "level" */ for (i =0 , p = test_bgn; i <RW_MGR_MEM_DQ_PER_READ_DQS ; i++, p++) {/* Use values before divide by 2 to reduce round off error */
@@ -2291,6 +2199,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,debug_cond (DLEVEL ==2 ,"vfifo_center: before: \ shift_dq[%u]=%d\n" , i, shift_dq); + addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_IN_DELAY_OFFSET ; temp_dq_in_delay1 =readl (addr + (p <<2 )); temp_dq_in_delay2 =readl (addr + (i <<2 ));
@@ -2338,8 +2247,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,* Do not remove this line as it makes sure all of our decisions * have been applied. Apply the update bit. */ - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update);return (dq_margin >=0 ) && (dqs_margin >=0 ); }
@@ -2534,7 +2442,6 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void) {uint32_t found_one;uint32_t bit_chk; -uint32_t addr;debug ("%s:%d\n" , __func__, __LINE__);
@@ -2546,9 +2453,8 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void)rw_mgr_mem_calibrate_read_load_patterns (0 ,1 ); found_one =0 ; - addr = (u32)&phy_mgr_cfg->phy_rlat; do { - writel(gbl->curr_read_lat, addr); + writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u", __func__, __LINE__, gbl->curr_read_lat);
@@ -2567,14 +2473,12 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void)/* reset the fifos to get pointers to known state */ - addr = (u32)&phy_mgr_cmd->fifo_reset; -writel (0 , addr); +writel (0 , &phy_mgr_cmd->fifo_reset);if (found_one) {/* add a fudge factor to the read latency that was determined */ gbl->curr_read_lat +=2 ; - addr = (u32)&phy_mgr_cfg->phy_rlat; -writel (gbl->curr_read_lat, addr); +writel (gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);debug_cond (DLEVEL ==2 ,"%s:%d lfifo: success: using \ read_lat=%u\n" , __func__, __LINE__, gbl->curr_read_lat);
@@ -2639,24 +2543,21 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,* instruction that sends out the data. We set the counter to a * large number so that the jump is always taken. */ - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2; -writel (0xFF , addr); +writel (0xFF , &sdr_rw_load_mgr_regs->load_cntr2);/* CNTR 3 - Not used */ if (test_dm) { mcc_instruction =RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 ; - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;writel (RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA , - addr); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3; + &sdr_rw_load_jump_mgr_regs->load_jump_add2);writel (RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP , - addr); + &sdr_rw_load_jump_mgr_regs->load_jump_add3); }else { mcc_instruction =RW_MGR_LFSR_WR_RD_BANK_0_WL_1 ; - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2; -writel (RW_MGR_LFSR_WR_RD_BANK_0_DATA , addr); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3; -writel (RW_MGR_LFSR_WR_RD_BANK_0_NOP , addr); +writel (RW_MGR_LFSR_WR_RD_BANK_0_DATA , + &sdr_rw_load_jump_mgr_regs->load_jump_add2); +writel (RW_MGR_LFSR_WR_RD_BANK_0_NOP , + &sdr_rw_load_jump_mgr_regs->load_jump_add3); } }else if (rw_wl_nop_cycles ==0 ) {/*
@@ -2664,19 +2565,17 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,* to the DQS enable instruction. We set the counter to a large * number so that the jump is always taken. */ - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2; -writel (0xFF , addr); +writel (0xFF , &sdr_rw_load_mgr_regs->load_cntr2);/* CNTR 3 - Not used */ if (test_dm) { mcc_instruction =RW_MGR_LFSR_WR_RD_DM_BANK_0 ; - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;writel (RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS , - addr); + &sdr_rw_load_jump_mgr_regs->load_jump_add2); }else { mcc_instruction =RW_MGR_LFSR_WR_RD_BANK_0 ; - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2; -writel (RW_MGR_LFSR_WR_RD_BANK_0_DQS , addr); +writel (RW_MGR_LFSR_WR_RD_BANK_0_DQS , + &sdr_rw_load_jump_mgr_regs->load_jump_add2); } }else {/*
@@ -2684,52 +2583,47 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,* and NOT take the jump. So we set the counter to 0. The jump * address doesn't count. */ - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2; -writel (0x0 , addr); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2; -writel (0x0 , addr); +writel (0x0 , &sdr_rw_load_mgr_regs->load_cntr2); +writel (0x0 , &sdr_rw_load_jump_mgr_regs->load_jump_add2);/* * CNTR 3 - Set the nop counter to the number of cycles we * need to loop for, minus 1. */ - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3; -writel (rw_wl_nop_cycles -1 , addr); +writel (rw_wl_nop_cycles -1 , &sdr_rw_load_mgr_regs->load_cntr3);if (test_dm) { mcc_instruction =RW_MGR_LFSR_WR_RD_DM_BANK_0 ; - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3; -writel (RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP , addr); +writel (RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP , + &sdr_rw_load_jump_mgr_regs->load_jump_add3); }else { mcc_instruction =RW_MGR_LFSR_WR_RD_BANK_0 ; - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3; -writel (RW_MGR_LFSR_WR_RD_BANK_0_NOP , addr); +writel (RW_MGR_LFSR_WR_RD_BANK_0_NOP , + &sdr_rw_load_jump_mgr_regs->load_jump_add3); } } - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RESET_READ_DATAPATH_OFFSET ; -writel (0 , addr); +writel (0 ,SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_RESET_READ_DATAPATH_OFFSET ); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;if (quick_write_mode) -writel (0x08 , addr); +writel (0x08 , &sdr_rw_load_mgr_regs->load_cntr0);else -writel (0x40 , addr); +writel (0x40 , &sdr_rw_load_mgr_regs->load_cntr0); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0; -writel (mcc_instruction, addr); +writel (mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);/* * CNTR 1 - This is used to ensure enough time elapses * for read data to come back. */ - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1; -writel (0x30 , addr); +writel (0x30 , &sdr_rw_load_mgr_regs->load_cntr1); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;if (test_dm) { -writel (RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT , addr); +writel (RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT , + &sdr_rw_load_jump_mgr_regs->load_jump_add1); }else { -writel (RW_MGR_LFSR_WR_RD_BANK_0_WAIT , addr); +writel (RW_MGR_LFSR_WR_RD_BANK_0_WAIT , + &sdr_rw_load_jump_mgr_regs->load_jump_add1); } addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;
@@ -2741,7 +2635,6 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn, uint32_t write_group, uint32_t use_dm, uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks) { - uint32_t addr; uint32_t r;uint32_t correct_mask_vg;uint32_t tmp_bit_chk;
@@ -2764,11 +2657,10 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_READ_WRITE ); tmp_bit_chk =0 ; - addr = (u32)&phy_mgr_cmd->fifo_reset; addr_rw_mgr =SDR_PHYGRP_RWMGRGRP_ADDRESS ;for (vg =RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS -1 ; ; vg--) {/* reset the fifos to get pointers to known state */ -writel (0 , addr); +writel (0 , &phy_mgr_cmd->fifo_reset); tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_WRITE_DQS /
@@ -2849,11 +2741,10 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, }/* Search for the left edge of the window for each bit */ - addr = (u32)&sdr_scc_mgr->update;for (d =0 ; d <=IO_IO_OUT1_DELAY_MAX ; d++) {scc_mgr_apply_group_dq_out1_delay (write_group, test_bgn, d); -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update);/* * Stop searching when the read test doesn't pass AND when
@@ -2933,12 +2824,11 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, }/* Search for the right edge of the window for each bit */ - addr = (u32)&sdr_scc_mgr->update;for (d =0 ; d <=IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, d + start_dqs); -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update);/* * Stop searching when the read test doesn't pass AND when
@@ -3071,7 +2961,6 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, dq_margin =IO_IO_OUT1_DELAY_MAX +1 ;/* add delay to bring centre of all DQ windows to the same "level" */ - addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ;for (i =0 , p = test_bgn; i <RW_MGR_MEM_DQ_PER_WRITE_DQS ; i++, p++) {/* Use values before divide by 2 to reduce round off error */ shift_dq = (left_edge[i] - right_edge[i] -
@@ -3081,6 +2970,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,debug_cond (DLEVEL ==2 ,"%s:%d write_center: before: shift_dq \ [%u]=%d\n" , __func__, __LINE__, i, shift_dq); + addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ; temp_dq_out1_delay =readl (addr + (i <<2 ));if (shift_dq + (int32_t )temp_dq_out1_delay > (int32_t )IO_IO_OUT1_DELAY_MAX ) {
@@ -3107,8 +2997,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,/* Move DQS */ scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, new_dqs); - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update);/* Centre DM */ debug_cond (DLEVEL ==2 ,"%s:%d write_center: DM\n" , __func__, __LINE__);
@@ -3126,10 +3015,9 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,int32_t win_best =0 ;/* Search for the/part of the window with DM shift */ - addr = (u32)&sdr_scc_mgr->update;for (d =IO_IO_OUT1_DELAY_MAX ; d >=0 ; d -=DELTA_D ) {scc_mgr_apply_group_dm_out1_delay (write_group, d); -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update); if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1, PASS_ALL_BITS, &bit_chk,
@@ -3173,7 +3061,6 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, }/* Search for the/part of the window with DQS shifts */ - addr = (u32)&sdr_scc_mgr->update;for (d =0 ; d <=IO_IO_OUT1_DELAY_MAX - new_dqs; d +=DELTA_D ) {/* * Note: This only shifts DQS, so are we limiting ourselve to
@@ -3182,7 +3069,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, d + new_dqs); -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update);if (rw_mgr_mem_calibrate_write_test (rank_bgn, write_group,1 ,PASS_ALL_BITS , &bit_chk,0 )) {
@@ -3245,8 +3132,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, dm_margin = left_edge[0 ] - mid;scc_mgr_apply_group_dm_out1_delay (write_group, mid); - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update); debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \ dm_margin=%d\n", __func__, __LINE__, left_edge[0],
@@ -3262,8 +3148,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,* Do not remove this line as it makes sure all of our * decisions have been applied. */ - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update);return (dq_margin >=0 ) && (dqs_margin >=0 ) && (dm_margin >=0 ); }
@@ -3292,7 +3177,6 @@ static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,static void mem_precharge_and_activate (void ) {uint32_t r; -uint32_t addr;for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r++) {if (param->skip_ranks[r]) {
@@ -3304,22 +3188,20 @@ static void mem_precharge_and_activate(void)set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_OFF );/* precharge all banks ... */ - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ; -writel (RW_MGR_PRECHARGE_ALL , addr); +writel (RW_MGR_PRECHARGE_ALL ,SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_RUN_SINGLE_GROUP_OFFSET ); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0; -writel (0x0F , addr); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0; -writel (RW_MGR_ACTIVATE_0_AND_1_WAIT1 , addr); +writel (0x0F , &sdr_rw_load_mgr_regs->load_cntr0); +writel (RW_MGR_ACTIVATE_0_AND_1_WAIT1 , + &sdr_rw_load_jump_mgr_regs->load_jump_add0); - addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1; -writel (0x0F , addr); - addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1; -writel (RW_MGR_ACTIVATE_0_AND_1_WAIT2 , addr); +writel (0x0F , &sdr_rw_load_mgr_regs->load_cntr1); +writel (RW_MGR_ACTIVATE_0_AND_1_WAIT2 , + &sdr_rw_load_jump_mgr_regs->load_jump_add1);/* activate rows */ - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ; -writel (RW_MGR_ACTIVATE_0_AND_1 , addr); +writel (RW_MGR_ACTIVATE_0_AND_1 ,SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_RUN_SINGLE_GROUP_OFFSET ); } }
@@ -3329,15 +3211,12 @@ static void mem_config(void)uint32_t rlat, wlat;uint32_t rw_wl_nop_cycles;uint32_t max_latency; -uint32_t addr;debug ("%s:%d\n" , __func__, __LINE__);/* read in write and read latency */ - addr = (u32)&data_mgr->t_wl_add; - wlat =readl (addr); + wlat =readl (&data_mgr->t_wl_add); + wlat +=readl (&data_mgr->mem_t_add); - addr = (u32)&data_mgr->mem_t_add; - wlat +=readl (addr);/* WL for hard phy does not include additive latency */ /*
@@ -3347,8 +3226,7 @@ static void mem_config(void)*/ wlat = wlat +1 ; - addr = (u32)&data_mgr->t_rl_add; - rlat =readl (addr); + rlat =readl (&data_mgr->t_rl_add); rw_wl_nop_cycles = wlat -2 ; gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
@@ -3370,13 +3248,11 @@ static void mem_config(void)if (gbl->curr_read_lat > max_latency) gbl->curr_read_lat = max_latency; - addr = (u32)&phy_mgr_cfg->phy_rlat; -writel (gbl->curr_read_lat, addr); +writel (gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);/* advertise write latency */ gbl->curr_write_lat = wlat; - addr = (u32)&phy_mgr_cfg->afi_wlat; -writel (wlat -2 , addr); +writel (wlat -2 , &phy_mgr_cfg->afi_wlat);/* initialize bit slips */ mem_precharge_and_activate ();
@@ -3387,7 +3263,6 @@ static void mem_skip_calibrate(void) {uint32_t vfifo_offset;uint32_t i, j, r; -uint32_t addr;debug ("%s:%d\n" , __func__, __LINE__);/* Need to update every shadow register set used by the interface */
@@ -3432,21 +3307,16 @@ static void mem_skip_calibrate(void)scc_mgr_set_dqdqs_output_phase (i, (1.25 *IO_DLL_CHAIN_LENGTH -2 )); } - addr = (u32)&sdr_scc_mgr->dqs_ena; -writel (0xff , addr); - addr = (u32)&sdr_scc_mgr->dqs_io_ena; -writel (0xff , addr); +writel (0xff , &sdr_scc_mgr->dqs_ena); +writel (0xff , &sdr_scc_mgr->dqs_io_ena); - addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_GROUP_COUNTER_OFFSET ;for (i =0 ; i <RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; i++) { -writel (i, addr); +writel (i,SDR_PHYGRP_SCCGRP_ADDRESS | +SCC_MGR_GROUP_COUNTER_OFFSET ); } - addr = (u32)&sdr_scc_mgr->dq_ena; -writel (0xff , addr); - addr = (u32)&sdr_scc_mgr->dm_ena; -writel (0xff , addr); - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (0xff , &sdr_scc_mgr->dq_ena); +writel (0xff , &sdr_scc_mgr->dm_ena); +writel (0 , &sdr_scc_mgr->update); }/* Compensate for simulation model behaviour */
@@ -3454,28 +3324,24 @@ static void mem_skip_calibrate(void)scc_mgr_set_dqs_bus_in_delay (i,10 );scc_mgr_load_dqs (i); } - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update);/* * ArriaV has hard FIFOs that can only be initialized by incrementing * in sequencer. */ vfifo_offset =CALIB_VFIFO_OFFSET ; - addr = (u32)&phy_mgr_cmd->inc_vfifo_hard_phy;for (j =0 ; j < vfifo_offset; j++) { -writel (0xff , addr); +writel (0xff , &phy_mgr_cmd->inc_vfifo_hard_phy); } - addr = (u32)&phy_mgr_cmd->fifo_reset; -writel (0 , addr); +writel (0 , &phy_mgr_cmd->fifo_reset);/* * For ACV with hard lfifo, we get the skip-cal setting from * generation-time constant. */ gbl->curr_read_lat =CALIB_LFIFO_OFFSET ; - addr = (u32)&phy_mgr_cfg->phy_rlat; -writel (gbl->curr_read_lat, addr); +writel (gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); }/* Memory calibration entry point */
@@ -3489,7 +3355,6 @@ static uint32_t mem_calibrate(void)uint32_t failing_groups =0 ;uint32_t group_failed =0 ;uint32_t sr_failed =0 ; -uint32_t addr;debug ("%s:%d\n" , __func__, __LINE__);/* Initialize the data settings */
@@ -3503,9 +3368,9 @@ static uint32_t mem_calibrate(void)mem_config ();uint32_t bypass_mode =0x1 ; - addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_GROUP_COUNTER_OFFSET ;for (i =0 ; i <RW_MGR_MEM_IF_READ_DQS_WIDTH ; i++) { -writel (i, addr); +writel (i,SDR_PHYGRP_SCCGRP_ADDRESS | +SCC_MGR_GROUP_COUNTER_OFFSET );scc_set_bypass_mode (i, bypass_mode); }
@@ -3539,8 +3404,8 @@ static uint32_t mem_calibrate(void)if (current_run ==0 )continue ; - addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_GROUP_COUNTER_OFFSET ; -writel (write_group, addr); +writel (write_group,SDR_PHYGRP_SCCGRP_ADDRESS | +SCC_MGR_GROUP_COUNTER_OFFSET );scc_mgr_zero_group (write_group, write_test_bgn,0 );
@@ -3664,8 +3529,7 @@ static uint32_t mem_calibrate(void)* Do not remove this line as it makes sure all of our decisions * have been applied. */ - addr = (u32)&sdr_scc_mgr->update; -writel (0 , addr); +writel (0 , &sdr_scc_mgr->update);return 1 ; }
@@ -3673,13 +3537,11 @@ static uint32_t run_mem_calibrate(void) {uint32_t pass;uint32_t debug_info; -uint32_t addr;debug ("%s:%d\n" , __func__, __LINE__);/* Reset pass/fail status shown on afi_cal_success/fail */ - addr = (u32)&phy_mgr_cfg->cal_status; -writel (PHY_MGR_CAL_RESET , addr); +writel (PHY_MGR_CAL_RESET , &phy_mgr_cfg->cal_status);/* stop tracking manger */ uint32_t ctrlcfg =readl (&sdr_ctrl->ctrl_cfg);
@@ -3692,8 +3554,7 @@ static uint32_t run_mem_calibrate(void) pass =mem_calibrate ();mem_precharge_and_activate (); - addr = (u32)&phy_mgr_cmd->fifo_reset; -writel (0 , addr); +writel (0 , &phy_mgr_cmd->fifo_reset);/* * Handoff:
@@ -3706,8 +3567,7 @@ static uint32_t run_mem_calibrate(void)* 0: AFI Mux Select * 1: DDIO Mux Select */ - addr = (u32)&phy_mgr_cfg->mux_sel; -writel (0x2 , addr); +writel (0x2 , &phy_mgr_cfg->mux_sel); }writel (ctrlcfg, &sdr_ctrl->ctrl_cfg);
@@ -3727,13 +3587,10 @@ static uint32_t run_mem_calibrate(void)/* Update the FOM in the register file */ debug_info = gbl->fom_in; debug_info |= gbl->fom_out <<8 ; - addr = (u32)&sdr_reg_file->fom; -writel (debug_info, addr); +writel (debug_info, &sdr_reg_file->fom); - addr = (u32)&phy_mgr_cfg->cal_debug_info; -writel (debug_info, addr); - addr = (u32)&phy_mgr_cfg->cal_status; -writel (PHY_MGR_CAL_SUCCESS , addr); +writel (debug_info, &phy_mgr_cfg->cal_debug_info); +writel (PHY_MGR_CAL_SUCCESS , &phy_mgr_cfg->cal_status); }else {printf ("%s: CALIBRATION FAILED\n" , __FILE__);
@@ -3741,19 +3598,15 @@ static uint32_t run_mem_calibrate(void) debug_info |= gbl->error_substage <<8 ; debug_info |= gbl->error_group <<16 ; - addr = (u32)&sdr_reg_file->failing_stage; -writel (debug_info, addr); - addr = (u32)&phy_mgr_cfg->cal_debug_info; -writel (debug_info, addr); - addr = (u32)&phy_mgr_cfg->cal_status; -writel (PHY_MGR_CAL_FAIL , addr); +writel (debug_info, &sdr_reg_file->failing_stage); +writel (debug_info, &phy_mgr_cfg->cal_debug_info); +writel (PHY_MGR_CAL_FAIL , &phy_mgr_cfg->cal_status);/* Update the failing group/stage in the register file */ debug_info = gbl->error_stage; debug_info |= gbl->error_substage <<8 ; debug_info |= gbl->error_group <<16 ; - addr = (u32)&sdr_reg_file->failing_stage; -writel (debug_info, addr); +writel (debug_info, &sdr_reg_file->failing_stage); }return pass;
@@ -3779,29 +3632,14 @@ static void hc_initialize_rom_data(void)static void initialize_reg_file (void ) { -uint32_t addr; -/* Initialize the register file with the correct data */ - addr = (u32)&sdr_reg_file->signature; -writel (REG_FILE_INIT_SEQ_SIGNATURE , addr); - - addr = (u32)&sdr_reg_file->debug_data_addr; -writel (0 , addr); - - addr = (u32)&sdr_reg_file->cur_stage; -writel (0 , addr); - - addr = (u32)&sdr_reg_file->fom; -writel (0 , addr); - - addr = (u32)&sdr_reg_file->failing_stage; -writel (0 , addr); - - addr = (u32)&sdr_reg_file->debug1; -writel (0 , addr); - - addr = (u32)&sdr_reg_file->debug2; -writel (0 , addr); +writel (REG_FILE_INIT_SEQ_SIGNATURE , &sdr_reg_file->signature); +writel (0 , &sdr_reg_file->debug_data_addr); +writel (0 , &sdr_reg_file->cur_stage); +writel (0 , &sdr_reg_file->fom); +writel (0 , &sdr_reg_file->failing_stage); +writel (0 , &sdr_reg_file->debug1); +writel (0 , &sdr_reg_file->debug2); }static void initialize_hps_phy (void )
@@ -3858,7 +3696,6 @@ static void initialize_tracking(void)uint32_t trk_sample_count =7500 ;uint32_t dtaps_per_ptap;uint32_t tmp_delay; -uint32_t addr;/* * compute usable version of value in case we skip full
@@ -3902,26 +3739,13 @@ static void initialize_tracking(void) concatenated_refresh = concatenated_refresh ^1000 ;/* trefi */ /* Initialize the register file with the correct data */ - addr = (u32)&sdr_reg_file->dtaps_per_ptap; -writel (dtaps_per_ptap, addr); - - addr = (u32)&sdr_reg_file->trk_sample_count; -writel (trk_sample_count, addr); - - addr = (u32)&sdr_reg_file->trk_longidle; -writel (concatenated_longidle, addr); - - addr = (u32)&sdr_reg_file->delays; -writel (concatenated_delays, addr); - - addr = (u32)&sdr_reg_file->trk_rw_mgr_addr; -writel (concatenated_rw_addr, addr); - - addr = (u32)&sdr_reg_file->trk_read_dqs_width; -writel (RW_MGR_MEM_IF_READ_DQS_WIDTH , addr); - - addr = (u32)&sdr_reg_file->trk_rfsh; -writel (concatenated_refresh, addr); +writel (dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap); +writel (trk_sample_count, &sdr_reg_file->trk_sample_count); +writel (concatenated_longidle, &sdr_reg_file->trk_longidle); +writel (concatenated_delays, &sdr_reg_file->delays); +writel (concatenated_rw_addr, &sdr_reg_file->trk_rw_mgr_addr); +writel (RW_MGR_MEM_IF_READ_DQS_WIDTH , &sdr_reg_file->trk_read_dqs_width); +writel (concatenated_refresh, &sdr_reg_file->trk_rfsh); }int sdram_calibration_full (void )
Signature · 1 line
2.1.4
PATCH 53/172 ddr: altera: Clean up hc_initialize_rom_data()
In reply to Marek VasutClean the function up, fix data types, add kerneldoc.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)
drivers/ddr/altera/sequencer.c +10 -10
@@ -3612,22 +3612,22 @@ static uint32_t run_mem_calibrate(void)return pass; } +/** +* hc_initialize_rom_data() - Initialize ROM data +* +* Initialize ROM data. +*/ static void hc_initialize_rom_data (void ) { -uint32_t i; -uint32_t addr; +u32 i, addr; addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_INST_ROM_WRITE_OFFSET ; -for (i =0 ; i <ARRAY_SIZE (inst_rom_init); i++) { -uint32_t data = inst_rom_init[i]; -writel (data, addr + (i <<2 )); - } +for (i =0 ; i <ARRAY_SIZE (inst_rom_init); i++) +writel (inst_rom_init[i], addr + (i <<2 )); addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_AC_ROM_WRITE_OFFSET ; -for (i =0 ; i <ARRAY_SIZE (ac_rom_init); i++) { -uint32_t data = ac_rom_init[i]; -writel (data, addr + (i <<2 )); - } +for (i =0 ; i <ARRAY_SIZE (ac_rom_init); i++) +writel (ac_rom_init[i], addr + (i <<2 )); }static void initialize_reg_file (void )
Signature · 1 line
2.1.4
PATCH 54/172 ddr: altera: Clean up initialize_reg_file()
In reply to Marek VasutAdd brief kerneldoc.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 5 +++++ 1 file changed, 5 insertions(+)
drivers/ddr/altera/sequencer.c +5 -0
@@ -3630,6 +3630,11 @@ static void hc_initialize_rom_data(void)writel (ac_rom_init[i], addr + (i <<2 )); } +/** +* initialize_reg_file() - Initialize SDR register file +* +* Initialize SDR register file. +*/ static void initialize_reg_file (void ) {/* Initialize the register file with the correct data */
Signature · 1 line
2.1.4
PATCH 55/172 ddr: altera: Clean up initialize_hps_phy()
In reply to Marek VasutAdd brief kerneldoc.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 5 +++++ 1 file changed, 5 insertions(+)
drivers/ddr/altera/sequencer.c +5 -0
@@ -3647,6 +3647,11 @@ static void initialize_reg_file(void)writel (0 , &sdr_reg_file->debug2); } +/** +* initialize_hps_phy() - Initialize HPS PHY +* +* Initialize HPS PHY. +*/ static void initialize_hps_phy (void ) {uint32_t reg;
Signature · 1 line
2.1.4
PATCH 56/172 ddr: altera: Clean up reg_file_set*()
In reply to Marek VasutTurn the insides of these functions into trivial clrsetbits_le32() and fix the data type of their argument to reflect it's actual size.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 43 +++++++----------------------------------- 1 file changed, 7 insertions(+), 36 deletions(-)
drivers/ddr/altera/sequencer.c +7 -36
@@ -99,49 +99,20 @@ static void set_failing_group_stage(uint32_t group, uint32_t stage, } } -static void reg_file_set_group (uint32_t set_group) +static void reg_file_set_group (u16 set_group) { -/* Read the current group and stage */ -uint32_t cur_stage_group =readl (&sdr_reg_file->cur_stage); - -/* Clear the group */ - cur_stage_group &=0x0000FFFF ; - -/* Set the group */ - cur_stage_group |= (set_group <<16 ); - -/* Write the data back */ -writel (cur_stage_group, &sdr_reg_file->cur_stage); +clrsetbits_le32 (&sdr_reg_file->cur_stage,0xffff0000 , set_group <<16 ); } -static void reg_file_set_stage (uint32_t set_stage) +static void reg_file_set_stage (u8 set_stage) { -/* Read the current group and stage */ -uint32_t cur_stage_group =readl (&sdr_reg_file->cur_stage); - -/* Clear the stage and substage */ - cur_stage_group &=0xFFFF0000 ; - -/* Set the stage */ - cur_stage_group |= (set_stage &0x000000FF ); - -/* Write the data back */ -writel (cur_stage_group, &sdr_reg_file->cur_stage); +clrsetbits_le32 (&sdr_reg_file->cur_stage,0xffff , set_stage &0xff ); } -static void reg_file_set_sub_stage (uint32_t set_sub_stage) +static void reg_file_set_sub_stage (u8 set_sub_stage) { -/* Read the current group and stage */ -uint32_t cur_stage_group =readl (&sdr_reg_file->cur_stage); - -/* Clear the substage */ - cur_stage_group &=0xFFFF00FF ; - -/* Set the sub stage */ - cur_stage_group |= ((set_sub_stage <<8 ) &0x0000FF00 ); - -/* Write the data back */ -writel (cur_stage_group, &sdr_reg_file->cur_stage); + set_sub_stage &=0xff ; +clrsetbits_le32 (&sdr_reg_file->cur_stage,0xff00 , set_sub_stage <<8 ); }static void initialize (void )
Signature · 1 line
2.1.4
PATCH 57/172 ddr: altera: Clean up scc manager function args
In reply to Marek VasutClean up the unused args of the functions used to configure the SCC manager.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-)
drivers/ddr/altera/sequencer.c +13 -17
@@ -417,8 +417,7 @@ static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)writel (delay, addr + (read_group <<2 )); } -static void scc_mgr_set_dq_out1_delay (uint32_t write_group, -uint32_t dq_in_group,uint32_t delay) +static void scc_mgr_set_dq_out1_delay (uint32_t dq_in_group,uint32_t delay) {uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ;
@@ -426,8 +425,7 @@ static void scc_mgr_set_dq_out1_delay(uint32_t write_group,writel (delay, addr + (dq_in_group <<2 )); } -static void scc_mgr_set_dq_in_delay (uint32_t write_group, -uint32_t dq_in_group,uint32_t delay) +static void scc_mgr_set_dq_in_delay (uint32_t dq_in_group,uint32_t delay) {uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_IN_DELAY_OFFSET ;
@@ -461,8 +459,7 @@ static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,writel (delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS <<2 )); } -static void scc_mgr_set_dm_out1_delay (uint32_t write_group, -uint32_t dm,uint32_t delay) +static void scc_mgr_set_dm_out1_delay (uint32_t dm,uint32_t delay) {uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ;
@@ -544,9 +541,9 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin, NUM_RANKS_PER_SHADOW_REG) {/* Zero all DQ config settings */ for (i =0 ; i <RW_MGR_MEM_DQ_PER_WRITE_DQS ; i++) { -scc_mgr_set_dq_out1_delay (write_group, i,0 ); +scc_mgr_set_dq_out1_delay (i,0 );if (!out_only) -scc_mgr_set_dq_in_delay (write_group, i,0 ); +scc_mgr_set_dq_in_delay (i,0 ); }/* multicast to all DQ enables */
@@ -554,7 +551,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,/* Zero all DM config settings */ for (i =0 ; i <RW_MGR_NUM_DM_PER_WRITE_GROUP ; i++) { -scc_mgr_set_dm_out1_delay (write_group, i,0 ); +scc_mgr_set_dm_out1_delay (i,0 ); }/* multicast to all DM enables */
@@ -627,7 +624,7 @@ static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group,uint32_t i, p;for (i =0 , p = group_bgn; i <RW_MGR_MEM_DQ_PER_READ_DQS ; i++, p++) { -scc_mgr_set_dq_in_delay (write_group, p, delay); +scc_mgr_set_dq_in_delay (p, delay);scc_mgr_load_dq (p); } }
@@ -640,7 +637,7 @@ static void scc_mgr_apply_group_dq_out1_delay(uint32_t write_group,uint32_t i, p;for (i =0 , p = group_bgn; i <RW_MGR_MEM_DQ_PER_WRITE_DQS ; i++, p++) { -scc_mgr_set_dq_out1_delay (write_group, i, delay1); +scc_mgr_set_dq_out1_delay (i, delay1);scc_mgr_load_dq (i); } }
@@ -652,7 +649,7 @@ static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group,uint32_t i;for (i =0 ; i <RW_MGR_NUM_DM_PER_WRITE_GROUP ; i++) { -scc_mgr_set_dm_out1_delay (write_group, i, delay1); +scc_mgr_set_dm_out1_delay (i, delay1);scc_mgr_load_dm (i); } }
@@ -1823,7 +1820,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delaydebug_cond (DLEVEL ==1 ,"en_phase_sweep_dq_in_delay: g=%u/%u " , write_group, read_group);debug_cond (DLEVEL ==1 ,"r=%u, i=%u p=%u d=%u\n" , r, i , p, d); -scc_mgr_set_dq_in_delay (write_group, p, d); +scc_mgr_set_dq_in_delay (p, d);scc_mgr_load_dq (p); }writel (0 , &sdr_scc_mgr->update);
@@ -1840,7 +1837,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay r += NUM_RANKS_PER_SHADOW_REG) {for (i =0 , p = test_bgn; i <RW_MGR_MEM_DQ_PER_READ_DQS ; i++, p++) { -scc_mgr_set_dq_in_delay (write_group, p,0 ); +scc_mgr_set_dq_in_delay (p,0 );scc_mgr_load_dq (p); }writel (0 , &sdr_scc_mgr->update);
@@ -2183,7 +2180,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,debug_cond (DLEVEL ==2 ,"vfifo_center: after: \ shift_dq[%u]=%d\n" , i, shift_dq); final_dq[i] = temp_dq_in_delay1 + shift_dq; -scc_mgr_set_dq_in_delay (write_group, p, final_dq[i]); +scc_mgr_set_dq_in_delay (p, final_dq[i]);scc_mgr_load_dq (p); debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
@@ -2951,8 +2948,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, }debug_cond (DLEVEL ==2 ,"write_center: after: shift_dq[%u]=%d\n" , i, shift_dq); -scc_mgr_set_dq_out1_delay (write_group, i, temp_dq_out1_delay + - shift_dq); +scc_mgr_set_dq_out1_delay (i, temp_dq_out1_delay + shift_dq);scc_mgr_load_dq (i); debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
Signature · 1 line
2.1.4
PATCH 58/172 ddr: altera: Reorder scc manager functions
In reply to Marek VasutThis patch just puts functions which look similar next to each other, so they can be sorted out. No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 195 ++++++++++++++++++++--------------------- 1 file changed, 95 insertions(+), 100 deletions(-)
drivers/ddr/altera/sequencer.c +95 -100
@@ -270,8 +270,15 @@ static void scc_mgr_initialize(void) } } -static void scc_mgr_set_dqs_bus_in_delay (uint32_t read_group, -uint32_t delay) +static void scc_mgr_set_dqdqs_output_phase (uint32_t write_group,uint32_t phase) +{ +u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQDQS_OUT_PHASE_OFFSET ; + +/* Load the setting in the SCC manager */ +writel (phase, addr + (write_group <<2 )); +} + +static void scc_mgr_set_dqs_bus_in_delay (uint32_t read_group,uint32_t delay) {u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQS_IN_DELAY_OFFSET ;
@@ -279,20 +286,84 @@ static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group,writel (delay, addr + (read_group <<2 )); } -static void scc_mgr_set_dqs_io_in_delay (uint32_t write_group, -uint32_t delay) +static void scc_mgr_set_dqs_en_phase (uint32_t read_group,uint32_t phase) +{ +u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQS_EN_PHASE_OFFSET ; + +/* Load the setting in the SCC manager */ +writel (phase, addr + (read_group <<2 )); +} + +static void scc_mgr_set_dqs_en_delay (uint32_t read_group,uint32_t delay) +{ +uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQS_EN_DELAY_OFFSET ; + +/* Load the setting in the SCC manager */ +writel (delay +IO_DQS_EN_DELAY_OFFSET , addr + (read_group <<2 )); +} + +static void scc_mgr_set_dqs_io_in_delay (uint32_t write_group,uint32_t delay) {u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_IN_DELAY_OFFSET ;writel (delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS <<2 )); } -static void scc_mgr_set_dqs_en_phase (uint32_t read_group,uint32_t phase) +static void scc_mgr_set_dq_in_delay (uint32_t dq_in_group,uint32_t delay) { -u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQS_EN_PHASE_OFFSET ; +uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_IN_DELAY_OFFSET ;/* Load the setting in the SCC manager */ -writel (phase, addr + (read_group <<2 )); +writel (delay, addr + (dq_in_group <<2 )); +} + +static void scc_mgr_set_dq_out1_delay (uint32_t dq_in_group,uint32_t delay) +{ +uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ; + +/* Load the setting in the SCC manager */ +writel (delay, addr + (dq_in_group <<2 )); +} + +static void scc_mgr_set_dqs_out1_delay (uint32_t write_group, +uint32_t delay) +{ +uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ; + +/* Load the setting in the SCC manager */ +writel (delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS <<2 )); +} + +static void scc_mgr_set_dm_out1_delay (uint32_t dm,uint32_t delay) +{ +uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ; + +/* Load the setting in the SCC manager */ +writel (delay, addr + ((RW_MGR_MEM_DQ_PER_WRITE_DQS +1 + dm) <<2 )); +} + +/* load up dqs config settings */ +static void scc_mgr_load_dqs (uint32_t dqs) +{ +writel (dqs, &sdr_scc_mgr->dqs_ena); +} + +/* load up dqs io config settings */ +static void scc_mgr_load_dqs_io (void ) +{ +writel (0 , &sdr_scc_mgr->dqs_io_ena); +} + +/* load up dq config settings */ +static void scc_mgr_load_dq (uint32_t dq_in_group) +{ +writel (dq_in_group, &sdr_scc_mgr->dq_ena); +} + +/* load up dm config settings */ +static void scc_mgr_load_dm (uint32_t dm) +{ +writel (dm, &sdr_scc_mgr->dm_ena); } static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
@@ -322,15 +393,6 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group, } } -static void scc_mgr_set_dqdqs_output_phase (uint32_t write_group, -uint32_t phase) -{ -u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQDQS_OUT_PHASE_OFFSET ; - -/* Load the setting in the SCC manager */ -writel (phase, addr + (write_group <<2 )); -} -static void scc_mgr_set_dqdqs_output_phase_all_ranks (uint32_t write_group,uint32_t phase) {
@@ -358,15 +420,6 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group, } } -static void scc_mgr_set_dqs_en_delay (uint32_t read_group,uint32_t delay) -{ -uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQS_EN_DELAY_OFFSET ; - -/* Load the setting in the SCC manager */ -writel (delay +IO_DQS_EN_DELAY_OFFSET , addr + - (read_group <<2 )); -} -static void scc_mgr_set_dqs_en_delay_all_ranks (uint32_t read_group,uint32_t delay) {
@@ -417,22 +470,6 @@ static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)writel (delay, addr + (read_group <<2 )); } -static void scc_mgr_set_dq_out1_delay (uint32_t dq_in_group,uint32_t delay) -{ -uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ; - -/* Load the setting in the SCC manager */ -writel (delay, addr + (dq_in_group <<2 )); -} - -static void scc_mgr_set_dq_in_delay (uint32_t dq_in_group,uint32_t delay) -{ -uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_IN_DELAY_OFFSET ; - -/* Load the setting in the SCC manager */ -writel (delay, addr + (dq_in_group <<2 )); -} -static void scc_mgr_set_hhp_extras (void ) {/*
@@ -450,24 +487,6 @@ static void scc_mgr_set_hhp_extras(void)writel (value, addr +SCC_MGR_HHP_EXTRAS_OFFSET ); } -static void scc_mgr_set_dqs_out1_delay (uint32_t write_group, -uint32_t delay) -{ -uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ; - -/* Load the setting in the SCC manager */ -writel (delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS <<2 )); -} - -static void scc_mgr_set_dm_out1_delay (uint32_t dm,uint32_t delay) -{ -uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ; - -/* Load the setting in the SCC manager */ -writel (delay, addr + - ((RW_MGR_MEM_DQ_PER_WRITE_DQS +1 + dm) <<2 )); -} -/* * USER Zero all DQS config * TODO: maybe rename to scc_mgr_zero_dqs_config (or something)
@@ -532,6 +551,23 @@ static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)writel (0 , &sdr_scc_mgr->update); } +static void scc_mgr_load_dqs_for_write_group (uint32_t write_group) +{ +uint32_t read_group; +uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena; +/* +* Although OCT affects only write data, the OCT delay is controlled +* by the DQS logic block which is instantiated once per read group. +* For protocols where a write group consists of multiple read groups, +* the setting must be scanned multiple times. +*/ +for (read_group = write_group *RW_MGR_MEM_IF_READ_DQS_WIDTH / +RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; + read_group < (write_group +1 ) *RW_MGR_MEM_IF_READ_DQS_WIDTH / +RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; ++read_group) +writel (read_group, addr); +} +static void scc_mgr_zero_group (uint32_t write_group,uint32_t test_begin,int32_t out_only) {
@@ -573,47 +609,6 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin, } } -/* load up dqs config settings */ -static void scc_mgr_load_dqs (uint32_t dqs) -{ -writel (dqs, &sdr_scc_mgr->dqs_ena); -} - -static void scc_mgr_load_dqs_for_write_group (uint32_t write_group) -{ -uint32_t read_group; -uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena; -/* -* Although OCT affects only write data, the OCT delay is controlled -* by the DQS logic block which is instantiated once per read group. -* For protocols where a write group consists of multiple read groups, -* the setting must be scanned multiple times. -*/ -for (read_group = write_group *RW_MGR_MEM_IF_READ_DQS_WIDTH / -RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; - read_group < (write_group +1 ) *RW_MGR_MEM_IF_READ_DQS_WIDTH / -RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; ++read_group) -writel (read_group, addr); -} - -/* load up dqs io config settings */ -static void scc_mgr_load_dqs_io (void ) -{ -writel (0 , &sdr_scc_mgr->dqs_io_ena); -} - -/* load up dq config settings */ -static void scc_mgr_load_dq (uint32_t dq_in_group) -{ -writel (dq_in_group, &sdr_scc_mgr->dq_ena); -} - -/* load up dm config settings */ -static void scc_mgr_load_dm (uint32_t dm) -{ -writel (dm, &sdr_scc_mgr->dm_ena); -} -/* * apply and load a particular input delay for the DQ pins in a group * group_bgn is the index of the first dq pin (in the write group)
Signature · 1 line
2.1.4
PATCH 59/172 ddr: altera: Implement universal scc manager config function
In reply to Marek VasutImplement unified scc_mgr_set() function and convert all those 9 scc_mgr_set_*() ad-hoc functions to call this one function.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 69 ++++++++++++++++++------------------------ 1 file changed, 29 insertions(+), 40 deletions(-)
drivers/ddr/altera/sequencer.c +29 -40
@@ -252,94 +252,83 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode) RW_MGR_SET_CS_AND_ODT_MASK_OFFSET); } -static void scc_mgr_initialize (void ) +/** +* scc_mgr_set() - Set SCC Manager register +* @off: Base offset in SCC Manager space +* @grp: Read/Write group +* @val: Value to be set +* +* This function sets the SCC Manager (Scan Chain Control Manager) register. +*/ +static void scc_mgr_set (u32 off,u32 grp,u32 val) { -u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_HHP_RFILE_OFFSET ; +writel (val,SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp <<2 )); +} +static void scc_mgr_initialize (void ) +{/* * Clear register file for HPS * 16 (2^4) is the size of the full register file in the scc mgr: * RFILE_DEPTH = log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS + -* MEM_IF_READ_DQS_WIDTH - 1) + 1; +* MEM_IF_READ_DQS_WIDTH - 1) + 1; */ -uint32_t i; +int i;for (i =0 ; i <16 ; i++) {debug_cond (DLEVEL ==1 ,"%s:%d: Clearing SCC RFILE index %u\n" , __func__, __LINE__, i); -writel (0 , addr + (i <<2 )); +scc_mgr_set (SCC_MGR_HHP_RFILE_OFFSET ,0 , i); } }static void scc_mgr_set_dqdqs_output_phase (uint32_t write_group,uint32_t phase) { -u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQDQS_OUT_PHASE_OFFSET ; - -/* Load the setting in the SCC manager */ -writel (phase, addr + (write_group <<2 )); +scc_mgr_set (SCC_MGR_DQDQS_OUT_PHASE_OFFSET , write_group, phase); }static void scc_mgr_set_dqs_bus_in_delay (uint32_t read_group,uint32_t delay) { -u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQS_IN_DELAY_OFFSET ; - -/* Load the setting in the SCC manager */ -writel (delay, addr + (read_group <<2 )); +scc_mgr_set (SCC_MGR_DQS_IN_DELAY_OFFSET , read_group, delay); }static void scc_mgr_set_dqs_en_phase (uint32_t read_group,uint32_t phase) { -u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQS_EN_PHASE_OFFSET ; - -/* Load the setting in the SCC manager */ -writel (phase, addr + (read_group <<2 )); +scc_mgr_set (SCC_MGR_DQS_EN_PHASE_OFFSET , read_group, phase); }static void scc_mgr_set_dqs_en_delay (uint32_t read_group,uint32_t delay) { -uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_DQS_EN_DELAY_OFFSET ; - -/* Load the setting in the SCC manager */ -writel (delay +IO_DQS_EN_DELAY_OFFSET , addr + (read_group <<2 )); +scc_mgr_set (SCC_MGR_DQS_EN_DELAY_OFFSET , read_group, delay); }static void scc_mgr_set_dqs_io_in_delay (uint32_t write_group,uint32_t delay) { -u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_IN_DELAY_OFFSET ; - -writel (delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS <<2 )); +scc_mgr_set (SCC_MGR_IO_IN_DELAY_OFFSET ,RW_MGR_MEM_DQ_PER_WRITE_DQS , + delay); }static void scc_mgr_set_dq_in_delay (uint32_t dq_in_group,uint32_t delay) { -uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_IN_DELAY_OFFSET ; - -/* Load the setting in the SCC manager */ -writel (delay, addr + (dq_in_group <<2 )); +scc_mgr_set (SCC_MGR_IO_IN_DELAY_OFFSET , dq_in_group, delay); }static void scc_mgr_set_dq_out1_delay (uint32_t dq_in_group,uint32_t delay) { -uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ; - -/* Load the setting in the SCC manager */ -writel (delay, addr + (dq_in_group <<2 )); +scc_mgr_set (SCC_MGR_IO_OUT1_DELAY_OFFSET , dq_in_group, delay); }static void scc_mgr_set_dqs_out1_delay (uint32_t write_group,uint32_t delay) { -uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ; - -/* Load the setting in the SCC manager */ -writel (delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS <<2 )); +scc_mgr_set (SCC_MGR_IO_OUT1_DELAY_OFFSET ,RW_MGR_MEM_DQ_PER_WRITE_DQS , + delay); }static void scc_mgr_set_dm_out1_delay (uint32_t dm,uint32_t delay) { -uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_IO_OUT1_DELAY_OFFSET ; - -/* Load the setting in the SCC manager */ -writel (delay, addr + ((RW_MGR_MEM_DQ_PER_WRITE_DQS +1 + dm) <<2 )); +scc_mgr_set (SCC_MGR_IO_OUT1_DELAY_OFFSET , +RW_MGR_MEM_DQ_PER_WRITE_DQS +1 + dm, + delay); }/* load up dqs config settings */
Signature · 1 line
2.1.4
PATCH 60/172 ddr: altera: Clean up scc_mgr_initialize()
In reply to Marek VasutClean up the comments and add kerneldoc. No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
drivers/ddr/altera/sequencer.c +10 -4
@@ -265,15 +265,21 @@ static void scc_mgr_set(u32 off, u32 grp, u32 val)writel (val,SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp <<2 )); } +/** +* scc_mgr_initialize() - Initialize SCC Manager registers +* +* Initialize SCC Manager registers. +*/ static void scc_mgr_initialize (void ) {/* -* Clear register file for HPS -* 16 (2^4) is the size of the full register file in the scc mgr: -* RFILE_DEPTH = log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS + -* MEM_IF_READ_DQS_WIDTH - 1) + 1; +* Clear register file for HPS. 16 (2^4) is the size of the +* full register file in the scc mgr: +* RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS + +* MEM_IF_READ_DQS_WIDTH - 1); */ int i; +for (i =0 ; i <16 ; i++) {debug_cond (DLEVEL ==1 ,"%s:%d: Clearing SCC RFILE index %u\n" , __func__, __LINE__, i);
Signature · 1 line
2.1.4
PATCH 61/172 ddr: altera: Shuffle around scc_mgr_set_*all_ranks()
In reply to Marek VasutShuffle the code around a bit, but without any functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-)
drivers/ddr/altera/sequencer.c +8 -11
@@ -365,10 +365,11 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group, uint32_t phase) {uint32_t r; -uint32_t update_scan_chains;for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) { +scc_mgr_set_dqs_en_phase (read_group, phase); +/* * USER although the h/w doesn't support different phases per * shadow register, for simplicity our scc manager modeling
@@ -377,11 +378,8 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,* for efficiency, the scan chain update should occur only * once to sr0. */ - update_scan_chains = (r ==0 ) ?1 :0 ; - -scc_mgr_set_dqs_en_phase (read_group, phase); -if (update_scan_chains) { +if (r ==0 ) {writel (read_group, &sdr_scc_mgr->dqs_ena);writel (0 , &sdr_scc_mgr->update); }
@@ -392,10 +390,11 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group, uint32_t phase) {uint32_t r; -uint32_t update_scan_chains;for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) { +scc_mgr_set_dqdqs_output_phase (write_group, phase); +/* * USER although the h/w doesn't support different phases per * shadow register, for simplicity our scc manager modeling
@@ -404,11 +403,8 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,* for efficiency, the scan chain update should occur only * once to sr0. */ - update_scan_chains = (r ==0 ) ?1 :0 ; -scc_mgr_set_dqdqs_output_phase (write_group, phase); - -if (update_scan_chains) { +if (r ==0 ) {writel (write_group, &sdr_scc_mgr->dqs_ena);writel (0 , &sdr_scc_mgr->update); }
@@ -424,7 +420,6 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group, r += NUM_RANKS_PER_SHADOW_REG) {scc_mgr_set_dqs_en_delay (read_group, delay); -writel (read_group, &sdr_scc_mgr->dqs_ena);/* * In shadow register mode, the T11 settings are stored in * registers in the core, which are updated by the DQS_ENA
@@ -433,6 +428,8 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,* select_shadow_regs_for_update with update_scan_chains * set to 0. */ + +writel (read_group, &sdr_scc_mgr->dqs_ena);writel (0 , &sdr_scc_mgr->update); }/*
Signature · 1 line
2.1.4
PATCH 62/172 ddr: altera: Implement universal scc_mgr_set_all_ranks()
In reply to Marek VasutImplement universal scc_mgr_set_all_ranks() function and convert various ad-hoc implementations of similar functionality to use this single function. Document the function in kerneldoc.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 95 +++++++++++++++++++----------------------- 1 file changed, 42 insertions(+), 53 deletions(-)
drivers/ddr/altera/sequencer.c +42 -53
@@ -361,77 +361,64 @@ static void scc_mgr_load_dm(uint32_t dm)writel (dm, &sdr_scc_mgr->dm_ena); } -static void scc_mgr_set_dqs_en_phase_all_ranks (uint32_t read_group, -uint32_t phase) +/** +* scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks +* @off: Base offset in SCC Manager space +* @grp: Read/Write group +* @val: Value to be set +* @update: If non-zero, trigger SCC Manager update for all ranks +* +* This function sets the SCC Manager (Scan Chain Control Manager) register +* and optionally triggers the SCC update for all ranks. +*/ +static void scc_mgr_set_all_ranks (const u32 off,const u32 grp,const u32 val, +const int update) { -uint32_t r; +u32 r;for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) { -scc_mgr_set_dqs_en_phase (read_group, phase); - -/* -* USER although the h/w doesn't support different phases per -* shadow register, for simplicity our scc manager modeling -* keeps different phase settings per shadow reg, and it's -* important for us to keep them in sync to match h/w. -* for efficiency, the scan chain update should occur only -* once to sr0. -*/ +scc_mgr_set (off, grp, val); -if (r ==0 ) { -writel (read_group, &sdr_scc_mgr->dqs_ena); +if (update || (r ==0 )) { +writel (grp, &sdr_scc_mgr->dqs_ena);writel (0 , &sdr_scc_mgr->update); } } } +static void scc_mgr_set_dqs_en_phase_all_ranks (u32 read_group,u32 phase) +{ +/* +* USER although the h/w doesn't support different phases per +* shadow register, for simplicity our scc manager modeling +* keeps different phase settings per shadow reg, and it's +* important for us to keep them in sync to match h/w. +* for efficiency, the scan chain update should occur only +* once to sr0. +*/ +scc_mgr_set_all_ranks (SCC_MGR_DQS_EN_PHASE_OFFSET , + read_group, phase,0 ); +} +static void scc_mgr_set_dqdqs_output_phase_all_ranks (uint32_t write_group,uint32_t phase) { -uint32_t r; - -for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; - r +=NUM_RANKS_PER_SHADOW_REG ) { -scc_mgr_set_dqdqs_output_phase (write_group, phase); - -/* -* USER although the h/w doesn't support different phases per -* shadow register, for simplicity our scc manager modeling -* keeps different phase settings per shadow reg, and it's -* important for us to keep them in sync to match h/w. -* for efficiency, the scan chain update should occur only -* once to sr0. -*/ - -if (r ==0 ) { -writel (write_group, &sdr_scc_mgr->dqs_ena); -writel (0 , &sdr_scc_mgr->update); - } - } +/* +* USER although the h/w doesn't support different phases per +* shadow register, for simplicity our scc manager modeling +* keeps different phase settings per shadow reg, and it's +* important for us to keep them in sync to match h/w. +* for efficiency, the scan chain update should occur only +* once to sr0. +*/ +scc_mgr_set_all_ranks (SCC_MGR_DQDQS_OUT_PHASE_OFFSET , + write_group, phase,0 ); }static void scc_mgr_set_dqs_en_delay_all_ranks (uint32_t read_group,uint32_t delay) { -uint32_t r; - -for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; - r +=NUM_RANKS_PER_SHADOW_REG ) { -scc_mgr_set_dqs_en_delay (read_group, delay); - -/* -* In shadow register mode, the T11 settings are stored in -* registers in the core, which are updated by the DQS_ENA -* signals. Not issuing the SCC_MGR_UPD command allows us to -* save lots of rank switching overhead, by calling -* select_shadow_regs_for_update with update_scan_chains -* set to 0. -*/ - -writel (read_group, &sdr_scc_mgr->dqs_ena); -writel (0 , &sdr_scc_mgr->update); - }/* * In shadow register mode, the T11 settings are stored in * registers in the core, which are updated by the DQS_ENA
@@ -440,6 +427,8 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,* select_shadow_regs_for_update with update_scan_chains * set to 0. */ +scc_mgr_set_all_ranks (SCC_MGR_DQS_EN_DELAY_OFFSET , + read_group, delay,1 );writel (0 , &sdr_scc_mgr->update); }
Signature · 1 line
2.1.4
PATCH 63/172 ddr: altera: Clean up scc_mgr_load_dqs_for_write_group()
In reply to Marek VasutMake this function more readable, no functional change. Also, zap the forward declaration, which is no longer needed.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-)
drivers/ddr/altera/sequencer.c +15 -11
@@ -13,8 +13,6 @@#include "sequencer_auto_inst_init.h" #include "sequencer_defines.h" -static void scc_mgr_load_dqs_for_write_group (uint32_t write_group); -static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs = (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS |0x800 );
@@ -532,21 +530,27 @@ static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)writel (0 , &sdr_scc_mgr->update); } -static void scc_mgr_load_dqs_for_write_group (uint32_t write_group) +/** +* scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group +* @write_group: Write group +* +* Load DQS settings for Write Group, do not trigger SCC update. +*/ +static void scc_mgr_load_dqs_for_write_group (const u32 write_group) { -uint32_t read_group; -uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena; +const int ratio =RW_MGR_MEM_IF_READ_DQS_WIDTH / +RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; +const int base = write_group * ratio; +int i;/* +* Load the setting in the SCC manager * Although OCT affects only write data, the OCT delay is controlled * by the DQS logic block which is instantiated once per read group. * For protocols where a write group consists of multiple read groups, -* the setting must be scanned multiple times. +* the setting must be set multiple times. */ -for (read_group = write_group *RW_MGR_MEM_IF_READ_DQS_WIDTH / -RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; - read_group < (write_group +1 ) *RW_MGR_MEM_IF_READ_DQS_WIDTH / -RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; ++read_group) -writel (read_group, addr); +for (i =0 ; i < ratio; i++) +writel (base + i, &sdr_scc_mgr->dqs_ena); } static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
Signature · 1 line
2.1.4
PATCH 64/172 ddr: altera: Clean up scc_set_bypass_mode()
In reply to Marek VasutThe mode argument of this function is not used at all, zap it.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-)
drivers/ddr/altera/sequencer.c +14 -11
@@ -503,12 +503,15 @@ static void scc_mgr_zero_all(void)writel (0 , &sdr_scc_mgr->update); } -static void scc_set_bypass_mode (uint32_t write_group,uint32_t mode) +/** +* scc_set_bypass_mode() - Set bypass mode and trigger SCC update +* @write_group: Write group +* +* Set bypass mode and trigger SCC update. +*/ +static void scc_set_bypass_mode (const u32 write_group) { -/* mode = 0 : Do NOT bypass - Half Rate Mode */ -/* mode = 1 : Bypass - Full Rate Mode */ - -/* only need to set once for all groups, pins, dq, dqs, dm */ +/* Only needed once to set all groups, pins, DQ, DQS, DM. */ if (write_group ==0 ) {debug_cond (DLEVEL ==1 ,"%s:%d Setting HHP Extras\n" , __func__, __LINE__);
@@ -516,17 +519,18 @@ static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)debug_cond (DLEVEL ==1 ,"%s:%d Done Setting HHP Extras\n" , __func__, __LINE__); } -/* multicast to all DQ enables */ + +/* Multicast to all DQ enables. */ writel (0xff , &sdr_scc_mgr->dq_ena);writel (0xff , &sdr_scc_mgr->dm_ena); -/* update current DQS IO enable */ +/* Update current DQS IO enable. */ writel (0 , &sdr_scc_mgr->dqs_io_ena); -/* update the DQS logic */ +/* Update the DQS logic. */ writel (write_group, &sdr_scc_mgr->dqs_ena); -/* hit update */ +/* Hit update. */ writel (0 , &sdr_scc_mgr->update); }
@@ -3314,11 +3318,10 @@ static uint32_t mem_calibrate(void)mem_config (); -uint32_t bypass_mode =0x1 ;for (i =0 ; i <RW_MGR_MEM_IF_READ_DQS_WIDTH ; i++) {writel (i,SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_GROUP_COUNTER_OFFSET ); -scc_set_bypass_mode (i, bypass_mode); +scc_set_bypass_mode (i); }if ((dyn_calib_steps &CALIB_SKIP_ALL ) ==CALIB_SKIP_ALL ) {
Signature · 1 line
2.1.4
PATCH 65/172 ddr: altera: Clean up scc_mgr_set_oct_out1_delay()
In reply to Marek VasutMake this function more readable, no functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-)
drivers/ddr/altera/sequencer.c +14 -9
@@ -430,11 +430,19 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,writel (0 , &sdr_scc_mgr->update); } -static void scc_mgr_set_oct_out1_delay (uint32_t write_group,uint32_t delay) +/** +* scc_mgr_set_oct_out1_delay() - Set OCT output delay +* @write_group: Write group +* @delay: Delay value +* +* This function sets the OCT output delay in SCC manager. +*/ +static void scc_mgr_set_oct_out1_delay (const u32 write_group,const u32 delay) { -uint32_t read_group; -uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_OCT_OUT1_DELAY_OFFSET ; - +const int ratio =RW_MGR_MEM_IF_READ_DQS_WIDTH / +RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; +const int base = write_group * ratio; +int i;/* * Load the setting in the SCC manager * Although OCT affects only write data, the OCT delay is controlled
@@ -442,11 +450,8 @@ static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)* For protocols where a write group consists of multiple read groups, * the setting must be set multiple times. */ -for (read_group = write_group *RW_MGR_MEM_IF_READ_DQS_WIDTH / -RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; - read_group < (write_group +1 ) *RW_MGR_MEM_IF_READ_DQS_WIDTH / -RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; ++read_group) -writel (delay, addr + (read_group <<2 )); +for (i =0 ; i < ratio; i++) +scc_mgr_set (SCC_MGR_OCT_OUT1_DELAY_OFFSET , base + i, delay); }static void scc_mgr_set_hhp_extras (void )
Signature · 1 line
2.1.4
PATCH 66/172 ddr: altera: Clean up scc_mgr_apply_group_dq_out1_delay()
In reply to Marek VasutRemove unused write_group and group_bgn argument from this function. Document the function using kerneldoc.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-)
drivers/ddr/altera/sequencer.c +12 -9
@@ -618,15 +618,18 @@ static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group, } } -/* apply and load a particular output delay for the DQ pins in a group */ -static void scc_mgr_apply_group_dq_out1_delay (uint32_t write_group, -uint32_t group_bgn, -uint32_t delay1) +/** +* scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group +* @delay: Delay value +* +* Apply and load a particular output delay for the DQ pins in a group. +*/ +static void scc_mgr_apply_group_dq_out1_delay (const u32 delay) { -uint32_t i, p; +int i; -for (i =0 , p = group_bgn; i <RW_MGR_MEM_DQ_PER_WRITE_DQS ; i++, p++) { -scc_mgr_set_dq_out1_delay (i, delay1); +for (i =0 ; i <RW_MGR_MEM_DQ_PER_WRITE_DQS ; i++) { +scc_mgr_set_dq_out1_delay (i, delay);scc_mgr_load_dq (i); } }
@@ -2699,7 +2702,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,/* Search for the left edge of the window for each bit */ for (d =0 ; d <=IO_IO_OUT1_DELAY_MAX ; d++) { -scc_mgr_apply_group_dq_out1_delay (write_group, test_bgn, d); +scc_mgr_apply_group_dq_out1_delay (write_group, d);writel (0 , &sdr_scc_mgr->update);
@@ -2748,7 +2751,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, }/* Reset DQ delay chains to 0 */ -scc_mgr_apply_group_dq_out1_delay (write_group, test_bgn,0 ); +scc_mgr_apply_group_dq_out1_delay (write_group,0 ); sticky_bit_chk =0 ;for (i =RW_MGR_MEM_DQ_PER_WRITE_DQS -1 ;; i--) { debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
Signature · 1 line
2.1.4
PATCH 67/172 ddr: altera: Clean up scc_mgr_*_delay() args
In reply to Marek VasutZap args which are not used by these functions, in particular the write_group is often passed, but unused.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-)
drivers/ddr/altera/sequencer.c +14 -18
@@ -305,7 +305,7 @@ static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)scc_mgr_set (SCC_MGR_DQS_EN_DELAY_OFFSET , read_group, delay); } -static void scc_mgr_set_dqs_io_in_delay (uint32_t write_group,uint32_t delay) +static void scc_mgr_set_dqs_io_in_delay (uint32_t delay) {scc_mgr_set (SCC_MGR_IO_IN_DELAY_OFFSET ,RW_MGR_MEM_DQ_PER_WRITE_DQS , delay);
@@ -321,8 +321,7 @@ static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)scc_mgr_set (SCC_MGR_IO_OUT1_DELAY_OFFSET , dq_in_group, delay); } -static void scc_mgr_set_dqs_out1_delay (uint32_t write_group, -uint32_t delay) +static void scc_mgr_set_dqs_out1_delay (uint32_t delay) {scc_mgr_set (SCC_MGR_IO_OUT1_DELAY_OFFSET ,RW_MGR_MEM_DQ_PER_WRITE_DQS , delay);
@@ -589,9 +588,9 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,/* zero all DQS io settings */ if (!out_only) -scc_mgr_set_dqs_io_in_delay (write_group,0 ); +scc_mgr_set_dqs_io_in_delay (0 );/* av/cv don't have out2 */ -scc_mgr_set_dqs_out1_delay (write_group,IO_DQS_OUT_RESERVE ); +scc_mgr_set_dqs_out1_delay (IO_DQS_OUT_RESERVE );scc_mgr_set_oct_out1_delay (write_group,IO_DQS_OUT_RESERVE );scc_mgr_load_dqs_for_write_group (write_group);
@@ -607,8 +606,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,* apply and load a particular input delay for the DQ pins in a group * group_bgn is the index of the first dq pin (in the write group) */ -static void scc_mgr_apply_group_dq_in_delay (uint32_t write_group, -uint32_t group_bgn,uint32_t delay) +static void scc_mgr_apply_group_dq_in_delay (uint32_t group_bgn,uint32_t delay) {uint32_t i, p;
@@ -635,8 +633,7 @@ static void scc_mgr_apply_group_dq_out1_delay(const u32 delay) }/* apply and load a particular output delay for the DM pins in a group */ -static void scc_mgr_apply_group_dm_out1_delay (uint32_t write_group, -uint32_t delay1) +static void scc_mgr_apply_group_dm_out1_delay (uint32_t delay1) {uint32_t i;
@@ -651,7 +648,7 @@ static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group,static void scc_mgr_apply_group_dqs_io_and_oct_out1 (uint32_t write_group,uint32_t delay) { -scc_mgr_set_dqs_out1_delay (write_group, delay); +scc_mgr_set_dqs_out1_delay (delay);scc_mgr_load_dqs_io ();scc_mgr_set_oct_out1_delay (write_group, delay);
@@ -709,7 +706,7 @@ static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group, write_group, group_bgn, delay, new_delay,IO_IO_OUT2_DELAY_MAX ,IO_IO_OUT2_DELAY_MAX , new_delay - IO_IO_OUT2_DELAY_MAX); -scc_mgr_set_dqs_out1_delay (write_group, new_delay - +scc_mgr_set_dqs_out1_delay (new_delay -IO_IO_OUT2_DELAY_MAX ); new_delay =IO_IO_OUT2_DELAY_MAX ; }
@@ -1805,8 +1802,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delayfor (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) { -for (i =0 , p = test_bgn, d =0 ; i <RW_MGR_MEM_DQ_PER_READ_DQS ; - i++, p++, d += delay_step) { +for (i =0 , p = test_bgn, d =0 ; i <RW_MGR_MEM_DQ_PER_READ_DQS ; i++, p++, d += delay_step) {debug_cond (DLEVEL ==1 ,"%s:%d rw_mgr_mem_calibrate_\ vfifo_find_dqs_" , __func__, __LINE__); debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
@@ -1932,7 +1928,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, }/* Reset DQ delay chains to 0 */ -scc_mgr_apply_group_dq_in_delay (write_group, test_bgn,0 ); +scc_mgr_apply_group_dq_in_delay (test_bgn,0 ); sticky_bit_chk =0 ;for (i =RW_MGR_MEM_DQ_PER_READ_DQS -1 ;; i--) { debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
@@ -2751,7 +2747,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, }/* Reset DQ delay chains to 0 */ -scc_mgr_apply_group_dq_out1_delay (write_group,0 ); +scc_mgr_apply_group_dq_out1_delay (0 ); sticky_bit_chk =0 ;for (i =RW_MGR_MEM_DQ_PER_WRITE_DQS -1 ;; i--) { debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
@@ -2975,7 +2971,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,/* Search for the/part of the window with DM shift */ for (d =IO_IO_OUT1_DELAY_MAX ; d >=0 ; d -=DELTA_D ) { -scc_mgr_apply_group_dm_out1_delay (write_group, d); +scc_mgr_apply_group_dm_out1_delay (d);writel (0 , &sdr_scc_mgr->update); if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
@@ -3008,7 +3004,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,/* Reset DM delay chains to 0 */ -scc_mgr_apply_group_dm_out1_delay (write_group,0 ); +scc_mgr_apply_group_dm_out1_delay (0 );/* * Check to see if the current window nudges up aganist 0 delay.
@@ -3090,7 +3086,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,else dm_margin = left_edge[0 ] - mid; -scc_mgr_apply_group_dm_out1_delay (write_group, mid); +scc_mgr_apply_group_dm_out1_delay (mid);writel (0 , &sdr_scc_mgr->update); debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
Signature · 1 line
2.1.4
PATCH 68/172 ddr: altera: Clean up scc_mgr_set_hhp_extras()
In reply to Marek VasutMinor coding style cleanup for this function. Furthermore, move ad-hoc debug_cond() calls from the only location from where this function is invoked into this actual function.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 37 ++++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-)
drivers/ddr/altera/sequencer.c +22 -15
@@ -453,21 +453,33 @@ static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)scc_mgr_set (SCC_MGR_OCT_OUT1_DELAY_OFFSET , base + i, delay); } +/** +* scc_mgr_set_hhp_extras() - Set HHP extras. +* +* Load the fixed setting in the SCC manager HHP extras. +*/ static void scc_mgr_set_hhp_extras (void ) {/* * Load the fixed setting in the SCC manager -* bits: 0:0 = 1'b1 - dqs bypass -* bits: 1:1 = 1'b1 - dq bypass -* bits: 4:2 = 3'b001 - rfifo_mode -* bits: 6:5 = 2'b01 - rfifo clock_select -* bits: 7:7 = 1'b0 - separate gating from ungating setting -* bits: 8:8 = 1'b0 - separate OE from Output delay setting +* bits: 0:0 = 1'b1 - DQS bypass +* bits: 1:1 = 1'b1 - DQ bypass +* bits: 4:2 = 3'b001 - rfifo_mode +* bits: 6:5 = 2'b01 - rfifo clock_select +* bits: 7:7 = 1'b0 - separate gating from ungating setting +* bits: 8:8 = 1'b0 - separate OE from Output delay setting */ -uint32_t value = (0 <<8 ) | (0 <<7 ) | (1 <<5 ) | (1 <<2 ) | (1 <<1 ) | (1 <<0 ); -uint32_t addr =SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_HHP_GLOBALS_OFFSET ; +const u32 value = (0 <<8 ) | (0 <<7 ) | (1 <<5 ) | + (1 <<2 ) | (1 <<1 ) | (1 <<0 ); +const u32 addr =SDR_PHYGRP_SCCGRP_ADDRESS | +SCC_MGR_HHP_GLOBALS_OFFSET | +SCC_MGR_HHP_EXTRAS_OFFSET ; -writel (value, addr +SCC_MGR_HHP_EXTRAS_OFFSET ); +debug_cond (DLEVEL ==1 ,"%s:%d Setting HHP Extras\n" , + __func__, __LINE__); +writel (value, addr); +debug_cond (DLEVEL ==1 ,"%s:%d Done Setting HHP Extras\n" , + __func__, __LINE__); }/*
@@ -516,13 +528,8 @@ static void scc_mgr_zero_all(void)static void scc_set_bypass_mode (const u32 write_group) {/* Only needed once to set all groups, pins, DQ, DQS, DM. */ -if (write_group ==0 ) { -debug_cond (DLEVEL ==1 ,"%s:%d Setting HHP Extras\n" , __func__, - __LINE__); +if (write_group ==0 )scc_mgr_set_hhp_extras (); -debug_cond (DLEVEL ==1 ,"%s:%d Done Setting HHP Extras\n" , - __func__, __LINE__); - }/* Multicast to all DQ enables. */ writel (0xff , &sdr_scc_mgr->dq_ena);
Signature · 1 line
2.1.4
PATCH 69/172 ddr: altera: Extract scc_mgr_set_hhp_extras()
In reply to Marek VasutMove scc_mgr_set_hhp_extras() out of scc_set_bypass_mode() as it has nothing to do in there. Instead, invoke it from mem_calibrate() just before invoking scc_set_bypass_mode().
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
drivers/ddr/altera/sequencer.c +4 -4
@@ -527,10 +527,6 @@ static void scc_mgr_zero_all(void)*/ static void scc_set_bypass_mode (const u32 write_group) { -/* Only needed once to set all groups, pins, DQ, DQS, DM. */ -if (write_group ==0 ) -scc_mgr_set_hhp_extras (); -/* Multicast to all DQ enables. */ writel (0xff , &sdr_scc_mgr->dq_ena);writel (0xff , &sdr_scc_mgr->dm_ena);
@@ -3332,6 +3328,10 @@ static uint32_t mem_calibrate(void)for (i =0 ; i <RW_MGR_MEM_IF_READ_DQS_WIDTH ; i++) {writel (i,SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_GROUP_COUNTER_OFFSET ); +/* Only needed once to set all groups, pins, DQ, DQS, DM. */ +if (i ==0 ) +scc_mgr_set_hhp_extras (); +scc_set_bypass_mode (i); }
Signature · 1 line
2.1.4
PATCH 70/172 ddr: altera: Clean up scc_mgr_zero_all()
In reply to Marek VasutAdd kerneldoc, clean up datatypes and fix minor indentation issue.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)
drivers/ddr/altera/sequencer.c +9 -8
@@ -482,20 +482,21 @@ static void scc_mgr_set_hhp_extras(void) __func__, __LINE__); } -/* -* USER Zero all DQS config -* TODO: maybe rename to scc_mgr_zero_dqs_config (or something) +/** +* scc_mgr_zero_all() - Zero all DQS config +* +* Zero all DQS config. */ static void scc_mgr_zero_all (void ) { -uint32_t i, r; +int i, r;/* * USER Zero all DQS config settings, across all groups and all * shadow registers */ -for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r += -NUM_RANKS_PER_SHADOW_REG ) { +for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; + r +=NUM_RANKS_PER_SHADOW_REG ) {for (i =0 ; i <RW_MGR_MEM_IF_READ_DQS_WIDTH ; i++) {/* * The phases actually don't exist on a per-rank basis,
@@ -509,12 +510,12 @@ static void scc_mgr_zero_all(void)for (i =0 ; i <RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; i++) {scc_mgr_set_dqdqs_output_phase (i,0 ); -/* av/cv don't have out2 */ +/* Arria V/Cyclone V don't have out2. */ scc_mgr_set_oct_out1_delay (i,IO_DQS_OUT_RESERVE ); } } -/* multicast to all DQS group enables */ +/* Multicast to all DQS group enables. */ writel (0xff , &sdr_scc_mgr->dqs_ena);writel (0 , &sdr_scc_mgr->update); }
Signature · 1 line
2.1.4
PATCH 71/172 ddr: altera: Clean up scc_mgr_zero_group()
In reply to Marek VasutFirst, zap unused argument of the function. Next, clean up the data types, constify where applicable, clean up comments and add kerneldoc.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 39 +++++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 18 deletions(-)
drivers/ddr/altera/sequencer.c +21 -18
@@ -565,43 +565,47 @@ static void scc_mgr_load_dqs_for_write_group(const u32 write_group)writel (base + i, &sdr_scc_mgr->dqs_ena); } -static void scc_mgr_zero_group (uint32_t write_group,uint32_t test_begin, -int32_t out_only) +/** +* scc_mgr_zero_group() - Zero all configs for a group +* +* Zero DQ, DM, DQS and OCT configs for a group. +*/ +static void scc_mgr_zero_group (const u32 write_group,const int out_only) { -uint32_t i, r; +int i, r; -for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r += -NUM_RANKS_PER_SHADOW_REG ) { -/* Zero all DQ config settings */ +for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; + r +=NUM_RANKS_PER_SHADOW_REG ) { +/* Zero all DQ config settings. */ for (i =0 ; i <RW_MGR_MEM_DQ_PER_WRITE_DQS ; i++) {scc_mgr_set_dq_out1_delay (i,0 );if (!out_only)scc_mgr_set_dq_in_delay (i,0 ); } -/* multicast to all DQ enables */ +/* Multicast to all DQ enables. */ writel (0xff , &sdr_scc_mgr->dq_ena); -/* Zero all DM config settings */ -for (i =0 ; i <RW_MGR_NUM_DM_PER_WRITE_GROUP ; i++) { +/* Zero all DM config settings. */ +for (i =0 ; i <RW_MGR_NUM_DM_PER_WRITE_GROUP ; i++)scc_mgr_set_dm_out1_delay (i,0 ); - } -/* multicast to all DM enables */ +/* Multicast to all DM enables. */ writel (0xff , &sdr_scc_mgr->dm_ena); -/* zero all DQS io settings */ +/* Zero all DQS IO settings. */ if (!out_only)scc_mgr_set_dqs_io_in_delay (0 ); -/* av/cv don't have out2 */ + +/* Arria V/Cyclone V don't have out2. */ scc_mgr_set_dqs_out1_delay (IO_DQS_OUT_RESERVE );scc_mgr_set_oct_out1_delay (write_group,IO_DQS_OUT_RESERVE );scc_mgr_load_dqs_for_write_group (write_group); -/* multicast to all DQS IO enables (only 1) */ +/* Multicast to all DQS IO enables (only 1 in total). */ writel (0 , &sdr_scc_mgr->dqs_io_ena); -/* hit update to zero everything */ +/* Hit update to zero everything. */ writel (0 , &sdr_scc_mgr->update); } }
@@ -2344,7 +2348,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,* first case). */ if (d >2 ) -scc_mgr_zero_group (write_group, write_test_bgn,1 ); +scc_mgr_zero_group (write_group,1 );return 1 ; }
@@ -3368,8 +3372,7 @@ static uint32_t mem_calibrate(void)writel (write_group,SDR_PHYGRP_SCCGRP_ADDRESS |SCC_MGR_GROUP_COUNTER_OFFSET ); -scc_mgr_zero_group (write_group, write_test_bgn, -0 ); +scc_mgr_zero_group (write_group,0 ); for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
Signature · 1 line
2.1.4
PATCH 72/172 FIXME: ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 1
In reply to Marek VasutApparently, in case of the DQ and DM, the value if the new_delay variable is calculated, but the value is not used. Zap the entire code which does calculate the value.
It is not clear to me whether or not the code is doing the right thing in the first place. Right now, it calls scc_mgr_load_dq() and scc_mgr_load_dm() respectively, but I suspect it might need to call scc_mgr_apply_group_dq_out1_delay() and scc_mgr_apply_group_dm_out1_delay() instead. This is something Altera must investigate.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 44 +++++++++--------------------------------- 1 file changed, 9 insertions(+), 35 deletions(-)
drivers/ddr/altera/sequencer.c +9 -35
@@ -664,45 +664,19 @@ static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group, }/* apply a delay to the entire output side: DQ, DM, DQS, OCT */ -static void scc_mgr_apply_group_all_out_delay_add (uint32_t write_group, -uint32_t group_bgn, -uint32_t delay) -{ -uint32_t i, p, new_delay; - -/* dq shift */ -for (i =0 , p = group_bgn; i <RW_MGR_MEM_DQ_PER_WRITE_DQS ; i++, p++) { - new_delay =READ_SCC_DQ_OUT2_DELAY ; - new_delay += delay; - -if (new_delay >IO_IO_OUT2_DELAY_MAX ) { -debug_cond (DLEVEL ==1 ,"%s:%d (%u, %u, %u) DQ[%u,%u]:\ -%u > %lu => %lu" , __func__, __LINE__, - write_group, group_bgn, delay, i, p, new_delay, - (long unsigned int )IO_IO_OUT2_DELAY_MAX , - (long unsigned int )IO_IO_OUT2_DELAY_MAX ); - new_delay =IO_IO_OUT2_DELAY_MAX ; - } +static void scc_mgr_apply_group_all_out_delay_add (const u32 write_group, +const u32 group_bgn, +const u32 delay) +{ +u32 i, new_delay; +/* DQ shift */ +for (i =0 ; i <RW_MGR_MEM_DQ_PER_WRITE_DQS ; i++)scc_mgr_load_dq (i); - } - -/* dm shift */ -for (i =0 ; i <RW_MGR_NUM_DM_PER_WRITE_GROUP ; i++) { - new_delay =READ_SCC_DM_IO_OUT2_DELAY ; - new_delay += delay; - -if (new_delay >IO_IO_OUT2_DELAY_MAX ) { -debug_cond (DLEVEL ==1 ,"%s:%d (%u, %u, %u) DM[%u]:\ -%u > %lu => %lu\n" , __func__, __LINE__, - write_group, group_bgn, delay, i, new_delay, - (long unsigned int )IO_IO_OUT2_DELAY_MAX , - (long unsigned int )IO_IO_OUT2_DELAY_MAX ); - new_delay =IO_IO_OUT2_DELAY_MAX ; - } +/* DM shift */ +for (i =0 ; i <RW_MGR_NUM_DM_PER_WRITE_GROUP ; i++)scc_mgr_load_dm (i); - }/* dqs shift */ new_delay =READ_SCC_DQS_IO_OUT2_DELAY ;
Signature · 1 line
2.1.4
PATCH 73/172 ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 2
In reply to Marek VasutClean the DQS and OCT parts of the function, clean up the chopped formatting strings in debug_cond() and slightly improve the code. Zap group_bgn argument as it is used only in debug messages. Document the function using kerneldoc. No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 50 ++++++++++++++++++++---------------------- 1 file changed, 24 insertions(+), 26 deletions(-)
drivers/ddr/altera/sequencer.c +24 -26
@@ -663,9 +663,14 @@ static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,scc_mgr_load_dqs_for_write_group (write_group); } -/* apply a delay to the entire output side: DQ, DM, DQS, OCT */ +/** +* scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT +* @write_group: Write group +* @delay: Delay value +* +* Apply a delay to the entire output side: DQ, DM, DQS, OCT. +*/ static void scc_mgr_apply_group_all_out_delay_add (const u32 write_group, -const u32 group_bgn,const u32 delay) {u32 i, new_delay;
@@ -678,36 +683,30 @@ static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,for (i =0 ; i <RW_MGR_NUM_DM_PER_WRITE_GROUP ; i++)scc_mgr_load_dm (i); -/* dqs shift */ - new_delay =READ_SCC_DQS_IO_OUT2_DELAY ; - new_delay += delay; - +/* DQS shift */ + new_delay =READ_SCC_DQS_IO_OUT2_DELAY + delay;if (new_delay >IO_IO_OUT2_DELAY_MAX ) { -debug_cond (DLEVEL ==1 ,"%s:%d (%u, %u, %u) DQS: %u > %d => %d;" -" adding %u to OUT1\n" , __func__, __LINE__, - write_group, group_bgn, delay, new_delay, -IO_IO_OUT2_DELAY_MAX ,IO_IO_OUT2_DELAY_MAX , +debug_cond (DLEVEL ==1 , +"%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n" , + __func__, __LINE__, write_group, delay, new_delay, +IO_IO_OUT2_DELAY_MAX , new_delay -IO_IO_OUT2_DELAY_MAX ); -scc_mgr_set_dqs_out1_delay (new_delay - -IO_IO_OUT2_DELAY_MAX ); - new_delay =IO_IO_OUT2_DELAY_MAX ; + new_delay -=IO_IO_OUT2_DELAY_MAX ; +scc_mgr_set_dqs_out1_delay (new_delay); }scc_mgr_load_dqs_io (); -/* oct shift */ - new_delay =READ_SCC_OCT_OUT2_DELAY ; - new_delay += delay; - +/* OCT shift */ + new_delay =READ_SCC_OCT_OUT2_DELAY + delay;if (new_delay >IO_IO_OUT2_DELAY_MAX ) { -debug_cond (DLEVEL ==1 ,"%s:%d (%u, %u, %u) DQS: %u > %d => %d;" -" adding %u to OUT1\n" , __func__, __LINE__, - write_group, group_bgn, delay, new_delay, -IO_IO_OUT2_DELAY_MAX ,IO_IO_OUT2_DELAY_MAX , +debug_cond (DLEVEL ==1 , +"%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n" , + __func__, __LINE__, write_group, delay, + new_delay,IO_IO_OUT2_DELAY_MAX , new_delay -IO_IO_OUT2_DELAY_MAX ); -scc_mgr_set_oct_out1_delay (write_group, new_delay - -IO_IO_OUT2_DELAY_MAX ); - new_delay =IO_IO_OUT2_DELAY_MAX ; + new_delay -=IO_IO_OUT2_DELAY_MAX ; +scc_mgr_set_oct_out1_delay (write_group, new_delay); }scc_mgr_load_dqs_for_write_group (write_group);
@@ -724,8 +723,7 @@ static void scc_mgr_apply_group_all_out_delay_add_all_ranks(for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) { -scc_mgr_apply_group_all_out_delay_add (write_group, - group_bgn, delay); +scc_mgr_apply_group_all_out_delay_add (write_group, delay);writel (0 , &sdr_scc_mgr->update); } }
Signature · 1 line
2.1.4
PATCH 74/172 ddr: altera: Clean up scc_mgr_apply_group_all_out_delay_add_all_ranks()
In reply to Marek VasutZap unused group_bgn parameter, fix and constify data types. Document in kerneldoc. No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-)
drivers/ddr/altera/sequencer.c +13 -9
@@ -712,17 +712,21 @@ static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,scc_mgr_load_dqs_for_write_group (write_group); } -/* -* USER apply a delay to the entire output side (DQ, DM, DQS, OCT) -* and to all ranks +/** +* scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks +* @write_group: Write group +* @delay: Delay value +* +* Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks. */ -static void scc_mgr_apply_group_all_out_delay_add_all_ranks ( -uint32_t write_group,uint32_t group_bgn,uint32_t delay) +static void +scc_mgr_apply_group_all_out_delay_add_all_ranks (const u32 write_group, +const u32 delay) { -uint32_t r; +int r;for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; - r +=NUM_RANKS_PER_SHADOW_REG ) { + r +=NUM_RANKS_PER_SHADOW_REG ) {scc_mgr_apply_group_all_out_delay_add (write_group, delay);writel (0 , &sdr_scc_mgr->update); }
@@ -2240,8 +2244,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,* calibrated output side yet. */ if (d >0 ) { -scc_mgr_apply_group_all_out_delay_add_all_ranks - (write_group, write_test_bgn, d); +scc_mgr_apply_group_all_out_delay_add_all_ranks ( + write_group, d); } for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
Signature · 1 line
2.1.4
PATCH 75/172 ddr: altera: Factor out instruction loading from rw_mgr_mem_initialize()
In reply to Marek VasutPull the duplicate code out into a separate function.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 74 +++++++++++++++++++++--------------------- 1 file changed, 37 insertions(+), 37 deletions(-)
drivers/ddr/altera/sequencer.c +37 -37
@@ -840,6 +840,37 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)debug ("%s:%d clocks=%u ... end\n" , __func__, __LINE__, clocks); } +/** +* rw_mgr_mem_init_load_regs() - Load instruction registers +* @cntr0: Counter 0 value +* @cntr1: Counter 1 value +* @cntr2: Counter 2 value +* @jump: Jump instruction value +* +* Load instruction registers. +*/ +static void rw_mgr_mem_init_load_regs (u32 cntr0,u32 cntr1,u32 cntr2,u32 jump) +{ +uint32_t grpaddr =SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_RUN_SINGLE_GROUP_OFFSET ; + +/* Load counters */ +writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (cntr0), + &sdr_rw_load_mgr_regs->load_cntr0); +writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (cntr1), + &sdr_rw_load_mgr_regs->load_cntr1); +writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (cntr2), + &sdr_rw_load_mgr_regs->load_cntr2); + +/* Load jump address */ +writel (jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0); +writel (jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1); +writel (jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2); + +/* Execute count instruction */ +writel (jump, grpaddr); +} +static void rw_mgr_mem_initialize (void ) {uint32_t r;
@@ -875,25 +906,9 @@ static void rw_mgr_mem_initialize(void)* One possible solution is n = 0 , a = 256 , b = 106 => a = FF, * b = 6A */ - -/* Load counters */ -writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TINIT_CNTR0_VAL ), - &sdr_rw_load_mgr_regs->load_cntr0); -writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TINIT_CNTR1_VAL ), - &sdr_rw_load_mgr_regs->load_cntr1); -writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TINIT_CNTR2_VAL ), - &sdr_rw_load_mgr_regs->load_cntr2); - -/* Load jump address */ -writel (RW_MGR_INIT_RESET_0_CKE_0 , - &sdr_rw_load_jump_mgr_regs->load_jump_add0); -writel (RW_MGR_INIT_RESET_0_CKE_0 , - &sdr_rw_load_jump_mgr_regs->load_jump_add1); -writel (RW_MGR_INIT_RESET_0_CKE_0 , - &sdr_rw_load_jump_mgr_regs->load_jump_add2); - -/* Execute count instruction */ -writel (RW_MGR_INIT_RESET_0_CKE_0 , grpaddr); +rw_mgr_mem_init_load_regs (SEQ_TINIT_CNTR0_VAL ,SEQ_TINIT_CNTR1_VAL , +SEQ_TINIT_CNTR2_VAL , +RW_MGR_INIT_RESET_0_CKE_0 );/* indicate that memory is stable */ writel (1 , &phy_mgr_cfg->reset_mem_stbl);
@@ -912,24 +927,9 @@ static void rw_mgr_mem_initialize(void)* One possible solution is n = 2 , a = 131 , b = 256 => a = 83, * b = FF */ - -/* Load counters */ -writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TRESET_CNTR0_VAL ), - &sdr_rw_load_mgr_regs->load_cntr0); -writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TRESET_CNTR1_VAL ), - &sdr_rw_load_mgr_regs->load_cntr1); -writel (SKIP_DELAY_LOOP_VALUE_OR_ZERO (SEQ_TRESET_CNTR2_VAL ), - &sdr_rw_load_mgr_regs->load_cntr2); - -/* Load jump address */ -writel (RW_MGR_INIT_RESET_1_CKE_0 , - &sdr_rw_load_jump_mgr_regs->load_jump_add0); -writel (RW_MGR_INIT_RESET_1_CKE_0 , - &sdr_rw_load_jump_mgr_regs->load_jump_add1); -writel (RW_MGR_INIT_RESET_1_CKE_0 , - &sdr_rw_load_jump_mgr_regs->load_jump_add2); - -writel (RW_MGR_INIT_RESET_1_CKE_0 , grpaddr); +rw_mgr_mem_init_load_regs (SEQ_TRESET_CNTR0_VAL ,SEQ_TRESET_CNTR1_VAL , +SEQ_TRESET_CNTR2_VAL , +RW_MGR_INIT_RESET_1_CKE_0 );/* bring up clock enable */
Signature · 1 line
2.1.4
PATCH 76/172 ddr: altera: Factor out common code
In reply to Marek VasutFactor out almost common code from rw_mgr_mem_handoff() and rw_mgr_mem_initialize() into separate rw_mgr_mem_load_user(). No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 175 ++++++++++++++++++----------------------- 1 file changed, 76 insertions(+), 99 deletions(-)
drivers/ddr/altera/sequencer.c +76 -99
@@ -871,12 +871,76 @@ static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)writel (jump, grpaddr); } -static void rw_mgr_mem_initialize (void ) +/** +* rw_mgr_mem_load_user() - Load user calibration values +* @fin1: Final instruction 1 +* @fin2: Final instruction 2 +* @precharge: If 1, precharge the banks at the end +* +* Load user calibration values and optionally precharge the banks. +*/ +static void rw_mgr_mem_load_user (const u32 fin1,const u32 fin2, +const int precharge) { -uint32_t r; -uint32_t grpaddr =SDR_PHYGRP_RWMGRGRP_ADDRESS | -RW_MGR_RUN_SINGLE_GROUP_OFFSET ; +u32 grpaddr =SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_RUN_SINGLE_GROUP_OFFSET ; +u32 r; + +for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r++) { +if (param->skip_ranks[r]) { +/* request to skip the rank */ +continue ; + } + +/* set rank */ +set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_OFF ); + +/* precharge all banks ... */ +if (precharge) +writel (RW_MGR_PRECHARGE_ALL , grpaddr); +/* +* USER Use Mirror-ed commands for odd ranks if address +* mirrorring is on +*/ +if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) &0x1 ) { +set_jump_as_return (); +writel (RW_MGR_MRS2_MIRR , grpaddr); +delay_for_n_mem_clocks (4 ); +set_jump_as_return (); +writel (RW_MGR_MRS3_MIRR , grpaddr); +delay_for_n_mem_clocks (4 ); +set_jump_as_return (); +writel (RW_MGR_MRS1_MIRR , grpaddr); +delay_for_n_mem_clocks (4 ); +set_jump_as_return (); +writel (fin1, grpaddr); + }else { +set_jump_as_return (); +writel (RW_MGR_MRS2 , grpaddr); +delay_for_n_mem_clocks (4 ); +set_jump_as_return (); +writel (RW_MGR_MRS3 , grpaddr); +delay_for_n_mem_clocks (4 ); +set_jump_as_return (); +writel (RW_MGR_MRS1 , grpaddr); +set_jump_as_return (); +writel (fin2, grpaddr); + } + +if (precharge) +continue ; + +set_jump_as_return (); +writel (RW_MGR_ZQCL , grpaddr); + +/* tZQinit = tDLLK = 512 ck cycles */ +delay_for_n_mem_clocks (512 ); + } +} + +static void rw_mgr_mem_initialize (void ) +{debug ("%s:%d\n" , __func__, __LINE__);/* The reset / cke part of initialization is broadcasted to all ranks */
@@ -936,49 +1000,8 @@ static void rw_mgr_mem_initialize(void)/* tXRP < 250 ck cycles */ delay_for_n_mem_clocks (250 ); -for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r++) { -if (param->skip_ranks[r]) { -/* request to skip the rank */ -continue ; - } - -/* set rank */ -set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_OFF ); - -/* -* USER Use Mirror-ed commands for odd ranks if address -* mirrorring is on -*/ -if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) &0x1 ) { -set_jump_as_return (); -writel (RW_MGR_MRS2_MIRR , grpaddr); -delay_for_n_mem_clocks (4 ); -set_jump_as_return (); -writel (RW_MGR_MRS3_MIRR , grpaddr); -delay_for_n_mem_clocks (4 ); -set_jump_as_return (); -writel (RW_MGR_MRS1_MIRR , grpaddr); -delay_for_n_mem_clocks (4 ); -set_jump_as_return (); -writel (RW_MGR_MRS0_DLL_RESET_MIRR , grpaddr); - }else { -set_jump_as_return (); -writel (RW_MGR_MRS2 , grpaddr); -delay_for_n_mem_clocks (4 ); -set_jump_as_return (); -writel (RW_MGR_MRS3 , grpaddr); -delay_for_n_mem_clocks (4 ); -set_jump_as_return (); -writel (RW_MGR_MRS1 , grpaddr); -set_jump_as_return (); -writel (RW_MGR_MRS0_DLL_RESET , grpaddr); - } -set_jump_as_return (); -writel (RW_MGR_ZQCL , grpaddr); - -/* tZQinit = tDLLK = 512 ck cycles */ -delay_for_n_mem_clocks (512 ); - } +rw_mgr_mem_load_user (RW_MGR_MRS0_DLL_RESET_MIRR ,RW_MGR_MRS0_DLL_RESET , +0 ); }/*
@@ -987,58 +1010,12 @@ static void rw_mgr_mem_initialize(void)*/ static void rw_mgr_mem_handoff (void ) { -uint32_t r; -uint32_t grpaddr =SDR_PHYGRP_RWMGRGRP_ADDRESS | -RW_MGR_RUN_SINGLE_GROUP_OFFSET ; - -debug ("%s:%d\n" , __func__, __LINE__); -for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r++) { -if (param->skip_ranks[r]) -/* request to skip the rank */ -continue ; -/* set rank */ -set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_OFF ); - -/* precharge all banks ... */ -writel (RW_MGR_PRECHARGE_ALL , grpaddr); - -/* load up MR settings specified by user */ - -/* -* Use Mirror-ed commands for odd ranks if address -* mirrorring is on -*/ -if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) &0x1 ) { -set_jump_as_return (); -writel (RW_MGR_MRS2_MIRR , grpaddr); -delay_for_n_mem_clocks (4 ); -set_jump_as_return (); -writel (RW_MGR_MRS3_MIRR , grpaddr); -delay_for_n_mem_clocks (4 ); -set_jump_as_return (); -writel (RW_MGR_MRS1_MIRR , grpaddr); -delay_for_n_mem_clocks (4 ); -set_jump_as_return (); -writel (RW_MGR_MRS0_USER_MIRR , grpaddr); - }else { -set_jump_as_return (); -writel (RW_MGR_MRS2 , grpaddr); -delay_for_n_mem_clocks (4 ); -set_jump_as_return (); -writel (RW_MGR_MRS3 , grpaddr); -delay_for_n_mem_clocks (4 ); -set_jump_as_return (); -writel (RW_MGR_MRS1 , grpaddr); -delay_for_n_mem_clocks (4 ); -set_jump_as_return (); -writel (RW_MGR_MRS0_USER , grpaddr); - } -/* -* USER need to wait tMOD (12CK or 15ns) time before issuing -* other commands, but we will have plenty of NIOS cycles before -* actual handoff so its okay. -*/ - } +rw_mgr_mem_load_user (RW_MGR_MRS0_USER_MIRR ,RW_MGR_MRS0_USER ,1 ); +/* +* USER need to wait tMOD (12CK or 15ns) time before issuing +* other commands, but we will have plenty of NIOS cycles before +* actual handoff so its okay. +*/ }/*
Signature · 1 line
2.1.4
PATCH 77/172 ddr: altera: Minor clean up of set_jump_as_return()
In reply to Marek VasutAdd kerneldoc and do a minor comment cleanup.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
drivers/ddr/altera/sequencer.c +8 -4
@@ -732,14 +732,18 @@ scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group, } } -/* optimization used to recover some slots in ddr3 inst_rom */ -/* could be applied to other protocols if we wanted to */ +/** +* set_jump_as_return() - Return instruction optimization +* +* Optimization used to recover some slots in ddr3 inst_rom could be +* applied to other protocols if we wanted to +*/ static void set_jump_as_return (void ) {/* -* to save space, we replace return with jump to special shared +* To save space, we replace return with jump to special shared * RETURN instruction so we set the counter to large value so that -* we always jump +* we always jump. */ writel (0xff , &sdr_rw_load_mgr_regs->load_cntr0);writel (RW_MGR_RETURN , &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Signature · 1 line
2.1.4
PATCH 78/172 ddr: altera: Fix ad-hoc iterative division implementation
In reply to Marek VasutContemporary CPUs can perform division just fine, use this functionality and zap another implementation of iterative division :-)
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-)
drivers/ddr/altera/sequencer.c +2 -9
@@ -2185,7 +2185,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, {uint32_t p, d, rank_bgn, sr;uint32_t dtaps_per_ptap; -uint32_t tmp_delay;uint32_t bit_chk;uint32_t grp_calibrated;uint32_t write_group, write_test_bgn;
@@ -2200,14 +2199,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, write_test_bgn = test_bgn;/* USER Determine number of delay taps for each phase tap */ - dtaps_per_ptap =0 ; - tmp_delay =0 ; -while (tmp_delay <IO_DELAY_PER_OPA_TAP ) { - dtaps_per_ptap++; - tmp_delay +=IO_DELAY_PER_DQS_EN_DCHAIN_TAP ; - } - dtaps_per_ptap--; - tmp_delay =0 ; + dtaps_per_ptap =DIV_ROUND_UP (IO_DELAY_PER_OPA_TAP , +IO_DELAY_PER_DQS_EN_DCHAIN_TAP ) -1 ;/* update info for sims */ reg_file_set_group (read_group);
Signature · 1 line
2.1.4
PATCH 79/172 ddr: altera: Rework initialize_tracking()
In reply to Marek VasutClean the function up by getting rid of all the insane XOR-leftshift combos when assembling register values. While at it, remove all the ad-hoc variables necessary for this XOR-leftshift voodoo. Finally, get rid of the iterative division implementation of two constants and replace it with a DIV_ROUND_UP() macro :-)
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 88 +++++++++++++++++------------------------- 1 file changed, 35 insertions(+), 53 deletions(-)
drivers/ddr/altera/sequencer.c +35 -53
@@ -3612,65 +3612,47 @@ static void initialize_hps_phy(void)writel (reg, &sdr_ctrl->phy_ctrl2); } +/** +* initialize_tracking() - Initialize tracking +* +* Initialize the register file with usable initial data. +*/ static void initialize_tracking (void ) { -uint32_t concatenated_longidle =0x0 ; -uint32_t concatenated_delays =0x0 ; -uint32_t concatenated_rw_addr =0x0 ; -uint32_t concatenated_refresh =0x0 ; -uint32_t trk_sample_count =7500 ; -uint32_t dtaps_per_ptap; -uint32_t tmp_delay; +/* +* Initialize the register file with the correct data. +* Compute usable version of value in case we skip full +* computation later. +*/ +writel (DIV_ROUND_UP (IO_DELAY_PER_OPA_TAP ,IO_DELAY_PER_DCHAIN_TAP ) -1 , + &sdr_reg_file->dtaps_per_ptap); + +/* trk_sample_count */ +writel (7500 , &sdr_reg_file->trk_sample_count); + +/* longidle outer loop [15:0] */ +writel ((10 <<16 ) | (100 <<0 ), &sdr_reg_file->trk_longidle);/* -* compute usable version of value in case we skip full -* computation later +* longidle sample count [31:24] +* trfc, worst case of 933Mhz 4Gb [23:16] +* trcd, worst case [15:8] +* vfifo wait [7:0] */ - dtaps_per_ptap =0 ; - tmp_delay =0 ; -while (tmp_delay <IO_DELAY_PER_OPA_TAP ) { - dtaps_per_ptap++; - tmp_delay +=IO_DELAY_PER_DCHAIN_TAP ; - } - dtaps_per_ptap--; - - concatenated_longidle = concatenated_longidle ^10 ; -/*longidle outer loop */ - concatenated_longidle = concatenated_longidle <<16 ; - concatenated_longidle = concatenated_longidle ^100 ; -/*longidle sample count */ - concatenated_delays = concatenated_delays ^243 ; -/* trfc, worst case of 933Mhz 4Gb */ - concatenated_delays = concatenated_delays <<8 ; - concatenated_delays = concatenated_delays ^14 ; -/* trcd, worst case */ - concatenated_delays = concatenated_delays <<8 ; - concatenated_delays = concatenated_delays ^10 ; -/* vfifo wait */ - concatenated_delays = concatenated_delays <<8 ; - concatenated_delays = concatenated_delays ^4 ; -/* mux delay */ - - concatenated_rw_addr = concatenated_rw_addr ^RW_MGR_IDLE ; - concatenated_rw_addr = concatenated_rw_addr <<8 ; - concatenated_rw_addr = concatenated_rw_addr ^RW_MGR_ACTIVATE_1 ; - concatenated_rw_addr = concatenated_rw_addr <<8 ; - concatenated_rw_addr = concatenated_rw_addr ^RW_MGR_SGLE_READ ; - concatenated_rw_addr = concatenated_rw_addr <<8 ; - concatenated_rw_addr = concatenated_rw_addr ^RW_MGR_PRECHARGE_ALL ; - - concatenated_refresh = concatenated_refresh ^RW_MGR_REFRESH_ALL ; - concatenated_refresh = concatenated_refresh <<24 ; - concatenated_refresh = concatenated_refresh ^1000 ;/* trefi */ +writel ((243 <<24 ) | (14 <<16 ) | (10 <<8 ) | (4 <<0 ), + &sdr_reg_file->delays); -/* Initialize the register file with the correct data */ -writel (dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap); -writel (trk_sample_count, &sdr_reg_file->trk_sample_count); -writel (concatenated_longidle, &sdr_reg_file->trk_longidle); -writel (concatenated_delays, &sdr_reg_file->delays); -writel (concatenated_rw_addr, &sdr_reg_file->trk_rw_mgr_addr); -writel (RW_MGR_MEM_IF_READ_DQS_WIDTH , &sdr_reg_file->trk_read_dqs_width); -writel (concatenated_refresh, &sdr_reg_file->trk_rfsh); +/* mux delay */ +writel ((RW_MGR_IDLE <<24 ) | (RW_MGR_ACTIVATE_1 <<16 ) | + (RW_MGR_SGLE_READ <<8 ) | (RW_MGR_PRECHARGE_ALL <<0 ), + &sdr_reg_file->trk_rw_mgr_addr); + +writel (RW_MGR_MEM_IF_READ_DQS_WIDTH , + &sdr_reg_file->trk_read_dqs_width); + +/* trefi [7:0] */ +writel ((RW_MGR_REFRESH_ALL <<24 ) | (1000 <<0 ), + &sdr_reg_file->trk_rfsh); }int sdram_calibration_full (void )
Signature · 1 line
2.1.4
PATCH 80/172 ddr: altera: Init my_param and my_gbl
In reply to Marek VasutInit both structures with zeroes and zap all those zeroing shenanigans further down in the sdram_calibration_full().
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-)
drivers/ddr/altera/sequencer.c +3 -10
@@ -3660,13 +3660,13 @@ int sdram_calibration_full(void)struct param_type my_param;struct gbl_type my_gbl;uint32_t pass; -uint32_t i; + +memset (&my_param,0 ,sizeof (my_param)); +memset (&my_gbl,0 ,sizeof (my_gbl)); param = &my_param; gbl = &my_gbl; -/* Initialize the debug mode flags */ - gbl->phy_debug_mode_flags =0 ;/* Set the calibration enabled by default */ gbl->phy_debug_mode_flags |=PHY_DEBUG_ENABLE_CAL_RPT ;/*
@@ -3686,13 +3686,6 @@ int sdram_calibration_full(void)initialize_tracking (); -/* USER Enable all ranks, groups */ -for (i =0 ; i <RW_MGR_MEM_NUMBER_OF_RANKS ; i++) - param->skip_ranks[i] =0 ; -for (i =0 ; i <NUM_SHADOW_REGS ; ++i) - param->skip_shadow_regs[i] =0 ; - param->skip_groups =0 ; -printf ("%s: Preparing to start memory calibration\n" , __FILE__);debug ("%s:%d\n" , __func__, __LINE__);
Signature · 1 line
2.1.4
PATCH 81/172 ddr: altera: Rename initialize() to phy_mgr_initialize()
In reply to Marek VasutJust perform the rename to make the name more descriptive, no functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/ddr/altera/sequencer.c +2 -2
@@ -113,7 +113,7 @@ static void reg_file_set_sub_stage(u8 set_sub_stage)clrsetbits_le32 (&sdr_reg_file->cur_stage,0xff00 , set_sub_stage <<8 ); } -static void initialize (void ) +static void phy_mgr_initialize (void ) {debug ("%s:%d\n" , __func__, __LINE__);/* USER calibration has control over path to memory */
@@ -3463,7 +3463,7 @@ static uint32_t run_mem_calibrate(void)writel (ctrlcfg &0xFFBFFFFF , &sdr_ctrl->ctrl_cfg); -initialize (); +phy_mgr_initialize ();rw_mgr_mem_initialize (); pass =mem_calibrate ();
Signature · 1 line
2.1.4
PATCH 82/172 ddr: altera: Clean up run_mem_calibrate()
In reply to Marek VasutClean the function up slightly by using clrsetbits_le32() to flip bits in registers instead of cryptic bitmasks. Zap condition checking for PHY_DEBUG_IN_DEBUG_MODE flag, which is never set. Split the calibration report into separate debug_mem_calibrate() function.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 56 +++++++++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 22 deletions(-)
drivers/ddr/altera/sequencer.c +34 -22
@@ -3448,44 +3448,57 @@ static uint32_t mem_calibrate(void)return 1 ; } -static uint32_t run_mem_calibrate (void ) +/** +* run_mem_calibrate() - Perform memory calibration +* +* This function triggers the entire memory calibration procedure. +*/ +static int run_mem_calibrate (void ) { -uint32_t pass; -uint32_t debug_info; +int pass;debug ("%s:%d\n" , __func__, __LINE__);/* Reset pass/fail status shown on afi_cal_success/fail */ writel (PHY_MGR_CAL_RESET , &phy_mgr_cfg->cal_status); -/* stop tracking manger */ -uint32_t ctrlcfg =readl (&sdr_ctrl->ctrl_cfg); - -writel (ctrlcfg &0xFFBFFFFF , &sdr_ctrl->ctrl_cfg); +/* Stop tracking manager. */ +clrbits_le32 (&sdr_ctrl->ctrl_cfg,1 <<22 );phy_mgr_initialize ();rw_mgr_mem_initialize (); +/* Perform the actual memory calibration. */ pass =mem_calibrate ();mem_precharge_and_activate ();writel (0 , &phy_mgr_cmd->fifo_reset); +/* Handoff. */ +rw_mgr_mem_handoff ();/* -* Handoff: -* Don't return control of the PHY back to AFI when in debug mode. +* In Hard PHY this is a 2-bit control: +* 0: AFI Mux Select +* 1: DDIO Mux Select */ -if ((gbl->phy_debug_mode_flags &PHY_DEBUG_IN_DEBUG_MODE ) ==0 ) { -rw_mgr_mem_handoff (); -/* -* In Hard PHY this is a 2-bit control: -* 0: AFI Mux Select -* 1: DDIO Mux Select -*/ -writel (0x2 , &phy_mgr_cfg->mux_sel); - } +writel (0x2 , &phy_mgr_cfg->mux_sel); -writel (ctrlcfg, &sdr_ctrl->ctrl_cfg); +/* Start tracking manager. */ +setbits_le32 (&sdr_ctrl->ctrl_cfg,1 <<22 ); + +return pass; +} + +/** +* debug_mem_calibrate() - Report result of memory calibration +* @pass: Value indicating whether calibration passed or failed +* +* This function reports the results of the memory calibration +* and writes debug information into the register file. +*/ +static void debug_mem_calibrate (int pass) +{ +uint32_t debug_info;if (pass) {printf ("%s: CALIBRATION PASSED\n" , __FILE__);
@@ -3524,7 +3537,7 @@ static uint32_t run_mem_calibrate(void)writel (debug_info, &sdr_reg_file->failing_stage); } -return pass; +printf ("%s: Calibration complete\n" , __FILE__); }/**
@@ -3732,7 +3745,6 @@ int sdram_calibration_full(void) skip_delay_mask =0x0 ; pass =run_mem_calibrate (); - -printf ("%s: Calibration complete\n" , __FILE__); +debug_mem_calibrate (pass);return pass; }
Signature · 1 line
2.1.4
PATCH 83/172 ddr: altera: Clean up phy_mgr_initialize()
In reply to Marek VasutZap the cryptic casts and rework the code into a slightly more readable form. No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-)
drivers/ddr/altera/sequencer.c +21 -16
@@ -113,10 +113,17 @@ static void reg_file_set_sub_stage(u8 set_sub_stage)clrsetbits_le32 (&sdr_reg_file->cur_stage,0xff00 , set_sub_stage <<8 ); } +/** +* phy_mgr_initialize() - Initialize PHY Manager +* +* Initialize PHY Manager. +*/ static void phy_mgr_initialize (void ) { +u32 ratio; +debug ("%s:%d\n" , __func__, __LINE__); -/* USER calibration has control over path to memory */ +/* Calibration has control over path to memory */ /* * In Hard PHY this is a 2-bit control: * 0: AFI Mux Select
@@ -132,21 +139,19 @@ static void phy_mgr_initialize(void)writel (0 , &phy_mgr_cfg->cal_debug_info); -if ((dyn_calib_steps &CALIB_SKIP_ALL ) !=CALIB_SKIP_ALL ) { - param->read_correct_mask_vg = ((uint32_t )1 << - (RW_MGR_MEM_DQ_PER_READ_DQS / -RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS )) -1 ; - param->write_correct_mask_vg = ((uint32_t )1 << - (RW_MGR_MEM_DQ_PER_READ_DQS / -RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS )) -1 ; - param->read_correct_mask = ((uint32_t )1 << -RW_MGR_MEM_DQ_PER_READ_DQS ) -1 ; - param->write_correct_mask = ((uint32_t )1 << -RW_MGR_MEM_DQ_PER_WRITE_DQS ) -1 ; - param->dm_correct_mask = ((uint32_t )1 << - (RW_MGR_MEM_DATA_WIDTH /RW_MGR_MEM_DATA_MASK_WIDTH )) - -1 ; - } +/* Init params only if we do NOT skip calibration. */ +if ((dyn_calib_steps &CALIB_SKIP_ALL ) ==CALIB_SKIP_ALL ) +return ; + + ratio =RW_MGR_MEM_DQ_PER_READ_DQS / +RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS ; + param->read_correct_mask_vg = (1 << ratio) -1 ; + param->write_correct_mask_vg = (1 << ratio) -1 ; + param->read_correct_mask = (1 <<RW_MGR_MEM_DQ_PER_READ_DQS ) -1 ; + param->write_correct_mask = (1 <<RW_MGR_MEM_DQ_PER_WRITE_DQS ) -1 ; + ratio =RW_MGR_MEM_DATA_WIDTH / +RW_MGR_MEM_DATA_MASK_WIDTH ; + param->dm_correct_mask = (1 << ratio) -1 ; }static void set_rank_and_odt_mask (uint32_t rank,uint32_t odt_mode)
Signature · 1 line
2.1.4
PATCH 84/172 ddr: altera: Clean up mem_config()
In reply to Marek VasutClean mem_config() function. First, reorder the math done in the function such that WLAT and RLAT computation is together. Then, scrap contradictory comments which do not match the result of the math at all. Next, extract the mem_precharge_and_activate() call from the end of the function as it is completely unrelated here. Finally, rename the function to mem_init_latency().
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 67 ++++++++++++++++++------------------------ drivers/ddr/altera/sequencer.h | 4 --- 2 files changed, 29 insertions(+), 42 deletions(-)
drivers/ddr/altera/sequencer.c +29 -38
@@ -3123,57 +3123,44 @@ static void mem_precharge_and_activate(void) } } -/* Configure various memory related parameters. */ -static void mem_config (void ) +/** +* mem_init_latency() - Configure memory RLAT and WLAT settings +* +* Configure memory RLAT and WLAT parameters. +*/ +static void mem_init_latency (void ) { -uint32_t rlat, wlat; -uint32_t rw_wl_nop_cycles; -uint32_t max_latency; - -debug ("%s:%d\n" , __func__, __LINE__); -/* read in write and read latency */ - wlat =readl (&data_mgr->t_wl_add); - wlat +=readl (&data_mgr->mem_t_add); - -/* WL for hard phy does not include additive latency */ -/* -* add addtional write latency to offset the address/command extra -* clock cycle. We change the AC mux setting causing AC to be delayed -* by one mem clock cycle. Only do this for DDR3 +* For AV/CV, LFIFO is hardened and always runs at full rate +* so max latency in AFI clocks, used here, is correspondingly +* smaller. */ - wlat = wlat +1 ; - - rlat =readl (&data_mgr->t_rl_add); +const u32 max_latency = (1 <<MAX_LATENCY_COUNT_WIDTH ) -1 ; +u32 rlat, wlat; - rw_wl_nop_cycles = wlat -2 ; - gbl->rw_wl_nop_cycles = rw_wl_nop_cycles; +debug ("%s:%d\n" , __func__, __LINE__);/* -* For AV/CV, lfifo is hardened and always runs at full rate so -* max latency in AFI clocks, used here, is correspondingly smaller. +* Read in write latency. +* WL for Hard PHY does not include additive latency. */ - max_latency = (1 <<MAX_LATENCY_COUNT_WIDTH )/1 -1 ; -/* configure for a burst length of 8 */ + wlat =readl (&data_mgr->t_wl_add); + wlat +=readl (&data_mgr->mem_t_add); -/* write latency */ -/* Adjust Write Latency for Hard PHY */ - wlat = wlat +1 ; + gbl->rw_wl_nop_cycles = wlat -1 ; -/* set a pretty high read latency initially */ - gbl->curr_read_lat = rlat +16 ; +/* Read in readl latency. */ + rlat =readl (&data_mgr->t_rl_add); +/* Set a pretty high read latency initially. */ + gbl->curr_read_lat = rlat +16 ;if (gbl->curr_read_lat > max_latency) gbl->curr_read_lat = max_latency;writel (gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); -/* advertise write latency */ - gbl->curr_write_lat = wlat; -writel (wlat -2 , &phy_mgr_cfg->afi_wlat); - -/* initialize bit slips */ -mem_precharge_and_activate (); +/* Advertise write latency. */ +writel (wlat, &phy_mgr_cfg->afi_wlat); }/* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */
@@ -3275,15 +3262,19 @@ static uint32_t mem_calibrate(void)uint32_t sr_failed =0 ;debug ("%s:%d\n" , __func__, __LINE__); -/* Initialize the data settings */ +/* Initialize the data settings */ gbl->error_substage =CAL_SUBSTAGE_NIL ; gbl->error_stage =CAL_STAGE_NIL ; gbl->error_group =0xff ; gbl->fom_in =0 ; gbl->fom_out =0 ; -mem_config (); +/* Initialize WLAT and RLAT. */ +mem_init_latency (); + +/* Initialize bit slips. */ +mem_precharge_and_activate ();for (i =0 ; i <RW_MGR_MEM_IF_READ_DQS_WIDTH ; i++) { writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
drivers/ddr/altera/sequencer.h +0 -4
@@ -242,10 +242,6 @@ struct gbl_type {uint32_t curr_read_lat; -/* current write latency */ - -uint32_t curr_write_lat; -/* error code */ uint32_t error_substage;
Signature · 1 line
2.1.4
PATCH 85/172 ddr: altera: Clean up mem_precharge_and_activate()
In reply to Marek VasutPerform minor cleanup of this function, fix datatype and add kerneldoc.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-)
drivers/ddr/altera/sequencer.c +11 -8
@@ -3091,21 +3091,24 @@ static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,return 1 ; } -/* precharge all banks and activate row 0 in bank "000..." and bank "111..." */ +/** +* mem_precharge_and_activate() - Precharge all banks and activate +* +* Precharge all banks and activate row 0 in bank "000..." and bank "111...". +*/ static void mem_precharge_and_activate (void ) { -uint32_t r; +int r;for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r++) { -if (param->skip_ranks[r]) { -/* request to skip the rank */ +/* Test if the rank should be skipped. */ +if (param->skip_ranks[r])continue ; - } -/* set rank */ +/* Set rank. */ set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_OFF ); -/* precharge all banks ... */ +/* Precharge all banks. */ writel (RW_MGR_PRECHARGE_ALL ,SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET );
@@ -3117,7 +3120,7 @@ static void mem_precharge_and_activate(void)writel (RW_MGR_ACTIVATE_0_AND_1_WAIT2 , &sdr_rw_load_jump_mgr_regs->load_jump_add1); -/* activate rows */ +/* Activate rows. */ writel (RW_MGR_ACTIVATE_0_AND_1 ,SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ); }
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2.1.4
PATCH 86/172 ddr: altera: Clean up set_rank_and_odt_mask() part 1
In reply to Marek VasutFirst, invert the logic of the if (odt_mode == ...) conditional to make the OFF mode harder to miss. It is a short piece of code right at the end, so move it up.
Also, clean up data types and constify where applicable and clean up the cs_and_odt_mask assignment. No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-)
drivers/ddr/altera/sequencer.c +11 -12
@@ -154,13 +154,16 @@ static void phy_mgr_initialize(void) param->dm_correct_mask = (1 << ratio) -1 ; } -static void set_rank_and_odt_mask (uint32_t rank,uint32_t odt_mode) +static void set_rank_and_odt_mask (const u32 rank,const u32 odt_mode) { -uint32_t odt_mask_0 =0 ; -uint32_t odt_mask_1 =0 ; -uint32_t cs_and_odt_mask; +u32 odt_mask_0 =0 ; +u32 odt_mask_1 =0 ; +u32 cs_and_odt_mask; -if (odt_mode ==RW_MGR_ODT_MODE_READ_WRITE ) { +if (odt_mode ==RW_MGR_ODT_MODE_OFF ) { + odt_mask_0 =0x0 ; + odt_mask_1 =0x0 ; + }else {/* RW_MGR_ODT_MODE_READ_WRITE */ if (RW_MGR_MEM_NUMBER_OF_RANKS ==1 ) {/* * 1 Rank
@@ -242,15 +245,11 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)break ; } } - }else { - odt_mask_0 =0x0 ; - odt_mask_1 =0x0 ; } - cs_and_odt_mask = - (0xFF & ~(1 << rank)) | - ((0xFF & odt_mask_0) <<8 ) | - ((0xFF & odt_mask_1) <<16 ); + cs_and_odt_mask = (0xFF & ~(1 << rank)) | + ((0xFF & odt_mask_0) <<8 ) | + ((0xFF & odt_mask_1) <<16 );writel (cs_and_odt_mask,SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_SET_CS_AND_ODT_MASK_OFFSET ); }
Signature · 1 line
2.1.4
PATCH 87/172 ddr: altera: Clean up set_rank_and_odt_mask() part 2
In reply to Marek VasutTurn the big inner if (RW_MGR_MEM_NUMBER_OF_RANKS == ...) conditional into a switch {} statement instead. No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-)
drivers/ddr/altera/sequencer.c +9 -11
@@ -164,16 +164,13 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode) odt_mask_0 =0x0 ; odt_mask_1 =0x0 ; }else {/* RW_MGR_ODT_MODE_READ_WRITE */ -if (RW_MGR_MEM_NUMBER_OF_RANKS ==1 ) { -/* -* 1 Rank -* Read: ODT = 0 -* Write: ODT = 1 -*/ +switch (RW_MGR_MEM_NUMBER_OF_RANKS ) { +case 1 :/* 1 Rank */ +/* Read: ODT = 0 ; Write: ODT = 1 */ odt_mask_0 =0x0 ; odt_mask_1 =0x1 ; - }else if (RW_MGR_MEM_NUMBER_OF_RANKS ==2 ) { -/* 2 Ranks */ +break ; +case 2 :/* 2 Ranks */ if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM ==1 ) {/* - Dual-Slot , Single-Rank * (1 chip-select per DIMM)
@@ -198,9 +195,9 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode) odt_mask_0 =0x0 ; odt_mask_1 =0x3 & (1 << rank); } - }else { -/* 4 Ranks -* Read: +break ; +case 4 :/* 4 Ranks */ +/* Read: * ----------+-----------------------+ * | | * | ODT |
@@ -244,6 +241,7 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode) odt_mask_1 =0xA ;break ; } +break ; } }
Signature · 1 line
2.1.4
PATCH 88/172 ddr: altera: Clean up set_rank_and_odt_mask() part 3
In reply to Marek VasutClean up comments and add kerneldoc.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-)
drivers/ddr/altera/sequencer.c +20 -14
@@ -154,6 +154,13 @@ static void phy_mgr_initialize(void) param->dm_correct_mask = (1 << ratio) -1 ; } +/** +* set_rank_and_odt_mask() - Set Rank and ODT mask +* @rank: Rank mask +* @odt_mode: ODT mode, OFF or READ_WRITE +* +* Set Rank and ODT mask (On-Die Termination). +*/ static void set_rank_and_odt_mask (const u32 rank,const u32 odt_mode) {u32 odt_mask_0 =0 ;
@@ -172,14 +179,15 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)break ;case 2 :/* 2 Ranks */ if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM ==1 ) { -/* - Dual-Slot , Single-Rank -* (1 chip-select per DIMM) -* OR -* - RDIMM, 4 total CS (2 CS per DIMM) -* means 2 DIMM -* Since MEM_NUMBER_OF_RANKS is 2 they are -* both single rank -* with 2 CS each (special for RDIMM) +/* +* - Dual-Slot , Single-Rank (1 CS per DIMM) +* OR +* - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM) +* +* Since MEM_NUMBER_OF_RANKS is 2, they +* are both single rank with 2 CS each +* (special for RDIMM). +* * Read: Turn on ODT on the opposite rank * Write: Turn on ODT on all ranks */
@@ -187,10 +195,10 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode) odt_mask_1 =0x3 ; }else {/* -* USER - Single-Slot , Dual-rank DIMMs -* (2 chip-selects per DIMM) -* USER Read: Turn on ODT off on all ranks -* USER Write: Turn on ODT on active rank +* - Single-Slot , Dual-Rank (2 CS per DIMM) +* +* Read: Turn on ODT off on all ranks +* Write: Turn on ODT on active rank */ odt_mask_0 =0x0 ; odt_mask_1 =0x3 & (1 << rank);
@@ -199,7 +207,6 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)case 4 :/* 4 Ranks */ /* Read: * ----------+-----------------------+ -* | | * | ODT | * Read From +-----------------------+ * Rank | 3 | 2 | 1 | 0 |
@@ -212,7 +219,6 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)* * Write: * ----------+-----------------------+ -* | | * | ODT | * Write To +-----------------------+ * Rank | 3 | 2 | 1 | 0 |
Signature · 1 line
2.1.4
PATCH 89/172 ddr: altera: Minor clean up of mem_skip_calibrate()
In reply to Marek VasutPerform minor coding style cleanup of the mem_skip_calibrate() function, clean up comments and add kerneldoc. No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-)
drivers/ddr/altera/sequencer.c +11 -8
@@ -3169,7 +3169,11 @@ static void mem_init_latency(void)writel (wlat, &phy_mgr_cfg->afi_wlat); } -/* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */ +/** +* @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings +* +* Set VFIFO and LFIFO to instant-on settings in skip calibration mode. +*/ static void mem_skip_calibrate (void ) {uint32_t vfifo_offset;
@@ -3178,7 +3182,7 @@ static void mem_skip_calibrate(void)debug ("%s:%d\n" , __func__, __LINE__);/* Need to update every shadow register set used by the interface */ for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; - r +=NUM_RANKS_PER_SHADOW_REG ) { + r +=NUM_RANKS_PER_SHADOW_REG ) {/* * Set output phase alignment settings appropriate for * skip calibration.
@@ -3215,8 +3219,8 @@ static void mem_skip_calibrate(void)* * (1.25 * IO_DLL_CHAIN_LENGTH - 2) */ -scc_mgr_set_dqdqs_output_phase (i, (1.25 * -IO_DLL_CHAIN_LENGTH -2 )); +scc_mgr_set_dqdqs_output_phase (i, +1.25 *IO_DLL_CHAIN_LENGTH -2 ); }writel (0xff , &sdr_scc_mgr->dqs_ena);writel (0xff , &sdr_scc_mgr->dqs_io_ena);
@@ -3242,14 +3246,13 @@ static void mem_skip_calibrate(void)* in sequencer. */ vfifo_offset =CALIB_VFIFO_OFFSET ; -for (j =0 ; j < vfifo_offset; j++) { +for (j =0 ; j < vfifo_offset; j++)writel (0xff , &phy_mgr_cmd->inc_vfifo_hard_phy); - }writel (0 , &phy_mgr_cmd->fifo_reset);/* -* For ACV with hard lfifo, we get the skip-cal setting from -* generation-time constant. +* For Arria V and Cyclone V with hard LFIFO, we get the skip-cal +* setting from generation-time constant. */ gbl->curr_read_lat =CALIB_LFIFO_OFFSET ;writel (gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
Signature · 1 line
2.1.4
PATCH 90/172 ddr: altera: Trivial mem_calibrate() indent cleanup
In reply to Marek VasutRedo the mega-condition such that if the calibration is to be skipped, the positive branch of the condition does all the work and returns. The negative branch, which is in fact the default behavior, is then converted to a code which is no longer conditional. This trims down the indent by one level.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 249 +++++++++++++++++++++-------------------- 1 file changed, 129 insertions(+), 120 deletions(-)
drivers/ddr/altera/sequencer.c +129 -120
@@ -3295,152 +3295,161 @@ static uint32_t mem_calibrate(void)scc_set_bypass_mode (i); } +/* Calibration is skipped. */ if ((dyn_calib_steps &CALIB_SKIP_ALL ) ==CALIB_SKIP_ALL ) {/* * Set VFIFO and LFIFO to instant-on settings in skip * calibration mode. */ mem_skip_calibrate (); - }else { -for (i =0 ; i <NUM_CALIB_REPEAT ; i++) { -/* -* Zero all delay chain/phase settings for all -* groups and all shadow register sets. -*/ -scc_mgr_zero_all (); - - run_groups = ~param->skip_groups; - -for (write_group =0 , write_test_bgn =0 ; write_group - <RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; write_group++, - write_test_bgn +=RW_MGR_MEM_DQ_PER_WRITE_DQS ) { -/* Initialized the group failure */ - group_failed =0 ; - - current_run = run_groups & ((1 << -RW_MGR_NUM_DQS_PER_WRITE_GROUP ) -1 ); - run_groups = run_groups >> -RW_MGR_NUM_DQS_PER_WRITE_GROUP ; - -if (current_run ==0 ) -continue ; -writel (write_group,SDR_PHYGRP_SCCGRP_ADDRESS | -SCC_MGR_GROUP_COUNTER_OFFSET ); -scc_mgr_zero_group (write_group,0 ); +/* +* Do not remove this line as it makes sure all of our +* decisions have been applied. +*/ +writel (0 , &sdr_scc_mgr->update); +return 1 ; + } -for (read_group = write_group * -RW_MGR_MEM_IF_READ_DQS_WIDTH / -RW_MGR_MEM_IF_WRITE_DQS_WIDTH , - read_test_bgn =0 ; - read_group < (write_group +1 ) * -RW_MGR_MEM_IF_READ_DQS_WIDTH / -RW_MGR_MEM_IF_WRITE_DQS_WIDTH && - group_failed ==0 ; - read_group++, read_test_bgn += -RW_MGR_MEM_DQ_PER_READ_DQS ) { -/* Calibrate the VFIFO */ -if (!((STATIC_CALIB_STEPS ) & -CALIB_SKIP_VFIFO )) { -if (!rw_mgr_mem_calibrate_vfifo - (read_group, - read_test_bgn)) { - group_failed =1 ; - -if (!(gbl-> - phy_debug_mode_flags & -PHY_DEBUG_SWEEP_ALL_GROUPS )) { -return 0 ; - } +/* Calibration is not skipped. */ +for (i =0 ; i <NUM_CALIB_REPEAT ; i++) { +/* +* Zero all delay chain/phase settings for all +* groups and all shadow register sets. +*/ +scc_mgr_zero_all (); + + run_groups = ~param->skip_groups; + +for (write_group =0 , write_test_bgn =0 ; write_group + <RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; write_group++, + write_test_bgn +=RW_MGR_MEM_DQ_PER_WRITE_DQS ) { +/* Initialized the group failure */ + group_failed =0 ; + + current_run = run_groups & ((1 << +RW_MGR_NUM_DQS_PER_WRITE_GROUP ) -1 ); + run_groups = run_groups >> +RW_MGR_NUM_DQS_PER_WRITE_GROUP ; + +if (current_run ==0 ) +continue ; + +writel (write_group,SDR_PHYGRP_SCCGRP_ADDRESS | +SCC_MGR_GROUP_COUNTER_OFFSET ); +scc_mgr_zero_group (write_group,0 ); + +for (read_group = write_group * +RW_MGR_MEM_IF_READ_DQS_WIDTH / +RW_MGR_MEM_IF_WRITE_DQS_WIDTH , + read_test_bgn =0 ; + read_group < (write_group +1 ) * +RW_MGR_MEM_IF_READ_DQS_WIDTH / +RW_MGR_MEM_IF_WRITE_DQS_WIDTH && + group_failed ==0 ; + read_group++, read_test_bgn += +RW_MGR_MEM_DQ_PER_READ_DQS ) { +/* Calibrate the VFIFO */ +if (!((STATIC_CALIB_STEPS ) & +CALIB_SKIP_VFIFO )) { +if (!rw_mgr_mem_calibrate_vfifo + (read_group, + read_test_bgn)) { + group_failed =1 ; + +if (!(gbl-> + phy_debug_mode_flags & +PHY_DEBUG_SWEEP_ALL_GROUPS )) { +return 0 ; } } } + } -/* Calibrate the output side */ -if (group_failed ==0 ) { -for (rank_bgn =0 , sr =0 ; rank_bgn - <RW_MGR_MEM_NUMBER_OF_RANKS ; - rank_bgn += -NUM_RANKS_PER_SHADOW_REG , - ++sr) { - sr_failed =0 ; -if (!((STATIC_CALIB_STEPS ) & -CALIB_SKIP_WRITES )) { -if ((STATIC_CALIB_STEPS ) - &CALIB_SKIP_DELAY_SWEEPS ) { -/* not needed in quick mode! */ - }else { -/* -* Determine if this set of -* ranks should be skipped -* entirely. -*/ -if (!param->skip_shadow_regs[sr]) { -if (!rw_mgr_mem_calibrate_writes - (rank_bgn, write_group, - write_test_bgn)) { - sr_failed =1 ; -if (!(gbl-> - phy_debug_mode_flags & -PHY_DEBUG_SWEEP_ALL_GROUPS )) { -return 0 ; - } - } +/* Calibrate the output side */ +if (group_failed ==0 ) { +for (rank_bgn =0 , sr =0 ; rank_bgn + <RW_MGR_MEM_NUMBER_OF_RANKS ; + rank_bgn += +NUM_RANKS_PER_SHADOW_REG , + ++sr) { + sr_failed =0 ; +if (!((STATIC_CALIB_STEPS ) & +CALIB_SKIP_WRITES )) { +if ((STATIC_CALIB_STEPS ) + &CALIB_SKIP_DELAY_SWEEPS ) { +/* not needed in quick mode! */ + }else { +/* +* Determine if this set of +* ranks should be skipped +* entirely. +*/ +if (!param->skip_shadow_regs[sr]) { +if (!rw_mgr_mem_calibrate_writes + (rank_bgn, write_group, + write_test_bgn)) { + sr_failed =1 ; +if (!(gbl-> + phy_debug_mode_flags & +PHY_DEBUG_SWEEP_ALL_GROUPS )) { +return 0 ; + } } } } -if (sr_failed !=0 ) - group_failed =1 ; } +if (sr_failed !=0 ) + group_failed =1 ; } + } -if (group_failed ==0 ) { -for (read_group = write_group * -RW_MGR_MEM_IF_READ_DQS_WIDTH / -RW_MGR_MEM_IF_WRITE_DQS_WIDTH , - read_test_bgn =0 ; - read_group < (write_group +1 ) - *RW_MGR_MEM_IF_READ_DQS_WIDTH - /RW_MGR_MEM_IF_WRITE_DQS_WIDTH && - group_failed ==0 ; - read_group++, read_test_bgn += -RW_MGR_MEM_DQ_PER_READ_DQS ) { -if (!((STATIC_CALIB_STEPS ) & -CALIB_SKIP_WRITES )) { -if (!rw_mgr_mem_calibrate_vfifo_end - (read_group, read_test_bgn)) { - group_failed =1 ; - -if (!(gbl->phy_debug_mode_flags - &PHY_DEBUG_SWEEP_ALL_GROUPS )) { -return 0 ; - } +if (group_failed ==0 ) { +for (read_group = write_group * +RW_MGR_MEM_IF_READ_DQS_WIDTH / +RW_MGR_MEM_IF_WRITE_DQS_WIDTH , + read_test_bgn =0 ; + read_group < (write_group +1 ) + *RW_MGR_MEM_IF_READ_DQS_WIDTH + /RW_MGR_MEM_IF_WRITE_DQS_WIDTH && + group_failed ==0 ; + read_group++, read_test_bgn += +RW_MGR_MEM_DQ_PER_READ_DQS ) { +if (!((STATIC_CALIB_STEPS ) & +CALIB_SKIP_WRITES )) { +if (!rw_mgr_mem_calibrate_vfifo_end + (read_group, read_test_bgn)) { + group_failed =1 ; + +if (!(gbl->phy_debug_mode_flags + &PHY_DEBUG_SWEEP_ALL_GROUPS )) { +return 0 ; } } } } - -if (group_failed !=0 ) - failing_groups++; } +if (group_failed !=0 ) + failing_groups++; + } + +/* +* USER If there are any failing groups then report +* the failure. +*/ +if (failing_groups !=0 ) +return 0 ; + +/* Calibrate the LFIFO */ +if (!((STATIC_CALIB_STEPS ) &CALIB_SKIP_LFIFO )) {/* -* USER If there are any failing groups then report -* the failure. +* If we're skipping groups as part of debug, +* don't calibrate LFIFO. */ -if (failing_groups !=0 ) -return 0 ; - -/* Calibrate the LFIFO */ -if (!((STATIC_CALIB_STEPS ) &CALIB_SKIP_LFIFO )) { -/* -* If we're skipping groups as part of debug, -* don't calibrate LFIFO. -*/ -if (param->skip_groups ==0 ) { -if (!rw_mgr_mem_calibrate_lfifo ()) -return 0 ; - } +if (param->skip_groups ==0 ) { +if (!rw_mgr_mem_calibrate_lfifo ()) +return 0 ; } } }
Signature · 1 line
2.1.4
PATCH 91/172 ddr: altera: Internal mem_calibrate() cleanup part 1
In reply to Marek VasutThis is kind of microseries-within-series indent cleanup. Rework the code for the first loop within the middle-loop of the mega-loop to make it actually readable and not an insane cryptic pile of indent failure.
It is likely that this patch has checkpatch warnings, but for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 40 +++++++++++++++++----------------------- 1 file changed, 17 insertions(+), 23 deletions(-)
drivers/ddr/altera/sequencer.c +17 -23
@@ -3270,6 +3270,9 @@ static uint32_t mem_calibrate(void)uint32_t group_failed =0 ;uint32_t sr_failed =0 ; +const u32 rwdqs_ratio =RW_MGR_MEM_IF_READ_DQS_WIDTH / +RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; +debug ("%s:%d\n" , __func__, __LINE__);/* Initialize the data settings */
@@ -3339,31 +3342,22 @@ static uint32_t mem_calibrate(void) SCC_MGR_GROUP_COUNTER_OFFSET);scc_mgr_zero_group (write_group,0 ); -for (read_group = write_group * -RW_MGR_MEM_IF_READ_DQS_WIDTH / -RW_MGR_MEM_IF_WRITE_DQS_WIDTH , - read_test_bgn =0 ; - read_group < (write_group +1 ) * -RW_MGR_MEM_IF_READ_DQS_WIDTH / -RW_MGR_MEM_IF_WRITE_DQS_WIDTH && - group_failed ==0 ; - read_group++, read_test_bgn += -RW_MGR_MEM_DQ_PER_READ_DQS ) { +for (read_group = write_group * rwdqs_ratio, + read_test_bgn =0 ; + read_group < (write_group +1 ) * rwdqs_ratio && group_failed ==0 ; + read_group++, + read_test_bgn +=RW_MGR_MEM_DQ_PER_READ_DQS ) { +if (STATIC_CALIB_STEPS &CALIB_SKIP_VFIFO ) +continue ; +/* Calibrate the VFIFO */ -if (!((STATIC_CALIB_STEPS ) & -CALIB_SKIP_VFIFO )) { -if (!rw_mgr_mem_calibrate_vfifo - (read_group, - read_test_bgn)) { - group_failed =1 ; +if (rw_mgr_mem_calibrate_vfifo (read_group, + read_test_bgn)) +continue ; -if (!(gbl-> - phy_debug_mode_flags & -PHY_DEBUG_SWEEP_ALL_GROUPS )) { -return 0 ; - } - } - } + group_failed =1 ; +if (!(gbl->phy_debug_mode_flags &PHY_DEBUG_SWEEP_ALL_GROUPS )) +return 0 ; }/* Calibrate the output side */
Signature · 1 line
2.1.4
PATCH 92/172 ddr: altera: Internal mem_calibrate() cleanup part 2
In reply to Marek VasutThis is kind of microseries-within-series indent cleanup. Rework the code for the second loop within the middle-loop of the mega-loop to make it actually readable and not an insane cryptic pile of indent failure.
It is likely that this patch has checkpatch warnings, but for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 57 ++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 33 deletions(-)
drivers/ddr/altera/sequencer.c +24 -33
@@ -3268,7 +3268,6 @@ static uint32_t mem_calibrate(void)uint32_t run_groups, current_run;uint32_t failing_groups =0 ;uint32_t group_failed =0 ; -uint32_t sr_failed =0 ;const u32 rwdqs_ratio =RW_MGR_MEM_IF_READ_DQS_WIDTH /RW_MGR_MEM_IF_WRITE_DQS_WIDTH ;
@@ -3361,40 +3360,32 @@ static uint32_t mem_calibrate(void) }/* Calibrate the output side */ -if (group_failed ==0 ) { -for (rank_bgn =0 , sr =0 ; rank_bgn - <RW_MGR_MEM_NUMBER_OF_RANKS ; - rank_bgn += -NUM_RANKS_PER_SHADOW_REG , - ++sr) { - sr_failed =0 ; -if (!((STATIC_CALIB_STEPS ) & -CALIB_SKIP_WRITES )) { -if ((STATIC_CALIB_STEPS ) - &CALIB_SKIP_DELAY_SWEEPS ) { -/* not needed in quick mode! */ - }else { +if (group_failed ==0 ) { +for (rank_bgn =0 , sr =0 ; + rank_bgn <RW_MGR_MEM_NUMBER_OF_RANKS ; + rank_bgn +=NUM_RANKS_PER_SHADOW_REG , sr++) { +if (STATIC_CALIB_STEPS &CALIB_SKIP_WRITES ) +continue ; + +/* Not needed in quick mode! */ +if (STATIC_CALIB_STEPS &CALIB_SKIP_DELAY_SWEEPS ) +continue ; +/* -* Determine if this set of -* ranks should be skipped -* entirely. +* Determine if this set of ranks +* should be skipped entirely. */ -if (!param->skip_shadow_regs[sr]) { -if (!rw_mgr_mem_calibrate_writes - (rank_bgn, write_group, - write_test_bgn)) { - sr_failed =1 ; -if (!(gbl-> - phy_debug_mode_flags & -PHY_DEBUG_SWEEP_ALL_GROUPS )) { -return 0 ; - } - } - } - } - } -if (sr_failed !=0 ) - group_failed =1 ; +if (param->skip_shadow_regs[sr]) +continue ; + +/* Calibrate WRITEs */ +if (rw_mgr_mem_calibrate_writes (rank_bgn, + write_group, write_test_bgn)) +continue ; + + group_failed =1 ; +if (!(gbl->phy_debug_mode_flags &PHY_DEBUG_SWEEP_ALL_GROUPS )) +return 0 ; } }
Signature · 1 line
2.1.4
PATCH 93/172 ddr: altera: Internal mem_calibrate() cleanup part 3
In reply to Marek VasutThis is kind of microseries-within-series indent cleanup. Rework the code for the third loop within the middle-loop of the mega-loop to make it actually readable and not an insane cryptic pile of indent failure.
It is likely that this patch has checkpatch warnings, but for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 37 +++++++++++++++---------------------- 1 file changed, 15 insertions(+), 22 deletions(-)
drivers/ddr/altera/sequencer.c +15 -22
@@ -3390,28 +3390,21 @@ static uint32_t mem_calibrate(void) }if (group_failed ==0 ) { -for (read_group = write_group * -RW_MGR_MEM_IF_READ_DQS_WIDTH / -RW_MGR_MEM_IF_WRITE_DQS_WIDTH , - read_test_bgn =0 ; - read_group < (write_group +1 ) - *RW_MGR_MEM_IF_READ_DQS_WIDTH - /RW_MGR_MEM_IF_WRITE_DQS_WIDTH && - group_failed ==0 ; - read_group++, read_test_bgn += -RW_MGR_MEM_DQ_PER_READ_DQS ) { -if (!((STATIC_CALIB_STEPS ) & -CALIB_SKIP_WRITES )) { -if (!rw_mgr_mem_calibrate_vfifo_end - (read_group, read_test_bgn)) { - group_failed =1 ; - -if (!(gbl->phy_debug_mode_flags - &PHY_DEBUG_SWEEP_ALL_GROUPS )) { -return 0 ; - } - } - } +for (read_group = write_group * rwdqs_ratio, + read_test_bgn =0 ; + read_group < (write_group +1 ) * rwdqs_ratio && group_failed ==0 ; + read_group++, + read_test_bgn +=RW_MGR_MEM_DQ_PER_READ_DQS ) { +if (STATIC_CALIB_STEPS &CALIB_SKIP_WRITES ) +continue ; + +if (rw_mgr_mem_calibrate_vfifo_end (read_group, + read_test_bgn)) +continue ; + + group_failed =1 ; +if (!(gbl->phy_debug_mode_flags &PHY_DEBUG_SWEEP_ALL_GROUPS )) +return 0 ; } }
Signature · 1 line
2.1.4
PATCH 94/172 ddr: altera: Internal mem_calibrate() cleanup part 4
In reply to Marek VasutThis is kind of microseries-within-series indent cleanup. Rework the code for the last loop within the mega-loop to make it actually readable and not an insane cryptic pile of indent failure.
It is likely that this patch has checkpatch warnings, but for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-)
drivers/ddr/altera/sequencer.c +12 -10
@@ -3419,17 +3419,19 @@ static uint32_t mem_calibrate(void)if (failing_groups !=0 )return 0 ; +if (STATIC_CALIB_STEPS &CALIB_SKIP_LFIFO ) +continue ; + +/* +* If we're skipping groups as part of debug, +* don't calibrate LFIFO. +*/ +if (param->skip_groups !=0 ) +continue ; +/* Calibrate the LFIFO */ -if (!((STATIC_CALIB_STEPS ) &CALIB_SKIP_LFIFO )) { -/* -* If we're skipping groups as part of debug, -* don't calibrate LFIFO. -*/ -if (param->skip_groups ==0 ) { -if (!rw_mgr_mem_calibrate_lfifo ()) -return 0 ; - } - } +if (!rw_mgr_mem_calibrate_lfifo ()) +return 0 ; }/*
Signature · 1 line
2.1.4
PATCH 95/172 ddr: altera: Internal mem_calibrate() cleanup part 5
In reply to Marek VasutThis is kind of microseries-within-series indent cleanup. Rework the code for the the middle-loop of the mega-loop this time and deal with the group_failed variable. Instead of checking if the group failed in the previous calibration part, just jump to the end of the loop if calibration did fail and increment the counter. This shaves away one more level of indent while making the code slightly more readable.
It is likely that this patch has checkpatch warnings, but for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 98 +++++++++++++++++++++++------------------- 1 file changed, 53 insertions(+), 45 deletions(-)
drivers/ddr/altera/sequencer.c +53 -45
@@ -3326,7 +3326,8 @@ static uint32_t mem_calibrate(void)for (write_group =0 , write_test_bgn =0 ; write_group <RW_MGR_MEM_IF_WRITE_DQS_WIDTH ; write_group++, write_test_bgn +=RW_MGR_MEM_DQ_PER_WRITE_DQS ) { -/* Initialized the group failure */ + +/* Initialize the group failure */ group_failed =0 ; current_run = run_groups & ((1 <<
@@ -3343,7 +3344,7 @@ static uint32_t mem_calibrate(void)for (read_group = write_group * rwdqs_ratio, read_test_bgn =0 ; - read_group < (write_group +1 ) * rwdqs_ratio && group_failed ==0 ; + read_group < (write_group +1 ) * rwdqs_ratio; read_group++, read_test_bgn +=RW_MGR_MEM_DQ_PER_READ_DQS ) {if (STATIC_CALIB_STEPS &CALIB_SKIP_VFIFO )
@@ -3354,62 +3355,69 @@ static uint32_t mem_calibrate(void) read_test_bgn))continue ; - group_failed =1 ;if (!(gbl->phy_debug_mode_flags &PHY_DEBUG_SWEEP_ALL_GROUPS ))return 0 ; + +/* The group failed, we're done. */ + goto grp_failed; }/* Calibrate the output side */ -if (group_failed ==0 ) { -for (rank_bgn =0 , sr =0 ; - rank_bgn <RW_MGR_MEM_NUMBER_OF_RANKS ; - rank_bgn +=NUM_RANKS_PER_SHADOW_REG , sr++) { -if (STATIC_CALIB_STEPS &CALIB_SKIP_WRITES ) -continue ; +for (rank_bgn =0 , sr =0 ; + rank_bgn <RW_MGR_MEM_NUMBER_OF_RANKS ; + rank_bgn +=NUM_RANKS_PER_SHADOW_REG , sr++) { +if (STATIC_CALIB_STEPS &CALIB_SKIP_WRITES ) +continue ; -/* Not needed in quick mode! */ -if (STATIC_CALIB_STEPS &CALIB_SKIP_DELAY_SWEEPS ) -continue ; +/* Not needed in quick mode! */ +if (STATIC_CALIB_STEPS &CALIB_SKIP_DELAY_SWEEPS ) +continue ; -/* -* Determine if this set of ranks -* should be skipped entirely. -*/ -if (param->skip_shadow_regs[sr]) -continue ; +/* +* Determine if this set of ranks +* should be skipped entirely. +*/ +if (param->skip_shadow_regs[sr]) +continue ; -/* Calibrate WRITEs */ -if (rw_mgr_mem_calibrate_writes (rank_bgn, - write_group, write_test_bgn)) -continue ; +/* Calibrate WRITEs */ +if (rw_mgr_mem_calibrate_writes (rank_bgn, + write_group, write_test_bgn)) +continue ; - group_failed =1 ; -if (!(gbl->phy_debug_mode_flags &PHY_DEBUG_SWEEP_ALL_GROUPS )) -return 0 ; - } + group_failed =1 ; +if (!(gbl->phy_debug_mode_flags &PHY_DEBUG_SWEEP_ALL_GROUPS )) +return 0 ; } -if (group_failed ==0 ) { -for (read_group = write_group * rwdqs_ratio, - read_test_bgn =0 ; - read_group < (write_group +1 ) * rwdqs_ratio && group_failed ==0 ; - read_group++, - read_test_bgn +=RW_MGR_MEM_DQ_PER_READ_DQS ) { -if (STATIC_CALIB_STEPS &CALIB_SKIP_WRITES ) -continue ; - -if (rw_mgr_mem_calibrate_vfifo_end (read_group, - read_test_bgn)) -continue ; - - group_failed =1 ; -if (!(gbl->phy_debug_mode_flags &PHY_DEBUG_SWEEP_ALL_GROUPS )) -return 0 ; - } +/* Some group failed, we're done. */ +if (group_failed) + goto grp_failed; + +for (read_group = write_group * rwdqs_ratio, + read_test_bgn =0 ; + read_group < (write_group +1 ) * rwdqs_ratio; + read_group++, + read_test_bgn +=RW_MGR_MEM_DQ_PER_READ_DQS ) { +if (STATIC_CALIB_STEPS &CALIB_SKIP_WRITES ) +continue ; + +if (rw_mgr_mem_calibrate_vfifo_end (read_group, + read_test_bgn)) +continue ; + +if (!(gbl->phy_debug_mode_flags &PHY_DEBUG_SWEEP_ALL_GROUPS )) +return 0 ; + +/* The group failed, we're done. */ + goto grp_failed; } -if (group_failed !=0 ) - failing_groups++; +/* No group failed, continue as usual. */ +continue ; + +grp_failed:/* A group failed, increment the counter. */ + failing_groups++; }/*
Signature · 1 line
2.1.4
PATCH 96/172 ddr: altera: Internal mem_calibrate() cleanup part 6
In reply to Marek VasutAdd kerneldoc to this function.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
drivers/ddr/altera/sequencer.c +5 -1
@@ -3258,7 +3258,11 @@ static void mem_skip_calibrate(void)writel (gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); } -/* Memory calibration entry point */ +/** +* mem_calibrate() - Memory calibration entry point. +* +* Perform memory calibration. +*/ static uint32_t mem_calibrate (void ) {uint32_t i;
Signature · 1 line
2.1.4
PATCH 97/172 ddr: altera: Minor clean up of rw_mgr_mem_initialize()
In reply to Marek VasutAdd kerneldoc and do a minor comment cleanup. No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)
drivers/ddr/altera/sequencer.c +8 -3
@@ -951,6 +951,11 @@ static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2, } } +/** +* rw_mgr_mem_initialize() - Initialize RW Manager +* +* Initialize RW Manager. +*/ static void rw_mgr_mem_initialize (void ) {debug ("%s:%d\n" , __func__, __LINE__);
@@ -969,7 +974,7 @@ static void rw_mgr_mem_initialize(void)* significant bits */ -/* start with memory RESET activated */ +/* Start with memory RESET activated */ /* tINIT = 200us */
@@ -986,7 +991,7 @@ static void rw_mgr_mem_initialize(void)SEQ_TINIT_CNTR2_VAL , RW_MGR_INIT_RESET_0_CKE_0); -/* indicate that memory is stable */ +/* Indicate that memory is stable. */ writel (1 , &phy_mgr_cfg->reset_mem_stbl);/*
@@ -1007,7 +1012,7 @@ static void rw_mgr_mem_initialize(void)SEQ_TRESET_CNTR2_VAL , RW_MGR_INIT_RESET_1_CKE_0); -/* bring up clock enable */ +/* Bring up clock enable. */ /* tXRP < 250 ck cycles */ delay_for_n_mem_clocks (250 );
Signature · 1 line
2.1.4
PATCH 98/172 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 1
In reply to Marek VasutThis patch just adds an expanded documentation header to the aforementioned function. This is needed to make it easier to match the purpose of this function with the documentation.
No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-)
drivers/ddr/altera/sequencer.c +12 -4
@@ -2186,11 +2186,19 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,return (dq_margin >=0 ) && (dqs_margin >=0 ); } -/* -* calibrate the read valid prediction FIFO. +/** +* rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO +* @rw_group: Read/Write Group +* @test_bgn: Rank at which the test begins +* +* Stage 1: Calibrate the read valid prediction FIFO. +* +* This function implements UniPHY calibration Stage 1, as explained in +* detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". * -* - read valid prediction will consist of finding a good DQS enable phase, -* DQS enable delay, DQS input phase, and DQS input delay. +* - read valid prediction will consist of finding: +* - DQS enable phase and DQS enable delay (DQS Enable Calibration) +* - DQS input phase and DQS input delay (DQ/DQS Centering) * - we also do a per-bit deskew on the DQ lines. */ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
Signature · 1 line
2.1.4
PATCH 99/172 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 2
In reply to Marek VasutThis is kind of microseries-within-series indent cleanup. This patch just tweaks the indentation so it is visible what is supposed to go where.
It is likely that this patch has checkpatch warnings, but for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 56 ++++++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 29 deletions(-)
drivers/ddr/altera/sequencer.c +27 -29
@@ -2243,8 +2243,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, write_group, d); } -for (p =0 ; p <=IO_DQDQS_OUT_PHASE_MAX && grp_calibrated ==0 ; - p++) { +for (p =0 ; p <=IO_DQDQS_OUT_PHASE_MAX && grp_calibrated ==0 ; p++) {/* set a particular dqdqs phase */ scc_mgr_set_dqdqs_output_phase_all_ranks (read_group, p);
@@ -2257,10 +2256,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,* using current DQDQS phase. */ rw_mgr_mem_calibrate_read_load_patterns (0 ,1 ); -if (!(gbl->phy_debug_mode_flags & -PHY_DEBUG_DISABLE_GUARANTEED_READ )) { +if (!(gbl->phy_debug_mode_flags &PHY_DEBUG_DISABLE_GUARANTEED_READ )) {if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks - (read_group,1 , &bit_chk)) { + (read_group,1 , &bit_chk)) {debug_cond (DLEVEL ==1 ,"%s:%d Guaranteed read test failed:" , __func__, __LINE__); debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
@@ -2269,37 +2267,37 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, } } -/* case:56390 */ +/* case:56390 */ grp_calibrated =1 ; -if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay - (write_group, read_group, test_bgn)) { -/* -* USER Read per-bit deskew can be done on a -* per shadow register basis. -*/ -for (rank_bgn =0 , sr =0 ; - rank_bgn <RW_MGR_MEM_NUMBER_OF_RANKS ; - rank_bgn +=NUM_RANKS_PER_SHADOW_REG , - ++sr) { +if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay + (write_group, read_group, test_bgn)) {/* -* Determine if this set of ranks -* should be skipped entirely. +* USER Read per-bit deskew can be done on a +* per shadow register basis. */ -if (!param->skip_shadow_regs[sr]) { +for (rank_bgn =0 , sr =0 ; + rank_bgn <RW_MGR_MEM_NUMBER_OF_RANKS ; + rank_bgn +=NUM_RANKS_PER_SHADOW_REG , + ++sr) {/* -* If doing read after write -* calibration, do not update -* FOM, now - do it then. +* Determine if this set of ranks +* should be skipped entirely. */ -if (!rw_mgr_mem_calibrate_vfifo_center - (rank_bgn, write_group, - read_group, test_bgn,1 ,0 )) { - grp_calibrated =0 ; - failed_substage = -CAL_SUBSTAGE_VFIFO_CENTER ; +if (!param->skip_shadow_regs[sr]) { +/* +* If doing read after write +* calibration, do not update +* FOM, now - do it then. +*/ +if (!rw_mgr_mem_calibrate_vfifo_center + (rank_bgn, write_group, + read_group, test_bgn, +1 ,0 )) { + grp_calibrated =0 ; + failed_substage =CAL_SUBSTAGE_VFIFO_CENTER ; + } } } - } }else { grp_calibrated =0 ; failed_substage =CAL_SUBSTAGE_DQS_EN_PHASE ;
Signature · 1 line
2.1.4
PATCH 100/172 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 3
In reply to Marek VasutThis is kind of microseries-within-series indent cleanup. This patch just tweaks the indentation so it is visible what to do with the grp_calibrated variable.
It is likely that this patch has checkpatch warnings, but for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-)
drivers/ddr/altera/sequencer.c +19 -19
@@ -2235,8 +2235,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,/* * In RLDRAMX we may be messing the delay of pins in * the same write group but outside of the current read -* the group, but that's ok because we haven't -* calibrated output side yet. +* the group, but that's ok because we haven't calibrated +* output side yet. */ if (d >0 ) { scc_mgr_apply_group_all_out_delay_add_all_ranks(
@@ -2276,27 +2276,27 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,* per shadow register basis. */ for (rank_bgn =0 , sr =0 ; - rank_bgn <RW_MGR_MEM_NUMBER_OF_RANKS ; - rank_bgn +=NUM_RANKS_PER_SHADOW_REG , - ++sr) { + rank_bgn <RW_MGR_MEM_NUMBER_OF_RANKS ; + rank_bgn +=NUM_RANKS_PER_SHADOW_REG , sr++) {/* * Determine if this set of ranks * should be skipped entirely. */ -if (!param->skip_shadow_regs[sr]) { -/* -* If doing read after write -* calibration, do not update -* FOM, now - do it then. -*/ -if (!rw_mgr_mem_calibrate_vfifo_center - (rank_bgn, write_group, - read_group, test_bgn, -1 ,0 )) { - grp_calibrated =0 ; - failed_substage =CAL_SUBSTAGE_VFIFO_CENTER ; - } - } +if (param->skip_shadow_regs[sr]) +continue ; +/* +* If doing read after write +* calibration, do not update +* FOM, now - do it then. +*/ +if (rw_mgr_mem_calibrate_vfifo_center + (rank_bgn, write_group, + read_group, test_bgn, +1 ,0 )) +continue ; + + grp_calibrated =0 ; + failed_substage =CAL_SUBSTAGE_VFIFO_CENTER ; } }else { grp_calibrated =0 ;
Signature · 1 line
2.1.4
PATCH 101/172 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 4
In reply to Marek VasutThis is kind of microseries-within-series indent cleanup. This patch cleans up the handling of grp_calibrated such that the variable isn't used all over the place, but just very localy. This allows trimming down the indent issues.
It is likely that this patch has checkpatch warnings, but for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 81 +++++++++++++++++++++--------------------- 1 file changed, 41 insertions(+), 40 deletions(-)
drivers/ddr/altera/sequencer.c +41 -40
@@ -2226,12 +2226,10 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,/* update info for sims */ reg_file_set_group (read_group); - grp_calibrated =0 ; -reg_file_set_sub_stage (CAL_SUBSTAGE_GUARANTEED_READ ); failed_substage =CAL_SUBSTAGE_GUARANTEED_READ ; -for (d =0 ; d <= dtaps_per_ptap && grp_calibrated ==0 ; d +=2 ) { +for (d =0 ; d <= dtaps_per_ptap; d +=2 ) {/* * In RLDRAMX we may be messing the delay of pins in * the same write group but outside of the current read
@@ -2243,7 +2241,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, write_group, d); } -for (p =0 ; p <=IO_DQDQS_OUT_PHASE_MAX && grp_calibrated ==0 ; p++) { +for (p =0 ; p <=IO_DQDQS_OUT_PHASE_MAX ; p++) {/* set a particular dqdqs phase */ scc_mgr_set_dqdqs_output_phase_all_ranks (read_group, p);
@@ -2268,49 +2266,52 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, }/* case:56390 */ - grp_calibrated =1 ; -if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay +if (!rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay (write_group, read_group, test_bgn)) { -/* -* USER Read per-bit deskew can be done on a -* per shadow register basis. -*/ -for (rank_bgn =0 , sr =0 ; - rank_bgn <RW_MGR_MEM_NUMBER_OF_RANKS ; - rank_bgn +=NUM_RANKS_PER_SHADOW_REG , sr++) { -/* -* Determine if this set of ranks -* should be skipped entirely. -*/ -if (param->skip_shadow_regs[sr]) -continue ; -/* -* If doing read after write -* calibration, do not update -* FOM, now - do it then. -*/ -if (rw_mgr_mem_calibrate_vfifo_center - (rank_bgn, write_group, - read_group, test_bgn, -1 ,0 )) -continue ; - - grp_calibrated =0 ; - failed_substage =CAL_SUBSTAGE_VFIFO_CENTER ; - } - }else { - grp_calibrated =0 ; failed_substage =CAL_SUBSTAGE_DQS_EN_PHASE ; +continue ; + } + +/* +* USER Read per-bit deskew can be done on a +* per shadow register basis. +*/ + grp_calibrated =1 ; +for (rank_bgn =0 , sr =0 ; + rank_bgn <RW_MGR_MEM_NUMBER_OF_RANKS ; + rank_bgn +=NUM_RANKS_PER_SHADOW_REG , sr++) { +/* +* Determine if this set of ranks +* should be skipped entirely. +*/ +if (param->skip_shadow_regs[sr]) +continue ; +/* +* If doing read after write +* calibration, do not update +* FOM, now - do it then. +*/ +if (rw_mgr_mem_calibrate_vfifo_center (rank_bgn, + write_group, read_group, + test_bgn,1 ,0 )) + +continue ; + + grp_calibrated =0 ; + failed_substage =CAL_SUBSTAGE_VFIFO_CENTER ; } + +if (grp_calibrated) + goto cal_done_ok; } } -if (grp_calibrated ==0 ) { -set_failing_group_stage (write_group,CAL_STAGE_VFIFO , - failed_substage); -return 0 ; - } +/* Calibration Stage 1 failed. */ +set_failing_group_stage (write_group,CAL_STAGE_VFIFO , failed_substage); +return 0 ; +/* Calibration Stage 1 completed OK. */ +cal_done_ok:/* * Reset the delay chains back to zero if they have moved > 1 * (check for > 1 because loop will increase d even when pass in
Signature · 1 line
2.1.4
PATCH 102/172 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 5
In reply to Marek VasutThis is kind of microseries-within-series indent cleanup. This patch fixes the broken formatting strings in debug_cond() invocations.
It is likely that this patch has checkpatch warnings, but for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-)
drivers/ddr/altera/sequencer.c +6 -7
@@ -2245,9 +2245,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,/* set a particular dqdqs phase */ scc_mgr_set_dqdqs_output_phase_all_ranks (read_group, p); -debug_cond (DLEVEL ==1 ,"%s:%d calibrate_vfifo: g=%u \ -p=%u d=%u\n" , __func__, __LINE__, - read_group, p, d); +debug_cond (DLEVEL ==1 , +"%s:%d calibrate_vfifo: g=%u p=%u d=%u\n" , + __func__, __LINE__, read_group, p, d);/* * Load up the patterns used by read calibration
@@ -2257,10 +2257,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,if (!(gbl->phy_debug_mode_flags &PHY_DEBUG_DISABLE_GUARANTEED_READ )) {if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks (read_group,1 , &bit_chk)) { -debug_cond (DLEVEL ==1 ,"%s:%d Guaranteed read test failed:" , - __func__, __LINE__); -debug_cond (DLEVEL ==1 ," g=%u p=%u d=%u\n" , - read_group, p, d); +debug_cond (DLEVEL ==1 , +"%s:%d Guaranteed read test failed: g=%u p=%u d=%u\n" , + __func__, __LINE__, read_group, p, d);break ; } }
Signature · 1 line
2.1.4
PATCH 103/172 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 6
In reply to Marek VasutThis is kind of microseries-within-series indent cleanup. It is clear that the read_group and write_group variables have the same value, to just make them into one variable called rw_group. While doing this, constify the variables as they are constant.
It is likely that this patch has checkpatch warnings, but for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 34 ++++++++++++++-------------------- 1 file changed, 14 insertions(+), 20 deletions(-)
drivers/ddr/altera/sequencer.c +14 -20
@@ -2201,30 +2201,25 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,* - DQS input phase and DQS input delay (DQ/DQS Centering) * - we also do a per-bit deskew on the DQ lines. */ -static uint32_t rw_mgr_mem_calibrate_vfifo (uint32_t read_group, -uint32_t test_bgn) +static int rw_mgr_mem_calibrate_vfifo (const u32 rw_group,const u32 test_bgn) {uint32_t p, d, rank_bgn, sr;uint32_t dtaps_per_ptap;uint32_t bit_chk;uint32_t grp_calibrated; -uint32_t write_group, write_test_bgn;uint32_t failed_substage; -debug ("%s:%d: %u %u\n" , __func__, __LINE__, read_group, test_bgn); +debug ("%s:%d: %u %u\n" , __func__, __LINE__, rw_group, test_bgn);/* update info for sims */ reg_file_set_stage (CAL_STAGE_VFIFO ); - write_group = read_group; - write_test_bgn = test_bgn; -/* USER Determine number of delay taps for each phase tap */ dtaps_per_ptap =DIV_ROUND_UP (IO_DELAY_PER_OPA_TAP ,IO_DELAY_PER_DQS_EN_DCHAIN_TAP ) -1 ;/* update info for sims */ -reg_file_set_group (read_group); +reg_file_set_group (rw_group);reg_file_set_sub_stage (CAL_SUBSTAGE_GUARANTEED_READ ); failed_substage =CAL_SUBSTAGE_GUARANTEED_READ ;
@@ -2232,22 +2227,22 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,for (d =0 ; d <= dtaps_per_ptap; d +=2 ) {/* * In RLDRAMX we may be messing the delay of pins in -* the same write group but outside of the current read -* the group, but that's ok because we haven't calibrated +* the same write rw_group but outside of the current read +* the rw_group, but that's ok because we haven't calibrated * output side yet. */ if (d >0 ) {scc_mgr_apply_group_all_out_delay_add_all_ranks ( - write_group, d); + rw_group, d); }for (p =0 ; p <=IO_DQDQS_OUT_PHASE_MAX ; p++) {/* set a particular dqdqs phase */ -scc_mgr_set_dqdqs_output_phase_all_ranks (read_group, p); +scc_mgr_set_dqdqs_output_phase_all_ranks (rw_group, p);debug_cond (DLEVEL ==1 ,"%s:%d calibrate_vfifo: g=%u p=%u d=%u\n" , - __func__, __LINE__, read_group, p, d); + __func__, __LINE__, rw_group, p, d);/* * Load up the patterns used by read calibration
@@ -2256,17 +2251,17 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,rw_mgr_mem_calibrate_read_load_patterns (0 ,1 );if (!(gbl->phy_debug_mode_flags &PHY_DEBUG_DISABLE_GUARANTEED_READ )) {if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks - (read_group,1 , &bit_chk)) { + (rw_group,1 , &bit_chk)) {debug_cond (DLEVEL ==1 ,"%s:%d Guaranteed read test failed: g=%u p=%u d=%u\n" , - __func__, __LINE__, read_group, p, d); + __func__, __LINE__, rw_group, p, d);break ; } }/* case:56390 */ if (!rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay - (write_group, read_group, test_bgn)) { + (rw_group, rw_group, test_bgn)) { failed_substage =CAL_SUBSTAGE_DQS_EN_PHASE ;continue ; }
@@ -2291,9 +2286,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,* FOM, now - do it then. */ if (rw_mgr_mem_calibrate_vfifo_center (rank_bgn, - write_group, read_group, + rw_group, rw_group, test_bgn,1 ,0 )) -continue ; grp_calibrated =0 ;
@@ -2306,7 +2300,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, }/* Calibration Stage 1 failed. */ -set_failing_group_stage (write_group,CAL_STAGE_VFIFO , failed_substage); +set_failing_group_stage (rw_group,CAL_STAGE_VFIFO , failed_substage);return 0 ;/* Calibration Stage 1 completed OK. */
@@ -2317,7 +2311,7 @@ cal_done_ok:* first case). */ if (d >2 ) -scc_mgr_zero_group (write_group,1 ); +scc_mgr_zero_group (rw_group,1 );return 1 ; }
Signature · 1 line
2.1.4
PATCH 104/172 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 7
In reply to Marek VasutMildly reorder the function so that the reg_file_set*() calls are in the same place. No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-)
drivers/ddr/altera/sequencer.c +6 -8
@@ -2211,19 +2211,17 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)debug ("%s:%d: %u %u\n" , __func__, __LINE__, rw_group, test_bgn); -/* update info for sims */ +/* Update info for sims */ +reg_file_set_group (rw_group);reg_file_set_stage (CAL_STAGE_VFIFO ); +reg_file_set_sub_stage (CAL_SUBSTAGE_GUARANTEED_READ ); -/* USER Determine number of delay taps for each phase tap */ + failed_substage =CAL_SUBSTAGE_GUARANTEED_READ ; + +/* USER Determine number of delay taps for each phase tap. */ dtaps_per_ptap =DIV_ROUND_UP (IO_DELAY_PER_OPA_TAP ,IO_DELAY_PER_DQS_EN_DCHAIN_TAP ) -1 ; -/* update info for sims */ -reg_file_set_group (rw_group); - -reg_file_set_sub_stage (CAL_SUBSTAGE_GUARANTEED_READ ); - failed_substage =CAL_SUBSTAGE_GUARANTEED_READ ; -for (d =0 ; d <= dtaps_per_ptap; d +=2 ) {/* * In RLDRAMX we may be messing the delay of pins in
Signature · 1 line
2.1.4
PATCH 105/172 ddr: altera: Extract guaranteed write from rw_mgr_mem_calibrate_vfifo()
In reply to Marek VasutJust extract this piece of functionality into separate function to make the code better separated. This matches the division in Altera documentation, Altera EMI_RM 2015.05.04 , section 1, the UniPHY Calibration Stages.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 76 ++++++++++++++++++++++++++++++------------ 1 file changed, 54 insertions(+), 22 deletions(-)
drivers/ddr/altera/sequencer.c +54 -22
@@ -7,6 +7,7 @@#include <common.h> #include <asm/io.h> #include <asm/arch/sdram.h> +#include <errno.h> #include "sequencer.h" #include "sequencer_auto.h" #include "sequencer_auto_ac_init.h"
@@ -2187,6 +2188,53 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, }/** +* rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device +* @rw_group: Read/Write Group +* @phase: DQ/DQS phase +* +* Because initially no communication ca be reliably performed with the memory +* device, the sequencer uses a guaranteed write mechanism to write data into +* the memory device. +*/ +static int rw_mgr_mem_calibrate_guaranteed_write (const u32 rw_group, +const u32 phase) +{ +u32 bit_chk; +int ret; + +/* Set a particular DQ/DQS phase. */ +scc_mgr_set_dqdqs_output_phase_all_ranks (rw_group, phase); + +debug_cond (DLEVEL ==1 ,"%s:%d guaranteed write: g=%u p=%u\n" , + __func__, __LINE__, rw_group, phase); + +/* +* Altera EMI_RM 2015.05.04 :: Figure 1-25 +* Load up the patterns used by read calibration using the +* current DQDQS phase. +*/ +rw_mgr_mem_calibrate_read_load_patterns (0 ,1 ); + +if (gbl->phy_debug_mode_flags &PHY_DEBUG_DISABLE_GUARANTEED_READ ) +return 0 ; + +/* +* Altera EMI_RM 2015.05.04 :: Figure 1-26 +* Back-to-Back reads of the patterns used for calibration. +*/ + ret =rw_mgr_mem_calibrate_read_test_patterns_all_ranks (rw_group,1 , + &bit_chk); +if (!ret) {/* FIXME: 0 means failure in this old code :-( */ +debug_cond (DLEVEL ==1 , +"%s:%d Guaranteed read test failed: g=%u p=%u\n" , + __func__, __LINE__, rw_group, phase); +return -EIO ; + } + +return 0 ; +} + +/** * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO * @rw_group: Read/Write Group * @test_bgn: Rank at which the test begins
@@ -2205,10 +2253,11 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) {uint32_t p, d, rank_bgn, sr;uint32_t dtaps_per_ptap; -uint32_t bit_chk;uint32_t grp_calibrated;uint32_t failed_substage; +int ret; +debug ("%s:%d: %u %u\n" , __func__, __LINE__, rw_group, test_bgn);/* Update info for sims */
@@ -2235,27 +2284,10 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) }for (p =0 ; p <=IO_DQDQS_OUT_PHASE_MAX ; p++) { -/* set a particular dqdqs phase */ -scc_mgr_set_dqdqs_output_phase_all_ranks (rw_group, p); - -debug_cond (DLEVEL ==1 , -"%s:%d calibrate_vfifo: g=%u p=%u d=%u\n" , - __func__, __LINE__, rw_group, p, d); - -/* -* Load up the patterns used by read calibration -* using current DQDQS phase. -*/ -rw_mgr_mem_calibrate_read_load_patterns (0 ,1 ); -if (!(gbl->phy_debug_mode_flags &PHY_DEBUG_DISABLE_GUARANTEED_READ )) { -if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks - (rw_group,1 , &bit_chk)) { -debug_cond (DLEVEL ==1 , -"%s:%d Guaranteed read test failed: g=%u p=%u d=%u\n" , - __func__, __LINE__, rw_group, p, d); -break ; - } - } +/* 1) Guaranteed Write */ + ret =rw_mgr_mem_calibrate_guaranteed_write (rw_group, p); +if (ret) +break ;/* case:56390 */ if (!rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
Signature · 1 line
2.1.4
PATCH 106/172 ddr: altera: Extract DQS enable calibration from rw_mgr_mem_calibrate_vfifo()
In reply to Marek VasutJust extract this piece of functionality into separate function to make the code better separated. This matches the division in Altera documentation, Altera EMI_RM 2015.05.04 , section 1, the UniPHY Calibration Stages.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-)
drivers/ddr/altera/sequencer.c +29 -3
@@ -2235,6 +2235,31 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group, }/** +* rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration +* @rw_group: Read/Write Group +* @test_bgn: Rank at which the test begins +* +* DQS enable calibration ensures reliable capture of the DQ signal without +* glitches on the DQS line. +*/ +static int rw_mgr_mem_calibrate_dqs_enable_calibration (const u32 rw_group, +const u32 test_bgn) +{ +int ret; + +/* +* Altera EMI_RM 2015.05.04 :: Figure 1-27 +* DQS and DQS Eanble Signal Relationships. +*/ + ret =rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay ( + rw_group, rw_group, test_bgn); +if (!ret)/* FIXME: 0 means failure in this old code :-( */ +return -EIO ; + +return 0 ; +} + +/** * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO * @rw_group: Read/Write Group * @test_bgn: Rank at which the test begins
@@ -2289,9 +2314,10 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)if (ret)break ; -/* case:56390 */ -if (!rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay - (rw_group, rw_group, test_bgn)) { +/* 2) DQS Enable Calibration */ + ret =rw_mgr_mem_calibrate_dqs_enable_calibration (rw_group, + test_bgn); +if (ret) { failed_substage =CAL_SUBSTAGE_DQS_EN_PHASE ;continue ; }
Signature · 1 line
2.1.4
PATCH 107/172 ddr: altera: Extract Centering DQ/DQS from rw_mgr_mem_calibrate_vfifo()
In reply to Marek VasutJust extract this piece of functionality into separate function to make the code better separated. This matches the division in Altera documentation, Altera EMI_RM 2015.05.04 , section 1, the UniPHY Calibration Stages.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 84 ++++++++++++++++++++++++++++-------------- 1 file changed, 57 insertions(+), 27 deletions(-)
drivers/ddr/altera/sequencer.c +57 -27
@@ -2260,6 +2260,53 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group, }/** +* rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS +* @rw_group: Read/Write Group +* @test_bgn: Rank at which the test begins +* @use_read_test: Perform a read test +* @update_fom: Update FOM +* +* The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads +* within a group. +*/ +static int +rw_mgr_mem_calibrate_dq_dqs_centering (const u32 rw_group,const u32 test_bgn, +const int use_read_test, +const int update_fom) + +{ +int ret, grp_calibrated; +u32 rank_bgn, sr; + +/* +* Altera EMI_RM 2015.05.04 :: Figure 1-28 +* Read per-bit deskew can be done on a per shadow register basis. +*/ + grp_calibrated =1 ; +for (rank_bgn =0 , sr =0 ; + rank_bgn <RW_MGR_MEM_NUMBER_OF_RANKS ; + rank_bgn +=NUM_RANKS_PER_SHADOW_REG , sr++) { +/* Check if this set of ranks should be skipped entirely. */ +if (param->skip_shadow_regs[sr]) +continue ; + + ret =rw_mgr_mem_calibrate_vfifo_center (rank_bgn, rw_group, + rw_group, test_bgn, + use_read_test, + update_fom); +if (ret) +continue ; + + grp_calibrated =0 ; + } + +if (!grp_calibrated) +return -EIO ; + +return 0 ; +} + +/** * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO * @rw_group: Read/Write Group * @test_bgn: Rank at which the test begins
@@ -2276,9 +2323,8 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,*/ static int rw_mgr_mem_calibrate_vfifo (const u32 rw_group,const u32 test_bgn) { -uint32_t p, d, rank_bgn, sr; +uint32_t p, d;uint32_t dtaps_per_ptap; -uint32_t grp_calibrated;uint32_t failed_substage;int ret;
@@ -2322,36 +2368,20 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)continue ; } +/* 3) Centering DQ/DQS */ /* -* USER Read per-bit deskew can be done on a -* per shadow register basis. +* If doing read after write calibration, do not update +* FOM now. Do it then. */ - grp_calibrated =1 ; -for (rank_bgn =0 , sr =0 ; - rank_bgn <RW_MGR_MEM_NUMBER_OF_RANKS ; - rank_bgn +=NUM_RANKS_PER_SHADOW_REG , sr++) { -/* -* Determine if this set of ranks -* should be skipped entirely. -*/ -if (param->skip_shadow_regs[sr]) -continue ; -/* -* If doing read after write -* calibration, do not update -* FOM, now - do it then. -*/ -if (rw_mgr_mem_calibrate_vfifo_center (rank_bgn, - rw_group, rw_group, - test_bgn,1 ,0 )) -continue ; - - grp_calibrated =0 ; + ret =rw_mgr_mem_calibrate_dq_dqs_centering (rw_group, + test_bgn,1 ,0 ); +if (ret) { failed_substage =CAL_SUBSTAGE_VFIFO_CENTER ; +continue ; } -if (grp_calibrated) - goto cal_done_ok; +/* All done. */ + goto cal_done_ok; } }
Signature · 1 line
2.1.4
PATCH 108/172 ddr: altera: Minor rw_mgr_mem_calibrate_read_load_patterns() cleanup
In reply to Marek VasutJust do an easy data type cleanup of this function, no functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-)
drivers/ddr/altera/sequencer.c +14 -6
@@ -1114,15 +1114,23 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks num_tries, bit_chk, 1); } -/* load up the patterns we are going to use during a read test */ -static void rw_mgr_mem_calibrate_read_load_patterns (uint32_t rank_bgn, -uint32_t all_ranks) +/** +* rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test +* @rank_bgn: Rank number +* @all_ranks: Test all ranks +* +* Load up the patterns we are going to use during a read test. +*/ +static void rw_mgr_mem_calibrate_read_load_patterns (const u32 rank_bgn, +const int all_ranks) { -uint32_t r; -uint32_t rank_end = all_ranks ?RW_MGR_MEM_NUMBER_OF_RANKS : - (rank_bgn +NUM_RANKS_PER_SHADOW_REG ); +const u32 rank_end = all_ranks ? +RW_MGR_MEM_NUMBER_OF_RANKS : + (rank_bgn +NUM_RANKS_PER_SHADOW_REG ); +u32 r;debug ("%s:%d\n" , __func__, __LINE__); +for (r = rank_bgn; r < rank_end; r++) {if (param->skip_ranks[r])/* request to skip the rank */
Signature · 1 line
2.1.4
PATCH 109/172 ddr: altera: Zap rw_mgr_mem_calibrate_read_test_patterns_all_ranks()
In reply to Marek VasutThis function is called from one single place and it's sole purpose is to call one single function with slightly modified arguments. Zap this function to skip this useless intermediate step.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-)
drivers/ddr/altera/sequencer.c +2 -9
@@ -1107,13 +1107,6 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,return *bit_chk == param->read_correct_mask; } -static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks - (uint32_t group,uint32_t num_tries,uint32_t *bit_chk) -{ -return rw_mgr_mem_calibrate_read_test_patterns (0 , group, - num_tries, bit_chk,1 ); -} -/** * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test * @rank_bgn: Rank number
@@ -2230,8 +2223,8 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,* Altera EMI_RM 2015.05.04 :: Figure 1-26 * Back-to-Back reads of the patterns used for calibration. */ - ret =rw_mgr_mem_calibrate_read_test_patterns_all_ranks (rw_group,1 , - &bit_chk); + ret =rw_mgr_mem_calibrate_read_test_patterns (0 , rw_group,1 , + &bit_chk,1 );if (!ret) {/* FIXME: 0 means failure in this old code :-( */ debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed: g=%u p=%u\n",
Signature · 1 line
2.1.4
PATCH 110/172 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_patterns()
In reply to Marek VasutRework this function such that the code is more readable. Zap unused parameter "num_tries" while at it. Also wrap parameter "bit_chk" into this function as it's value is not used outside. Finally, fix the return value from this function to match the common expectation, where 0 means success.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 96 ++++++++++++++++++++++-------------------- 1 file changed, 50 insertions(+), 46 deletions(-)
drivers/ddr/altera/sequencer.c +50 -46
@@ -1036,31 +1036,42 @@ static void rw_mgr_mem_handoff(void)*/ } -/* -* performs a guaranteed read on the patterns we are going to use during a -* read test to ensure memory works +/** +* rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns +* @rank_bgn: Rank number +* @group: Read/Write Group +* @all_ranks: Test all ranks +* +* Performs a guaranteed read on the patterns we are going to use during a +* read test to ensure memory works. */ -static uint32_t rw_mgr_mem_calibrate_read_test_patterns (uint32_t rank_bgn, -uint32_t group,uint32_t num_tries,uint32_t *bit_chk, -uint32_t all_ranks) +static int +rw_mgr_mem_calibrate_read_test_patterns (const u32 rank_bgn,const u32 group, +const u32 all_ranks) { -uint32_t r, vg; -uint32_t correct_mask_vg; -uint32_t tmp_bit_chk; -uint32_t rank_end = all_ranks ?RW_MGR_MEM_NUMBER_OF_RANKS : - (rank_bgn +NUM_RANKS_PER_SHADOW_REG ); -uint32_t addr; -uint32_t base_rw_mgr; +const u32 addr =SDR_PHYGRP_RWMGRGRP_ADDRESS | +RW_MGR_RUN_SINGLE_GROUP_OFFSET ; +const u32 addr_offset = + (group *RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS ) <<2 ; +const u32 rank_end = all_ranks ? +RW_MGR_MEM_NUMBER_OF_RANKS : + (rank_bgn +NUM_RANKS_PER_SHADOW_REG ); +const u32 shift_ratio =RW_MGR_MEM_DQ_PER_READ_DQS / +RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS ; +const u32 correct_mask_vg = param->read_correct_mask_vg; - *bit_chk = param->read_correct_mask; - correct_mask_vg = param->read_correct_mask_vg; +u32 tmp_bit_chk, base_rw_mgr, bit_chk; +int vg, r; +int ret =0 ; + + bit_chk = param->read_correct_mask;for (r = rank_bgn; r < rank_end; r++) { +/* Request to skip the rank */ if (param->skip_ranks[r]) -/* request to skip the rank */ continue ; -/* set rank */ +/* Set rank */ set_rank_and_odt_mask (r,RW_MGR_ODT_MODE_READ_WRITE );/* Load up a constant bursts of read commands */
@@ -1073,38 +1084,36 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn, &sdr_rw_load_jump_mgr_regs->load_jump_add1); tmp_bit_chk =0 ; -for (vg =RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS -1 ; ; vg--) { -/* reset the fifos to get pointers to known state */ - +for (vg =RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS -1 ; + vg >=0 ; vg--) { +/* Reset the FIFOs to get pointers to known state. */ writel (0 , &phy_mgr_cmd->fifo_reset);writel (0 ,SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RESET_READ_DATAPATH_OFFSET ); - - tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS - /RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS ); - - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ; -writel (RW_MGR_GUARANTEED_READ , addr + - ((group *RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS + - vg) <<2 )); +writel (RW_MGR_GUARANTEED_READ , + addr + addr_offset + (vg <<2 )); base_rw_mgr =readl (SDR_PHYGRP_RWMGRGRP_ADDRESS ); - tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr)); - -if (vg ==0 ) -break ; + tmp_bit_chk <<= shift_ratio; + tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr; } - *bit_chk &= tmp_bit_chk; + + bit_chk &= tmp_bit_chk; } - addr =SDR_PHYGRP_RWMGRGRP_ADDRESS |RW_MGR_RUN_SINGLE_GROUP_OFFSET ;writel (RW_MGR_CLEAR_DQS_ENABLE , addr + (group <<2 ));set_rank_and_odt_mask (0 ,RW_MGR_ODT_MODE_OFF ); -debug_cond (DLEVEL ==1 ,"%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\ -%lu\n" , __func__, __LINE__, group, *bit_chk, param->read_correct_mask, - (long unsigned int )(*bit_chk == param->read_correct_mask)); -return *bit_chk == param->read_correct_mask; + +if (bit_chk != param->read_correct_mask) + ret = -EIO ; + +debug_cond (DLEVEL ==1 , +"%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n" , + __func__, __LINE__, group, bit_chk, + param->read_correct_mask, ret); + +return ret; }/**
@@ -2200,7 +2209,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,static int rw_mgr_mem_calibrate_guaranteed_write (const u32 rw_group,const u32 phase) { -u32 bit_chk;int ret;/* Set a particular DQ/DQS phase. */
@@ -2223,16 +2231,12 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,* Altera EMI_RM 2015.05.04 :: Figure 1-26 * Back-to-Back reads of the patterns used for calibration. */ - ret =rw_mgr_mem_calibrate_read_test_patterns (0 , rw_group,1 , - &bit_chk,1 ); -if (!ret) {/* FIXME: 0 means failure in this old code :-( */ + ret =rw_mgr_mem_calibrate_read_test_patterns (0 , rw_group,1 ); +if (ret)debug_cond (DLEVEL ==1 ,"%s:%d Guaranteed read test failed: g=%u p=%u\n" , __func__, __LINE__, rw_group, phase); -return -EIO ; - } - -return 0 ; +return ret; }/**
Signature · 1 line
2.1.4
PATCH 111/172 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 1
In reply to Marek VasutStart cleaning up this function. In the first part, just fix the incorrectly broken debug strings and fix return value to respect the common convention.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 61 +++++++++++++++++++++--------------------- 1 file changed, 30 insertions(+), 31 deletions(-)
drivers/ddr/altera/sequencer.c +30 -31
@@ -1770,57 +1770,59 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)* Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different * dq_in_delay values */ -static uint32_t +static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay (uint32_t write_group,uint32_t read_group,uint32_t test_bgn) { -uint32_t found; -uint32_t i; -uint32_t p; -uint32_t d; -uint32_t r; - -const uint32_t delay_step =IO_IO_IN_DELAY_MAX / - (RW_MGR_MEM_DQ_PER_READ_DQS -1 ); -/* we start at zero, so have one less dq to devide among */ +/* We start at zero, so have one less dq to devide among */ +const u32 delay_step =IO_IO_IN_DELAY_MAX / + (RW_MGR_MEM_DQ_PER_READ_DQS -1 ); +int found; +u32 i, p, d, r; -debug ("%s:%d (%u,%u,%u)" , __func__, __LINE__, write_group, read_group, - test_bgn); - -/* try different dq_in_delays since the dq path is shorter than dqs */ +debug ("%s:%d (%u,%u,%u)\n" , __func__, __LINE__, + write_group, read_group, test_bgn); +/* Try different dq_in_delays since the DQ path is shorter than DQS. */ for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) { -for (i =0 , p = test_bgn, d =0 ; i <RW_MGR_MEM_DQ_PER_READ_DQS ; i++, p++, d += delay_step) { -debug_cond (DLEVEL ==1 ,"%s:%d rw_mgr_mem_calibrate_\ -vfifo_find_dqs_" , __func__, __LINE__); -debug_cond (DLEVEL ==1 ,"en_phase_sweep_dq_in_delay: g=%u/%u " , - write_group, read_group); -debug_cond (DLEVEL ==1 ,"r=%u, i=%u p=%u d=%u\n" , r, i , p, d); +for (i =0 , p = test_bgn, d =0 ; + i <RW_MGR_MEM_DQ_PER_READ_DQS ; + i++, p++, d += delay_step) { +debug_cond (DLEVEL ==1 , +"%s:%d: g=%u/%u r=%u i=%u p=%u d=%u\n" , + __func__, __LINE__, write_group, read_group, + r, i, p, d); +scc_mgr_set_dq_in_delay (p, d);scc_mgr_load_dq (p); } +writel (0 , &sdr_scc_mgr->update); } found =rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase (read_group); -debug_cond (DLEVEL ==1 ,"%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\ -en_phase_sweep_dq" , __func__, __LINE__); -debug_cond (DLEVEL ==1 ,"_in_delay: g=%u/%u found=%u; Reseting delay \ -chain to zero\n" , write_group, read_group, found); +debug_cond (DLEVEL ==1 , +"%s:%d: g=%u/%u found=%u; Reseting delay chain to zero\n" , + __func__, __LINE__, write_group, read_group, found);for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) { -for (i =0 , p = test_bgn; i <RW_MGR_MEM_DQ_PER_READ_DQS ; - i++, p++) { +for (i =0 , p = test_bgn; + i <RW_MGR_MEM_DQ_PER_READ_DQS ; + i++, p++) {scc_mgr_set_dq_in_delay (p,0 );scc_mgr_load_dq (p); } +writel (0 , &sdr_scc_mgr->update); } -return found; +if (!found) +return -EINVAL ; + +return 0 ; }/* per-bit deskew DQ and center */
@@ -2258,10 +2260,7 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,*/ ret =rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay ( rw_group, rw_group, test_bgn); -if (!ret)/* FIXME: 0 means failure in this old code :-( */ -return -EIO ; - -return 0 ; +return ret; }/**
Signature · 1 line
2.1.4
PATCH 112/172 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 2
In reply to Marek VasutThe read_group and write_group params have the same value for all (one) invocations of this function, just merge them into a single param.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-)
drivers/ddr/altera/sequencer.c +8 -10
@@ -1772,7 +1772,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)*/ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay -(uint32_t write_group,uint32_t read_group,uint32_t test_bgn) +(const u32 rw_group,const u32 test_bgn) {/* We start at zero, so have one less dq to devide among */ const u32 delay_step = IO_IO_IN_DELAY_MAX /
@@ -1780,8 +1780,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delayint found;u32 i, p, d, r; -debug ("%s:%d (%u,%u,%u)\n" , __func__, __LINE__, - write_group, read_group, test_bgn); +debug ("%s:%d (%u,%u)\n" , __func__, __LINE__, rw_group, test_bgn);/* Try different dq_in_delays since the DQ path is shorter than DQS. */ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
@@ -1790,9 +1789,8 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay i <RW_MGR_MEM_DQ_PER_READ_DQS ; i++, p++, d += delay_step) {debug_cond (DLEVEL ==1 , -"%s:%d: g=%u/%u r=%u i=%u p=%u d=%u\n" , - __func__, __LINE__, write_group, read_group, - r, i, p, d); +"%s:%d: g=%u r=%u i=%u p=%u d=%u\n" , + __func__, __LINE__, rw_group, r, i, p, d);scc_mgr_set_dq_in_delay (p, d);scc_mgr_load_dq (p);
@@ -1801,11 +1799,11 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delaywritel (0 , &sdr_scc_mgr->update); } - found =rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase (read_group); + found =rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase (rw_group);debug_cond (DLEVEL ==1 , -"%s:%d: g=%u/%u found=%u; Reseting delay chain to zero\n" , - __func__, __LINE__, write_group, read_group, found); +"%s:%d: g=%u found=%u; Reseting delay chain to zero\n" , + __func__, __LINE__, rw_group, found);for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) {
@@ -2259,7 +2257,7 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,* DQS and DQS Eanble Signal Relationships. */ ret =rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay ( - rw_group, rw_group, test_bgn); + rw_group, test_bgn);return ret; }
Signature · 1 line
2.1.4
PATCH 113/172 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 3
In reply to Marek VasutReplace at least one of the loops in this function with call of a standard function call instead of the ad-hoc implementation. The other one cannot be replaced, since the delay is incremented for each group.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-)
drivers/ddr/altera/sequencer.c +1 -7
@@ -1807,13 +1807,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delayfor (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; r +=NUM_RANKS_PER_SHADOW_REG ) { -for (i =0 , p = test_bgn; - i <RW_MGR_MEM_DQ_PER_READ_DQS ; - i++, p++) { -scc_mgr_set_dq_in_delay (p,0 ); -scc_mgr_load_dq (p); - } - +scc_mgr_apply_group_dq_in_delay (test_bgn,0 );writel (0 , &sdr_scc_mgr->update); }
Signature · 1 line
2.1.4
PATCH 114/172 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 4
In reply to Marek VasutThis function is only invoked from rw_mgr_mem_calibrate_dqs_enable_calibration() and at this point, it is just one level of indirection, so wrap the rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() into rw_mgr_mem_calibrate_dqs_enable_calibration() to get rid of the level of indirection.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 103 +++++++++++++++++++---------------------- 1 file changed, 47 insertions(+), 56 deletions(-)
drivers/ddr/altera/sequencer.c +47 -56
@@ -1766,57 +1766,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)return 1 ; } -/* -* Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different -* dq_in_delay values -*/ -static int -rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay -(const u32 rw_group,const u32 test_bgn) -{ -/* We start at zero, so have one less dq to devide among */ -const u32 delay_step =IO_IO_IN_DELAY_MAX / - (RW_MGR_MEM_DQ_PER_READ_DQS -1 ); -int found; -u32 i, p, d, r; - -debug ("%s:%d (%u,%u)\n" , __func__, __LINE__, rw_group, test_bgn); - -/* Try different dq_in_delays since the DQ path is shorter than DQS. */ -for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; - r +=NUM_RANKS_PER_SHADOW_REG ) { -for (i =0 , p = test_bgn, d =0 ; - i <RW_MGR_MEM_DQ_PER_READ_DQS ; - i++, p++, d += delay_step) { -debug_cond (DLEVEL ==1 , -"%s:%d: g=%u r=%u i=%u p=%u d=%u\n" , - __func__, __LINE__, rw_group, r, i, p, d); - -scc_mgr_set_dq_in_delay (p, d); -scc_mgr_load_dq (p); - } - -writel (0 , &sdr_scc_mgr->update); - } - - found =rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase (rw_group); - -debug_cond (DLEVEL ==1 , -"%s:%d: g=%u found=%u; Reseting delay chain to zero\n" , - __func__, __LINE__, rw_group, found); - -for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; - r +=NUM_RANKS_PER_SHADOW_REG ) { -scc_mgr_apply_group_dq_in_delay (test_bgn,0 ); -writel (0 , &sdr_scc_mgr->update); - } - -if (!found) -return -EINVAL ; - -return 0 ; -} -/* per-bit deskew DQ and center */ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
@@ -2244,15 +2193,57 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,static int rw_mgr_mem_calibrate_dqs_enable_calibration (const u32 rw_group,const u32 test_bgn) { -int ret; -/* * Altera EMI_RM 2015.05.04 :: Figure 1-27 * DQS and DQS Eanble Signal Relationships. */ - ret =rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay ( - rw_group, test_bgn); -return ret; + +/* We start at zero, so have one less dq to devide among */ +const u32 delay_step =IO_IO_IN_DELAY_MAX / + (RW_MGR_MEM_DQ_PER_READ_DQS -1 ); +int found; +u32 i, p, d, r; + +debug ("%s:%d (%u,%u)\n" , __func__, __LINE__, rw_group, test_bgn); + +/* Try different dq_in_delays since the DQ path is shorter than DQS. */ +for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; + r +=NUM_RANKS_PER_SHADOW_REG ) { +for (i =0 , p = test_bgn, d =0 ; + i <RW_MGR_MEM_DQ_PER_READ_DQS ; + i++, p++, d += delay_step) { +debug_cond (DLEVEL ==1 , +"%s:%d: g=%u r=%u i=%u p=%u d=%u\n" , + __func__, __LINE__, rw_group, r, i, p, d); + +scc_mgr_set_dq_in_delay (p, d); +scc_mgr_load_dq (p); + } + +writel (0 , &sdr_scc_mgr->update); + } + +/* +* Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different +* dq_in_delay values +*/ + found =rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase (rw_group); + +debug_cond (DLEVEL ==1 , +"%s:%d: g=%u found=%u; Reseting delay chain to zero\n" , + __func__, __LINE__, rw_group, found); + +for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; + r +=NUM_RANKS_PER_SHADOW_REG ) { +scc_mgr_apply_group_dq_in_delay (test_bgn,0 ); +writel (0 , &sdr_scc_mgr->update); + } + +if (!found) +return -EINVAL ; + +return 0 ; + }/**
Signature · 1 line
2.1.4
PATCH 115/172 ddr: altera: Clean up sdr_find_window_centre() part 1
In reply to Marek VasutClean up the arguments of this function. Most of the pointers passed into the function are either not needed at all, or can be passed as value instead of reference. Also fix the broken multiline debug strings. No functional change.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 64 +++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 32 deletions(-)
drivers/ddr/altera/sequencer.c +32 -32
@@ -1480,40 +1480,41 @@ static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk, } } -static int sdr_find_window_centre (uint32_t *grp,uint32_t *bit_chk, -uint32_t *work_bgn,uint32_t *v,uint32_t *d, -uint32_t *p,uint32_t *work_mid, -uint32_t *work_end) +static int sdr_find_window_centre (const u32 grp,const u32 work_bgn, +const u32 work_end,const u32 val) { -int i; +u32 bit_chk, work_mid, v = val;int tmp_delay =0 ; +int i, p, d; - *work_mid = (*work_bgn + *work_end) /2 ; + work_mid = (work_bgn + work_end) /2 ;debug_cond (DLEVEL ==2 ,"work_bgn=%d work_end=%d work_mid=%d\n" , - *work_bgn, *work_end, *work_mid); + work_bgn, work_end, work_mid);/* Get the middle delay to be less than a VFIFO delay */ -for (*p =0 ; *p <=IO_DQS_EN_PHASE_MAX ; - (*p)++, tmp_delay +=IO_DELAY_PER_OPA_TAP ) +for (p =0 ; p <=IO_DQS_EN_PHASE_MAX ; + p++, tmp_delay +=IO_DELAY_PER_OPA_TAP ) ; +debug_cond (DLEVEL ==2 ,"vfifo ptap delay %d\n" , tmp_delay); -while (*work_mid > tmp_delay) - *work_mid -= tmp_delay; -debug_cond (DLEVEL ==2 ,"new work_mid %d\n" , *work_mid); +while (work_mid > tmp_delay) + work_mid -= tmp_delay; +debug_cond (DLEVEL ==2 ,"new work_mid %d\n" , work_mid); tmp_delay =0 ; -for (*p =0 ; *p <=IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid; - (*p)++, tmp_delay +=IO_DELAY_PER_OPA_TAP ) +for (p =0 ; p <=IO_DQS_EN_PHASE_MAX && tmp_delay < work_mid; + p++, tmp_delay +=IO_DELAY_PER_OPA_TAP ) ; tmp_delay -=IO_DELAY_PER_OPA_TAP ; -debug_cond (DLEVEL ==2 ,"new p %d, tmp_delay=%d\n" , (*p) -1 , tmp_delay); -for (*d =0 ; *d <=IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++, - tmp_delay +=IO_DELAY_PER_DQS_EN_DCHAIN_TAP ) +debug_cond (DLEVEL ==2 ,"new p %d, tmp_delay=%d\n" , p -1 , tmp_delay); + +for (d =0 ; d <=IO_DQS_EN_DELAY_MAX && tmp_delay < work_mid; + d++, tmp_delay +=IO_DELAY_PER_DQS_EN_DCHAIN_TAP ) ; -debug_cond (DLEVEL ==2 ,"new d %d, tmp_delay=%d\n" , *d, tmp_delay); +debug_cond (DLEVEL ==2 ,"new d %d, tmp_delay=%d\n" , d, tmp_delay); -scc_mgr_set_dqs_en_phase_all_ranks (*grp, (*p) -1 ); -scc_mgr_set_dqs_en_delay_all_ranks (*grp, *d); +scc_mgr_set_dqs_en_phase_all_ranks (grp, p -1 ); +scc_mgr_set_dqs_en_delay_all_ranks (grp, d);/* * push vfifo until we can successfully calibrate. We can do this
@@ -1521,22 +1522,25 @@ static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,*/ for (i =0 ; i <VFIFO_SIZE ; i++) {debug_cond (DLEVEL ==2 ,"find_dqs_en_phase: center: vfifo=%u\n" , - *v); -if (rw_mgr_mem_calibrate_read_test_all_ranks (*grp,1 , + v); +if (rw_mgr_mem_calibrate_read_test_all_ranks (grp,1 ,PASS_ONE_BIT , - bit_chk,0 )) { + &bit_chk,0 )) {break ; }/* fiddle with FIFO */ -rw_mgr_incr_vfifo (*grp, v); +rw_mgr_incr_vfifo (grp, &v); }if (i >=VFIFO_SIZE ) { -debug_cond (DLEVEL ==2 ,"%s:%d find_dqs_en_phase: center: \ -failed\n" , __func__, __LINE__); +debug_cond (DLEVEL ==2 ,"%s:%d center: failed.\n" , + __func__, __LINE__);return 0 ; }else { +debug_cond (DLEVEL ==2 , +"%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n" , + __func__, __LINE__, v, p -1 , d);return 1 ; } }
@@ -1548,7 +1552,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)uint32_t max_working_cnt;uint32_t bit_chk;uint32_t dtaps_per_ptap; -uint32_t work_bgn, work_mid, work_end; +uint32_t work_bgn, work_end;uint32_t found_passing_read, found_failing_read, initial_failing_dtap;debug ("%s:%d %u\n" , __func__, __LINE__, grp);
@@ -1756,13 +1760,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)/* ******************************************** */ /* * step 6: Find the centre of the window * */ -if (sdr_find_window_centre (&grp, &bit_chk, &work_bgn, &v, &d, &p, - &work_mid, &work_end) ==0 ) +if (sdr_find_window_centre (grp, work_bgn, work_end, v) ==0 )return 0 ; -debug_cond (DLEVEL ==2 ,"%s:%d find_dqs_en_phase: center found: \ -vfifo=%u ptap=%u dtap=%u\n" , __func__, __LINE__, - v, p-1 , d);return 1 ; }
Signature · 1 line
2.1.4
PATCH 116/172 ddr: altera: Clean up sdr_find_window_centre() part 2
In reply to Marek VasutThis function is a treasure trove of ad-hoc iterative implementations of mathematical functions. Replace all of those with their non-iterative counterpart.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-)
drivers/ddr/altera/sequencer.c +15 -16
@@ -1492,28 +1492,27 @@ static int sdr_find_window_centre(const u32 grp, const u32 work_bgn,debug_cond (DLEVEL ==2 ,"work_bgn=%d work_end=%d work_mid=%d\n" , work_bgn, work_end, work_mid);/* Get the middle delay to be less than a VFIFO delay */ -for (p =0 ; p <=IO_DQS_EN_PHASE_MAX ; - p++, tmp_delay +=IO_DELAY_PER_OPA_TAP ) - ; + tmp_delay = (IO_DQS_EN_PHASE_MAX +1 ) *IO_DELAY_PER_OPA_TAP ;debug_cond (DLEVEL ==2 ,"vfifo ptap delay %d\n" , tmp_delay); -while (work_mid > tmp_delay) - work_mid -= tmp_delay; + work_mid %= tmp_delay;debug_cond (DLEVEL ==2 ,"new work_mid %d\n" , work_mid); - tmp_delay =0 ; -for (p =0 ; p <=IO_DQS_EN_PHASE_MAX && tmp_delay < work_mid; - p++, tmp_delay +=IO_DELAY_PER_OPA_TAP ) - ; - tmp_delay -=IO_DELAY_PER_OPA_TAP ; -debug_cond (DLEVEL ==2 ,"new p %d, tmp_delay=%d\n" , p -1 , tmp_delay); + tmp_delay =rounddown (work_mid,IO_DELAY_PER_OPA_TAP ); +if (tmp_delay >IO_DQS_EN_PHASE_MAX *IO_DELAY_PER_OPA_TAP ) + tmp_delay =IO_DQS_EN_PHASE_MAX *IO_DELAY_PER_OPA_TAP ; + p = tmp_delay /IO_DELAY_PER_OPA_TAP ; + +debug_cond (DLEVEL ==2 ,"new p %d, tmp_delay=%d\n" , p, tmp_delay); + + d =DIV_ROUND_UP (work_mid - tmp_delay,IO_DELAY_PER_DQS_EN_DCHAIN_TAP ); +if (d >IO_DQS_EN_DELAY_MAX ) + d =IO_DQS_EN_DELAY_MAX ; + tmp_delay += d *IO_DELAY_PER_DQS_EN_DCHAIN_TAP ; -for (d =0 ; d <=IO_DQS_EN_DELAY_MAX && tmp_delay < work_mid; - d++, tmp_delay +=IO_DELAY_PER_DQS_EN_DCHAIN_TAP ) - ;debug_cond (DLEVEL ==2 ,"new d %d, tmp_delay=%d\n" , d, tmp_delay); -scc_mgr_set_dqs_en_phase_all_ranks (grp, p -1 ); +scc_mgr_set_dqs_en_phase_all_ranks (grp, p);scc_mgr_set_dqs_en_delay_all_ranks (grp, d);/*
@@ -1540,7 +1539,7 @@ static int sdr_find_window_centre(const u32 grp, const u32 work_bgn, }else {debug_cond (DLEVEL ==2 ,"%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n" , - __func__, __LINE__, v, p -1 , d); + __func__, __LINE__, v, p, d);return 1 ; } }
Signature · 1 line
2.1.4
PATCH 117/172 ddr: altera: Clean up sdr_find_window_centre() part 3
In reply to Marek VasutReorder the end of the function a little by moving the conditional debug output around a little. Rename the function from _centre() to _center(). Document the function in kerneldoc.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-)
drivers/ddr/altera/sequencer.c +20 -15
@@ -1480,7 +1480,16 @@ static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk, } } -static int sdr_find_window_centre (const u32 grp,const u32 work_bgn, +/** +* sdr_find_window_center() - Find center of the working DQS window. +* @grp: Read/Write group +* @work_bgn: First working settings +* @work_end: Last working settings +* @val: VFIFO value +* +* Find center of the working DQS enable window. +*/ +static int sdr_find_window_center (const u32 grp,const u32 work_bgn,const u32 work_end,const u32 val) {u32 bit_chk, work_mid, v = val;
@@ -1525,23 +1534,19 @@ static int sdr_find_window_centre(const u32 grp, const u32 work_bgn,if (rw_mgr_mem_calibrate_read_test_all_ranks (grp,1 ,PASS_ONE_BIT , &bit_chk,0 )) { -break ; +debug_cond (DLEVEL ==2 , +"%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n" , + __func__, __LINE__, v, p, d); +return 0 ; } -/* fiddle with FIFO */ +/* Fiddle with FIFO. */ rw_mgr_incr_vfifo (grp, &v); } -if (i >=VFIFO_SIZE ) { -debug_cond (DLEVEL ==2 ,"%s:%d center: failed.\n" , - __func__, __LINE__); -return 0 ; - }else { -debug_cond (DLEVEL ==2 , -"%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n" , - __func__, __LINE__, v, p, d); -return 1 ; - } +debug_cond (DLEVEL ==2 ,"%s:%d center: failed.\n" , + __func__, __LINE__); +return -EINVAL ; }/* find a good dqs enable to use */
@@ -1759,8 +1764,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)/* ******************************************** */ /* * step 6: Find the centre of the window * */ -if (sdr_find_window_centre (grp, work_bgn, work_end, v) ==0 ) -return 0 ; +if (sdr_find_window_centre (grp, work_bgn, work_end, v)) +return 0 ;/* FIXME: Old code, return 0 means failure :-( */ return 1 ; }
Signature · 1 line
2.1.4
PATCH 118/172 ddr: altera: Clean up sdr_*_phase() part 1
In reply to Marek VasutRename find_working_phase() to sdr_working_phase() for the sake of consistency.
Signed-off-by Marek Vasut <[email protected]>
--- drivers/ddr/altera/sequencer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/ddr/altera/sequencer.c +3 -3
@@ -1332,7 +1332,7 @@ static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk) } } -static int find_working_phase (uint32_t *grp,uint32_t *bit_chk, +static int sdr_working_phase (uint32_t *grp,uint32_t *bit_chk,uint32_t dtaps_per_ptap,uint32_t *work_bgn,uint32_t *v,uint32_t *d,uint32_t *p,uint32_t *i,uint32_t *max_working_cnt)
@@ -1579,8 +1579,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)/* ******************************************************** */ /* * step 2: find first working phase, increment in ptaps * */ work_bgn =0 ; -if (find_working_phase (&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d, - &p, &i, &max_working_cnt) ==0 ) +if (sdr_working_phase (&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d, + &p, &i, &max_working_cnt) ==0 )return 0 ; work_end = work_bgn;
Signature · 1 line
2.1.4