Another posting of the Dove PMU series
Subsystems (5)
cover Another posting of the Dove PMU series
What it says in the subject. Not hopeful of a successful outcome, so I'm not going to bother wasting time writing stuff here.
Documentation/devicetree/bindings/soc/dove/pmu.txt | 56 ++ arch/arm/Kconfig | 1 + arch/arm/boot/dts/dove.dtsi | 604 +++++++++++---------- arch/arm/mach-dove/common.c | 25 + arch/arm/mach-dove/include/mach/pm.h | 17 - arch/arm/mach-dove/irq.c | 87 --- arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/dove.c | 2 + drivers/soc/Makefile | 2 + drivers/soc/dove/Makefile | 1 + drivers/soc/dove/pmu.c | 512 +++++++++++++++++ include/linux/soc/dove/pmu.h | 24 + 12 files changed, 942 insertions(+), 390 deletions(-)
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PATCH 1/7 dt-bindings: add Marvell PMU documentation
Add the required DT binding documentation for the Marvell PMU driver.
--- Documentation/devicetree/bindings/soc/dove/pmu.txt | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/dove/pmu.txt
Documentation/devicetree/bindings/soc/dove/pmu.txt new file +56 -0
@@ -0,0 +1,56 @@ +Device Tree bindings for Marvell PMU + +Required properties: + - compatible: value should be "marvell,dove-pmu". + May also include "simple-bus" if there are child devices, in which + case the ranges node is required. + - reg: two base addresses and sizes of the PM controller and PMU. + - interrupts: single interrupt number for the PMU interrupt + - interrupt-controller: must be specified as the PMU itself is an + interrupt controller. + - #interrupt-cells: must be 1. + - #reset-cells: must be 1. + - domains: sub-node containing domain descriptions + +Optional properties: + - ranges: defines the address mapping for child devices, as per the + standard property of this name. Required when compatible includes + "simple-bus". + +Power domain descriptions are listed as child nodes of the "domains" +sub-node. Each domain has the following properties: + +Required properties: + - #power-domain-cells: must be 0. + +Optional properties: + - marvell,pmu_pwr_mask: specifies the mask value for PMU power register + - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register + - resets: points to the reset manager (PMU node) and reset index. + +Example: + + pmu: power-management at d0000 { + compatible = "marvell,dove-pmu"; + reg = <0xd0000 0x8000>, <0xd8000 0x8000>; + interrupts = <33>; + interrupt-controller; + #interrupt-cells = <1>; + #reset-cells = <1>; + + domains { + vpu_domain: vpu-domain { + #power-domain-cells = <0>; + marvell,pmu_pwr_mask = <0x00000008>; + marvell,pmu_iso_mask = <0x00000001>; + resets = <&pmu 16>; + }; + + gpu_domain: gpu-domain { + #power-domain-cells = <0>; + marvell,pmu_pwr_mask = <0x00000004>; + marvell,pmu_iso_mask = <0x00000002>; + resets = <&pmu 18>; + }; + }; + };
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2.1.0
PATCH 1/7 dt-bindings: add Marvell PMU documentation
Quoted 1 line · Russell King
Add the required DT binding documentation for the Marvell PMU driver.
Looks mostly fine to me.
Quoted 20 lines
Signed-off-by Russell King <[email protected]>--- Documentation/devicetree/bindings/soc/dove/pmu.txt | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/dove/pmu.txtDocumentation/devicetree/bindings/soc/dove/pmu.txt new file +8
-0@@ -0,0 +1,56 @@ +Device Tree bindings for Marvell PMU + +Required properties: + - compatible: value should be "marvell,dove-pmu". + May also include "simple-bus" if there are child devices, in which + case the ranges node is required. + - reg: two base addresses and sizes of the PM controller and PMU. + - interrupts: single interrupt number for the PMU interrupt
Documentation/devicetree/bindings/soc/dove/pmu.txt line 18
Quoted 10 lines
Documentation/devicetree/bindings/soc/dove/pmu.txt new file +10
-0+ - interrupt-controller: must be specified as the PMU itself is an + interrupt controller. + - #interrupt-cells: must be 1. + - #reset-cells: must be 1. + - domains: sub-node containing domain descriptions + +Optional properties: + - ranges: defines the address mapping for child devices, as per the + standard property of this name. Required when compatible includes + "simple-bus".
When would this be used? Your example has child devices, but not this.
Quoted 41 lines
Documentation/devicetree/bindings/soc/dove/pmu.txt new file +38
-1+ +Power domain descriptions are listed as child nodes of the "domains" +sub-node. Each domain has the following properties: + +Required properties: + - #power-domain-cells: must be 0. + +Optional properties: + - marvell,pmu_pwr_mask: specifies the mask value for PMU power register + - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register + - resets: points to the reset manager (PMU node) and reset index. + +Example: + + pmu: power-management at d0000 { + compatible = "marvell,dove-pmu"; + reg = <0xd0000 0x8000>, <0xd8000 0x8000>; + interrupts = <33>; + interrupt-controller; + #interrupt-cells = <1>; + #reset-cells = <1>; + + domains { + vpu_domain: vpu-domain { + #power-domain-cells = <0>; + marvell,pmu_pwr_mask = <0x00000008>; + marvell,pmu_iso_mask = <0x00000001>; + resets = <&pmu 16>; + }; + + gpu_domain: gpu-domain { + #power-domain-cells = <0>; + marvell,pmu_pwr_mask = <0x00000004>; + marvell,pmu_iso_mask = <0x00000002>; + resets = <&pmu 18>; + }; + }; + }; --2.1.0
PATCH 1/7 dt-bindings: add Marvell PMU documentation
Quoted 30 lines · Rob Herring
Quoted 1 line · Russell King
Add the required DT binding documentation for the Marvell PMU driver.
Looks mostly fine to me.
Quoted 24 lines
Signed-off-by Russell King <[email protected]>--- Documentation/devicetree/bindings/soc/dove/pmu.txt | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/dove/pmu.txtDocumentation/devicetree/bindings/soc/dove/pmu.txt new file +12
-0@@ -0,0 +1,56 @@ +Device Tree bindings for Marvell PMU + +Required properties: + - compatible: value should be "marvell,dove-pmu". + May also include "simple-bus" if there are child devices, in which + case the ranges node is required. + - reg: two base addresses and sizes of the PM controller and PMU. + - interrupts: single interrupt number for the PMU interrupt + - interrupt-controller: must be specified as the PMU itself is an + interrupt controller. + - #interrupt-cells: must be 1. + - #reset-cells: must be 1.
Quoted 8 lines
Documentation/devicetree/bindings/soc/dove/pmu.txt line 18
Quoted 6 lines
Documentation/devicetree/bindings/soc/dove/pmu.txt new file +6
-0+ - domains: sub-node containing domain descriptions + +Optional properties: + - ranges: defines the address mapping for child devices, as per the + standard property of this name. Required when compatible includes + "simple-bus".When would this be used? Your example has child devices, but not this.
Precisely as it says. No, my example does not have child devices, it has child nodes which describe the power domains.
"simple-bus" is needed when we list sub-devices of the PMU below it, such as the RTC, pinmux, clock gating, and GPIO, all of which already exist today above the PMU, incorrectly (IMHO) described as individual separate devices. Please see patch 2, which modifies the Dove DT file moving these devices below the PMU, as I previously stated was my intent to do during discussion of the last submission.
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PATCH 2/7 ARM: dt: Add PMU node, making PMU child devices childs of this node
In reply to Russell King - ARM LinuxAdd the PMU node, and move the child devices of the PMU node beneath this new node, giving it a "simple-bus" so that the OF platform device creator will create these child devices. No functional change from this is expected.
The PMU provides multiple features, including an interrupt, reset, power and isolation controller.
--- arch/arm/boot/dts/dove.dtsi | 590 +++++++++++++++++++++++--------------------- 1 file changed, 304 insertions(+), 286 deletions(-)
arch/arm/boot/dts/dove.dtsi +304 -286
@@ -383,293 +383,311 @@ status = "disabled"; }; - thermal: thermal-diode at d001c { - compatible = "marvell,dove-thermal"; - reg = <0xd001c 0x0c>, <0xd005c 0x08>; - }; - - gate_clk: clock-gating-ctrl at d0038 { - compatible = "marvell,dove-gating-clock"; - reg = <0xd0038 0x4>; - clocks = <&core_clk 0>; - #clock-cells = <1>; - }; - - pinctrl: pin-ctrl at d0200 { - compatible = "marvell,dove-pinctrl"; - reg = <0xd0200 0x14>, - <0xd0440 0x04>; - clocks = <&gate_clk 22>; - - pmx_gpio_0: pmx-gpio-0 { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_gpio_1: pmx-gpio-1 { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_gpio_2: pmx-gpio-2 { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_gpio_3: pmx-gpio-3 { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_gpio_4: pmx-gpio-4 { - marvell,pins = "mpp4"; - marvell,function = "gpio"; - }; - - pmx_gpio_5: pmx-gpio-5 { - marvell,pins = "mpp5"; - marvell,function = "gpio"; - }; - - pmx_gpio_6: pmx-gpio-6 { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - pmx_gpio_7: pmx-gpio-7 { - marvell,pins = "mpp7"; - marvell,function = "gpio"; - }; - - pmx_gpio_8: pmx-gpio-8 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - - pmx_gpio_9: pmx-gpio-9 { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_pcie1_clkreq: pmx-pcie1-clkreq { - marvell,pins = "mpp9"; - marvell,function = "pex1"; - }; - - pmx_gpio_10: pmx-gpio-10 { - marvell,pins = "mpp10"; - marvell,function = "gpio"; - }; - - pmx_gpio_11: pmx-gpio-11 { - marvell,pins = "mpp11"; - marvell,function = "gpio"; - }; - - pmx_pcie0_clkreq: pmx-pcie0-clkreq { - marvell,pins = "mpp11"; - marvell,function = "pex0"; - }; - - pmx_gpio_12: pmx-gpio-12 { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_gpio_13: pmx-gpio-13 { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_audio1_extclk: pmx-audio1-extclk { - marvell,pins = "mpp13"; - marvell,function = "audio1"; - }; - - pmx_gpio_14: pmx-gpio-14 { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_gpio_15: pmx-gpio-15 { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_gpio_16: pmx-gpio-16 { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_gpio_17: pmx-gpio-17 { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_gpio_18: pmx-gpio-18 { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - pmx_gpio_19: pmx-gpio-19 { - marvell,pins = "mpp19"; - marvell,function = "gpio"; - }; - - pmx_gpio_20: pmx-gpio-20 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_gpio_21: pmx-gpio-21 { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_camera: pmx-camera { - marvell,pins = "mpp_camera"; - marvell,function = "camera"; - }; - - pmx_camera_gpio: pmx-camera-gpio { - marvell,pins = "mpp_camera"; - marvell,function = "gpio"; - }; - - pmx_sdio0: pmx-sdio0 { - marvell,pins = "mpp_sdio0"; - marvell,function = "sdio0"; - }; - - pmx_sdio0_gpio: pmx-sdio0-gpio { - marvell,pins = "mpp_sdio0"; - marvell,function = "gpio"; - }; - - pmx_sdio1: pmx-sdio1 { - marvell,pins = "mpp_sdio1"; - marvell,function = "sdio1"; - }; - - pmx_sdio1_gpio: pmx-sdio1-gpio { - marvell,pins = "mpp_sdio1"; - marvell,function = "gpio"; - }; - - pmx_audio1_gpio: pmx-audio1-gpio { - marvell,pins = "mpp_audio1"; - marvell,function = "gpio"; - }; - - pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { - marvell,pins = "mpp_audio1"; - marvell,function = "i2s1/spdifo"; - }; - - pmx_spi0: pmx-spi0 { - marvell,pins = "mpp_spi0"; - marvell,function = "spi0"; - }; - - pmx_spi0_gpio: pmx-spi0-gpio { - marvell,pins = "mpp_spi0"; - marvell,function = "gpio"; - }; - - pmx_spi1_4_7: pmx-spi1-4-7 { - marvell,pins = "mpp4", "mpp5", - "mpp6", "mpp7"; - marvell,function = "spi1"; - }; - - pmx_spi1_20_23: pmx-spi1-20-23 { - marvell,pins = "mpp20", "mpp21", - "mpp22", "mpp23"; - marvell,function = "spi1"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp_uart1"; - marvell,function = "uart1"; - }; - - pmx_uart1_gpio: pmx-uart1-gpio { - marvell,pins = "mpp_uart1"; - marvell,function = "gpio"; - }; - - pmx_nand: pmx-nand { - marvell,pins = "mpp_nand"; - marvell,function = "nand"; - }; - - pmx_nand_gpo: pmx-nand-gpo { - marvell,pins = "mpp_nand"; - marvell,function = "gpo"; - }; - - pmx_i2c1: pmx-i2c1 { - marvell,pins = "mpp17", "mpp19"; - marvell,function = "twsi"; - }; - - pmx_i2c2: pmx-i2c2 { - marvell,pins = "mpp_audio1"; - marvell,function = "twsi"; - }; - - pmx_ssp_i2c2: pmx-ssp-i2c2 { - marvell,pins = "mpp_audio1"; - marvell,function = "ssp/twsi"; - }; - - pmx_i2cmux_0: pmx-i2cmux-0 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt1"; - }; - - pmx_i2cmux_1: pmx-i2cmux-1 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt2"; - }; - - pmx_i2cmux_2: pmx-i2cmux-2 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt3"; - }; - }; - - core_clk: core-clocks at d0214 { - compatible = "marvell,dove-core-clock"; - reg = <0xd0214 0x4>; - #clock-cells = <1>; - }; - - gpio0: gpio-ctrl at d0400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xd0400 0x20>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <12>, <13>, <14>, <60>; - }; - - gpio1: gpio-ctrl at d0420 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xd0420 0x20>; - ngpios = <32>; + pmu: power-management at d0000 { + compatible = "marvell,dove-pmu", "simple-bus"; + reg = <0xd0000 0x8000>, <0xd8000 0x8000>; + ranges = <0x00000000 0x000d0000 0x8000 + 0x00008000 0x000d8000 0x8000>; + interrupts = <33>; interrupt-controller; - #interrupt-cells = <2>; - interrupts = <61>; - }; - - rtc: real-time-clock at d8500 { - compatible = "marvell,orion-rtc"; - reg = <0xd8500 0x20>; + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + #reset-cells = <1>; + + domains { + }; + + thermal: thermal-diode at 001c { + compatible = "marvell,dove-thermal"; + reg = <0x001c 0x0c>, <0x005c 0x08>; + }; + + gate_clk: clock-gating-ctrl at 0038 { + compatible = "marvell,dove-gating-clock"; + reg = <0x0038 0x4>; + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; + + pinctrl: pin-ctrl at 0200 { + compatible = "marvell,dove-pinctrl"; + reg = <0x0200 0x14>, + <0x0440 0x04>; + clocks = <&gate_clk 22>; + + pmx_gpio_0: pmx-gpio-0 { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_gpio_1: pmx-gpio-1 { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_gpio_2: pmx-gpio-2 { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_gpio_3: pmx-gpio-3 { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_gpio_4: pmx-gpio-4 { + marvell,pins = "mpp4"; + marvell,function = "gpio"; + }; + + pmx_gpio_5: pmx-gpio-5 { + marvell,pins = "mpp5"; + marvell,function = "gpio"; + }; + + pmx_gpio_6: pmx-gpio-6 { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + + pmx_gpio_7: pmx-gpio-7 { + marvell,pins = "mpp7"; + marvell,function = "gpio"; + }; + + pmx_gpio_8: pmx-gpio-8 { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + + pmx_gpio_9: pmx-gpio-9 { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + + pmx_pcie1_clkreq: pmx-pcie1-clkreq { + marvell,pins = "mpp9"; + marvell,function = "pex1"; + }; + + pmx_gpio_10: pmx-gpio-10 { + marvell,pins = "mpp10"; + marvell,function = "gpio"; + }; + + pmx_gpio_11: pmx-gpio-11 { + marvell,pins = "mpp11"; + marvell,function = "gpio"; + }; + + pmx_pcie0_clkreq: pmx-pcie0-clkreq { + marvell,pins = "mpp11"; + marvell,function = "pex0"; + }; + + pmx_gpio_12: pmx-gpio-12 { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_gpio_13: pmx-gpio-13 { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_audio1_extclk: pmx-audio1-extclk { + marvell,pins = "mpp13"; + marvell,function = "audio1"; + }; + + pmx_gpio_14: pmx-gpio-14 { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_gpio_15: pmx-gpio-15 { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_gpio_16: pmx-gpio-16 { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_gpio_17: pmx-gpio-17 { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_gpio_18: pmx-gpio-18 { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; + + pmx_gpio_19: pmx-gpio-19 { + marvell,pins = "mpp19"; + marvell,function = "gpio"; + }; + + pmx_gpio_20: pmx-gpio-20 { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + + pmx_gpio_21: pmx-gpio-21 { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_camera: pmx-camera { + marvell,pins = "mpp_camera"; + marvell,function = "camera"; + }; + + pmx_camera_gpio: pmx-camera-gpio { + marvell,pins = "mpp_camera"; + marvell,function = "gpio"; + }; + + pmx_sdio0: pmx-sdio0 { + marvell,pins = "mpp_sdio0"; + marvell,function = "sdio0"; + }; + + pmx_sdio0_gpio: pmx-sdio0-gpio { + marvell,pins = "mpp_sdio0"; + marvell,function = "gpio"; + }; + + pmx_sdio1: pmx-sdio1 { + marvell,pins = "mpp_sdio1"; + marvell,function = "sdio1"; + }; + + pmx_sdio1_gpio: pmx-sdio1-gpio { + marvell,pins = "mpp_sdio1"; + marvell,function = "gpio"; + }; + + pmx_audio1_gpio: pmx-audio1-gpio { + marvell,pins = "mpp_audio1"; + marvell,function = "gpio"; + }; + + pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { + marvell,pins = "mpp_audio1"; + marvell,function = "i2s1/spdifo"; + }; + + pmx_spi0: pmx-spi0 { + marvell,pins = "mpp_spi0"; + marvell,function = "spi0"; + }; + + pmx_spi0_gpio: pmx-spi0-gpio { + marvell,pins = "mpp_spi0"; + marvell,function = "gpio"; + }; + + pmx_spi1_4_7: pmx-spi1-4-7 { + marvell,pins = "mpp4", "mpp5", + "mpp6", "mpp7"; + marvell,function = "spi1"; + }; + + pmx_spi1_20_23: pmx-spi1-20-23 { + marvell,pins = "mpp20", "mpp21", + "mpp22", "mpp23"; + marvell,function = "spi1"; + }; + + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp_uart1"; + marvell,function = "uart1"; + }; + + pmx_uart1_gpio: pmx-uart1-gpio { + marvell,pins = "mpp_uart1"; + marvell,function = "gpio"; + }; + + pmx_nand: pmx-nand { + marvell,pins = "mpp_nand"; + marvell,function = "nand"; + }; + + pmx_nand_gpo: pmx-nand-gpo { + marvell,pins = "mpp_nand"; + marvell,function = "gpo"; + }; + + pmx_i2c1: pmx-i2c1 { + marvell,pins = "mpp17", "mpp19"; + marvell,function = "twsi"; + }; + + pmx_i2c2: pmx-i2c2 { + marvell,pins = "mpp_audio1"; + marvell,function = "twsi"; + }; + + pmx_ssp_i2c2: pmx-ssp-i2c2 { + marvell,pins = "mpp_audio1"; + marvell,function = "ssp/twsi"; + }; + + pmx_i2cmux_0: pmx-i2cmux-0 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt1"; + }; + + pmx_i2cmux_1: pmx-i2cmux-1 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt2"; + }; + + pmx_i2cmux_2: pmx-i2cmux-2 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt3"; + }; + }; + + core_clk: core-clocks at 0214 { + compatible = "marvell,dove-core-clock"; + reg = <0x0214 0x4>; + #clock-cells = <1>; + }; + + gpio0: gpio-ctrl at 0400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x0400 0x20>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <12>, <13>, <14>, <60>; + }; + + gpio1: gpio-ctrl at 0420 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x0420 0x20>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <61>; + }; + + rtc: real-time-clock at 8500 { + compatible = "marvell,orion-rtc"; + reg = <0x8500 0x20>; + }; }; gconf: global-config at e802c {
Signature · 1 line
2.1.0
PATCH 3/7 ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets
In reply to Russell King - ARM LinuxThe PMU device contains an interrupt controller, power control and resets. The interrupt controller is a little sub-standard in that there is no race free way to clear down pending interrupts, so we try to avoid problems by reducing the window as much as possible, and clearing as infrequently as possible.
The interrupt support is implemented using an IRQ domain, and the parent interrupt referenced in the standard DT way.
The power domains and reset support is closely related - there is a defined sequence for powering down a domain which is tightly coupled with asserting the reset. Hence, it makes sense to group these two together, and in order to avoid any locking contention disrupting this sequence, we avoid the use of syscon or regmap.
This patch adds the core PMU driver: power domains must be defined in the DT file in order to make use of them. The reset controller can be referenced in the standard way for reset controllers.
--- arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/dove.c | 2 + drivers/soc/Makefile | 1 + drivers/soc/dove/Makefile | 1 + drivers/soc/dove/pmu.c | 412 +++++++++++++++++++++++++++++++++++++++++++ include/linux/soc/dove/pmu.h | 6 + 6 files changed, 423 insertions(+) create mode 100644 drivers/soc/dove/Makefile create mode 100644 drivers/soc/dove/pmu.c create mode 100644 include/linux/soc/dove/pmu.h
arch/arm/mach-mvebu/Kconfig +1 -0
@@ -96,6 +96,7 @@ config MACH_DOVE select MACH_MVEBU_ANY select ORION_IRQCHIP select ORION_TIMER + select PM_GENERIC_DOMAINS if PM select PINCTRL_DOVE help Say 'Y' here if you want your kernel to support the
arch/arm/mach-mvebu/dove.c +2 -0
@@ -12,6 +12,7 @@#include <linux/mbus.h> #include <linux/of.h> #include <linux/of_platform.h> +#include <linux/soc/dove/pmu.h> #include <asm/hardware/cache-tauros2.h> #include <asm/mach/arch.h> #include "common.h"
@@ -24,6 +25,7 @@ static void __init dove_init(void)tauros2_init (0 );#endif BUG_ON (mvebu_mbus_dt_init (false)); +dove_init_pmu ();of_platform_populate (NULL , of_default_bus_match_table,NULL ,NULL ); }
drivers/soc/Makefile +1 -0
@@ -2,6 +2,7 @@ # Makefile for the Linux Kernel SOC specific device drivers. # +obj-$(CONFIG_MACH_DOVE) += dove/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_ARCH_TEGRA) += tegra/
drivers/soc/dove/Makefile new file +1 -0
@@ -0,0 +1 @@ +obj-y += pmu.o
drivers/soc/dove/pmu.c new file +412 -0
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include/linux/soc/dove/pmu.h new file +6 -0
@@ -0,0 +1,6 @@ +#ifndef LINUX_SOC_DOVE_PMU_H +#define LINUX_SOC_DOVE_PMU_H + +int dove_init_pmu (void ); + +#endif
Signature · 1 line
2.1.0
PATCH 4/7 ARM: dt: dove: wire up RTC interrupt
In reply to Russell King - ARM LinuxNow that we have a PMU driver, we can wire up the RTC interrupt in the DT description for Dove.
--- arch/arm/boot/dts/dove.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm/boot/dts/dove.dtsi +1 -0
@@ -687,6 +687,7 @@ rtc: real-time-clock at 8500 { compatible = "marvell,orion-rtc"; reg = <0x8500 0x20>; + interrupts = <5>; }; };
Signature · 1 line
2.1.0
PATCH 5/7 ARM: dt: dove: add video decoder power domain description
In reply to Russell King - ARM LinuxAdd the description of the video decoder power domain to the PMU DT entry.
--- arch/arm/boot/dts/dove.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
arch/arm/boot/dts/dove.dtsi +6 -0
@@ -396,6 +396,12 @@ #reset-cells = <1>; domains { + vpu_domain: vpu-domain { + #power-domain-cells = <0>; + marvell,pmu_pwr_mask = <0x00000008>; + marvell,pmu_iso_mask = <0x00000001>; + resets = <&pmu 16>; + }; }; thermal: thermal-diode at 001c {
Signature · 1 line
2.1.0
PATCH 6/7 ARM: dt: dove: add GPU power domain description
In reply to Russell King - ARM LinuxAdd the description of the GPU power domain to the PMU DT entry.
--- arch/arm/boot/dts/dove.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm/boot/dts/dove.dtsi +7 -0
@@ -402,6 +402,13 @@ marvell,pmu_iso_mask = <0x00000001>; resets = <&pmu 16>; }; + + gpu_domain: gpu-domain { + #power-domain-cells = <0>; + marvell,pmu_pwr_mask = <0x00000004>; + marvell,pmu_iso_mask = <0x00000002>; + resets = <&pmu 18>; + }; }; thermal: thermal-diode at 001c {
Signature · 1 line
2.1.0
PATCH 7/7 ARM: dove: convert legacy dove to PMU support
In reply to Russell King - ARM LinuxSince Dove has non-DT support, convert the legacy support to use the new PMU driver.
--- arch/arm/Kconfig | 1 + arch/arm/mach-dove/common.c | 25 +++++++++ arch/arm/mach-dove/include/mach/pm.h | 17 ------ arch/arm/mach-dove/irq.c | 87 ------------------------------ drivers/soc/Makefile | 1 + drivers/soc/dove/pmu.c | 100 +++++++++++++++++++++++++++++++++++ include/linux/soc/dove/pmu.h | 18 +++++++ 7 files changed, 145 insertions(+), 104 deletions(-)
arch/arm/Kconfig +1 -0
@@ -514,6 +514,7 @@ config ARCH_DOVE select PINCTRL select PINCTRL_DOVE select PLAT_ORION_LEGACY + select PM_GENERIC_DOMAINS if PM help Support for the Marvell Dove SoC 88AP510
arch/arm/mach-dove/common.c +25 -0
@@ -16,6 +16,7 @@#include <linux/platform_data/dma-mv_xor.h> #include <linux/platform_data/usb-ehci-orion.h> #include <linux/platform_device.h> +#include <linux/soc/dove/pmu.h> #include <asm/hardware/cache-tauros2.h> #include <asm/mach/arch.h> #include <asm/mach/map.h>
@@ -375,6 +376,29 @@ void __init dove_setup_cpu_wins(void) DOVE_SCRATCHPAD_SIZE); } +static const struct dove_pmu_domain_initdata pmu_domains[]__initconst = { + { + .pwr_mask =PMU_PWR_VPU_PWR_DWN_MASK , + .rst_mask =PMU_SW_RST_VIDEO_MASK , + .iso_mask =PMU_ISO_VIDEO_MASK , + .name ="vpu-domain" , + }, { + .pwr_mask =PMU_PWR_GPU_PWR_DWN_MASK , + .rst_mask =PMU_SW_RST_GPU_MASK , + .iso_mask =PMU_ISO_GPU_MASK , + .name ="gpu-domain" , + }, { +/* sentinel */ + }, +}; + +static const struct dove_pmu_initdata pmu_data__initconst = { + .pmc_base =DOVE_PMU_VIRT_BASE , + .pmu_base =DOVE_PMU_VIRT_BASE +0x8000 , + .irq =IRQ_DOVE_PMU , + .domains = pmu_domains, +}; +void __init dove_init (void ) { pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
@@ -389,6 +413,7 @@ void __init dove_init(void)dove_clk_init ();/* internal devices that every board has */ +dove_init_pmu_legacy (&pmu_data);dove_rtc_init ();dove_xor0_init ();dove_xor1_init ();
arch/arm/mach-dove/include/mach/pm.h +0 -17
@@ -51,22 +51,5 @@#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50) -#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54) - -static inline int pmu_to_irq (int pin) -{ -if (pin <NR_PMU_IRQS ) -return pin +IRQ_DOVE_PMU_START ; - -return -EINVAL ; -} - -static inline int irq_to_pmu (int irq) -{ -if (IRQ_DOVE_PMU_START <= irq && irq <NR_IRQS ) -return irq -IRQ_DOVE_PMU_START ; - -return -EINVAL ; -}#endif
arch/arm/mach-dove/irq.c +0 -87
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drivers/soc/Makefile +1 -0
@@ -2,6 +2,7 @@ # Makefile for the Linux Kernel SOC specific device drivers. # +obj-$(CONFIG_ARCH_DOVE) += dove/ obj-$(CONFIG_MACH_DOVE) += dove/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_QCOM) += qcom/
drivers/soc/dove/pmu.c +100 -0
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include/linux/soc/dove/pmu.h +18 -0
@@ -1,6 +1,24 @@#ifndef LINUX_SOC_DOVE_PMU_H #define LINUX_SOC_DOVE_PMU_H +#include <linux/types.h> + +struct dove_pmu_domain_initdata { +u32 pwr_mask; +u32 rst_mask; +u32 iso_mask; +const char *name; +}; + +struct dove_pmu_initdata { +void __iomem *pmc_base; +void __iomem *pmu_base; +int irq; +const struct dove_pmu_domain_initdata *domains; +}; + +int dove_init_pmu_legacy (const struct dove_pmu_initdata *); +int dove_init_pmu (void );#endif
Signature · 1 line
2.1.0
Andrew Lunn
maintainercover Another posting of the Dove PMU series
In reply to Russell King - ARM LinuxQuoted 2 lines · Russell King - ARM Linux
What it says in the subject. Not hopeful of a successful outcome, so I'm not going to bother wasting time writing stuff here.
Hi Gregory
I took at look at Russell's patches. I rebased them onto -rc1. There were a few minor merge problems, all easy to fix. I added
Signed-off-by: since i did make changes, but 99.9% of the credit for these patches is definitely to Russell.
The last patch, which is converting mach-dove to use the new PMU driver however does not build. With mvebu_v7_defconfig i get:
CC drivers/soc/dove/pmu.odrivers/soc/dove/pmu.c: In function dove_init_pmu_legacy?:drivers/soc/dove/pmu.c:400:46: error: IRQ_DOVE_PMU_START undeclared (first use in this function)
irq_domain_associate_many(pmu->irq_domain, IRQ_DOVE_PMU_START,
^
drivers/soc/dove/pmu.c:400:46: note: each undeclared identifier is reported only once for each function it appears in
and dove_defconfig:
CC arch/arm/mach-dove/common.oarch/arm/mach-dove/common.c:381:15: error: PWR_VPU_PWR_DWN_MASK undeclared here (not in a function)
.pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK,
^
arch/arm/mach-dove/common.c:382:15: error: PMU_SW_RST_VIDEO_MASK undeclared here (not in a function)
.rst_mask = PMU_SW_RST_VIDEO_MASK,
^
arch/arm/mach-dove/common.c:383:15: error: PMU_ISO_VIDEO_MASK undeclared here (not in a function)
.iso_mask = PMU_ISO_VIDEO_MASK,
^
arch/arm/mach-dove/common.c:386:15: error: PMU_PWR_GPU_PWR_DWN_MASK undeclared here (not in a function)
.pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK,
^
arch/arm/mach-dove/common.c:387:15: error: PMU_SW_RST_GPU_MASK undeclared here (not in a function)
.rst_mask = PMU_SW_RST_GPU_MASK,
^arch/arm/mach-dove/common.c:388:15: error: PMU_ISO_GPU_MASK undeclared here (not in a function)
.iso_mask = PMU_ISO_GPU_MASK,
So i've dropped the last patch.
I boot tested mvebu_v7_defconfig with these patches, and ran the rtctest, which shows the RTC interrupt it working. The vpu and gpu power domains are in /sys, but i don't have anything connected to the HDMI port in order to test them.
You can find the patches here:
https://github.com/lunn/linux.git v4.2-rc1-dove-pmu
Andrew
cover Another posting of the Dove PMU series
Hi Andrew,
Quoted 44 lines · Andrew Lunn
Quoted 2 lines · Russell King - ARM Linux
What it says in the subject. Not hopeful of a successful outcome, so I'm not going to bother wasting time writing stuff here.
Hi Gregory
I took at look at Russell's patches. I rebased them onto -rc1. There were a few minor merge problems, all easy to fix. I added
Signed-off-by: since i did make changes, but 99.9% of the credit for these patches is definitely to Russell.The last patch, which is converting mach-dove to use the new PMU driver however does not build. With
mvebu_v7_defconfigi get:CC
drivers/soc/dove/pmu.odrivers/soc/dove/pmu.c: In functiondove_init_pmu_legacy?:drivers/soc/dove/pmu.c:400:46: error:IRQ_DOVE_PMU_STARTundeclared (first use in this function)
irq_domain_associate_many(pmu->irq_domain,IRQ_DOVE_PMU_START,^
drivers/soc/dove/pmu.c:400:46: note: each undeclared identifier is reported only once for each function it appears inand
dove_defconfig:CC
arch/arm/mach-dove/common.oarch/arm/mach-dove/common.c:381:15: error:PWR_VPU_PWR_DWN_MASKundeclared here (not in a function)
.pwr_mask =PMU_PWR_VPU_PWR_DWN_MASK,^ arch/arm/mach-dove/common.c:382:15: error: PMU_SW_RST_VIDEO_MASK undeclared here (not in a function) .rst_mask = PMU_SW_RST_VIDEO_MASK, ^ arch/arm/mach-dove/common.c:383:15: error: PMU_ISO_VIDEO_MASK undeclared here (not in a function) .iso_mask = PMU_ISO_VIDEO_MASK, ^ arch/arm/mach-dove/common.c:386:15: error: PMU_PWR_GPU_PWR_DWN_MASK undeclared here (not in a function) .pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK, ^ arch/arm/mach-dove/common.c:387:15: error: PMU_SW_RST_GPU_MASK undeclared here (not in a function) .rst_mask = PMU_SW_RST_GPU_MASK, ^
arch/arm/mach-dove/common.c:388:15: error:PMU_ISO_GPU_MASKundeclared here (not in a function)
.iso_mask =PMU_ISO_GPU_MASK,So i've dropped the last patch.
Quoted 8 lines
I boot tested
mvebu_v7_defconfigwith these patches, and ran the rtctest, which shows the RTC interrupt it working. The vpu and gpu power domains are in /sys, but i don't have anything connected to the HDMI port in order to test them.You can find the patches here:
https://github.com/lunn/linux.git v4.2-rc1-dove-pmu
I have merged your branch in mvebu/for-next and if there is no complain then it will be part of the next pull request.
Thanks,
Gregory
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
cover Another posting of the Dove PMU series
In reply to Andrew LunnQuoted 4 lines · Andrew Lunn
I took at look at Russell's patches. I rebased them onto -rc1. There were a few minor merge problems, all easy to fix. I added
Signed-off-by: since i did make changes, but 99.9% of the credit for these patches is definitely to Russell.
Thanks.
If you're committing patches into git to be sent upstream, you _should_ _always_ add your signed-off-by. Signed-off-by not only tracks who has touched the patch, but also the people who were responsible for it being committed into git.
So, by committing patches into git, you should always add your S-o-b.
Quoted 27 lines
With
mvebu_v7_defconfigi get:CC
drivers/soc/dove/pmu.odrivers/soc/dove/pmu.c: In functiondove_init_pmu_legacy?:drivers/soc/dove/pmu.c:400:46: error:IRQ_DOVE_PMU_STARTundeclared (first use in this function)
irq_domain_associate_many(pmu->irq_domain,IRQ_DOVE_PMU_START,^
drivers/soc/dove/pmu.c:400:46: note: each undeclared identifier is reported only once for each function it appears inand
dove_defconfig:CC
arch/arm/mach-dove/common.oarch/arm/mach-dove/common.c:381:15: error:PWR_VPU_PWR_DWN_MASKundeclared here (not in a function)
.pwr_mask =PMU_PWR_VPU_PWR_DWN_MASK,^ arch/arm/mach-dove/common.c:382:15: error: PMU_SW_RST_VIDEO_MASK undeclared here (not in a function) .rst_mask = PMU_SW_RST_VIDEO_MASK, ^ arch/arm/mach-dove/common.c:383:15: error: PMU_ISO_VIDEO_MASK undeclared here (not in a function) .iso_mask = PMU_ISO_VIDEO_MASK, ^ arch/arm/mach-dove/common.c:386:15: error: PMU_PWR_GPU_PWR_DWN_MASK undeclared here (not in a function) .pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK, ^ arch/arm/mach-dove/common.c:387:15: error: PMU_SW_RST_GPU_MASK undeclared here (not in a function) .rst_mask = PMU_SW_RST_GPU_MASK, ^
Quoted 4 lines
arch/arm/mach-dove/common.c:388:15: error:PMU_ISO_GPU_MASKundeclared here (not in a function)
.iso_mask =PMU_ISO_GPU_MASK,So i've dropped the last patch.
That's fine. I'll work on resolving those.
Thanks.
Signature · 2 lines
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