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T102xRDB: Enable ifc nand ecc encode and decode

PATCH New Raghav Dogra 2 participants 2 messages May 22, 2015 – Jul 31, 2015

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Raghav Dogra

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PATCH 1/1 T102xRDB: Enable ifc nand ecc encode and decode

From: Jaiprakash Singh <[email protected]>

IFC nand ecc encode and decode mode are not correctly set in CSOR register during nand initialization.Enable ecc encode/decode in 4-bit mode

Signed-off-by Jaiprakash Singh <[email protected]>
---
 include/configs/T102xRDB.h |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
include/configs/T102xRDB.h +3 -1
index deff617..12082c3 100644
@@ -395,7 +395,9 @@ unsigned long get_board_ddr_clk(void);
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
 #elif defined(CONFIG_T1023RDB)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_RAL_3	/* RAL 3Bytes */ \
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL 3Bytes */ \
 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
 				| CSOR_NAND_SPRZ_128	/* Spare size = 128 */ \
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1.7.9.5
#1 lore raw

PATCH 1/1 T102xRDB: Enable ifc nand ecc encode and decode

Quoted 8 lines · Raghav Dogra

From: Jaiprakash Singh <[email protected]>

IFC nand ecc encode and decode mode are not correctly set in CSOR register during nand initialization.Enable ecc encode/decode in 4-bit mode

Signed-off-by Jaiprakash Singh <[email protected]>

---

Applied to u-boot-mpc85xx master after fixing subject.

Thanks.

York