power: pmic: add pfuze3000 support
Subsystems (7)
PATCH v4 1/13 power: pmic: add pfuze3000 support
* Add pmic pfuze3000 support, implement power_pfuze3000_init to be used in power_init_board callback function.
Signed-off-by Adrian Alonso <[email protected]>
Signed-off-by Peng Fan <[email protected]>
---
Changes for V2:
- Correct pfuze device name to pfuze3000; Freescale documentation uses Pfuze 3000 as product name for the pmic, align driver name with the actual product name.
Changes for V3: Resend
Changes for V4: Resend
drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_pfuze3000.c | 32 +++++++++++++++ include/power/pfuze3000_pmic.h | 78 +++++++++++++++++++++++++++++++++++++ 3 files changed, 111 insertions(+) create mode 100644 drivers/power/pmic/pmic_pfuze3000.c create mode 100644 include/power/pfuze3000_pmic.h
drivers/power/pmic/Makefile +1 -0
@@ -14,6 +14,7 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o +obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
drivers/power/pmic/pmic_pfuze3000.c new file +32 -0
@@ -0,0 +1,32 @@ +/* +* Copyright (C) 2015 Freescale Semiconductor, Inc. +* Peng Fan <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <errno.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> + +int power_pfuze3000_init (unsigned char bus) +{ +static const char name[] ="PFUZE3000" ; +struct pmic *p =pmic_alloc (); + +if (!p) { +printf ("%s: POWER allocation error!\n" , __func__); +return -ENOMEM ; + } + + p->name = name; + p->interface =PMIC_I2C ; + p->number_of_regs =PMIC_NUM_OF_REGS ; + p->hw.i2c.addr =CONFIG_POWER_PFUZE3000_I2C_ADDR ; + p->hw.i2c.tx_num =1 ; + p->bus = bus; + +return 0 ; +}
include/power/pfuze3000_pmic.h new file +78 -0
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Signature · 1 line
2.1.4
PATCH v4 2/13 imx: iomux-v3: add imx7d support for iomuxc
* Add imx7d support for iomux controller
* imx7d has two iomux controllers iomuxc (0x3033000) and iomuxc-lpsr (0x302C0000) each conroller provides control and mux mode pad registers but shares iomuxc input select register with iomuxc-lpsr IOMUX_CONFIG_LPSR flag is used to properly set daisy chain settings for iomuxc-lpsr pads.
* Since mx7d introduces LPSR IOMUX pins, add new base to IOMUX v3 driver for these LPSR pins.
Signed-off-by Adrian Alonso <[email protected]>
Signed-off-by Fugang Duan <[email protected]>
Signed-off-by Ye.Li <[email protected]>
---
Changes for V2:
- Update commit log information
Changes for V3: Resend
Changes for V4:
- Fix Copyright year information
arch/arm/imx-common/iomux-v3.c | 18 + arch/arm/include/asm/arch-mx7/mx7-pins.h | 19 + arch/arm/include/asm/arch-mx7/mx7d_pins.h | 1308 ++++++++++++++++++++++++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 32 + 4 files changed, 1377 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx7/mx7-pins.h create mode 100644 arch/arm/include/asm/arch-mx7/mx7d_pins.h
arch/arm/imx-common/iomux-v3.c +18 -0
@@ -41,6 +41,18 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) }#endif +#ifdef CONFIG_IOMUX_LPSR +u32 lpsr = (pad &MUX_MODE_LPSR ) >>MUX_MODE_SHIFT ; + +if (lpsr ==IOMUX_CONFIG_LPSR ) { + base = (void *)IOMUXC_LPSR_BASE_ADDR ; + mux_mode &= ~IOMUX_CONFIG_LPSR ; +/* set daisy chain sel_input */ +if (sel_input_ofs) + sel_input_ofs +=IOMUX_LPSR_SEL_INPUT_OFS ; + } +#endif +if (mux_ctrl_ofs)__raw_writel (mux_mode, base + mux_ctrl_ofs);
@@ -55,6 +67,12 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)if (!(pad_ctrl &NO_PAD_CTRL ) && pad_ctrl_ofs)__raw_writel (pad_ctrl, base + pad_ctrl_ofs);#endif + +#ifdef CONFIG_IOMUX_LPSR +if (lpsr ==IOMUX_CONFIG_LPSR ) + base = (void *)IOMUXC_BASE_ADDR ; +#endif + }/* configures a list of pads within declared with IOMUX_PADS macro */
arch/arm/include/asm/arch-mx7/mx7-pins.h new file +19 -0
@@ -0,0 +1,19 @@ +/* +* Copyright (C) 2015 Freescale Semiconductor, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#ifndef __ASM_ARCH_MX7_PINS_H__ +#define __ASM_ARCH_MX7_PINS_H__ + +#include <asm/imx-common/iomux-v3.h> + +#if defined(CONFIG_MX7D ) +#include "mx7d_pins.h" +#elif defined(CONFIG_MX7S ) +#include "mx7s_pins.h" +#else +#error "Please select cpu" +#endif /* CONFIG_MX7D */ + +#endif /*__ASM_ARCH_MX7_PINS_H__ */
arch/arm/include/asm/arch-mx7/mx7d_pins.h new file +1308 -0
1,308 lines not on this page · raw message
arch/arm/include/asm/imx-common/iomux-v3.h +32 -0
@@ -85,6 +85,36 @@ typedef u64 iomux_v3_cfg_t;#define NO_PAD_CTRL (1 << 17) +#ifdef CONFIG_MX7 + +#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000 +#define IOMUX_CONFIG_LPSR 0x8 +#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ + MUX_MODE_SHIFT) + +#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0) +#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0) +#define PAD_CTL_DSE_1P8V_70OHM (0x2<<0) +#define PAD_CTL_DSE_1P8V_23OHM (0x3<<0) + +#define PAD_CTL_DSE_3P3V_196OHM (0x0<<0) +#define PAD_CTL_DSE_3P3V_49OHM (0x1<<0) +#define PAD_CTL_DSE_3P3V_98OHM (0x2<<0) +#define PAD_CTL_DSE_3P3V_32OHM (0x3<<0) + +#define PAD_CTL_SRE_FAST (0 << 2) +#define PAD_CTL_SRE_SLOW (0x1 << 2) + +#define PAD_CTL_HYS (0x1 << 3) +#define PAD_CTL_PUE (0x1 << 4) + +#define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) | PAD_CTL_PUE) + +#else +#ifdef CONFIG_MX6 #define PAD_CTL_HYS (1 << 16)
@@ -167,6 +197,8 @@ typedef u64 iomux_v3_cfg_t;#define PAD_CTL_SRE_SLOW (0 << 0)#define PAD_CTL_SRE_FAST (1 << 0) +#endif +#define IOMUX_CONFIG_SION 0x10#define GPIO_PIN_MASK 0x1f
Signature · 1 line
2.1.4
PATCH v4 2/13 imx: iomux-v3: add imx7d support for iomuxc
Hi Adrian,
Quoted 9 lines · Adrian Alonso
* Add imx7d support for iomux controller
* imx7d has two iomux controllers iomuxc (0x3033000) and iomuxc-lpsr (0x302C0000) each conroller provides control and mux mode pad registers but shares iomuxc input select register with iomuxc-lpsrIOMUX_CONFIG_LPSRflag is used to properly set daisy chain settings for iomuxc-lpsr pads.
* Since mx7d introduces LPSR IOMUX pins, add new base to IOMUX v3 driver for these LPSR pins.
I have a main question. For i.MX6, we could factorize (mainly thanks Tim's work) the major SOC variants, getting some important goals, as having a single u-boot image running on different variations of the same board.
This was reached deciding at run time which is the pin, its register and the value to be written - instead of fixing at build time.
Exceptions are the SOC that cannot be substitute by another one on the same board, because they are not pin compatible: for example, MX&SX.
Now you are introducing the new architecture for MX7, but it looks like you get rid of these improvements. It can be right or false, then my questions:
- has MX7 quite the same variations as MX6 ? I mean a qaud, dual and solo that are pin-to-pin compatible ?
- if this is true, why do you not use the same way as for imx6 ? See MX6_PAD_DECL macros.
Best regards,
Stefano Babic
Quoted 1,444 lines
Signed-off-by Adrian Alonso <[email protected]>Signed-off-by Fugang Duan <[email protected]>Signed-off-by Ye.Li <[email protected]>---
Changes for V2:
- Update commit log information
Changes for V3: Resend
Changes for V4:
- Fix Copyright year informationarch/arm/imx-common/iomux-v3.c | 18 + arch/arm/include/asm/arch-mx7/mx7-pins.h | 19 + arch/arm/include/asm/arch-mx7/mx7d_pins.h | 1308 ++++++++++++++++++++++++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 32 + 4 files changed, 1377 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx7/mx7-pins.h create mode 100644 arch/arm/include/asm/arch-mx7/mx7d_pins.harch/arm/imx-common/iomux-v3.c +18
-0@@ -41,6 +41,18 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) }#endif +#ifdef CONFIG_IOMUX_LPSR +u32 lpsr = (pad &MUX_MODE_LPSR ) >>MUX_MODE_SHIFT ; + +if (lpsr ==IOMUX_CONFIG_LPSR ) { + base = (void *)IOMUXC_LPSR_BASE_ADDR ; + mux_mode &= ~IOMUX_CONFIG_LPSR ; +/* set daisy chain sel_input */ +if (sel_input_ofs) + sel_input_ofs +=IOMUX_LPSR_SEL_INPUT_OFS ; + } +#endif +if (mux_ctrl_ofs)__raw_writel (mux_mode, base + mux_ctrl_ofs);@@ -55,6 +67,12 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)if (!(pad_ctrl &NO_PAD_CTRL ) && pad_ctrl_ofs)__raw_writel (pad_ctrl, base + pad_ctrl_ofs);#endif + +#ifdef CONFIG_IOMUX_LPSR +if (lpsr ==IOMUX_CONFIG_LPSR ) + base = (void *)IOMUXC_BASE_ADDR ; +#endif + }/* configures a list of pads within declared with IOMUX_PADS macro */ arch/arm/include/asm/arch-mx7/mx7-pins.h new file +19
-0@@ -0,0 +1,19 @@ +/* +* Copyright (C) 2015 Freescale Semiconductor, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#ifndef __ASM_ARCH_MX7_PINS_H__ +#define __ASM_ARCH_MX7_PINS_H__ + +#include <asm/imx-common/iomux-v3.h> + +#if defined(CONFIG_MX7D ) +#include "mx7d_pins.h" +#elif defined(CONFIG_MX7S ) +#include "mx7s_pins.h" +#else +#error "Please select cpu" +#endif /* CONFIG_MX7D */ + +#endif /*__ASM_ARCH_MX7_PINS_H__ */ arch/arm/include/asm/arch-mx7/mx7d_pins.h new file +1308
-0@@ -0,0 +1,1308 @@ +/* +* Copyright (C) 2015 Freescale Semiconductor, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ASM_ARCH_IMX7D_PINS_H__ +#define __ASM_ARCH_IMX7D_PINS_H__ + +#include <asm/imx-common/iomux-v3.h> + +enum { +MX7D_PAD_GPIO1_IO00__GPIO1_IO0 =IOMUX_PAD (0x0030 ,0x0000 ,IOMUX_CONFIG_LPSR |0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO00__PWM4_OUT =IOMUX_PAD (0x0030 ,0x0000 ,IOMUX_CONFIG_LPSR |1 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B =IOMUX_PAD (0x0030 ,0x0000 ,IOMUX_CONFIG_LPSR |3 ,0x0000 ,0 ,0 ), + +MX7D_PAD_GPIO1_IO01__GPIO1_IO1 =IOMUX_PAD (0x0034 ,0x0004 ,IOMUX_CONFIG_LPSR |0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO01__PWM1_OUT =IOMUX_PAD (0x0034 ,0x0004 ,IOMUX_CONFIG_LPSR |1 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 =IOMUX_PAD (0x0034 ,0x0004 ,IOMUX_CONFIG_LPSR |2 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO01__SAI1_MCLK =IOMUX_PAD (0x0034 ,0x0004 ,IOMUX_CONFIG_LPSR |3 ,0x0000 ,0 ,0 ), + +MX7D_PAD_GPIO1_IO02__GPIO1_IO2 =IOMUX_PAD (0x0038 ,0x0008 ,IOMUX_CONFIG_LPSR |0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO02__PWM2_OUT =IOMUX_PAD (0x0038 ,0x0008 ,IOMUX_CONFIG_LPSR |1 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 =IOMUX_PAD (0x0038 ,0x0008 ,IOMUX_CONFIG_LPSR |2 ,0x0564 ,3 ,0 ), +MX7D_PAD_GPIO1_IO02__SAI2_MCLK =IOMUX_PAD (0x0038 ,0x0008 ,IOMUX_CONFIG_LPSR |3 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO02__CCM_CLKO1 =IOMUX_PAD (0x0038 ,0x0008 ,IOMUX_CONFIG_LPSR |5 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO02__USB_OTG1_ID =IOMUX_PAD (0x0038 ,0x0008 ,IOMUX_CONFIG_LPSR |7 ,0x0734 ,3 ,0 ), + +MX7D_PAD_GPIO1_IO03__GPIO1_IO3 =IOMUX_PAD (0x003c ,0x000C ,IOMUX_CONFIG_LPSR |0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO03__PWM3_OUT =IOMUX_PAD (0x003c ,0x000C ,IOMUX_CONFIG_LPSR |1 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 =IOMUX_PAD (0x003c ,0x000C ,IOMUX_CONFIG_LPSR |2 ,0x0570 ,3 ,0 ), +MX7D_PAD_GPIO1_IO03__SAI3_MCLK =IOMUX_PAD (0x003c ,0x000C ,IOMUX_CONFIG_LPSR |3 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO03__CCM_CLKO2 =IOMUX_PAD (0x003c ,0x000C ,IOMUX_CONFIG_LPSR |5 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO03__USB_OTG2_ID =IOMUX_PAD (0x003c ,0x000C ,IOMUX_CONFIG_LPSR |7 ,0x0730 ,3 ,0 ), + +MX7D_PAD_GPIO1_IO04__GPIO1_IO4 =IOMUX_PAD (0x0040 ,0x0010 ,IOMUX_CONFIG_LPSR |0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO04__USB_OTG1_OC =IOMUX_PAD (0x0040 ,0x0010 ,IOMUX_CONFIG_LPSR |1 ,0x072C ,1 ,0 ), +MX7D_PAD_GPIO1_IO04__FLEXTIMER_CH4 =IOMUX_PAD (0x0040 ,0x0010 ,IOMUX_CONFIG_LPSR |2 ,0x0594 ,1 ,0 ), +MX7D_PAD_GPIO1_IO04__UART5_CTS_B =IOMUX_PAD (0x0040 ,0x0010 ,IOMUX_CONFIG_LPSR |3 ,0x0710 ,4 ,0 ), +MX7D_PAD_GPIO1_IO04__I2C1_SCL =IOMUX_PAD (0x0040 ,0x0010 ,IOMUX_CONFIG_LPSR |IOMUX_CONFIG_SION |4 ,0x05D4 ,2 ,0 ), + +MX7D_PAD_GPIO1_IO05__GPIO1_IO5 =IOMUX_PAD (0x0044 ,0x0014 ,IOMUX_CONFIG_LPSR |0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR =IOMUX_PAD (0x0044 ,0x0014 ,IOMUX_CONFIG_LPSR |1 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 =IOMUX_PAD (0x0044 ,0x0014 ,IOMUX_CONFIG_LPSR |2 ,0x0598 ,1 ,0 ), +MX7D_PAD_GPIO1_IO05__UART5_RTS_B =IOMUX_PAD (0x0044 ,0x0014 ,IOMUX_CONFIG_LPSR |3 ,0x0710 ,5 ,0 ), +MX7D_PAD_GPIO1_IO05__I2C1_SDA =IOMUX_PAD (0x0044 ,0x0014 ,IOMUX_CONFIG_LPSR |IOMUX_CONFIG_SION |4 ,0x05D8 ,2 ,0 ), + +MX7D_PAD_GPIO1_IO06__GPIO1_IO6 =IOMUX_PAD (0x0048 ,0x0018 ,IOMUX_CONFIG_LPSR |0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO06__USB_OTG2_OC =IOMUX_PAD (0x0048 ,0x0018 ,IOMUX_CONFIG_LPSR |1 ,0x0728 ,1 ,0 ), +MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 =IOMUX_PAD (0x0048 ,0x0018 ,IOMUX_CONFIG_LPSR |2 ,0x059C ,1 ,0 ), +MX7D_PAD_GPIO1_IO06__UART5_RX_DATA =IOMUX_PAD (0x0048 ,0x0018 ,IOMUX_CONFIG_LPSR |3 ,0x0714 ,4 ,0 ), +MX7D_PAD_GPIO1_IO06__I2C2_SCL =IOMUX_PAD (0x0048 ,0x0018 ,IOMUX_CONFIG_LPSR |IOMUX_CONFIG_SION |4 ,0x05DC ,2 ,0 ), +MX7D_PAD_GPIO1_IO06__CCM_WAIT =IOMUX_PAD (0x0048 ,0x0018 ,IOMUX_CONFIG_LPSR |5 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO06__KPP_ROW4 =IOMUX_PAD (0x0048 ,0x0018 ,IOMUX_CONFIG_LPSR |6 ,0x0624 ,1 ,0 ), + +MX7D_PAD_GPIO1_IO07__GPIO1_IO7 =IOMUX_PAD (0x004c ,0x001c ,IOMUX_CONFIG_LPSR |0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR =IOMUX_PAD (0x004c ,0x001c ,IOMUX_CONFIG_LPSR |1 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 =IOMUX_PAD (0x004c ,0x001c ,IOMUX_CONFIG_LPSR |2 ,0x05A0 ,1 ,0 ), +MX7D_PAD_GPIO1_IO07__UART5_TX_DATA =IOMUX_PAD (0x004c ,0x001c ,IOMUX_CONFIG_LPSR |3 ,0x0714 ,5 ,0 ), +MX7D_PAD_GPIO1_IO07__I2C2_SDA =IOMUX_PAD (0x004c ,0x001c ,IOMUX_CONFIG_LPSR |IOMUX_CONFIG_SION |4 ,0x05E0 ,2 ,0 ), +MX7D_PAD_GPIO1_IO07__CCM_STOP =IOMUX_PAD (0x004c ,0x001c ,IOMUX_CONFIG_LPSR |5 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO07__KPP_COL4 =IOMUX_PAD (0x004c ,0x001c ,IOMUX_CONFIG_LPSR |6 ,0x0604 ,1 ,0 ), +}; + +enum { +MX7D_PAD_GPIO1_IO08__GPIO1_IO8 =IOMUX_PAD (0x026C ,0x0014 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO08__SD1_VSELECT =IOMUX_PAD (0x026C ,0x0014 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B =IOMUX_PAD (0x026C ,0x0014 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO08__UART3_DCE_RX =IOMUX_PAD (0x026C ,0x0014 ,3 ,0x0704 ,0 ,0 ), +MX7D_PAD_GPIO1_IO08__UART3_DTE_TX =IOMUX_PAD (0x026C ,0x0014 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO08__I2C3_SCL =IOMUX_PAD (0x026C ,0x0014 ,IOMUX_CONFIG_SION |4 ,0x05E4 ,0 ,0 ), +MX7D_PAD_GPIO1_IO08__KPP_COL5 =IOMUX_PAD (0x026C ,0x0014 ,6 ,0x0608 ,0 ,0 ), +MX7D_PAD_GPIO1_IO08__PWM1_OUT =IOMUX_PAD (0x026C ,0x0014 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_GPIO1_IO09__GPIO1_IO9 =IOMUX_PAD (0x0270 ,0x0018 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO09__SD1_LCTL =IOMUX_PAD (0x0270 ,0x0018 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 =IOMUX_PAD (0x0270 ,0x0018 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO09__UART3_DCE_TX =IOMUX_PAD (0x0270 ,0x0018 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO09__UART3_DTE_RX =IOMUX_PAD (0x0270 ,0x0018 ,3 ,0x0704 ,1 ,0 ), +MX7D_PAD_GPIO1_IO09__I2C3_SDA =IOMUX_PAD (0x0270 ,0x0018 ,IOMUX_CONFIG_SION |4 ,0x05E8 ,0 ,0 ), +MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY =IOMUX_PAD (0x0270 ,0x0018 ,5 ,0x04F4 ,0 ,0 ), +MX7D_PAD_GPIO1_IO09__KPP_ROW5 =IOMUX_PAD (0x0270 ,0x0018 ,6 ,0x0628 ,0 ,0 ), +MX7D_PAD_GPIO1_IO09__PWM2_OUT =IOMUX_PAD (0x0270 ,0x0018 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_GPIO1_IO10__GPIO1_IO10 =IOMUX_PAD (0x0274 ,0x001C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO10__SD2_LCTL =IOMUX_PAD (0x0274 ,0x001C ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO10__ENET1_MDIO =IOMUX_PAD (0x0274 ,0x001C ,2 ,0x0568 ,0 ,0 ), +MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS =IOMUX_PAD (0x0274 ,0x001C ,3 ,0x0700 ,0 ,0 ), +MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS =IOMUX_PAD (0x0274 ,0x001C ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO10__I2C4_SCL =IOMUX_PAD (0x0274 ,0x001C ,IOMUX_CONFIG_SION |4 ,0x05EC ,0 ,0 ), +MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA =IOMUX_PAD (0x0274 ,0x001C ,5 ,0x05A4 ,0 ,0 ), +MX7D_PAD_GPIO1_IO10__KPP_COL6 =IOMUX_PAD (0x0274 ,0x001C ,6 ,0x060C ,0 ,0 ), +MX7D_PAD_GPIO1_IO10__PWM3_OUT =IOMUX_PAD (0x0274 ,0x001C ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_GPIO1_IO11__GPIO1_IO11 =IOMUX_PAD (0x0278 ,0x0020 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO11__SD3_LCTL =IOMUX_PAD (0x0278 ,0x0020 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO11__ENET1_MDC =IOMUX_PAD (0x0278 ,0x0020 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS =IOMUX_PAD (0x0278 ,0x0020 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS =IOMUX_PAD (0x0278 ,0x0020 ,3 ,0x0700 ,1 ,0 ), +MX7D_PAD_GPIO1_IO11__I2C4_SDA =IOMUX_PAD (0x0278 ,0x0020 ,IOMUX_CONFIG_SION |4 ,0x05F0 ,0 ,0 ), +MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB =IOMUX_PAD (0x0278 ,0x0020 ,5 ,0x05A8 ,0 ,0 ), +MX7D_PAD_GPIO1_IO11__KPP_ROW6 =IOMUX_PAD (0x0278 ,0x0020 ,6 ,0x062C ,0 ,0 ), +MX7D_PAD_GPIO1_IO11__PWM4_OUT =IOMUX_PAD (0x0278 ,0x0020 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_GPIO1_IO12__GPIO1_IO12 =IOMUX_PAD (0x027C ,0x0024 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO12__SD2_VSELECT =IOMUX_PAD (0x027C ,0x0024 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 =IOMUX_PAD (0x027C ,0x0024 ,2 ,0x0564 ,0 ,0 ), +MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX =IOMUX_PAD (0x027C ,0x0024 ,3 ,0x04DC ,0 ,0 ), +MX7D_PAD_GPIO1_IO12__CM4_NMI =IOMUX_PAD (0x027C ,0x0024 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 =IOMUX_PAD (0x027C ,0x0024 ,5 ,0x04E4 ,0 ,0 ), +MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 =IOMUX_PAD (0x027C ,0x0024 ,6 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO12__USB_OTG1_ID =IOMUX_PAD (0x027C ,0x0024 ,7 ,0x0734 ,0 ,0 ), + +MX7D_PAD_GPIO1_IO13__GPIO1_IO13 =IOMUX_PAD (0x0280 ,0x0028 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO13__SD3_VSELECT =IOMUX_PAD (0x0280 ,0x0028 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 =IOMUX_PAD (0x0280 ,0x0028 ,2 ,0x0570 ,0 ,0 ), +MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX =IOMUX_PAD (0x0280 ,0x0028 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY =IOMUX_PAD (0x0280 ,0x0028 ,4 ,0x04F4 ,1 ,0 ), +MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 =IOMUX_PAD (0x0280 ,0x0028 ,5 ,0x04E8 ,0 ,0 ), +MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL =IOMUX_PAD (0x0280 ,0x0028 ,6 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO13__USB_OTG2_ID =IOMUX_PAD (0x0280 ,0x0028 ,7 ,0x0730 ,0 ,0 ), + +MX7D_PAD_GPIO1_IO14__GPIO1_IO14 =IOMUX_PAD (0x0284 ,0x002C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO14__SD3_CD_B =IOMUX_PAD (0x0284 ,0x002C ,1 ,0x0738 ,0 ,0 ), +MX7D_PAD_GPIO1_IO14__ENET2_MDIO =IOMUX_PAD (0x0284 ,0x002C ,2 ,0x0574 ,0 ,0 ), +MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX =IOMUX_PAD (0x0284 ,0x002C ,3 ,0x04E0 ,0 ,0 ), +MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B =IOMUX_PAD (0x0284 ,0x002C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 =IOMUX_PAD (0x0284 ,0x002C ,5 ,0x04EC ,0 ,0 ), +MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 =IOMUX_PAD (0x0284 ,0x002C ,6 ,0x06D8 ,0 ,0 ), + +MX7D_PAD_GPIO1_IO15__GPIO1_IO15 =IOMUX_PAD (0x0288 ,0x0030 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO15__SD3_WP =IOMUX_PAD (0x0288 ,0x0030 ,1 ,0x073C ,0 ,0 ), +MX7D_PAD_GPIO1_IO15__ENET2_MDC =IOMUX_PAD (0x0288 ,0x0030 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX =IOMUX_PAD (0x0288 ,0x0030 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B =IOMUX_PAD (0x0288 ,0x0030 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 =IOMUX_PAD (0x0288 ,0x0030 ,5 ,0x04F0 ,0 ,0 ), +MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 =IOMUX_PAD (0x0288 ,0x0030 ,6 ,0x06DC ,0 ,0 ), + +MX7D_PAD_EPDC_DATA00__EPDC_DATA0 =IOMUX_PAD (0x02A4 ,0x0034 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD =IOMUX_PAD (0x02A4 ,0x0034 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 =IOMUX_PAD (0x02A4 ,0x0034 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA00__KPP_ROW3 =IOMUX_PAD (0x02A4 ,0x0034 ,3 ,0x0620 ,0 ,0 ), +MX7D_PAD_EPDC_DATA00__EIM_AD0 =IOMUX_PAD (0x02A4 ,0x0034 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA00__GPIO2_IO0 =IOMUX_PAD (0x02A4 ,0x0034 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA00__LCD_DATA0 =IOMUX_PAD (0x02A4 ,0x0034 ,6 ,0x0638 ,0 ,0 ), +MX7D_PAD_EPDC_DATA00__LCD_CLK =IOMUX_PAD (0x02A4 ,0x0034 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA01__EPDC_DATA1 =IOMUX_PAD (0x02A8 ,0x0038 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK =IOMUX_PAD (0x02A8 ,0x0038 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 =IOMUX_PAD (0x02A8 ,0x0038 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA01__KPP_COL3 =IOMUX_PAD (0x02A8 ,0x0038 ,3 ,0x0600 ,0 ,0 ), +MX7D_PAD_EPDC_DATA01__EIM_AD1 =IOMUX_PAD (0x02A8 ,0x0038 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA01__GPIO2_IO1 =IOMUX_PAD (0x02A8 ,0x0038 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA01__LCD_DATA1 =IOMUX_PAD (0x02A8 ,0x0038 ,6 ,0x063C ,0 ,0 ), +MX7D_PAD_EPDC_DATA01__LCD_ENABLE =IOMUX_PAD (0x02A8 ,0x0038 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA02__EPDC_DATA2 =IOMUX_PAD (0x02AC ,0x003C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B =IOMUX_PAD (0x02AC ,0x003C ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 =IOMUX_PAD (0x02AC ,0x003C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA02__KPP_ROW2 =IOMUX_PAD (0x02AC ,0x003C ,3 ,0x061C ,0 ,0 ), +MX7D_PAD_EPDC_DATA02__EIM_AD2 =IOMUX_PAD (0x02AC ,0x003C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA02__GPIO2_IO2 =IOMUX_PAD (0x02AC ,0x003C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA02__LCD_DATA2 =IOMUX_PAD (0x02AC ,0x003C ,6 ,0x0640 ,0 ,0 ), +MX7D_PAD_EPDC_DATA02__LCD_VSYNC =IOMUX_PAD (0x02AC ,0x003C ,7 ,0x0698 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA03__EPDC_DATA3 =IOMUX_PAD (0x02B0 ,0x0040 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN =IOMUX_PAD (0x02B0 ,0x0040 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 =IOMUX_PAD (0x02B0 ,0x0040 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA03__KPP_COL2 =IOMUX_PAD (0x02B0 ,0x0040 ,3 ,0x05FC ,0 ,0 ), +MX7D_PAD_EPDC_DATA03__EIM_AD3 =IOMUX_PAD (0x02B0 ,0x0040 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA03__GPIO2_IO3 =IOMUX_PAD (0x02B0 ,0x0040 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA03__LCD_DATA3 =IOMUX_PAD (0x02B0 ,0x0040 ,6 ,0x0644 ,0 ,0 ), +MX7D_PAD_EPDC_DATA03__LCD_HSYNC =IOMUX_PAD (0x02B0 ,0x0040 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA04__EPDC_DATA4 =IOMUX_PAD (0x02B4 ,0x0044 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD =IOMUX_PAD (0x02B4 ,0x0044 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA04__QSPI_A_DQS =IOMUX_PAD (0x02B4 ,0x0044 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA04__KPP_ROW1 =IOMUX_PAD (0x02B4 ,0x0044 ,3 ,0x0618 ,0 ,0 ), +MX7D_PAD_EPDC_DATA04__EIM_AD4 =IOMUX_PAD (0x02B4 ,0x0044 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA04__GPIO2_IO4 =IOMUX_PAD (0x02B4 ,0x0044 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA04__LCD_DATA4 =IOMUX_PAD (0x02B4 ,0x0044 ,6 ,0x0648 ,0 ,0 ), +MX7D_PAD_EPDC_DATA04__JTAG_FAIL =IOMUX_PAD (0x02B4 ,0x0044 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA05__EPDC_DATA5 =IOMUX_PAD (0x02B8 ,0x0048 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD =IOMUX_PAD (0x02B8 ,0x0048 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK =IOMUX_PAD (0x02B8 ,0x0048 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA05__KPP_COL1 =IOMUX_PAD (0x02B8 ,0x0048 ,3 ,0x05F8 ,0 ,0 ), +MX7D_PAD_EPDC_DATA05__EIM_AD5 =IOMUX_PAD (0x02B8 ,0x0048 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA05__GPIO2_IO5 =IOMUX_PAD (0x02B8 ,0x0048 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA05__LCD_DATA5 =IOMUX_PAD (0x02B8 ,0x0048 ,6 ,0x064C ,0 ,0 ), +MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE =IOMUX_PAD (0x02B8 ,0x0048 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA06__EPDC_DATA6 =IOMUX_PAD (0x02BC ,0x004C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK =IOMUX_PAD (0x02BC ,0x004C ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B =IOMUX_PAD (0x02BC ,0x004C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA06__KPP_ROW0 =IOMUX_PAD (0x02BC ,0x004C ,3 ,0x0614 ,0 ,0 ), +MX7D_PAD_EPDC_DATA06__EIM_AD6 =IOMUX_PAD (0x02BC ,0x004C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA06__GPIO2_IO6 =IOMUX_PAD (0x02BC ,0x004C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA06__LCD_DATA6 =IOMUX_PAD (0x02BC ,0x004C ,6 ,0x0650 ,0 ,0 ), +MX7D_PAD_EPDC_DATA06__JTAG_DE_B =IOMUX_PAD (0x02BC ,0x004C ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA07__EPDC_DATA7 =IOMUX_PAD (0x02C0 ,0x0050 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B =IOMUX_PAD (0x02C0 ,0x0050 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B =IOMUX_PAD (0x02C0 ,0x0050 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA07__KPP_COL0 =IOMUX_PAD (0x02C0 ,0x0050 ,3 ,0x05F4 ,0 ,0 ), +MX7D_PAD_EPDC_DATA07__EIM_AD7 =IOMUX_PAD (0x02C0 ,0x0050 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA07__GPIO2_IO7 =IOMUX_PAD (0x02C0 ,0x0050 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA07__LCD_DATA7 =IOMUX_PAD (0x02C0 ,0x0050 ,6 ,0x0654 ,0 ,0 ), +MX7D_PAD_EPDC_DATA07__JTAG_DONE =IOMUX_PAD (0x02C0 ,0x0050 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA08__EPDC_DATA8 =IOMUX_PAD (0x02C4 ,0x0054 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD =IOMUX_PAD (0x02C4 ,0x0054 ,1 ,0x06E4 ,0 ,0 ), +MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 =IOMUX_PAD (0x02C4 ,0x0054 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA08__UART6_DCE_RX =IOMUX_PAD (0x02C4 ,0x0054 ,3 ,0x071C ,0 ,0 ), +MX7D_PAD_EPDC_DATA08__UART6_DTE_TX =IOMUX_PAD (0x02C4 ,0x0054 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA08__EIM_OE =IOMUX_PAD (0x02C4 ,0x0054 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA08__GPIO2_IO8 =IOMUX_PAD (0x02C4 ,0x0054 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA08__LCD_DATA8 =IOMUX_PAD (0x02C4 ,0x0054 ,6 ,0x0658 ,0 ,0 ), +MX7D_PAD_EPDC_DATA08__LCD_BUSY =IOMUX_PAD (0x02C4 ,0x0054 ,7 ,0x0634 ,0 ,0 ), +MX7D_PAD_EPDC_DATA08__EPDC_SDCLK =IOMUX_PAD (0x02C4 ,0x0054 ,8 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA09__EPDC_DATA9 =IOMUX_PAD (0x02C8 ,0x0058 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK =IOMUX_PAD (0x02C8 ,0x0058 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 =IOMUX_PAD (0x02C8 ,0x0058 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA09__UART6_DCE_TX =IOMUX_PAD (0x02C8 ,0x0058 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA09__UART6_DTE_RX =IOMUX_PAD (0x02C8 ,0x0058 ,3 ,0x071C ,1 ,0 ), +MX7D_PAD_EPDC_DATA09__EIM_RW =IOMUX_PAD (0x02C8 ,0x0058 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA09__GPIO2_IO9 =IOMUX_PAD (0x02C8 ,0x0058 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA09__LCD_DATA9 =IOMUX_PAD (0x02C8 ,0x0058 ,6 ,0x065C ,0 ,0 ), +MX7D_PAD_EPDC_DATA09__LCD_DATA0 =IOMUX_PAD (0x02C8 ,0x0058 ,7 ,0x0638 ,1 ,0 ), +MX7D_PAD_EPDC_DATA09__EPDC_SDLE =IOMUX_PAD (0x02C8 ,0x0058 ,8 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA10__EPDC_DATA10 =IOMUX_PAD (0x02CC ,0x005C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B =IOMUX_PAD (0x02CC ,0x005C ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 =IOMUX_PAD (0x02CC ,0x005C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS =IOMUX_PAD (0x02CC ,0x005C ,3 ,0x0718 ,0 ,0 ), +MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS =IOMUX_PAD (0x02CC ,0x005C ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA10__EIM_CS0_B =IOMUX_PAD (0x02CC ,0x005C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA10__GPIO2_IO10 =IOMUX_PAD (0x02CC ,0x005C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA10__LCD_DATA10 =IOMUX_PAD (0x02CC ,0x005C ,6 ,0x0660 ,0 ,0 ), +MX7D_PAD_EPDC_DATA10__LCD_DATA9 =IOMUX_PAD (0x02CC ,0x005C ,7 ,0x065C ,1 ,0 ), +MX7D_PAD_EPDC_DATA10__EPDC_SDOE =IOMUX_PAD (0x02CC ,0x005C ,8 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA11__EPDC_DATA11 =IOMUX_PAD (0x02D0 ,0x0060 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN =IOMUX_PAD (0x02D0 ,0x0060 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 =IOMUX_PAD (0x02D0 ,0x0060 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS =IOMUX_PAD (0x02D0 ,0x0060 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS =IOMUX_PAD (0x02D0 ,0x0060 ,3 ,0x0718 ,1 ,0 ), +MX7D_PAD_EPDC_DATA11__EIM_BCLK =IOMUX_PAD (0x02D0 ,0x0060 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA11__GPIO2_IO11 =IOMUX_PAD (0x02D0 ,0x0060 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA11__LCD_DATA11 =IOMUX_PAD (0x02D0 ,0x0060 ,6 ,0x0664 ,0 ,0 ), +MX7D_PAD_EPDC_DATA11__LCD_DATA1 =IOMUX_PAD (0x02D0 ,0x0060 ,7 ,0x063C ,1 ,0 ), +MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 =IOMUX_PAD (0x02D0 ,0x0060 ,8 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA12__EPDC_DATA12 =IOMUX_PAD (0x02D4 ,0x0064 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD =IOMUX_PAD (0x02D4 ,0x0064 ,1 ,0x06E0 ,0 ,0 ), +MX7D_PAD_EPDC_DATA12__QSPI_B_DQS =IOMUX_PAD (0x02D4 ,0x0064 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA12__UART7_DCE_RX =IOMUX_PAD (0x02D4 ,0x0064 ,3 ,0x0724 ,0 ,0 ), +MX7D_PAD_EPDC_DATA12__UART7_DTE_TX =IOMUX_PAD (0x02D4 ,0x0064 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA12__EIM_LBA_B =IOMUX_PAD (0x02D4 ,0x0064 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA12__GPIO2_IO12 =IOMUX_PAD (0x02D4 ,0x0064 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA12__LCD_DATA12 =IOMUX_PAD (0x02D4 ,0x0064 ,6 ,0x0668 ,0 ,0 ), +MX7D_PAD_EPDC_DATA12__LCD_DATA21 =IOMUX_PAD (0x02D4 ,0x0064 ,7 ,0x068C ,0 ,0 ), +MX7D_PAD_EPDC_DATA12__EPDC_GDCLK =IOMUX_PAD (0x02D4 ,0x0064 ,8 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA13__EPDC_DATA13 =IOMUX_PAD (0x02D8 ,0x0068 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD =IOMUX_PAD (0x02D8 ,0x0068 ,1 ,0x06EC ,0 ,0 ), +MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK =IOMUX_PAD (0x02D8 ,0x0068 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA13__UART7_DCE_TX =IOMUX_PAD (0x02D8 ,0x0068 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA13__UART7_DTE_RX =IOMUX_PAD (0x02D8 ,0x0068 ,3 ,0x0724 ,1 ,0 ), +MX7D_PAD_EPDC_DATA13__EIM_WAIT =IOMUX_PAD (0x02D8 ,0x0068 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA13__GPIO2_IO13 =IOMUX_PAD (0x02D8 ,0x0068 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA13__LCD_DATA13 =IOMUX_PAD (0x02D8 ,0x0068 ,6 ,0x066C ,0 ,0 ), +MX7D_PAD_EPDC_DATA13__LCD_CS =IOMUX_PAD (0x02D8 ,0x0068 ,7 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA13__EPDC_GDOE =IOMUX_PAD (0x02D8 ,0x0068 ,8 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA14__EPDC_DATA14 =IOMUX_PAD (0x02DC ,0x006C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK =IOMUX_PAD (0x02DC ,0x006C ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B =IOMUX_PAD (0x02DC ,0x006C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS =IOMUX_PAD (0x02DC ,0x006C ,3 ,0x0720 ,0 ,0 ), +MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS =IOMUX_PAD (0x02DC ,0x006C ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA14__EIM_EB_B0 =IOMUX_PAD (0x02DC ,0x006C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA14__GPIO2_IO14 =IOMUX_PAD (0x02DC ,0x006C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA14__LCD_DATA14 =IOMUX_PAD (0x02DC ,0x006C ,6 ,0x0670 ,0 ,0 ), +MX7D_PAD_EPDC_DATA14__LCD_DATA22 =IOMUX_PAD (0x02DC ,0x006C ,7 ,0x0690 ,0 ,0 ), +MX7D_PAD_EPDC_DATA14__EPDC_GDSP =IOMUX_PAD (0x02DC ,0x006C ,8 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_DATA15__EPDC_DATA15 =IOMUX_PAD (0x02E0 ,0x0070 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B =IOMUX_PAD (0x02E0 ,0x0070 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B =IOMUX_PAD (0x02E0 ,0x0070 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS =IOMUX_PAD (0x02E0 ,0x0070 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS =IOMUX_PAD (0x02E0 ,0x0070 ,3 ,0x0720 ,1 ,0 ), +MX7D_PAD_EPDC_DATA15__EIM_CS1_B =IOMUX_PAD (0x02E0 ,0x0070 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA15__GPIO2_IO15 =IOMUX_PAD (0x02E0 ,0x0070 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA15__LCD_DATA15 =IOMUX_PAD (0x02E0 ,0x0070 ,6 ,0x0674 ,0 ,0 ), +MX7D_PAD_EPDC_DATA15__LCD_WR_RWN =IOMUX_PAD (0x02E0 ,0x0070 ,7 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM =IOMUX_PAD (0x02E0 ,0x0070 ,8 ,0x0000 ,0 ,0 ), + +MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK =IOMUX_PAD (0x02E4 ,0x0074 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN =IOMUX_PAD (0x02E4 ,0x0074 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 =IOMUX_PAD (0x02E4 ,0x0074 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCLK__KPP_ROW4 =IOMUX_PAD (0x02E4 ,0x0074 ,3 ,0x0624 ,0 ,0 ), +MX7D_PAD_EPDC_SDCLK__EIM_AD10 =IOMUX_PAD (0x02E4 ,0x0074 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 =IOMUX_PAD (0x02E4 ,0x0074 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCLK__LCD_CLK =IOMUX_PAD (0x02E4 ,0x0074 ,6 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCLK__LCD_DATA20 =IOMUX_PAD (0x02E4 ,0x0074 ,7 ,0x0688 ,0 ,0 ), + +MX7D_PAD_EPDC_SDLE__EPDC_SDLE =IOMUX_PAD (0x02E8 ,0x0078 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD =IOMUX_PAD (0x02E8 ,0x0078 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 =IOMUX_PAD (0x02E8 ,0x0078 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDLE__KPP_COL4 =IOMUX_PAD (0x02E8 ,0x0078 ,3 ,0x0604 ,0 ,0 ), +MX7D_PAD_EPDC_SDLE__EIM_AD11 =IOMUX_PAD (0x02E8 ,0x0078 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDLE__GPIO2_IO17 =IOMUX_PAD (0x02E8 ,0x0078 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDLE__LCD_DATA16 =IOMUX_PAD (0x02E8 ,0x0078 ,6 ,0x0678 ,0 ,0 ), +MX7D_PAD_EPDC_SDLE__LCD_DATA8 =IOMUX_PAD (0x02E8 ,0x0078 ,7 ,0x0658 ,1 ,0 ), + +MX7D_PAD_EPDC_SDOE__EPDC_SDOE =IOMUX_PAD (0x02EC ,0x007C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 =IOMUX_PAD (0x02EC ,0x007C ,1 ,0x0584 ,0 ,0 ), +MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 =IOMUX_PAD (0x02EC ,0x007C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDOE__KPP_COL5 =IOMUX_PAD (0x02EC ,0x007C ,3 ,0x0608 ,1 ,0 ), +MX7D_PAD_EPDC_SDOE__EIM_AD12 =IOMUX_PAD (0x02EC ,0x007C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDOE__GPIO2_IO18 =IOMUX_PAD (0x02EC ,0x007C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDOE__LCD_DATA17 =IOMUX_PAD (0x02EC ,0x007C ,6 ,0x067C ,0 ,0 ), +MX7D_PAD_EPDC_SDOE__LCD_DATA23 =IOMUX_PAD (0x02EC ,0x007C ,7 ,0x0694 ,0 ,0 ), + +MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR =IOMUX_PAD (0x02F0 ,0x0080 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 =IOMUX_PAD (0x02F0 ,0x0080 ,1 ,0x0588 ,0 ,0 ), +MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 =IOMUX_PAD (0x02F0 ,0x0080 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDSHR__KPP_ROW5 =IOMUX_PAD (0x02F0 ,0x0080 ,3 ,0x0628 ,1 ,0 ), +MX7D_PAD_EPDC_SDSHR__EIM_AD13 =IOMUX_PAD (0x02F0 ,0x0080 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 =IOMUX_PAD (0x02F0 ,0x0080 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDSHR__LCD_DATA18 =IOMUX_PAD (0x02F0 ,0x0080 ,6 ,0x0680 ,0 ,0 ), +MX7D_PAD_EPDC_SDSHR__LCD_DATA10 =IOMUX_PAD (0x02F0 ,0x0080 ,7 ,0x0660 ,1 ,0 ), + +MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 =IOMUX_PAD (0x02F4 ,0x0084 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 =IOMUX_PAD (0x02F4 ,0x0084 ,1 ,0x058C ,0 ,0 ), +MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL =IOMUX_PAD (0x02F4 ,0x0084 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE0__EIM_AD14 =IOMUX_PAD (0x02F4 ,0x0084 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 =IOMUX_PAD (0x02F4 ,0x0084 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE0__LCD_DATA19 =IOMUX_PAD (0x02F4 ,0x0084 ,6 ,0x0684 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE0__LCD_DATA5 =IOMUX_PAD (0x02F4 ,0x0084 ,7 ,0x064C ,1 ,0 ), + +MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 =IOMUX_PAD (0x02F8 ,0x0088 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 =IOMUX_PAD (0x02F8 ,0x0088 ,1 ,0x0590 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC =IOMUX_PAD (0x02F8 ,0x0088 ,2 ,0x0578 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER =IOMUX_PAD (0x02F8 ,0x0088 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE1__EIM_AD15 =IOMUX_PAD (0x02F8 ,0x0088 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 =IOMUX_PAD (0x02F8 ,0x0088 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE1__LCD_DATA20 =IOMUX_PAD (0x02F8 ,0x0088 ,6 ,0x0688 ,1 ,0 ), +MX7D_PAD_EPDC_SDCE1__LCD_DATA4 =IOMUX_PAD (0x02F8 ,0x0088 ,7 ,0x0648 ,1 ,0 ), + +MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 =IOMUX_PAD (0x02FC ,0x008C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN =IOMUX_PAD (0x02FC ,0x008C ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 =IOMUX_PAD (0x02FC ,0x008C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE2__KPP_COL6 =IOMUX_PAD (0x02FC ,0x008C ,3 ,0x060C ,1 ,0 ), +MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 =IOMUX_PAD (0x02FC ,0x008C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 =IOMUX_PAD (0x02FC ,0x008C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE2__LCD_DATA21 =IOMUX_PAD (0x02FC ,0x008C ,6 ,0x068C ,1 ,0 ), +MX7D_PAD_EPDC_SDCE2__LCD_DATA3 =IOMUX_PAD (0x02FC ,0x008C ,7 ,0x0644 ,1 ,0 ), + +MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 =IOMUX_PAD (0x0300 ,0x0090 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD =IOMUX_PAD (0x0300 ,0x0090 ,1 ,0x06E8 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 =IOMUX_PAD (0x0300 ,0x0090 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE3__KPP_ROW6 =IOMUX_PAD (0x0300 ,0x0090 ,3 ,0x062C ,1 ,0 ), +MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 =IOMUX_PAD (0x0300 ,0x0090 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 =IOMUX_PAD (0x0300 ,0x0090 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_SDCE3__LCD_DATA22 =IOMUX_PAD (0x0300 ,0x0090 ,6 ,0x0690 ,1 ,0 ), +MX7D_PAD_EPDC_SDCE3__LCD_DATA2 =IOMUX_PAD (0x0300 ,0x0090 ,7 ,0x0640 ,1 ,0 ), + +MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK =IOMUX_PAD (0x0304 ,0x0094 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 =IOMUX_PAD (0x0304 ,0x0094 ,1 ,0x05AC ,0 ,0 ), +MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 =IOMUX_PAD (0x0304 ,0x0094 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDCLK__KPP_COL7 =IOMUX_PAD (0x0304 ,0x0094 ,3 ,0x0610 ,0 ,0 ), +MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 =IOMUX_PAD (0x0304 ,0x0094 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 =IOMUX_PAD (0x0304 ,0x0094 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDCLK__LCD_DATA23 =IOMUX_PAD (0x0304 ,0x0094 ,6 ,0x0694 ,1 ,0 ), +MX7D_PAD_EPDC_GDCLK__LCD_DATA16 =IOMUX_PAD (0x0304 ,0x0094 ,7 ,0x0678 ,1 ,0 ), + +MX7D_PAD_EPDC_GDOE__EPDC_GDOE =IOMUX_PAD (0x0308 ,0x0098 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 =IOMUX_PAD (0x0308 ,0x0098 ,1 ,0x05B0 ,0 ,0 ), +MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 =IOMUX_PAD (0x0308 ,0x0098 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDOE__KPP_ROW7 =IOMUX_PAD (0x0308 ,0x0098 ,3 ,0x0630 ,0 ,0 ), +MX7D_PAD_EPDC_GDOE__EIM_ADDR19 =IOMUX_PAD (0x0308 ,0x0098 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDOE__GPIO2_IO25 =IOMUX_PAD (0x0308 ,0x0098 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDOE__LCD_WR_RWN =IOMUX_PAD (0x0308 ,0x0098 ,6 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDOE__LCD_DATA18 =IOMUX_PAD (0x0308 ,0x0098 ,7 ,0x0680 ,1 ,0 ), + +MX7D_PAD_EPDC_GDRL__EPDC_GDRL =IOMUX_PAD (0x030C ,0x009C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 =IOMUX_PAD (0x030C ,0x009C ,1 ,0x05B4 ,0 ,0 ), +MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL =IOMUX_PAD (0x030C ,0x009C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDRL__EIM_ADDR20 =IOMUX_PAD (0x030C ,0x009C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDRL__GPIO2_IO26 =IOMUX_PAD (0x030C ,0x009C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDRL__LCD_RD_E =IOMUX_PAD (0x030C ,0x009C ,6 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDRL__LCD_DATA19 =IOMUX_PAD (0x030C ,0x009C ,7 ,0x0684 ,1 ,0 ), + +MX7D_PAD_EPDC_GDSP__EPDC_GDSP =IOMUX_PAD (0x0310 ,0x00A0 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 =IOMUX_PAD (0x0310 ,0x00A0 ,1 ,0x05B8 ,0 ,0 ), +MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC =IOMUX_PAD (0x0310 ,0x00A0 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDSP__ENET2_TX_ER =IOMUX_PAD (0x0310 ,0x00A0 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDSP__EIM_ADDR21 =IOMUX_PAD (0x0310 ,0x00A0 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDSP__GPIO2_IO27 =IOMUX_PAD (0x0310 ,0x00A0 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_GDSP__LCD_BUSY =IOMUX_PAD (0x0310 ,0x00A0 ,6 ,0x0634 ,1 ,0 ), +MX7D_PAD_EPDC_GDSP__LCD_DATA17 =IOMUX_PAD (0x0310 ,0x00A0 ,7 ,0x067C ,1 ,0 ), + +MX7D_PAD_EPDC_BDR0__EPDC_BDR0 =IOMUX_PAD (0x0314 ,0x00A4 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK =IOMUX_PAD (0x0314 ,0x00A4 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 =IOMUX_PAD (0x0314 ,0x00A4 ,3 ,0x0570 ,1 ,0 ), +MX7D_PAD_EPDC_BDR0__EIM_ADDR22 =IOMUX_PAD (0x0314 ,0x00A4 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_BDR0__GPIO2_IO28 =IOMUX_PAD (0x0314 ,0x00A4 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_BDR0__LCD_CS =IOMUX_PAD (0x0314 ,0x00A4 ,6 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_BDR0__LCD_DATA7 =IOMUX_PAD (0x0314 ,0x00A4 ,7 ,0x0654 ,1 ,0 ), + +MX7D_PAD_EPDC_BDR1__EPDC_BDR1 =IOMUX_PAD (0x0318 ,0x00A8 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN =IOMUX_PAD (0x0318 ,0x00A8 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK =IOMUX_PAD (0x0318 ,0x00A8 ,2 ,0x0578 ,1 ,0 ), +MX7D_PAD_EPDC_BDR1__EIM_AD8 =IOMUX_PAD (0x0318 ,0x00A8 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_BDR1__GPIO2_IO29 =IOMUX_PAD (0x0318 ,0x00A8 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_BDR1__LCD_ENABLE =IOMUX_PAD (0x0318 ,0x00A8 ,6 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_BDR1__LCD_DATA6 =IOMUX_PAD (0x0318 ,0x00A8 ,7 ,0x0650 ,1 ,0 ), + +MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM =IOMUX_PAD (0x031C ,0x00AC ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA =IOMUX_PAD (0x031C ,0x00AC ,1 ,0x05CC ,0 ,0 ), +MX7D_PAD_EPDC_PWR_COM__ENET2_CRS =IOMUX_PAD (0x031C ,0x00AC ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_PWR_COM__EIM_AD9 =IOMUX_PAD (0x031C ,0x00AC ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 =IOMUX_PAD (0x031C ,0x00AC ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC =IOMUX_PAD (0x031C ,0x00AC ,6 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 =IOMUX_PAD (0x031C ,0x00AC ,7 ,0x0664 ,1 ,0 ), + +MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT =IOMUX_PAD (0x0320 ,0x00B0 ,0 ,0x0580 ,0 ,0 ), +MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB =IOMUX_PAD (0x0320 ,0x00B0 ,1 ,0x05D0 ,0 ,0 ), +MX7D_PAD_EPDC_PWR_STAT__ENET2_COL =IOMUX_PAD (0x0320 ,0x00B0 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 =IOMUX_PAD (0x0320 ,0x00B0 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 =IOMUX_PAD (0x0320 ,0x00B0 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC =IOMUX_PAD (0x0320 ,0x00B0 ,6 ,0x0698 ,1 ,0 ), +MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 =IOMUX_PAD (0x0320 ,0x00B0 ,7 ,0x0668 ,1 ,0 ), + +MX7D_PAD_LCD_CLK__LCD_CLK =IOMUX_PAD (0x0324 ,0x00B4 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_CLK__ECSPI4_MISO =IOMUX_PAD (0x0324 ,0x00B4 ,1 ,0x0558 ,0 ,0 ), +MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN =IOMUX_PAD (0x0324 ,0x00B4 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_CLK__CSI_DATA16 =IOMUX_PAD (0x0324 ,0x00B4 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_CLK__UART2_DCE_RX =IOMUX_PAD (0x0324 ,0x00B4 ,4 ,0x06FC ,0 ,0 ), +MX7D_PAD_LCD_CLK__UART2_DTE_TX =IOMUX_PAD (0x0324 ,0x00B4 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_CLK__GPIO3_IO0 =IOMUX_PAD (0x0324 ,0x00B4 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_ENABLE__LCD_ENABLE =IOMUX_PAD (0x0328 ,0x00B8 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI =IOMUX_PAD (0x0328 ,0x00B8 ,1 ,0x055C ,0 ,0 ), +MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN =IOMUX_PAD (0x0328 ,0x00B8 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_ENABLE__CSI_DATA17 =IOMUX_PAD (0x0328 ,0x00B8 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_ENABLE__UART2_DCE_TX =IOMUX_PAD (0x0328 ,0x00B8 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_ENABLE__UART2_DTE_RX =IOMUX_PAD (0x0328 ,0x00B8 ,4 ,0x06FC ,1 ,0 ), +MX7D_PAD_LCD_ENABLE__GPIO3_IO1 =IOMUX_PAD (0x0328 ,0x00B8 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_HSYNC__LCD_HSYNC =IOMUX_PAD (0x032C ,0x00BC ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK =IOMUX_PAD (0x032C ,0x00BC ,1 ,0x0554 ,0 ,0 ), +MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN =IOMUX_PAD (0x032C ,0x00BC ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_HSYNC__CSI_DATA18 =IOMUX_PAD (0x032C ,0x00BC ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS =IOMUX_PAD (0x032C ,0x00BC ,4 ,0x06F8 ,0 ,0 ), +MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS =IOMUX_PAD (0x032C ,0x00BC ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_HSYNC__GPIO3_IO2 =IOMUX_PAD (0x032C ,0x00BC ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_VSYNC__LCD_VSYNC =IOMUX_PAD (0x0330 ,0x00C0 ,0 ,0x0698 ,2 ,0 ), +MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 =IOMUX_PAD (0x0330 ,0x00C0 ,1 ,0x0560 ,0 ,0 ), +MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN =IOMUX_PAD (0x0330 ,0x00C0 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_VSYNC__CSI_DATA19 =IOMUX_PAD (0x0330 ,0x00C0 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS =IOMUX_PAD (0x0330 ,0x00C0 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS =IOMUX_PAD (0x0330 ,0x00C0 ,4 ,0x06F8 ,1 ,0 ), +MX7D_PAD_LCD_VSYNC__GPIO3_IO3 =IOMUX_PAD (0x0330 ,0x00C0 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_RESET__LCD_RESET =IOMUX_PAD (0x0334 ,0x00C4 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_RESET__GPT1_COMPARE1 =IOMUX_PAD (0x0334 ,0x00C4 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI =IOMUX_PAD (0x0334 ,0x00C4 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_RESET__CSI_FIELD =IOMUX_PAD (0x0334 ,0x00C4 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_RESET__EIM_DTACK_B =IOMUX_PAD (0x0334 ,0x00C4 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_RESET__GPIO3_IO4 =IOMUX_PAD (0x0334 ,0x00C4 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA00__LCD_DATA0 =IOMUX_PAD (0x0338 ,0x00C8 ,0 ,0x0638 ,2 ,0 ), +MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 =IOMUX_PAD (0x0338 ,0x00C8 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA00__CSI_DATA20 =IOMUX_PAD (0x0338 ,0x00C8 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA00__EIM_DATA0 =IOMUX_PAD (0x0338 ,0x00C8 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA00__GPIO3_IO5 =IOMUX_PAD (0x0338 ,0x00C8 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 =IOMUX_PAD (0x0338 ,0x00C8 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA01__LCD_DATA1 =IOMUX_PAD (0x033C ,0x00CC ,0 ,0x063C ,2 ,0 ), +MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 =IOMUX_PAD (0x033C ,0x00CC ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA01__CSI_DATA21 =IOMUX_PAD (0x033C ,0x00CC ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA01__EIM_DATA1 =IOMUX_PAD (0x033C ,0x00CC ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA01__GPIO3_IO6 =IOMUX_PAD (0x033C ,0x00CC ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 =IOMUX_PAD (0x033C ,0x00CC ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA02__LCD_DATA2 =IOMUX_PAD (0x0340 ,0x00D0 ,0 ,0x0640 ,2 ,0 ), +MX7D_PAD_LCD_DATA02__GPT1_CLK =IOMUX_PAD (0x0340 ,0x00D0 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA02__CSI_DATA22 =IOMUX_PAD (0x0340 ,0x00D0 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA02__EIM_DATA2 =IOMUX_PAD (0x0340 ,0x00D0 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA02__GPIO3_IO7 =IOMUX_PAD (0x0340 ,0x00D0 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 =IOMUX_PAD (0x0340 ,0x00D0 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA03__LCD_DATA3 =IOMUX_PAD (0x0344 ,0x00D4 ,0 ,0x0644 ,2 ,0 ), +MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 =IOMUX_PAD (0x0344 ,0x00D4 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA03__CSI_DATA23 =IOMUX_PAD (0x0344 ,0x00D4 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA03__EIM_DATA3 =IOMUX_PAD (0x0344 ,0x00D4 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA03__GPIO3_IO8 =IOMUX_PAD (0x0344 ,0x00D4 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 =IOMUX_PAD (0x0344 ,0x00D4 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA04__LCD_DATA4 =IOMUX_PAD (0x0348 ,0x00D8 ,0 ,0x0648 ,2 ,0 ), +MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 =IOMUX_PAD (0x0348 ,0x00D8 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA04__CSI_VSYNC =IOMUX_PAD (0x0348 ,0x00D8 ,3 ,0x0520 ,0 ,0 ), +MX7D_PAD_LCD_DATA04__EIM_DATA4 =IOMUX_PAD (0x0348 ,0x00D8 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA04__GPIO3_IO9 =IOMUX_PAD (0x0348 ,0x00D8 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 =IOMUX_PAD (0x0348 ,0x00D8 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA05__LCD_DATA5 =IOMUX_PAD (0x034C ,0x00DC ,0 ,0x064C ,2 ,0 ), +MX7D_PAD_LCD_DATA05__CSI_HSYNC =IOMUX_PAD (0x034C ,0x00DC ,3 ,0x0518 ,0 ,0 ), +MX7D_PAD_LCD_DATA05__EIM_DATA5 =IOMUX_PAD (0x034C ,0x00DC ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA05__GPIO3_IO10 =IOMUX_PAD (0x034C ,0x00DC ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 =IOMUX_PAD (0x034C ,0x00DC ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA06__LCD_DATA6 =IOMUX_PAD (0x0350 ,0x00E0 ,0 ,0x0650 ,2 ,0 ), +MX7D_PAD_LCD_DATA06__CSI_PIXCLK =IOMUX_PAD (0x0350 ,0x00E0 ,3 ,0x051C ,0 ,0 ), +MX7D_PAD_LCD_DATA06__EIM_DATA6 =IOMUX_PAD (0x0350 ,0x00E0 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA06__GPIO3_IO11 =IOMUX_PAD (0x0350 ,0x00E0 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 =IOMUX_PAD (0x0350 ,0x00E0 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA07__LCD_DATA7 =IOMUX_PAD (0x0354 ,0x00E4 ,0 ,0x0654 ,2 ,0 ), +MX7D_PAD_LCD_DATA07__CSI_MCLK =IOMUX_PAD (0x0354 ,0x00E4 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA07__EIM_DATA7 =IOMUX_PAD (0x0354 ,0x00E4 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA07__GPIO3_IO12 =IOMUX_PAD (0x0354 ,0x00E4 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 =IOMUX_PAD (0x0354 ,0x00E4 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA08__LCD_DATA8 =IOMUX_PAD (0x0358 ,0x00E8 ,0 ,0x0658 ,2 ,0 ), +MX7D_PAD_LCD_DATA08__CSI_DATA9 =IOMUX_PAD (0x0358 ,0x00E8 ,3 ,0x0514 ,0 ,0 ), +MX7D_PAD_LCD_DATA08__EIM_DATA8 =IOMUX_PAD (0x0358 ,0x00E8 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA08__GPIO3_IO13 =IOMUX_PAD (0x0358 ,0x00E8 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 =IOMUX_PAD (0x0358 ,0x00E8 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA09__LCD_DATA9 =IOMUX_PAD (0x035C ,0x00EC ,0 ,0x065C ,2 ,0 ), +MX7D_PAD_LCD_DATA09__CSI_DATA8 =IOMUX_PAD (0x035C ,0x00EC ,3 ,0x0510 ,0 ,0 ), +MX7D_PAD_LCD_DATA09__EIM_DATA9 =IOMUX_PAD (0x035C ,0x00EC ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA09__GPIO3_IO14 =IOMUX_PAD (0x035C ,0x00EC ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 =IOMUX_PAD (0x035C ,0x00EC ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA10__LCD_DATA10 =IOMUX_PAD (0x0360 ,0x00F0 ,0 ,0x0660 ,2 ,0 ), +MX7D_PAD_LCD_DATA10__CSI_DATA7 =IOMUX_PAD (0x0360 ,0x00F0 ,3 ,0x050C ,0 ,0 ), +MX7D_PAD_LCD_DATA10__EIM_DATA10 =IOMUX_PAD (0x0360 ,0x00F0 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA10__GPIO3_IO15 =IOMUX_PAD (0x0360 ,0x00F0 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 =IOMUX_PAD (0x0360 ,0x00F0 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA11__LCD_DATA11 =IOMUX_PAD (0x0364 ,0x00F4 ,0 ,0x0664 ,2 ,0 ), +MX7D_PAD_LCD_DATA11__CSI_DATA6 =IOMUX_PAD (0x0364 ,0x00F4 ,3 ,0x0508 ,0 ,0 ), +MX7D_PAD_LCD_DATA11__EIM_DATA11 =IOMUX_PAD (0x0364 ,0x00F4 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA11__GPIO3_IO16 =IOMUX_PAD (0x0364 ,0x00F4 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 =IOMUX_PAD (0x0364 ,0x00F4 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA12__LCD_DATA12 =IOMUX_PAD (0x0368 ,0x00F8 ,0 ,0x0668 ,2 ,0 ), +MX7D_PAD_LCD_DATA12__CSI_DATA5 =IOMUX_PAD (0x0368 ,0x00F8 ,3 ,0x0504 ,0 ,0 ), +MX7D_PAD_LCD_DATA12__EIM_DATA12 =IOMUX_PAD (0x0368 ,0x00F8 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA12__GPIO3_IO17 =IOMUX_PAD (0x0368 ,0x00F8 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 =IOMUX_PAD (0x0368 ,0x00F8 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA13__LCD_DATA13 =IOMUX_PAD (0x036C ,0x00FC ,0 ,0x066C ,1 ,0 ), +MX7D_PAD_LCD_DATA13__CSI_DATA4 =IOMUX_PAD (0x036C ,0x00FC ,3 ,0x0500 ,0 ,0 ), +MX7D_PAD_LCD_DATA13__EIM_DATA13 =IOMUX_PAD (0x036C ,0x00FC ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA13__GPIO3_IO18 =IOMUX_PAD (0x036C ,0x00FC ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 =IOMUX_PAD (0x036C ,0x00FC ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA14__LCD_DATA14 =IOMUX_PAD (0x0370 ,0x0100 ,0 ,0x0670 ,1 ,0 ), +MX7D_PAD_LCD_DATA14__CSI_DATA3 =IOMUX_PAD (0x0370 ,0x0100 ,3 ,0x04FC ,0 ,0 ), +MX7D_PAD_LCD_DATA14__EIM_DATA14 =IOMUX_PAD (0x0370 ,0x0100 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA14__GPIO3_IO19 =IOMUX_PAD (0x0370 ,0x0100 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 =IOMUX_PAD (0x0370 ,0x0100 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA15__LCD_DATA15 =IOMUX_PAD (0x0374 ,0x0104 ,0 ,0x0674 ,1 ,0 ), +MX7D_PAD_LCD_DATA15__CSI_DATA2 =IOMUX_PAD (0x0374 ,0x0104 ,3 ,0x04F8 ,0 ,0 ), +MX7D_PAD_LCD_DATA15__EIM_DATA15 =IOMUX_PAD (0x0374 ,0x0104 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA15__GPIO3_IO20 =IOMUX_PAD (0x0374 ,0x0104 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 =IOMUX_PAD (0x0374 ,0x0104 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA16__LCD_DATA16 =IOMUX_PAD (0x0378 ,0x0108 ,0 ,0x0678 ,2 ,0 ), +MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 =IOMUX_PAD (0x0378 ,0x0108 ,1 ,0x0594 ,0 ,0 ), +MX7D_PAD_LCD_DATA16__CSI_DATA1 =IOMUX_PAD (0x0378 ,0x0108 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA16__EIM_CRE =IOMUX_PAD (0x0378 ,0x0108 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA16__GPIO3_IO21 =IOMUX_PAD (0x0378 ,0x0108 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 =IOMUX_PAD (0x0378 ,0x0108 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA17__LCD_DATA17 =IOMUX_PAD (0x037C ,0x010C ,0 ,0x067C ,2 ,0 ), +MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 =IOMUX_PAD (0x037C ,0x010C ,1 ,0x0598 ,0 ,0 ), +MX7D_PAD_LCD_DATA17__CSI_DATA0 =IOMUX_PAD (0x037C ,0x010C ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN =IOMUX_PAD (0x037C ,0x010C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA17__GPIO3_IO22 =IOMUX_PAD (0x037C ,0x010C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 =IOMUX_PAD (0x037C ,0x010C ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA18__LCD_DATA18 =IOMUX_PAD (0x0380 ,0x0110 ,0 ,0x0680 ,2 ,0 ), +MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 =IOMUX_PAD (0x0380 ,0x0110 ,1 ,0x059C ,0 ,0 ), +MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO =IOMUX_PAD (0x0380 ,0x0110 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA18__CSI_DATA15 =IOMUX_PAD (0x0380 ,0x0110 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA18__EIM_CS2_B =IOMUX_PAD (0x0380 ,0x0110 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA18__GPIO3_IO23 =IOMUX_PAD (0x0380 ,0x0110 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 =IOMUX_PAD (0x0380 ,0x0110 ,6 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA19__EIM_CS3_B =IOMUX_PAD (0x0384 ,0x0114 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA19__GPIO3_IO24 =IOMUX_PAD (0x0384 ,0x0114 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 =IOMUX_PAD (0x0384 ,0x0114 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA19__LCD_DATA19 =IOMUX_PAD (0x0384 ,0x0114 ,0 ,0x0684 ,2 ,0 ), +MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 =IOMUX_PAD (0x0384 ,0x0114 ,1 ,0x05A0 ,0 ,0 ), +MX7D_PAD_LCD_DATA19__CSI_DATA14 =IOMUX_PAD (0x0384 ,0x0114 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA20__EIM_ADDR23 =IOMUX_PAD (0x0388 ,0x0118 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA20__GPIO3_IO25 =IOMUX_PAD (0x0388 ,0x0118 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA20__I2C3_SCL =IOMUX_PAD (0x0388 ,0x0118 ,IOMUX_CONFIG_SION |6 ,0x05E4 ,1 ,0 ), + +MX7D_PAD_LCD_DATA20__LCD_DATA20 =IOMUX_PAD (0x0388 ,0x0118 ,0 ,0x0688 ,2 ,0 ), +MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 =IOMUX_PAD (0x0388 ,0x0118 ,1 ,0x05BC ,0 ,0 ), +MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT =IOMUX_PAD (0x0388 ,0x0118 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA20__CSI_DATA13 =IOMUX_PAD (0x0388 ,0x0118 ,3 ,0x0000 ,0 ,0 ), + +MX7D_PAD_LCD_DATA21__LCD_DATA21 =IOMUX_PAD (0x038C ,0x011C ,0 ,0x068C ,2 ,0 ), +MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 =IOMUX_PAD (0x038C ,0x011C ,1 ,0x05C0 ,0 ,0 ), +MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT =IOMUX_PAD (0x038C ,0x011C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA21__CSI_DATA12 =IOMUX_PAD (0x038C ,0x011C ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA21__EIM_ADDR24 =IOMUX_PAD (0x038C ,0x011C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA21__GPIO3_IO26 =IOMUX_PAD (0x038C ,0x011C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA21__I2C3_SDA =IOMUX_PAD (0x038C ,0x011C ,IOMUX_CONFIG_SION |6 ,0x05E8 ,1 ,0 ), + +MX7D_PAD_LCD_DATA22__LCD_DATA22 =IOMUX_PAD (0x0390 ,0x0120 ,0 ,0x0690 ,2 ,0 ), +MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 =IOMUX_PAD (0x0390 ,0x0120 ,1 ,0x05C4 ,0 ,0 ), +MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT =IOMUX_PAD (0x0390 ,0x0120 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA22__CSI_DATA11 =IOMUX_PAD (0x0390 ,0x0120 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA22__EIM_ADDR25 =IOMUX_PAD (0x0390 ,0x0120 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA22__GPIO3_IO27 =IOMUX_PAD (0x0390 ,0x0120 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA22__I2C4_SCL =IOMUX_PAD (0x0390 ,0x0120 ,IOMUX_CONFIG_SION |6 ,0x05EC ,1 ,0 ), + +MX7D_PAD_LCD_DATA23__LCD_DATA23 =IOMUX_PAD (0x0394 ,0x0124 ,0 ,0x0694 ,2 ,0 ), +MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 =IOMUX_PAD (0x0394 ,0x0124 ,1 ,0x05C8 ,0 ,0 ), +MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT =IOMUX_PAD (0x0394 ,0x0124 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA23__CSI_DATA10 =IOMUX_PAD (0x0394 ,0x0124 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA23__EIM_ADDR26 =IOMUX_PAD (0x0394 ,0x0124 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA23__GPIO3_IO28 =IOMUX_PAD (0x0394 ,0x0124 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_LCD_DATA23__I2C4_SDA =IOMUX_PAD (0x0394 ,0x0124 ,IOMUX_CONFIG_SION |6 ,0x05F0 ,1 ,0 ), + +MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX =IOMUX_PAD (0x0398 ,0x0128 ,0 ,0x0000 ,0 ,0 ), + +MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX =IOMUX_PAD (0x0398 ,0x0128 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART1_RX_DATA__I2C1_SCL =IOMUX_PAD (0x0398 ,0x0128 ,IOMUX_CONFIG_SION |1 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY =IOMUX_PAD (0x0398 ,0x0128 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 =IOMUX_PAD (0x0398 ,0x0128 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN =IOMUX_PAD (0x0398 ,0x0128 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 =IOMUX_PAD (0x0398 ,0x0128 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART1_RX_DATA__ENET1_MDIO =IOMUX_PAD (0x0398 ,0x0128 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX =IOMUX_PAD (0x039C ,0x012C ,0 ,0x0000 ,0 ,0 ), + +MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX =IOMUX_PAD (0x039C ,0x012C ,0 ,0x06F4 ,1 ,0 ), +MX7D_PAD_UART1_TX_DATA__I2C1_SDA =IOMUX_PAD (0x039C ,0x012C ,IOMUX_CONFIG_SION |1 ,0x05D8 ,0 ,0 ), +MX7D_PAD_UART1_TX_DATA__SAI3_MCLK =IOMUX_PAD (0x039C ,0x012C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 =IOMUX_PAD (0x039C ,0x012C ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT =IOMUX_PAD (0x039C ,0x012C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 =IOMUX_PAD (0x039C ,0x012C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART1_TX_DATA__ENET1_MDC =IOMUX_PAD (0x039C ,0x012C ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX =IOMUX_PAD (0x03A0 ,0x0130 ,0 ,0x0000 ,0 ,0 ), + +MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX =IOMUX_PAD (0x03A0 ,0x0130 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART2_RX_DATA__I2C2_SCL =IOMUX_PAD (0x03A0 ,0x0130 ,IOMUX_CONFIG_SION |1 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK =IOMUX_PAD (0x03A0 ,0x0130 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 =IOMUX_PAD (0x03A0 ,0x0130 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN =IOMUX_PAD (0x03A0 ,0x0130 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 =IOMUX_PAD (0x03A0 ,0x0130 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART2_RX_DATA__ENET2_MDIO =IOMUX_PAD (0x03A0 ,0x0130 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX =IOMUX_PAD (0x03A4 ,0x0134 ,0 ,0x0000 ,0 ,0 ), + +MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX =IOMUX_PAD (0x03A4 ,0x0134 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART2_TX_DATA__I2C2_SDA =IOMUX_PAD (0x03A4 ,0x0134 ,IOMUX_CONFIG_SION |1 ,0x05E0 ,0 ,0 ), +MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 =IOMUX_PAD (0x03A4 ,0x0134 ,2 ,0x06C8 ,0 ,0 ), +MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY =IOMUX_PAD (0x03A4 ,0x0134 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT =IOMUX_PAD (0x03A4 ,0x0134 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 =IOMUX_PAD (0x03A4 ,0x0134 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART2_TX_DATA__ENET2_MDC =IOMUX_PAD (0x03A4 ,0x0134 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX =IOMUX_PAD (0x03A8 ,0x0138 ,0 ,0x0704 ,2 ,0 ), + +MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX =IOMUX_PAD (0x03A8 ,0x0138 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC =IOMUX_PAD (0x03A8 ,0x0138 ,1 ,0x072C ,0 ,0 ), +MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC =IOMUX_PAD (0x03A8 ,0x0138 ,2 ,0x06CC ,0 ,0 ), +MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO =IOMUX_PAD (0x03A8 ,0x0138 ,3 ,0x0528 ,0 ,0 ), +MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN =IOMUX_PAD (0x03A8 ,0x0138 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 =IOMUX_PAD (0x03A8 ,0x0138 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_RX_DATA__SD1_LCTL =IOMUX_PAD (0x03A8 ,0x0138 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX =IOMUX_PAD (0x03AC ,0x013C ,0 ,0x0000 ,0 ,0 ), + +MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX =IOMUX_PAD (0x03AC ,0x013C ,0 ,0x0704 ,3 ,0 ), +MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR =IOMUX_PAD (0x03AC ,0x013C ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK =IOMUX_PAD (0x03AC ,0x013C ,2 ,0x06D0 ,0 ,0 ), +MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI =IOMUX_PAD (0x03AC ,0x013C ,3 ,0x052C ,0 ,0 ), +MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT =IOMUX_PAD (0x03AC ,0x013C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 =IOMUX_PAD (0x03AC ,0x013C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_TX_DATA__SD2_LCTL =IOMUX_PAD (0x03AC ,0x013C ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS =IOMUX_PAD (0x03B0 ,0x0140 ,0 ,0x0000 ,0 ,0 ), + +MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS =IOMUX_PAD (0x03B0 ,0x0140 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_RTS_B__USB_OTG2_OC =IOMUX_PAD (0x03B0 ,0x0140 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 =IOMUX_PAD (0x03B0 ,0x0140 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK =IOMUX_PAD (0x03B0 ,0x0140 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN =IOMUX_PAD (0x03B0 ,0x0140 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_RTS_B__GPIO4_IO6 =IOMUX_PAD (0x03B0 ,0x0140 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_RTS_B__SD3_LCTL =IOMUX_PAD (0x03B0 ,0x0140 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS =IOMUX_PAD (0x03B4 ,0x0144 ,0 ,0x0000 ,0 ,0 ), + +MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS =IOMUX_PAD (0x03B4 ,0x0144 ,0 ,0x0700 ,3 ,0 ), +MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR =IOMUX_PAD (0x03B4 ,0x0144 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC =IOMUX_PAD (0x03B4 ,0x0144 ,2 ,0x06D4 ,0 ,0 ), +MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 =IOMUX_PAD (0x03B4 ,0x0144 ,3 ,0x0530 ,0 ,0 ), +MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT =IOMUX_PAD (0x03B4 ,0x0144 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_CTS_B__GPIO4_IO7 =IOMUX_PAD (0x03B4 ,0x0144 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_UART3_CTS_B__SD1_VSELECT =IOMUX_PAD (0x03B4 ,0x0144 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_I2C1_SCL__I2C1_SCL =IOMUX_PAD (0x03B8 ,0x0148 ,IOMUX_CONFIG_SION |0 ,0x05D4 ,1 ,0 ), +MX7D_PAD_I2C1_SCL__UART4_DCE_CTS =IOMUX_PAD (0x03B8 ,0x0148 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C1_SCL__UART4_DTE_RTS =IOMUX_PAD (0x03B8 ,0x0148 ,1 ,0x0708 ,0 ,0 ), +MX7D_PAD_I2C1_SCL__FLEXCAN1_RX =IOMUX_PAD (0x03B8 ,0x0148 ,2 ,0x04DC ,1 ,0 ), +MX7D_PAD_I2C1_SCL__ECSPI3_MISO =IOMUX_PAD (0x03B8 ,0x0148 ,3 ,0x0548 ,0 ,0 ), +MX7D_PAD_I2C1_SCL__GPIO4_IO8 =IOMUX_PAD (0x03B8 ,0x0148 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C1_SCL__SD2_VSELECT =IOMUX_PAD (0x03B8 ,0x0148 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_I2C1_SDA__I2C1_SDA =IOMUX_PAD (0x03BC ,0x014C ,IOMUX_CONFIG_SION |0 ,0x05D8 ,1 ,0 ), +MX7D_PAD_I2C1_SDA__UART4_DCE_RTS =IOMUX_PAD (0x03BC ,0x014C ,1 ,0x0708 ,1 ,0 ), +MX7D_PAD_I2C1_SDA__UART4_DTE_CTS =IOMUX_PAD (0x03BC ,0x014C ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C1_SDA__FLEXCAN1_TX =IOMUX_PAD (0x03BC ,0x014C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C1_SDA__ECSPI3_MOSI =IOMUX_PAD (0x03BC ,0x014C ,3 ,0x054C ,0 ,0 ), +MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 =IOMUX_PAD (0x03BC ,0x014C ,4 ,0x0564 ,1 ,0 ), +MX7D_PAD_I2C1_SDA__GPIO4_IO9 =IOMUX_PAD (0x03BC ,0x014C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C1_SDA__SD3_VSELECT =IOMUX_PAD (0x03BC ,0x014C ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_I2C2_SCL__I2C2_SCL =IOMUX_PAD (0x03C0 ,0x0150 ,IOMUX_CONFIG_SION |0 ,0x05DC ,1 ,0 ), +MX7D_PAD_I2C2_SCL__UART4_DCE_RX =IOMUX_PAD (0x03C0 ,0x0150 ,1 ,0x070C ,0 ,0 ), +MX7D_PAD_I2C2_SCL__UART4_DTE_TX =IOMUX_PAD (0x03C0 ,0x0150 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B =IOMUX_PAD (0x03C0 ,0x0150 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C2_SCL__ECSPI3_SCLK =IOMUX_PAD (0x03C0 ,0x0150 ,3 ,0x0544 ,0 ,0 ), +MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 =IOMUX_PAD (0x03C0 ,0x0150 ,4 ,0x0570 ,2 ,0 ), +MX7D_PAD_I2C2_SCL__GPIO4_IO10 =IOMUX_PAD (0x03C0 ,0x0150 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C2_SCL__SD3_CD_B =IOMUX_PAD (0x03C0 ,0x0150 ,6 ,0x0738 ,1 ,0 ), + +MX7D_PAD_I2C2_SDA__I2C2_SDA =IOMUX_PAD (0x03C4 ,0x0154 ,IOMUX_CONFIG_SION |0 ,0x05E0 ,1 ,0 ), +MX7D_PAD_I2C2_SDA__UART4_DCE_TX =IOMUX_PAD (0x03C4 ,0x0154 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C2_SDA__UART4_DTE_RX =IOMUX_PAD (0x03C4 ,0x0154 ,1 ,0x070C ,1 ,0 ), +MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB =IOMUX_PAD (0x03C4 ,0x0154 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C2_SDA__ECSPI3_SS0 =IOMUX_PAD (0x03C4 ,0x0154 ,3 ,0x0550 ,0 ,0 ), +MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 =IOMUX_PAD (0x03C4 ,0x0154 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C2_SDA__GPIO4_IO11 =IOMUX_PAD (0x03C4 ,0x0154 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C2_SDA__SD3_WP =IOMUX_PAD (0x03C4 ,0x0154 ,6 ,0x073C ,1 ,0 ), + +MX7D_PAD_I2C3_SCL__I2C3_SCL =IOMUX_PAD (0x03C8 ,0x0158 ,IOMUX_CONFIG_SION |0 ,0x05E4 ,2 ,0 ), +MX7D_PAD_I2C3_SCL__UART5_DCE_CTS =IOMUX_PAD (0x03C8 ,0x0158 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C3_SCL__UART5_DTE_RTS =IOMUX_PAD (0x03C8 ,0x0158 ,1 ,0x0710 ,0 ,0 ), +MX7D_PAD_I2C3_SCL__FLEXCAN2_RX =IOMUX_PAD (0x03C8 ,0x0158 ,2 ,0x04E0 ,1 ,0 ), +MX7D_PAD_I2C3_SCL__CSI_VSYNC =IOMUX_PAD (0x03C8 ,0x0158 ,3 ,0x0520 ,1 ,0 ), +MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 =IOMUX_PAD (0x03C8 ,0x0158 ,4 ,0x06D8 ,1 ,0 ), +MX7D_PAD_I2C3_SCL__GPIO4_IO12 =IOMUX_PAD (0x03C8 ,0x0158 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C3_SCL__EPDC_BDR0 =IOMUX_PAD (0x03C8 ,0x0158 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_I2C3_SDA__I2C3_SDA =IOMUX_PAD (0x03CC ,0x015C ,IOMUX_CONFIG_SION |0 ,0x05E8 ,2 ,0 ), +MX7D_PAD_I2C3_SDA__UART5_DCE_RTS =IOMUX_PAD (0x03CC ,0x015C ,1 ,0x0710 ,1 ,0 ), +MX7D_PAD_I2C3_SDA__UART5_DTE_CTS =IOMUX_PAD (0x03CC ,0x015C ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C3_SDA__FLEXCAN2_TX =IOMUX_PAD (0x03CC ,0x015C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C3_SDA__CSI_HSYNC =IOMUX_PAD (0x03CC ,0x015C ,3 ,0x0518 ,1 ,0 ), +MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 =IOMUX_PAD (0x03CC ,0x015C ,4 ,0x06DC ,1 ,0 ), +MX7D_PAD_I2C3_SDA__GPIO4_IO13 =IOMUX_PAD (0x03CC ,0x015C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C3_SDA__EPDC_BDR1 =IOMUX_PAD (0x03CC ,0x015C ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_I2C4_SCL__I2C4_SCL =IOMUX_PAD (0x03D0 ,0x0160 ,IOMUX_CONFIG_SION |0 ,0x05EC ,2 ,0 ), +MX7D_PAD_I2C4_SCL__UART5_DCE_RX =IOMUX_PAD (0x03D0 ,0x0160 ,1 ,0x0714 ,0 ,0 ), +MX7D_PAD_I2C4_SCL__UART5_DTE_TX =IOMUX_PAD (0x03D0 ,0x0160 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B =IOMUX_PAD (0x03D0 ,0x0160 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C4_SCL__CSI_PIXCLK =IOMUX_PAD (0x03D0 ,0x0160 ,3 ,0x051C ,1 ,0 ), +MX7D_PAD_I2C4_SCL__USB_OTG1_ID =IOMUX_PAD (0x03D0 ,0x0160 ,4 ,0x0734 ,1 ,0 ), +MX7D_PAD_I2C4_SCL__GPIO4_IO14 =IOMUX_PAD (0x03D0 ,0x0160 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C4_SCL__EPDC_VCOM0 =IOMUX_PAD (0x03D0 ,0x0160 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_I2C4_SDA__I2C4_SDA =IOMUX_PAD (0x03D4 ,0x0164 ,IOMUX_CONFIG_SION |0 ,0x05F0 ,2 ,0 ), +MX7D_PAD_I2C4_SDA__UART5_DCE_TX =IOMUX_PAD (0x03D4 ,0x0164 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C4_SDA__UART5_DTE_RX =IOMUX_PAD (0x03D4 ,0x0164 ,1 ,0x0714 ,1 ,0 ), +MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB =IOMUX_PAD (0x03D4 ,0x0164 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C4_SDA__CSI_MCLK =IOMUX_PAD (0x03D4 ,0x0164 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C4_SDA__USB_OTG2_ID =IOMUX_PAD (0x03D4 ,0x0164 ,4 ,0x0730 ,1 ,0 ), +MX7D_PAD_I2C4_SDA__GPIO4_IO15 =IOMUX_PAD (0x03D4 ,0x0164 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_I2C4_SDA__EPDC_VCOM1 =IOMUX_PAD (0x03D4 ,0x0164 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK =IOMUX_PAD (0x03D8 ,0x0168 ,0 ,0x0524 ,1 ,0 ), +MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX =IOMUX_PAD (0x03D8 ,0x0168 ,1 ,0x071C ,2 ,0 ), +MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX =IOMUX_PAD (0x03D8 ,0x0168 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 =IOMUX_PAD (0x03D8 ,0x0168 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 =IOMUX_PAD (0x03D8 ,0x0168 ,3 ,0x04F8 ,1 ,0 ), +MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 =IOMUX_PAD (0x03D8 ,0x0168 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM =IOMUX_PAD (0x03D8 ,0x0168 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI =IOMUX_PAD (0x03DC ,0x016C ,0 ,0x052C ,1 ,0 ), +MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX =IOMUX_PAD (0x03DC ,0x016C ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX =IOMUX_PAD (0x03DC ,0x016C ,1 ,0x071C ,3 ,0 ), +MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 =IOMUX_PAD (0x03DC ,0x016C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 =IOMUX_PAD (0x03DC ,0x016C ,3 ,0x04FC ,1 ,0 ), +MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 =IOMUX_PAD (0x03DC ,0x016C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT =IOMUX_PAD (0x03DC ,0x016C ,6 ,0x0580 ,1 ,0 ), + +MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO =IOMUX_PAD (0x03E0 ,0x0170 ,0 ,0x0528 ,1 ,0 ), +MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS =IOMUX_PAD (0x03E0 ,0x0170 ,1 ,0x0718 ,2 ,0 ), +MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS =IOMUX_PAD (0x03E0 ,0x0170 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI1_MISO__SD2_DATA6 =IOMUX_PAD (0x03E0 ,0x0170 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI1_MISO__CSI_DATA4 =IOMUX_PAD (0x03E0 ,0x0170 ,3 ,0x0500 ,1 ,0 ), +MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 =IOMUX_PAD (0x03E0 ,0x0170 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ =IOMUX_PAD (0x03E0 ,0x0170 ,6 ,0x057C ,0 ,0 ), + +MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 =IOMUX_PAD (0x03E4 ,0x0174 ,0 ,0x0530 ,1 ,0 ), +MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS =IOMUX_PAD (0x03E4 ,0x0174 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS =IOMUX_PAD (0x03E4 ,0x0174 ,1 ,0x0718 ,3 ,0 ), +MX7D_PAD_ECSPI1_SS0__SD2_DATA7 =IOMUX_PAD (0x03E4 ,0x0174 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI1_SS0__CSI_DATA5 =IOMUX_PAD (0x03E4 ,0x0174 ,3 ,0x0504 ,1 ,0 ), +MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 =IOMUX_PAD (0x03E4 ,0x0174 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 =IOMUX_PAD (0x03E4 ,0x0174 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK =IOMUX_PAD (0x03E8 ,0x0178 ,0 ,0x0534 ,0 ,0 ), +MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX =IOMUX_PAD (0x03E8 ,0x0178 ,1 ,0x0724 ,2 ,0 ), +MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX =IOMUX_PAD (0x03E8 ,0x0178 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 =IOMUX_PAD (0x03E8 ,0x0178 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 =IOMUX_PAD (0x03E8 ,0x0178 ,3 ,0x0508 ,1 ,0 ), +MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 =IOMUX_PAD (0x03E8 ,0x0178 ,4 ,0x066C ,2 ,0 ), +MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 =IOMUX_PAD (0x03E8 ,0x0178 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 =IOMUX_PAD (0x03E8 ,0x0178 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI =IOMUX_PAD (0x03EC ,0x017C ,0 ,0x053C ,0 ,0 ), +MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX =IOMUX_PAD (0x03EC ,0x017C ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX =IOMUX_PAD (0x03EC ,0x017C ,1 ,0x0724 ,3 ,0 ), +MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 =IOMUX_PAD (0x03EC ,0x017C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 =IOMUX_PAD (0x03EC ,0x017C ,3 ,0x050C ,1 ,0 ), +MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 =IOMUX_PAD (0x03EC ,0x017C ,4 ,0x0670 ,2 ,0 ), +MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 =IOMUX_PAD (0x03EC ,0x017C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 =IOMUX_PAD (0x03EC ,0x017C ,6 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 =IOMUX_PAD (0x03F0 ,0x0180 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 =IOMUX_PAD (0x03F0 ,0x0180 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO =IOMUX_PAD (0x03F0 ,0x0180 ,0 ,0x0538 ,0 ,0 ), +MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS =IOMUX_PAD (0x03F0 ,0x0180 ,1 ,0x0720 ,2 ,0 ), +MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS =IOMUX_PAD (0x03F0 ,0x0180 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI2_MISO__SD1_DATA6 =IOMUX_PAD (0x03F0 ,0x0180 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI2_MISO__CSI_DATA8 =IOMUX_PAD (0x03F0 ,0x0180 ,3 ,0x0510 ,1 ,0 ), +MX7D_PAD_ECSPI2_MISO__LCD_DATA15 =IOMUX_PAD (0x03F0 ,0x0180 ,4 ,0x0674 ,2 ,0 ), + +MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 =IOMUX_PAD (0x03F4 ,0x0184 ,0 ,0x0540 ,0 ,0 ), +MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS =IOMUX_PAD (0x03F4 ,0x0184 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS =IOMUX_PAD (0x03F4 ,0x0184 ,1 ,0x0720 ,3 ,0 ), +MX7D_PAD_ECSPI2_SS0__SD1_DATA7 =IOMUX_PAD (0x03F4 ,0x0184 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI2_SS0__CSI_DATA9 =IOMUX_PAD (0x03F4 ,0x0184 ,3 ,0x0514 ,1 ,0 ), +MX7D_PAD_ECSPI2_SS0__LCD_RESET =IOMUX_PAD (0x03F4 ,0x0184 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 =IOMUX_PAD (0x03F4 ,0x0184 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE =IOMUX_PAD (0x03F4 ,0x0184 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD1_CD_B__SD1_CD_B =IOMUX_PAD (0x03F8 ,0x0188 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_CD_B__UART6_DCE_RX =IOMUX_PAD (0x03F8 ,0x0188 ,2 ,0x071C ,4 ,0 ), +MX7D_PAD_SD1_CD_B__UART6_DTE_TX =IOMUX_PAD (0x03F8 ,0x0188 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_CD_B__ECSPI4_MISO =IOMUX_PAD (0x03F8 ,0x0188 ,3 ,0x0558 ,1 ,0 ), +MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 =IOMUX_PAD (0x03F8 ,0x0188 ,4 ,0x0584 ,1 ,0 ), +MX7D_PAD_SD1_CD_B__GPIO5_IO0 =IOMUX_PAD (0x03F8 ,0x0188 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_CD_B__CCM_CLKO1 =IOMUX_PAD (0x03F8 ,0x0188 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD1_WP__SD1_WP =IOMUX_PAD (0x03FC ,0x018C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_WP__UART6_DCE_TX =IOMUX_PAD (0x03FC ,0x018C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_WP__UART6_DTE_RX =IOMUX_PAD (0x03FC ,0x018C ,2 ,0x071C ,5 ,0 ), +MX7D_PAD_SD1_WP__ECSPI4_MOSI =IOMUX_PAD (0x03FC ,0x018C ,3 ,0x055C ,1 ,0 ), +MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 =IOMUX_PAD (0x03FC ,0x018C ,4 ,0x0588 ,1 ,0 ), +MX7D_PAD_SD1_WP__GPIO5_IO1 =IOMUX_PAD (0x03FC ,0x018C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_WP__CCM_CLKO2 =IOMUX_PAD (0x03FC ,0x018C ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD1_RESET_B__SD1_RESET_B =IOMUX_PAD (0x0400 ,0x0190 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_RESET_B__SAI3_MCLK =IOMUX_PAD (0x0400 ,0x0190 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS =IOMUX_PAD (0x0400 ,0x0190 ,2 ,0x0718 ,4 ,0 ), +MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS =IOMUX_PAD (0x0400 ,0x0190 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK =IOMUX_PAD (0x0400 ,0x0190 ,3 ,0x0554 ,1 ,0 ), +MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 =IOMUX_PAD (0x0400 ,0x0190 ,4 ,0x058C ,1 ,0 ), +MX7D_PAD_SD1_RESET_B__GPIO5_IO2 =IOMUX_PAD (0x0400 ,0x0190 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD1_CLK__SD1_CLK =IOMUX_PAD (0x0404 ,0x0194 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_CLK__SAI3_RX_SYNC =IOMUX_PAD (0x0404 ,0x0194 ,1 ,0x06CC ,1 ,0 ), +MX7D_PAD_SD1_CLK__UART6_DCE_CTS =IOMUX_PAD (0x0404 ,0x0194 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_CLK__UART6_DTE_RTS =IOMUX_PAD (0x0404 ,0x0194 ,2 ,0x0718 ,5 ,0 ), +MX7D_PAD_SD1_CLK__ECSPI4_SS0 =IOMUX_PAD (0x0404 ,0x0194 ,3 ,0x0560 ,1 ,0 ), +MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 =IOMUX_PAD (0x0404 ,0x0194 ,4 ,0x0590 ,1 ,0 ), +MX7D_PAD_SD1_CLK__GPIO5_IO3 =IOMUX_PAD (0x0404 ,0x0194 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD1_CMD__SD1_CMD =IOMUX_PAD (0x0408 ,0x0198 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_CMD__SAI3_RX_BCLK =IOMUX_PAD (0x0408 ,0x0198 ,1 ,0x06C4 ,1 ,0 ), +MX7D_PAD_SD1_CMD__ECSPI4_SS1 =IOMUX_PAD (0x0408 ,0x0198 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 =IOMUX_PAD (0x0408 ,0x0198 ,4 ,0x05AC ,1 ,0 ), +MX7D_PAD_SD1_CMD__GPIO5_IO4 =IOMUX_PAD (0x0408 ,0x0198 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD1_DATA0__SD1_DATA0 =IOMUX_PAD (0x040C ,0x019C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 =IOMUX_PAD (0x040C ,0x019C ,1 ,0x06C8 ,1 ,0 ), +MX7D_PAD_SD1_DATA0__UART7_DCE_RX =IOMUX_PAD (0x040C ,0x019C ,2 ,0x0724 ,4 ,0 ), +MX7D_PAD_SD1_DATA0__UART7_DTE_TX =IOMUX_PAD (0x040C ,0x019C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA0__ECSPI4_SS2 =IOMUX_PAD (0x040C ,0x019C ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 =IOMUX_PAD (0x040C ,0x019C ,4 ,0x05B0 ,1 ,0 ), +MX7D_PAD_SD1_DATA0__GPIO5_IO5 =IOMUX_PAD (0x040C ,0x019C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 =IOMUX_PAD (0x040C ,0x019C ,6 ,0x04E4 ,1 ,0 ), + +MX7D_PAD_SD1_DATA1__SD1_DATA1 =IOMUX_PAD (0x0410 ,0x01A0 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK =IOMUX_PAD (0x0410 ,0x01A0 ,1 ,0x06D0 ,1 ,0 ), +MX7D_PAD_SD1_DATA1__UART7_DCE_TX =IOMUX_PAD (0x0410 ,0x01A0 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA1__UART7_DTE_RX =IOMUX_PAD (0x0410 ,0x01A0 ,2 ,0x0724 ,5 ,0 ), +MX7D_PAD_SD1_DATA1__ECSPI4_SS3 =IOMUX_PAD (0x0410 ,0x01A0 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 =IOMUX_PAD (0x0410 ,0x01A0 ,4 ,0x05B4 ,1 ,0 ), +MX7D_PAD_SD1_DATA1__GPIO5_IO6 =IOMUX_PAD (0x0410 ,0x01A0 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 =IOMUX_PAD (0x0410 ,0x01A0 ,6 ,0x04E8 ,1 ,0 ), + +MX7D_PAD_SD1_DATA2__SD1_DATA2 =IOMUX_PAD (0x0414 ,0x01A4 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC =IOMUX_PAD (0x0414 ,0x01A4 ,1 ,0x06D4 ,1 ,0 ), +MX7D_PAD_SD1_DATA2__UART7_DCE_CTS =IOMUX_PAD (0x0414 ,0x01A4 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA2__UART7_DTE_RTS =IOMUX_PAD (0x0414 ,0x01A4 ,2 ,0x0720 ,4 ,0 ), +MX7D_PAD_SD1_DATA2__ECSPI4_RDY =IOMUX_PAD (0x0414 ,0x01A4 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 =IOMUX_PAD (0x0414 ,0x01A4 ,4 ,0x05B8 ,1 ,0 ), +MX7D_PAD_SD1_DATA2__GPIO5_IO7 =IOMUX_PAD (0x0414 ,0x01A4 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 =IOMUX_PAD (0x0414 ,0x01A4 ,6 ,0x04EC ,1 ,0 ), + +MX7D_PAD_SD1_DATA3__SD1_DATA3 =IOMUX_PAD (0x0418 ,0x01A8 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 =IOMUX_PAD (0x0418 ,0x01A8 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA3__UART7_DCE_RTS =IOMUX_PAD (0x0418 ,0x01A8 ,2 ,0x0720 ,5 ,0 ), +MX7D_PAD_SD1_DATA3__UART7_DTE_CTS =IOMUX_PAD (0x0418 ,0x01A8 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA3__ECSPI3_SS1 =IOMUX_PAD (0x0418 ,0x01A8 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA =IOMUX_PAD (0x0418 ,0x01A8 ,4 ,0x05A4 ,1 ,0 ), +MX7D_PAD_SD1_DATA3__GPIO5_IO8 =IOMUX_PAD (0x0418 ,0x01A8 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 =IOMUX_PAD (0x0418 ,0x01A8 ,6 ,0x04F0 ,1 ,0 ), + +MX7D_PAD_SD2_CD_B__SD2_CD_B =IOMUX_PAD (0x041C ,0x01AC ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_CD_B__ENET1_MDIO =IOMUX_PAD (0x041C ,0x01AC ,1 ,0x0568 ,2 ,0 ), +MX7D_PAD_SD2_CD_B__ENET2_MDIO =IOMUX_PAD (0x041C ,0x01AC ,2 ,0x0574 ,2 ,0 ), +MX7D_PAD_SD2_CD_B__ECSPI3_SS2 =IOMUX_PAD (0x041C ,0x01AC ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB =IOMUX_PAD (0x041C ,0x01AC ,4 ,0x05A8 ,1 ,0 ), +MX7D_PAD_SD2_CD_B__GPIO5_IO9 =IOMUX_PAD (0x041C ,0x01AC ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 =IOMUX_PAD (0x041C ,0x01AC ,6 ,0x06D8 ,2 ,0 ), + +MX7D_PAD_SD2_WP__SD2_WP =IOMUX_PAD (0x0420 ,0x01B0 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_WP__ENET1_MDC =IOMUX_PAD (0x0420 ,0x01B0 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_WP__ENET2_MDC =IOMUX_PAD (0x0420 ,0x01B0 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_WP__ECSPI3_SS3 =IOMUX_PAD (0x0420 ,0x01B0 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_WP__USB_OTG1_ID =IOMUX_PAD (0x0420 ,0x01B0 ,4 ,0x0734 ,2 ,0 ), +MX7D_PAD_SD2_WP__GPIO5_IO10 =IOMUX_PAD (0x0420 ,0x01B0 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 =IOMUX_PAD (0x0420 ,0x01B0 ,6 ,0x06DC ,2 ,0 ), + +MX7D_PAD_SD2_RESET_B__SD2_RESET_B =IOMUX_PAD (0x0424 ,0x01B4 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_RESET_B__SAI2_MCLK =IOMUX_PAD (0x0424 ,0x01B4 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_RESET_B__SD2_RESET =IOMUX_PAD (0x0424 ,0x01B4 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_RESET_B__ECSPI3_RDY =IOMUX_PAD (0x0424 ,0x01B4 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_RESET_B__USB_OTG2_ID =IOMUX_PAD (0x0424 ,0x01B4 ,4 ,0x0730 ,2 ,0 ), +MX7D_PAD_SD2_RESET_B__GPIO5_IO11 =IOMUX_PAD (0x0424 ,0x01B4 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD2_CLK__SD2_CLK =IOMUX_PAD (0x0428 ,0x01B8 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_CLK__SAI2_RX_SYNC =IOMUX_PAD (0x0428 ,0x01B8 ,1 ,0x06B8 ,0 ,0 ), +MX7D_PAD_SD2_CLK__MQS_RIGHT =IOMUX_PAD (0x0428 ,0x01B8 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_CLK__GPT4_CLK =IOMUX_PAD (0x0428 ,0x01B8 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_CLK__GPIO5_IO12 =IOMUX_PAD (0x0428 ,0x01B8 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD2_CMD__SD2_CMD =IOMUX_PAD (0x042C ,0x01BC ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_CMD__SAI2_RX_BCLK =IOMUX_PAD (0x042C ,0x01BC ,1 ,0x06B0 ,0 ,0 ), +MX7D_PAD_SD2_CMD__MQS_LEFT =IOMUX_PAD (0x042C ,0x01BC ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 =IOMUX_PAD (0x042C ,0x01BC ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD =IOMUX_PAD (0x042C ,0x01BC ,4 ,0x06EC ,1 ,0 ), +MX7D_PAD_SD2_CMD__GPIO5_IO13 =IOMUX_PAD (0x042C ,0x01BC ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD2_DATA0__SD2_DATA0 =IOMUX_PAD (0x0430 ,0x01C0 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 =IOMUX_PAD (0x0430 ,0x01C0 ,1 ,0x06B4 ,0 ,0 ), +MX7D_PAD_SD2_DATA0__UART4_DCE_RX =IOMUX_PAD (0x0430 ,0x01C0 ,2 ,0x070C ,2 ,0 ), +MX7D_PAD_SD2_DATA0__UART4_DTE_TX =IOMUX_PAD (0x0430 ,0x01C0 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 =IOMUX_PAD (0x0430 ,0x01C0 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK =IOMUX_PAD (0x0430 ,0x01C0 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA0__GPIO5_IO14 =IOMUX_PAD (0x0430 ,0x01C0 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD2_DATA1__SD2_DATA1 =IOMUX_PAD (0x0434 ,0x01C4 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK =IOMUX_PAD (0x0434 ,0x01C4 ,1 ,0x06BC ,0 ,0 ), +MX7D_PAD_SD2_DATA1__UART4_DCE_TX =IOMUX_PAD (0x0434 ,0x01C4 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA1__UART4_DTE_RX =IOMUX_PAD (0x0434 ,0x01C4 ,2 ,0x070C ,3 ,0 ), +MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 =IOMUX_PAD (0x0434 ,0x01C4 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B =IOMUX_PAD (0x0434 ,0x01C4 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA1__GPIO5_IO15 =IOMUX_PAD (0x0434 ,0x01C4 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD2_DATA2__SD2_DATA2 =IOMUX_PAD (0x0438 ,0x01C8 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC =IOMUX_PAD (0x0438 ,0x01C8 ,1 ,0x06C0 ,0 ,0 ), +MX7D_PAD_SD2_DATA2__UART4_DCE_CTS =IOMUX_PAD (0x0438 ,0x01C8 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA2__UART4_DTE_RTS =IOMUX_PAD (0x0438 ,0x01C8 ,2 ,0x0708 ,2 ,0 ), +MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 =IOMUX_PAD (0x0438 ,0x01C8 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN =IOMUX_PAD (0x0438 ,0x01C8 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA2__GPIO5_IO16 =IOMUX_PAD (0x0438 ,0x01C8 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD2_DATA3__SD2_DATA3 =IOMUX_PAD (0x043C ,0x01CC ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 =IOMUX_PAD (0x043C ,0x01CC ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA3__UART4_DCE_RTS =IOMUX_PAD (0x043C ,0x01CC ,2 ,0x0708 ,3 ,0 ), +MX7D_PAD_SD2_DATA3__UART4_DTE_CTS =IOMUX_PAD (0x043C ,0x01CC ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 =IOMUX_PAD (0x043C ,0x01CC ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD =IOMUX_PAD (0x043C ,0x01CC ,4 ,0x06E8 ,1 ,0 ), +MX7D_PAD_SD2_DATA3__GPIO5_IO17 =IOMUX_PAD (0x043C ,0x01CC ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD3_CLK__SD3_CLK =IOMUX_PAD (0x0440 ,0x01D0 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_CLK__NAND_CLE =IOMUX_PAD (0x0440 ,0x01D0 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_CLK__ECSPI4_MISO =IOMUX_PAD (0x0440 ,0x01D0 ,2 ,0x0558 ,2 ,0 ), +MX7D_PAD_SD3_CLK__SAI3_RX_SYNC =IOMUX_PAD (0x0440 ,0x01D0 ,3 ,0x06CC ,2 ,0 ), +MX7D_PAD_SD3_CLK__GPT3_CLK =IOMUX_PAD (0x0440 ,0x01D0 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_CLK__GPIO6_IO0 =IOMUX_PAD (0x0440 ,0x01D0 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD3_CMD__SD3_CMD =IOMUX_PAD (0x0444 ,0x01D4 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_CMD__NAND_ALE =IOMUX_PAD (0x0444 ,0x01D4 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_CMD__ECSPI4_MOSI =IOMUX_PAD (0x0444 ,0x01D4 ,2 ,0x055C ,2 ,0 ), +MX7D_PAD_SD3_CMD__SAI3_RX_BCLK =IOMUX_PAD (0x0444 ,0x01D4 ,3 ,0x06C4 ,2 ,0 ), +MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 =IOMUX_PAD (0x0444 ,0x01D4 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_CMD__GPIO6_IO1 =IOMUX_PAD (0x0444 ,0x01D4 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD3_DATA0__SD3_DATA0 =IOMUX_PAD (0x0448 ,0x01D8 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA0__NAND_DATA00 =IOMUX_PAD (0x0448 ,0x01D8 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA0__ECSPI4_SS0 =IOMUX_PAD (0x0448 ,0x01D8 ,2 ,0x0560 ,2 ,0 ), +MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 =IOMUX_PAD (0x0448 ,0x01D8 ,3 ,0x06C8 ,2 ,0 ), +MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 =IOMUX_PAD (0x0448 ,0x01D8 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA0__GPIO6_IO2 =IOMUX_PAD (0x0448 ,0x01D8 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD3_DATA1__SD3_DATA1 =IOMUX_PAD (0x044C ,0x01DC ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA1__NAND_DATA01 =IOMUX_PAD (0x044C ,0x01DC ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA1__ECSPI4_SCLK =IOMUX_PAD (0x044C ,0x01DC ,2 ,0x0554 ,2 ,0 ), +MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK =IOMUX_PAD (0x044C ,0x01DC ,3 ,0x06D0 ,2 ,0 ), +MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 =IOMUX_PAD (0x044C ,0x01DC ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA1__GPIO6_IO3 =IOMUX_PAD (0x044C ,0x01DC ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD3_DATA2__SD3_DATA2 =IOMUX_PAD (0x0450 ,0x01E0 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA2__NAND_DATA02 =IOMUX_PAD (0x0450 ,0x01E0 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA2__I2C3_SDA =IOMUX_PAD (0x0450 ,0x01E0 ,IOMUX_CONFIG_SION |2 ,0x05E8 ,3 ,0 ), +MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC =IOMUX_PAD (0x0450 ,0x01E0 ,3 ,0x06D4 ,2 ,0 ), +MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 =IOMUX_PAD (0x0450 ,0x01E0 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA2__GPIO6_IO4 =IOMUX_PAD (0x0450 ,0x01E0 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD3_DATA3__SD3_DATA3 =IOMUX_PAD (0x0454 ,0x01E4 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA3__NAND_DATA03 =IOMUX_PAD (0x0454 ,0x01E4 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA3__I2C3_SCL =IOMUX_PAD (0x0454 ,0x01E4 ,IOMUX_CONFIG_SION |2 ,0x05E4 ,3 ,0 ), +MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 =IOMUX_PAD (0x0454 ,0x01E4 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 =IOMUX_PAD (0x0454 ,0x01E4 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA3__GPIO6_IO5 =IOMUX_PAD (0x0454 ,0x01E4 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD3_DATA4__SD3_DATA4 =IOMUX_PAD (0x0458 ,0x01E8 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA4__NAND_DATA04 =IOMUX_PAD (0x0458 ,0x01E8 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA4__UART3_DCE_RX =IOMUX_PAD (0x0458 ,0x01E8 ,3 ,0x0704 ,4 ,0 ), +MX7D_PAD_SD3_DATA4__UART3_DTE_TX =IOMUX_PAD (0x0458 ,0x01E8 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA4__FLEXCAN2_RX =IOMUX_PAD (0x0458 ,0x01E8 ,4 ,0x04E0 ,2 ,0 ), +MX7D_PAD_SD3_DATA4__GPIO6_IO6 =IOMUX_PAD (0x0458 ,0x01E8 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD3_DATA5__SD3_DATA5 =IOMUX_PAD (0x045C ,0x01EC ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA5__NAND_DATA05 =IOMUX_PAD (0x045C ,0x01EC ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA5__UART3_DCE_TX =IOMUX_PAD (0x045C ,0x01EC ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA5__UART3_DTE_RX =IOMUX_PAD (0x045C ,0x01EC ,3 ,0x0704 ,5 ,0 ), +MX7D_PAD_SD3_DATA5__FLEXCAN1_TX =IOMUX_PAD (0x045C ,0x01EC ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA5__GPIO6_IO7 =IOMUX_PAD (0x045C ,0x01EC ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD3_DATA6__SD3_DATA6 =IOMUX_PAD (0x0460 ,0x01F0 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA6__NAND_DATA06 =IOMUX_PAD (0x0460 ,0x01F0 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA6__SD3_WP =IOMUX_PAD (0x0460 ,0x01F0 ,2 ,0x073C ,2 ,0 ), +MX7D_PAD_SD3_DATA6__UART3_DCE_RTS =IOMUX_PAD (0x0460 ,0x01F0 ,3 ,0x0700 ,4 ,0 ), +MX7D_PAD_SD3_DATA6__UART3_DTE_CTS =IOMUX_PAD (0x0460 ,0x01F0 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA6__FLEXCAN2_TX =IOMUX_PAD (0x0460 ,0x01F0 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA6__GPIO6_IO8 =IOMUX_PAD (0x0460 ,0x01F0 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD3_DATA7__SD3_DATA7 =IOMUX_PAD (0x0464 ,0x01F4 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA7__NAND_DATA07 =IOMUX_PAD (0x0464 ,0x01F4 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA7__SD3_CD_B =IOMUX_PAD (0x0464 ,0x01F4 ,2 ,0x0738 ,2 ,0 ), +MX7D_PAD_SD3_DATA7__UART3_DCE_CTS =IOMUX_PAD (0x0464 ,0x01F4 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_DATA7__UART3_DTE_RTS =IOMUX_PAD (0x0464 ,0x01F4 ,3 ,0x0700 ,5 ,0 ), +MX7D_PAD_SD3_DATA7__FLEXCAN1_RX =IOMUX_PAD (0x0464 ,0x01F4 ,4 ,0x04DC ,2 ,0 ), +MX7D_PAD_SD3_DATA7__GPIO6_IO9 =IOMUX_PAD (0x0464 ,0x01F4 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD3_STROBE__SD3_STROBE =IOMUX_PAD (0x0468 ,0x01F8 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_STROBE__NAND_RE_B =IOMUX_PAD (0x0468 ,0x01F8 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_STROBE__GPIO6_IO10 =IOMUX_PAD (0x0468 ,0x01F8 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SD3_RESET_B__SD3_RESET_B =IOMUX_PAD (0x046C ,0x01FC ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_RESET_B__NAND_WE_B =IOMUX_PAD (0x046C ,0x01FC ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_RESET_B__SD3_RESET =IOMUX_PAD (0x046C ,0x01FC ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_RESET_B__SAI3_MCLK =IOMUX_PAD (0x046C ,0x01FC ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SD3_RESET_B__GPIO6_IO11 =IOMUX_PAD (0x046C ,0x01FC ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 =IOMUX_PAD (0x0470 ,0x0200 ,0 ,0x06A0 ,0 ,0 ), +MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B =IOMUX_PAD (0x0470 ,0x0200 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX =IOMUX_PAD (0x0470 ,0x0200 ,2 ,0x0714 ,2 ,0 ), +MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX =IOMUX_PAD (0x0470 ,0x0200 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX =IOMUX_PAD (0x0470 ,0x0200 ,3 ,0x04DC ,3 ,0 ), +MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD =IOMUX_PAD (0x0470 ,0x0200 ,4 ,0x06E4 ,1 ,0 ), +MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 =IOMUX_PAD (0x0470 ,0x0200 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET =IOMUX_PAD (0x0470 ,0x0200 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK =IOMUX_PAD (0x0474 ,0x0204 ,0 ,0x06A8 ,0 ,0 ), +MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B =IOMUX_PAD (0x0474 ,0x0204 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX =IOMUX_PAD (0x0474 ,0x0204 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX =IOMUX_PAD (0x0474 ,0x0204 ,2 ,0x0714 ,3 ,0 ), +MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX =IOMUX_PAD (0x0474 ,0x0204 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK =IOMUX_PAD (0x0474 ,0x0204 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 =IOMUX_PAD (0x0474 ,0x0204 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET =IOMUX_PAD (0x0474 ,0x0204 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC =IOMUX_PAD (0x0478 ,0x0208 ,0 ,0x06AC ,0 ,0 ), +MX7D_PAD_SAI1_TX_SYNC__NAND_DQS =IOMUX_PAD (0x0478 ,0x0208 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS =IOMUX_PAD (0x0478 ,0x0208 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS =IOMUX_PAD (0x0478 ,0x0208 ,2 ,0x0710 ,2 ,0 ), +MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX =IOMUX_PAD (0x0478 ,0x0208 ,3 ,0x04E0 ,3 ,0 ), +MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B =IOMUX_PAD (0x0478 ,0x0208 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 =IOMUX_PAD (0x0478 ,0x0208 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT =IOMUX_PAD (0x0478 ,0x0208 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 =IOMUX_PAD (0x047C ,0x020C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_DATA__NAND_READY_B =IOMUX_PAD (0x047C ,0x020C ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS =IOMUX_PAD (0x047C ,0x020C ,2 ,0x0710 ,3 ,0 ), +MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS =IOMUX_PAD (0x047C ,0x020C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX =IOMUX_PAD (0x047C ,0x020C ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN =IOMUX_PAD (0x047C ,0x020C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 =IOMUX_PAD (0x047C ,0x020C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET =IOMUX_PAD (0x047C ,0x020C ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC =IOMUX_PAD (0x0480 ,0x0210 ,0 ,0x06A4 ,0 ,0 ), +MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B =IOMUX_PAD (0x0480 ,0x0210 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC =IOMUX_PAD (0x0480 ,0x0210 ,2 ,0x06B8 ,1 ,0 ), +MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL =IOMUX_PAD (0x0480 ,0x0210 ,IOMUX_CONFIG_SION |3 ,0x05EC ,3 ,0 ), +MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD =IOMUX_PAD (0x0480 ,0x0210 ,4 ,0x06E0 ,1 ,0 ), +MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 =IOMUX_PAD (0x0480 ,0x0210 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT =IOMUX_PAD (0x0480 ,0x0210 ,6 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 =IOMUX_PAD (0x0480 ,0x0210 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK =IOMUX_PAD (0x0484 ,0x0214 ,0 ,0x069C ,0 ,0 ), +MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B =IOMUX_PAD (0x0484 ,0x0214 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK =IOMUX_PAD (0x0484 ,0x0214 ,2 ,0x06B0 ,1 ,0 ), +MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA =IOMUX_PAD (0x0484 ,0x0214 ,IOMUX_CONFIG_SION |3 ,0x05F0 ,3 ,0 ), +MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA =IOMUX_PAD (0x0484 ,0x0214 ,4 ,0x05CC ,1 ,0 ), +MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 =IOMUX_PAD (0x0484 ,0x0214 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT =IOMUX_PAD (0x0484 ,0x0214 ,6 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 =IOMUX_PAD (0x0484 ,0x0214 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SAI1_MCLK__SAI1_MCLK =IOMUX_PAD (0x0488 ,0x0218 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_MCLK__NAND_WP_B =IOMUX_PAD (0x0488 ,0x0218 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_MCLK__SAI2_MCLK =IOMUX_PAD (0x0488 ,0x0218 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY =IOMUX_PAD (0x0488 ,0x0218 ,3 ,0x04F4 ,3 ,0 ), +MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB =IOMUX_PAD (0x0488 ,0x0218 ,4 ,0x05D0 ,1 ,0 ), +MX7D_PAD_SAI1_MCLK__GPIO6_IO18 =IOMUX_PAD (0x0488 ,0x0218 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK =IOMUX_PAD (0x0488 ,0x0218 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC =IOMUX_PAD (0x048C ,0x021C ,0 ,0x06C0 ,1 ,0 ), +MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO =IOMUX_PAD (0x048C ,0x021C ,1 ,0x0548 ,1 ,0 ), +MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX =IOMUX_PAD (0x048C ,0x021C ,2 ,0x070C ,4 ,0 ), +MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX =IOMUX_PAD (0x048C ,0x021C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS =IOMUX_PAD (0x048C ,0x021C ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS =IOMUX_PAD (0x048C ,0x021C ,3 ,0x06F0 ,0 ,0 ), +MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 =IOMUX_PAD (0x048C ,0x021C ,4 ,0x05BC ,1 ,0 ), +MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 =IOMUX_PAD (0x048C ,0x021C ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK =IOMUX_PAD (0x0490 ,0x0220 ,0 ,0x06BC ,1 ,0 ), +MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI =IOMUX_PAD (0x0490 ,0x0220 ,1 ,0x054C ,1 ,0 ), +MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX =IOMUX_PAD (0x0490 ,0x0220 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX =IOMUX_PAD (0x0490 ,0x0220 ,2 ,0x070C ,5 ,0 ), +MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS =IOMUX_PAD (0x0490 ,0x0220 ,3 ,0x06F0 ,1 ,0 ), +MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS =IOMUX_PAD (0x0490 ,0x0220 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 =IOMUX_PAD (0x0490 ,0x0220 ,4 ,0x05C0 ,1 ,0 ), +MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 =IOMUX_PAD (0x0490 ,0x0220 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 =IOMUX_PAD (0x0494 ,0x0224 ,0 ,0x06B4 ,1 ,0 ), +MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK =IOMUX_PAD (0x0494 ,0x0224 ,1 ,0x0544 ,1 ,0 ), +MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS =IOMUX_PAD (0x0494 ,0x0224 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS =IOMUX_PAD (0x0494 ,0x0224 ,2 ,0x0708 ,4 ,0 ), +MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS =IOMUX_PAD (0x0494 ,0x0224 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS =IOMUX_PAD (0x0494 ,0x0224 ,3 ,0x06F8 ,2 ,0 ), +MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 =IOMUX_PAD (0x0494 ,0x0224 ,4 ,0x05C4 ,1 ,0 ), +MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 =IOMUX_PAD (0x0494 ,0x0224 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI2_RX_DATA__KPP_COL7 =IOMUX_PAD (0x0494 ,0x0224 ,6 ,0x0610 ,1 ,0 ), + +MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 =IOMUX_PAD (0x0498 ,0x0228 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 =IOMUX_PAD (0x0498 ,0x0228 ,1 ,0x0550 ,1 ,0 ), +MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS =IOMUX_PAD (0x0498 ,0x0228 ,2 ,0x0708 ,5 ,0 ), +MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS =IOMUX_PAD (0x0498 ,0x0228 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS =IOMUX_PAD (0x0498 ,0x0228 ,3 ,0x06F8 ,3 ,0 ), +MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS =IOMUX_PAD (0x0498 ,0x0228 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 =IOMUX_PAD (0x0498 ,0x0228 ,4 ,0x05C8 ,1 ,0 ), +MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 =IOMUX_PAD (0x0498 ,0x0228 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 =IOMUX_PAD (0x0498 ,0x0228 ,6 ,0x0630 ,1 ,0 ), + +MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 =IOMUX_PAD (0x049C ,0x022C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT =IOMUX_PAD (0x049C ,0x022C ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL =IOMUX_PAD (0x049C ,0x022C ,IOMUX_CONFIG_SION |2 ,0x05E4 ,4 ,0 ), +MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS =IOMUX_PAD (0x049C ,0x022C ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS =IOMUX_PAD (0x049C ,0x022C ,3 ,0x06F0 ,2 ,0 ), +MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 =IOMUX_PAD (0x049C ,0x022C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 =IOMUX_PAD (0x049C ,0x022C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 =IOMUX_PAD (0x049C ,0x022C ,6 ,0x0620 ,1 ,0 ), + +MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 =IOMUX_PAD (0x04A0 ,0x0230 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT =IOMUX_PAD (0x04A0 ,0x0230 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA =IOMUX_PAD (0x04A0 ,0x0230 ,IOMUX_CONFIG_SION |2 ,0x05E8 ,4 ,0 ), +MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS =IOMUX_PAD (0x04A0 ,0x0230 ,3 ,0x06F0 ,3 ,0 ), +MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS =IOMUX_PAD (0x04A0 ,0x0230 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 =IOMUX_PAD (0x04A0 ,0x0230 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 =IOMUX_PAD (0x04A0 ,0x0230 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 =IOMUX_PAD (0x04A0 ,0x0230 ,6 ,0x0600 ,1 ,0 ), + +MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 =IOMUX_PAD (0x04A4 ,0x0234 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX =IOMUX_PAD (0x04A4 ,0x0234 ,1 ,0x04DC ,4 ,0 ), +MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK =IOMUX_PAD (0x04A4 ,0x0234 ,2 ,0x0534 ,1 ,0 ), +MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX =IOMUX_PAD (0x04A4 ,0x0234 ,3 ,0x06F4 ,2 ,0 ), +MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX =IOMUX_PAD (0x04A4 ,0x0234 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 =IOMUX_PAD (0x04A4 ,0x0234 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 =IOMUX_PAD (0x04A4 ,0x0234 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 =IOMUX_PAD (0x04A4 ,0x0234 ,6 ,0x061C ,1 ,0 ), + +MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 =IOMUX_PAD (0x04A8 ,0x0238 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX =IOMUX_PAD (0x04A8 ,0x0238 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI =IOMUX_PAD (0x04A8 ,0x0238 ,2 ,0x053C ,1 ,0 ), +MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX =IOMUX_PAD (0x04A8 ,0x0238 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX =IOMUX_PAD (0x04A8 ,0x0238 ,3 ,0x06F4 ,3 ,0 ), +MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 =IOMUX_PAD (0x04A8 ,0x0238 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 =IOMUX_PAD (0x04A8 ,0x0238 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 =IOMUX_PAD (0x04A8 ,0x0238 ,6 ,0x05FC ,1 ,0 ), + +MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL =IOMUX_PAD (0x04AC ,0x023C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 =IOMUX_PAD (0x04AC ,0x023C ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 =IOMUX_PAD (0x04AC ,0x023C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 =IOMUX_PAD (0x04AC ,0x023C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 =IOMUX_PAD (0x04AC ,0x023C ,6 ,0x0618 ,1 ,0 ), + +MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC =IOMUX_PAD (0x04B0 ,0x0240 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER =IOMUX_PAD (0x04B0 ,0x0240 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 =IOMUX_PAD (0x04B0 ,0x0240 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 =IOMUX_PAD (0x04B0 ,0x0240 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 =IOMUX_PAD (0x04B0 ,0x0240 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 =IOMUX_PAD (0x04B0 ,0x0240 ,6 ,0x0000 ,0 ,0 ), + +MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 =IOMUX_PAD (0x04B4 ,0x0244 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT =IOMUX_PAD (0x04B4 ,0x0244 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 =IOMUX_PAD (0x04B4 ,0x0244 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 =IOMUX_PAD (0x04B4 ,0x0244 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 =IOMUX_PAD (0x04B4 ,0x0244 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 =IOMUX_PAD (0x04B4 ,0x0244 ,6 ,0x0614 ,1 ,0 ), + +MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 =IOMUX_PAD (0x04B8 ,0x0248 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT =IOMUX_PAD (0x04B8 ,0x0248 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY =IOMUX_PAD (0x04B8 ,0x0248 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 =IOMUX_PAD (0x04B8 ,0x0248 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 =IOMUX_PAD (0x04B8 ,0x0248 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 =IOMUX_PAD (0x04B8 ,0x0248 ,6 ,0x05F4 ,1 ,0 ), + +MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 =IOMUX_PAD (0x04BC ,0x024C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX =IOMUX_PAD (0x04BC ,0x024C ,1 ,0x04E0 ,4 ,0 ), +MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO =IOMUX_PAD (0x04BC ,0x024C ,2 ,0x0538 ,1 ,0 ), +MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL =IOMUX_PAD (0x04BC ,0x024C ,IOMUX_CONFIG_SION |3 ,0x05EC ,4 ,0 ), +MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED =IOMUX_PAD (0x04BC ,0x024C ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 =IOMUX_PAD (0x04BC ,0x024C ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 =IOMUX_PAD (0x04C0 ,0x0250 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX =IOMUX_PAD (0x04C0 ,0x0250 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 =IOMUX_PAD (0x04C0 ,0x0250 ,2 ,0x0540 ,1 ,0 ), +MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA =IOMUX_PAD (0x04C0 ,0x0250 ,IOMUX_CONFIG_SION |3 ,0x05F0 ,4 ,0 ), +MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ =IOMUX_PAD (0x04C0 ,0x0250 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 =IOMUX_PAD (0x04C0 ,0x0250 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS =IOMUX_PAD (0x04C0 ,0x0250 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL =IOMUX_PAD (0x04C4 ,0x0254 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC =IOMUX_PAD (0x04C4 ,0x0254 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 =IOMUX_PAD (0x04C4 ,0x0254 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 =IOMUX_PAD (0x04C4 ,0x0254 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 =IOMUX_PAD (0x04C4 ,0x0254 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC =IOMUX_PAD (0x04C8 ,0x0258 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER =IOMUX_PAD (0x04C8 ,0x0258 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK =IOMUX_PAD (0x04C8 ,0x0258 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 =IOMUX_PAD (0x04C8 ,0x0258 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 =IOMUX_PAD (0x04C8 ,0x0258 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 =IOMUX_PAD (0x04C8 ,0x0258 ,5 ,0x0000 ,0 ,0 ), + +MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK =IOMUX_PAD (0x04CC ,0x025C ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 =IOMUX_PAD (0x04CC ,0x025C ,1 ,0x0564 ,2 ,0 ), +MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 =IOMUX_PAD (0x04CC ,0x025C ,2 ,0x06A0 ,1 ,0 ), +MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 =IOMUX_PAD (0x04CC ,0x025C ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ =IOMUX_PAD (0x04CC ,0x025C ,4 ,0x057C ,1 ,0 ), +MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 =IOMUX_PAD (0x04CC ,0x025C ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 =IOMUX_PAD (0x04CC ,0x025C ,6 ,0x04E4 ,2 ,0 ), +MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 =IOMUX_PAD (0x04CC ,0x025C ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK =IOMUX_PAD (0x04D0 ,0x0260 ,0 ,0x056C ,0 ,0 ), +MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B =IOMUX_PAD (0x04D0 ,0x0260 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK =IOMUX_PAD (0x04D0 ,0x0260 ,2 ,0x06A8 ,1 ,0 ), +MX7D_PAD_ENET1_RX_CLK__GPT2_CLK =IOMUX_PAD (0x04D0 ,0x0260 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE =IOMUX_PAD (0x04D0 ,0x0260 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 =IOMUX_PAD (0x04D0 ,0x0260 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 =IOMUX_PAD (0x04D0 ,0x0260 ,6 ,0x04E8 ,2 ,0 ), +MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 =IOMUX_PAD (0x04D0 ,0x0260 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_ENET1_CRS__ENET1_CRS =IOMUX_PAD (0x04D4 ,0x0264 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB =IOMUX_PAD (0x04D4 ,0x0264 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC =IOMUX_PAD (0x04D4 ,0x0264 ,2 ,0x06AC ,1 ,0 ), +MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 =IOMUX_PAD (0x04D4 ,0x0264 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 =IOMUX_PAD (0x04D4 ,0x0264 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_CRS__GPIO7_IO14 =IOMUX_PAD (0x04D4 ,0x0264 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 =IOMUX_PAD (0x04D4 ,0x0264 ,6 ,0x04EC ,2 ,0 ), +MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 =IOMUX_PAD (0x04D4 ,0x0264 ,7 ,0x0000 ,0 ,0 ), + +MX7D_PAD_ENET1_COL__ENET1_COL =IOMUX_PAD (0x04D8 ,0x0268 ,0 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY =IOMUX_PAD (0x04D8 ,0x0268 ,1 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 =IOMUX_PAD (0x04D8 ,0x0268 ,2 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 =IOMUX_PAD (0x04D8 ,0x0268 ,3 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 =IOMUX_PAD (0x04D8 ,0x0268 ,4 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_COL__GPIO7_IO15 =IOMUX_PAD (0x04D8 ,0x0268 ,5 ,0x0000 ,0 ,0 ), +MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 =IOMUX_PAD (0x04D8 ,0x0268 ,6 ,0x04F0 ,2 ,0 ), +MX7D_PAD_ENET1_COL__CSU_INT_DEB =IOMUX_PAD (0x04D8 ,0x0268 ,7 ,0x0000 ,0 ,0 ), +}; +#endif /* __ASM_ARCH_IMX7D_PINS_H__ */ arch/arm/include/asm/imx-common/iomux-v3.h +32
-0@@ -85,6 +85,36 @@ typedef u64 iomux_v3_cfg_t;#define NO_PAD_CTRL (1 << 17) +#ifdef CONFIG_MX7 + +#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000 +#define IOMUX_CONFIG_LPSR 0x8 +#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ + MUX_MODE_SHIFT) + +#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0) +#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0) +#define PAD_CTL_DSE_1P8V_70OHM (0x2<<0) +#define PAD_CTL_DSE_1P8V_23OHM (0x3<<0) + +#define PAD_CTL_DSE_3P3V_196OHM (0x0<<0) +#define PAD_CTL_DSE_3P3V_49OHM (0x1<<0) +#define PAD_CTL_DSE_3P3V_98OHM (0x2<<0) +#define PAD_CTL_DSE_3P3V_32OHM (0x3<<0) + +#define PAD_CTL_SRE_FAST (0 << 2) +#define PAD_CTL_SRE_SLOW (0x1 << 2) + +#define PAD_CTL_HYS (0x1 << 3) +#define PAD_CTL_PUE (0x1 << 4) + +#define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) | PAD_CTL_PUE) + +#else +#ifdef CONFIG_MX6 #define PAD_CTL_HYS (1 << 16)@@ -167,6 +197,8 @@ typedef u64 iomux_v3_cfg_t;#define PAD_CTL_SRE_SLOW (0 << 0)#define PAD_CTL_SRE_FAST (1 << 0) +#endif +#define IOMUX_CONFIG_SION 0x10#define GPIO_PIN_MASK 0x1f
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================
Fabio Estevam
reviewerPATCH v4 2/13 imx: iomux-v3: add imx7d support for iomuxc
Hi Stefano,
Quoted 11 lines · Stefano Babic
I have a main question. For i.MX6, we could factorize (mainly thanks Tim's work) the major SOC variants, getting some important goals, as having a single u-boot image running on different variations of the same board.
This was reached deciding at run time which is the pin, its register and the value to be written - instead of fixing at build time.
Exceptions are the SOC that cannot be substitute by another one on the same board, because they are not pin compatible: for example, MX&SX.
Quoted 6 lines
Now you are introducing the new architecture for MX7, but it looks like you get rid of these improvements. It can be right or false, then my questions:
- has MX7 quite the same variations as MX6 ? I mean a qaud, dual and solo that are pin-to-pin compatible ?
No, mx7 is not pin compatible with the mx6 family.
Regards,
Fabio Estevam
PATCH v4 2/13 imx: iomux-v3: add imx7d support for iomuxc
Hi Fabio,
Quoted 15 lines · Fabio Estevam
Hi Stefano,
Quoted 11 lines · Stefano Babic
I have a main question. For i.MX6, we could factorize (mainly thanks Tim's work) the major SOC variants, getting some important goals, as having a single u-boot image running on different variations of the same board.
This was reached deciding at run time which is the pin, its register and the value to be written - instead of fixing at build time.
Exceptions are the SOC that cannot be substitute by another one on the same board, because they are not pin compatible: for example, MX&SX.
Quoted 9 lines
Quoted 6 lines
Now you are introducing the new architecture for MX7, but it looks like you get rid of these improvements. It can be right or false, then my questions:
- has MX7 quite the same variations as MX6 ? I mean a qaud, dual and solo that are pin-to-pin compatible ?
No, mx7 is not pin compatible with the mx6 family.
Thanks, got it.
Regards,
Stefano
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================
PATCH v4 3/13 imx: mxc_gpio: add support for imx7d SoC
In reply to Adrian Alonso* Add mxc_gpio support for imx7d SoC
* Use CONFIG_MX7 to extend mxc gpio driver support for imx7d
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Adrian Alonso <[email protected]>
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Resend
arch/arm/include/asm/arch-mx7/gpio.h | 12 ++++++++++++ drivers/gpio/mxc_gpio.c | 8 +++++--- 2 files changed, 17 insertions(+), 3 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx7/gpio.h
arch/arm/include/asm/arch-mx7/gpio.h new file +12 -0
@@ -0,0 +1,12 @@ +/* +* Copyright (C) 2015 Freescale Semiconductor, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ASM_ARCH_MX7_GPIO_H +#define __ASM_ARCH_MX7_GPIO_H + +#include <asm/imx-common/gpio.h> + +#endif /* __ASM_ARCH_MX7_GPIO_H */
drivers/gpio/mxc_gpio.c +5 -3
@@ -40,14 +40,16 @@ static unsigned long gpio_ports[] = { [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR,#if defined(CONFIG_MX25 ) || defined(CONFIG_MX27 ) || defined(CONFIG_MX51 ) || \ - defined(CONFIG_MX53 ) || defined(CONFIG_MX6 ) + defined(CONFIG_MX53 ) || defined(CONFIG_MX6 ) || \ + defined(CONFIG_MX7 ) [3] = GPIO4_BASE_ADDR,#endif -#if defined(CONFIG_MX27 ) || defined(CONFIG_MX53 ) || defined(CONFIG_MX6 ) +#if defined(CONFIG_MX27 ) || defined(CONFIG_MX53 ) || defined(CONFIG_MX6 ) || \ + defined(CONFIG_MX7 ) [4] = GPIO5_BASE_ADDR, [5] = GPIO6_BASE_ADDR,#endif -#if defined(CONFIG_MX53 ) || defined(CONFIG_MX6 ) +#if defined(CONFIG_MX53 ) || defined(CONFIG_MX6 ) || defined(CONFIG_MX7 ) [6] = GPIO7_BASE_ADDR,#endif };
Signature · 1 line
2.1.4
PATCH v4 4/13 imx: ocotp: mxc add i.MX7D support
In reply to Adrian Alonso* Ocotp of i.MX7D has different operation rule.
This patch is to add support for i.MX7D ocotp.
Signed-off-by Adrian Alonso <[email protected]>
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Ye.Li <[email protected]>
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Resend
drivers/misc/mxc_ocotp.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-)
drivers/misc/mxc_ocotp.c +73 -1
@@ -25,8 +25,21 @@#define BM_CTRL_ERROR 0x00000200#define BM_CTRL_BUSY 0x00000100#define BO_CTRL_ADDR 0 +#ifdef CONFIG_MX7 +#define BM_CTRL_ADDR 0x0000000f +#define BM_CTRL_RELOAD 0x00000400 +#else #define BM_CTRL_ADDR 0x0000007f - +#endif + +#ifdef CONFIG_MX7 +#define BO_TIMING_FSOURCE 12 +#define BM_TIMING_FSOURCE 0x0007f000 +#define BV_TIMING_FSOURCE_NS 1001 +#define BO_TIMING_PROG 0 +#define BM_TIMING_PROG 0x00000fff +#define BV_TIMING_PROG_US 10 +#else #define BO_TIMING_STROBE_READ 16#define BM_TIMING_STROBE_READ 0x003f0000#define BV_TIMING_STROBE_READ_NS 37
@@ -36,6 +49,7 @@#define BO_TIMING_STROBE_PROG 0#define BM_TIMING_STROBE_PROG 0x00000fff#define BV_TIMING_STROBE_PROG_US 10 +#endif #define BM_READ_CTRL_READ_FUSE 0x00000001
@@ -109,6 +123,25 @@ int fuse_read(u32 bank, u32 word, u32 *val)return finish_access (regs, __func__); } +#ifdef CONFIG_MX7 +static void set_timing (struct ocotp_regs *regs) +{ +u32 ipg_clk; +u32 fsource, prog; +u32 timing; + + ipg_clk =mxc_get_clock (MXC_IPG_CLK ); + + fsource =DIV_ROUND_UP ((ipg_clk /1000 ) *BV_TIMING_FSOURCE_NS , + +1000000 ) +1 ; + prog =DIV_ROUND_CLOSEST (ipg_clk *BV_TIMING_PROG_US ,1000000 ) +1 ; + + timing =BF (fsource,TIMING_FSOURCE ) |BF (prog,TIMING_PROG ); + +clrsetbits_le32 (®s->timing,BM_TIMING_FSOURCE |BM_TIMING_PROG , + timing); +} +#else static void set_timing (struct ocotp_regs *regs) {u32 ipg_clk;
@@ -130,12 +163,17 @@ static void set_timing(struct ocotp_regs *regs)clrsetbits_le32 (®s->timing,BM_TIMING_STROBE_READ |BM_TIMING_RELAX |BM_TIMING_STROBE_PROG , timing); } +#endif static void setup_direct_access (struct ocotp_regs *regs,u32 bank,u32 word,int write) {u32 wr_unlock = write ?BV_CTRL_WR_UNLOCK_KEY :0 ; +#ifdef CONFIG_MX7 +u32 addr = bank; +#else u32 addr = bank <<3 | word; +#endif set_timing (regs); clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
@@ -155,7 +193,11 @@ int fuse_sense(u32 bank, u32 word, u32 *val)setup_direct_access (regs, bank, word, false);writel (BM_READ_CTRL_READ_FUSE , ®s->read_ctrl);wait_busy (regs,1 ); +#ifdef CONFIG_MX7 + *val =readl ((®s->read_fuse_data0) + (word <<2 )); +#else *val =readl (®s->read_fuse_data); +#endif return finish_access (regs, __func__); }
@@ -176,8 +218,38 @@ int fuse_prog(u32 bank, u32 word, u32 val)return ret;setup_direct_access (regs, bank, word, true); +#ifdef CONFIG_MX7 +switch (word) { +case 0 : +writel (0 , ®s->data1); +writel (0 , ®s->data2); +writel (0 , ®s->data3); +writel (val, ®s->data0); +break ; +case 1 : +writel (val, ®s->data1); +writel (0 , ®s->data2); +writel (0 , ®s->data3); +writel (0 , ®s->data0); +break ; +case 2 : +writel (0 , ®s->data1); +writel (val, ®s->data2); +writel (0 , ®s->data3); +writel (0 , ®s->data0); +break ; +case 3 : +writel (0 , ®s->data1); +writel (0 , ®s->data2); +writel (val, ®s->data3); +writel (0 , ®s->data0); +break ; + } +wait_busy (regs,BV_TIMING_PROG_US ); +#else writel (val, ®s->data);wait_busy (regs,BV_TIMING_STROBE_PROG_US ); +#endif udelay (WRITE_POSTAMBLE_US );return finish_access (regs, __func__);
Signature · 1 line
2.1.4
PATCH v4 5/13 imx: mx7 dm thermal driver support
In reply to Adrian Alonso* Add thermal driver support for imx7 SoC read_cpu_temperature is SoC dependent
* Redefine config macro to support imx7 and imx6 SoC
Signed-off-by Adrian Alonso <[email protected]>
Signed-off-by Peng Fan <[email protected]>
---
Changes for V2:
- Rework patch so it can be applyed on top of patch
imx6: standardise OCOTP and fuse config to mx6_common
Changes for V3: Resend
Changes for V4: Resend
arch/arm/imx-common/cpu.c | 10 ++-- drivers/thermal/Makefile | 2 +- drivers/thermal/imx_thermal.c | 100 +++++++++++++++++++++++++++++++++++--- include/configs/embestmx6boards.h | 2 +- include/configs/gw_ventana.h | 2 +- include/configs/mx6cuboxi.h | 2 +- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/tbs2910.h | 2 +- 10 files changed, 108 insertions(+), 18 deletions(-)
arch/arm/imx-common/cpu.c +7 -3
@@ -148,14 +148,16 @@ int print_cpuinfo(void)u32 cpurev;__maybe_unused u32 max_freq; -#if defined(CONFIG_MX6 ) && defined(CONFIG_IMX6_THERMAL ) +#if defined(CONFIG_IMX_THERMAL )struct udevice *thermal_dev; -int cpu_tmp, minc, maxc, ret; +int cpu_tmp, ret;#endif cpurev =get_cpu_rev ();#if defined(CONFIG_MX6 ) +int minc, maxc; + printf("CPU: Freescale i.MX%s rev%d.%d", get_imx_type((cpurev & 0xFF000) >> 12), (cpurev & 0x000F0) >> 4,
@@ -175,7 +177,7 @@ int print_cpuinfo(void) mxc_get_clock(MXC_ARM_CLK) / 1000000);#endif -#if defined(CONFIG_MX6 ) && defined(CONFIG_IMX6_THERMAL ) +#if defined(CONFIG_MX6 ) && defined(CONFIG_IMX_THERMAL )puts ("CPU: " );switch (get_cpu_temp_grade (&minc, &maxc)) {case TEMP_AUTOMOTIVE :
@@ -192,6 +194,8 @@ int print_cpuinfo(void)break ; }printf ("(%dC to %dC)" , minc, maxc); +#endif +#if defined(CONFIG_IMX_THERMAL ) ret =uclass_get_device (UCLASS_THERMAL ,0 , &thermal_dev);if (!ret) { ret =thermal_get_temp (thermal_dev, &cpu_tmp);
drivers/thermal/Makefile +1 -1
@@ -6,4 +6,4 @@ # obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o -obj-$(CONFIG_IMX6_THERMAL) += imx_thermal.o +obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
drivers/thermal/imx_thermal.c +93 -7
133 lines not on this page · raw message
include/configs/embestmx6boards.h +1 -1
@@ -19,7 +19,7 @@#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
include/configs/gw_ventana.h +1 -1
@@ -57,7 +57,7 @@#define CONFIG_CMD_GPIO /* Thermal */ -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL /* Serial */ #define CONFIG_MXC_UART
include/configs/mx6cuboxi.h +1 -1
@@ -14,7 +14,7 @@#define CONFIG_SPL_MMC_SUPPORT #include "imx6_spl.h" -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)#define CONFIG_BOARD_EARLY_INIT_F
include/configs/mx6sabre_common.h +1 -1
@@ -11,7 +11,7 @@#include "mx6_common.h" -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
include/configs/mx6slevk.h +1 -1
@@ -190,6 +190,6 @@#define CONFIG_SYS_MMC_ENV_DEV 1/* SDHC2*/ #endif -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL #endif /* __CONFIG_H */
include/configs/mx6sxsabresd.h +1 -1
@@ -176,7 +176,7 @@#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1)#endif -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL #define CONFIG_CMD_TIME
include/configs/tbs2910.h +1 -1
@@ -21,7 +21,7 @@#define CONFIG_SYS_PROMPT "Matrix U-Boot> "#define CONFIG_SYS_HZ 1000 -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1
Signature · 1 line
2.1.4
PATCH v4 6/13 imx: system counter driver for imx7d and mx6ul
In reply to Adrian Alonso* The system counter driver for imx7d abd mx6ul, move this timer driver to imx-common and rename it as syscounter.c
For mx6ul and mx7, configurations are used for choose the GPT timer or system counter timer (default).
GPT timer: CONFIG_GPT_TIMER
System counter timer: CONFIG_SYSCOUNTER_TIMER
For mx6dqp GPT timer is the default setting.
Signed-off-by Adrian Alonso <[email protected]>
Signed-off-by Ye.Li <[email protected]>
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Resend
arch/arm/imx-common/syscounter.c | 126 +++++++++++++++++++++++++++ arch/arm/include/asm/imx-common/syscounter.h | 29 ++++++ include/configs/mx6_common.h | 1 + 3 files changed, 156 insertions(+) create mode 100644 arch/arm/imx-common/syscounter.c create mode 100644 arch/arm/include/asm/imx-common/syscounter.h
arch/arm/imx-common/syscounter.c new file +126 -0
@@ -0,0 +1,126 @@ +/* +* Copyright (C) 2014-2015 Freescale Semiconductor, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +* +* The file use ls102xa/timer.c as a reference. +*/ + +#include <common.h> +#include <asm/io.h> +#include <div64.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/syscounter.h> + +DECLARE_GLOBAL_DATA_PTR ; + +/* +* This function is intended for SHORT delays only. +* It will overflow at around 10 seconds @ 400MHz, +* or 20 seconds @ 200MHz. +*/ +unsigned long usec2ticks (unsigned long usec) +{ +ulong ticks; + +if (usec <1000 ) + ticks = ((usec * (get_tbclk ()/1000 )) +500 ) /1000 ; +else + ticks = ((usec /10 ) * (get_tbclk () /100000 )); + +return ticks; +} + +static inline unsigned long long tick_to_time (unsigned long long tick) +{ +unsigned long freq; + + asmvolatile ("mrc p15, 0, %0, c14, c0, 0" :"=r" (freq)); + + tick *=CONFIG_SYS_HZ ; +do_div (tick, freq); + +return tick; +} + +static inline unsigned long long us_to_tick (unsigned long long usec) +{ +unsigned long freq; + + asmvolatile ("mrc p15, 0, %0, c14, c0, 0" :"=r" (freq)); + + usec = usec * freq +999999 ; +do_div (usec,1000000 ); + +return usec; +} + +int timer_init (void ) +{ +struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR ; +unsigned long val, freq; + + freq =CONFIG_SC_TIMER_CLK ; + asm("mcr p15, 0, %0, c14, c0, 0" : :"r" (freq)); + +writel (freq, &sctr->cntfid0); + +/* Enable system counter */ + val =readl (&sctr->cntcr); + val &= ~(SC_CNTCR_FREQ0 |SC_CNTCR_FREQ1 ); + val |=SC_CNTCR_FREQ0 |SC_CNTCR_ENABLE |SC_CNTCR_HDBG ; +writel (val, &sctr->cntcr); + + gd->arch.tbl =0 ; + gd->arch.tbu =0 ; + +return 0 ; +} + +unsigned long long get_ticks (void ) +{ +unsigned long long now; + + asm("mrrc p15, 0, %Q0, %R0, c14" :"=r" (now)); + + gd->arch.tbl = (unsigned long )(now &0xffffffff ); + gd->arch.tbu = (unsigned long )(now >>32 ); + +return now; +} + +ulong get_timer_masked (void ) +{ +return tick_to_time (get_ticks ()); +} + +ulong get_timer (ulong base) +{ +return get_timer_masked () - base; +} + +void __udelay (unsigned long usec) +{ +unsigned long long tmp; +ulong tmo; + + tmo =us_to_tick (usec); + tmp =get_ticks () + tmo;/* get current timestamp */ + +while (get_ticks () < tmp)/* loop till event */ +/*NOP*/ ; +} + +/* +* This function is derived from PowerPC code (timebase clock frequency). +* On ARM it returns the number of timer ticks per second. +*/ +ulong get_tbclk (void ) +{ +unsigned long freq; + + asmvolatile ("mrc p15, 0, %0, c14, c0, 0" :"=r" (freq)); + +return freq; +}
arch/arm/include/asm/imx-common/syscounter.h new file +29 -0
@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2014-2015 Freescale Semiconductor, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef _ASM_ARCH_SYSTEM_COUNTER_H +#define _ASM_ARCH_SYSTEM_COUNTER_H + +/* System Counter */ +struct sctr_regs { +u32 cntcr; +u32 cntsr; +u32 cntcv1; +u32 cntcv2; +u32 resv1[4 ]; +u32 cntfid0; +u32 cntfid1; +u32 cntfid2; +u32 resv2[1001 ]; +u32 counterid[1 ]; +}; + +#define SC_CNTCR_ENABLE (1 << 0) +#define SC_CNTCR_HDBG (1 << 1) +#define SC_CNTCR_FREQ0 (1 << 8) +#define SC_CNTCR_FREQ1 (1 << 9) + +#endif
include/configs/mx6_common.h +1 -0
@@ -30,6 +30,7 @@#define CONFIG_MP #define CONFIG_MXC_GPT_HCLK +#define CONFIG_GPT_TIMER #define CONFIG_SYS_NO_FLASH
Signature · 1 line
2.1.4
PATCH v4 6/13 imx: system counter driver for imx7d and mx6ul
Hi Adrian,
Quoted 31 lines · Adrian Alonso
* The system counter driver for imx7d abd mx6ul, move this timer driver to imx-common and rename it as
syscounter.cFor mx6ul and mx7, configurations are used for choose the GPT timer or system counter timer (default).
GPT timer:
CONFIG_GPT_TIMER
System counter timer:CONFIG_SYSCOUNTER_TIMERFor mx6dqp GPT timer is the default setting.
Signed-off-by Adrian Alonso <[email protected]>Signed-off-by Ye.Li <[email protected]>---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Resendarch/arm/imx-common/syscounter.c | 126 +++++++++++++++++++++++++++ arch/arm/include/asm/imx-common/syscounter.h | 29 ++++++ include/configs/mx6_common.h | 1 + 3 files changed, 156 insertions(+)create mode 100644
arch/arm/imx-common/syscounter.ccreate mode 100644arch/arm/include/asm/imx-common/syscounter.harch/arm/imx-common/syscounter.c new file +0
-0
arch/arm/imx-common/syscounter.c line 2
Quoted 2 lines
arch/arm/imx-common/syscounter.c new file +2
-0@@ -0,0 +1,126 @@ +/* +* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
Don't want to play "license police", but the file is created in 2015, and the copyright says 2014-2015. Can you please check this out? Thanks.
Quoted 130 lines
arch/arm/imx-common/syscounter.c new file +124
-0+* +* SPDX-License-Identifier: GPL-2.0+ +* +* The file use ls102xa/timer.c as a reference. +*/ + +#include <common.h> +#include <asm/io.h> +#include <div64.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/syscounter.h> + +DECLARE_GLOBAL_DATA_PTR ; + +/* +* This function is intended for SHORT delays only. +* It will overflow at around 10 seconds @ 400MHz, +* or 20 seconds @ 200MHz. +*/ +unsigned long usec2ticks (unsigned long usec) +{ +ulong ticks; + +if (usec <1000 ) + ticks = ((usec * (get_tbclk ()/1000 )) +500 ) /1000 ; +else + ticks = ((usec /10 ) * (get_tbclk () /100000 )); + +return ticks; +} + +static inline unsigned long long tick_to_time (unsigned long long tick) +{ +unsigned long freq; + + asmvolatile ("mrc p15, 0, %0, c14, c0, 0" :"=r" (freq)); + + tick *=CONFIG_SYS_HZ ; +do_div (tick, freq); + +return tick; +} + +static inline unsigned long long us_to_tick (unsigned long long usec) +{ +unsigned long freq; + + asmvolatile ("mrc p15, 0, %0, c14, c0, 0" :"=r" (freq)); + + usec = usec * freq +999999 ; +do_div (usec,1000000 ); + +return usec; +} + +int timer_init (void ) +{ +struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR ; +unsigned long val, freq; + + freq =CONFIG_SC_TIMER_CLK ; + asm("mcr p15, 0, %0, c14, c0, 0" : :"r" (freq)); + +writel (freq, &sctr->cntfid0); + +/* Enable system counter */ + val =readl (&sctr->cntcr); + val &= ~(SC_CNTCR_FREQ0 |SC_CNTCR_FREQ1 ); + val |=SC_CNTCR_FREQ0 |SC_CNTCR_ENABLE |SC_CNTCR_HDBG ; +writel (val, &sctr->cntcr); + + gd->arch.tbl =0 ; + gd->arch.tbu =0 ; + +return 0 ; +} + +unsigned long long get_ticks (void ) +{ +unsigned long long now; + + asm("mrrc p15, 0, %Q0, %R0, c14" :"=r" (now)); + + gd->arch.tbl = (unsigned long )(now &0xffffffff ); + gd->arch.tbu = (unsigned long )(now >>32 ); + +return now; +} + +ulong get_timer_masked (void ) +{ +return tick_to_time (get_ticks ()); +} + +ulong get_timer (ulong base) +{ +return get_timer_masked () - base; +} + +void __udelay (unsigned long usec) +{ +unsigned long long tmp; +ulong tmo; + + tmo =us_to_tick (usec); + tmp =get_ticks () + tmo;/* get current timestamp */ + +while (get_ticks () < tmp)/* loop till event */ +/*NOP*/ ; +} + +/* +* This function is derived from PowerPC code (timebase clock frequency). +* On ARM it returns the number of timer ticks per second. +*/ +ulong get_tbclk (void ) +{ +unsigned long freq; + + asmvolatile ("mrc p15, 0, %0, c14, c0, 0" :"=r" (freq)); + +return freq; +}arch/arm/include/asm/imx-common/syscounter.h new file +0
-0
arch/arm/include/asm/imx-common/syscounter.h line 2
Quoted 2 lines
arch/arm/include/asm/imx-common/syscounter.h new file +2
-0@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
Same here.
Quoted 33 lines
arch/arm/include/asm/imx-common/syscounter.h new file +27
-0+* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef _ASM_ARCH_SYSTEM_COUNTER_H +#define _ASM_ARCH_SYSTEM_COUNTER_H + +/* System Counter */ +struct sctr_regs { +u32 cntcr; +u32 cntsr; +u32 cntcv1; +u32 cntcv2; +u32 resv1[4 ]; +u32 cntfid0; +u32 cntfid1; +u32 cntfid2; +u32 resv2[1001 ]; +u32 counterid[1 ]; +}; + +#define SC_CNTCR_ENABLE (1 << 0) +#define SC_CNTCR_HDBG (1 << 1) +#define SC_CNTCR_FREQ0 (1 << 8) +#define SC_CNTCR_FREQ1 (1 << 9) + +#endif include/configs/mx6_common.h +0
-0
include/configs/mx6_common.h line 36
Quoted 7 lines
include/configs/mx6_common.h +1
-0@@ -30,6 +30,7 @@#define CONFIG_MP #define CONFIG_MXC_GPT_HCLK +#define CONFIG_GPT_TIMER #define CONFIG_SYS_NO_FLASH
Kind regards,
Nikolay
PATCH v4 6/13 imx: system counter driver for imx7d and mx6ul
Hi Nikolay,
Quoted 37 lines
-----Original Message-----
From: Nikolay Dimitrov [mailto:picmaster at mail.bg]
Sent: Friday, July 31, 2015 7:41 AM
To: Alonso Lazcano Adrian-B38018
Cc: u-boot
Subject: Re: [U-Boot] [PATCH 06/13][v4] imx: system counter driver for imx7d and mx6ulHi Adrian,
Quoted 11 lines · Adrian Alonso
* The system counter driver for imx7d abd mx6ul, move this timer driver to imx-common and rename it as
syscounter.cFor mx6ul and mx7, configurations are used for choose the GPT timer or system counter timer (default).
GPT timer:
CONFIG_GPT_TIMER
System counter timer:CONFIG_SYSCOUNTER_TIMERFor mx6dqp GPT timer is the default setting.
Quoted 8 lines
Signed-off-by Adrian Alonso <[email protected]>Signed-off-by Ye.Li <[email protected]>---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Resendarch/arm/imx-common/syscounter.c | 126+++++++++++++++++++++++++++
Quoted 6 lines
arch/arm/include/asm/imx-common/syscounter.h | 29 ++++++ include/configs/mx6_common.h | 1 + 3 files changed, 156 insertions(+)create mode 100644
arch/arm/imx-common/syscounter.ccreate mode 100644arch/arm/include/asm/imx-common/syscounter.h
Quoted 12 lines
arch/arm/imx-common/syscounter.c line 2
Quoted 9 lines
arch/arm/imx-common/syscounter.c new file +2
-0@@ -0,0 +1,126 @@ +/* +* Copyright (C) 2014-2015 Freescale Semiconductor, Inc. Don't want to play "license police", but the file is created in 2015, and the copyright says 2014-2015. Can you please check this out? Thanks.
[Adrian] Thanks for pointing that, will be corrected.
Quoted 179 lines
Quoted 131 lines
arch/arm/imx-common/syscounter.c new file +123
-0+* +* SPDX-License-Identifier: GPL-2.0+ +* +* The file use ls102xa/timer.c as a reference. +*/ + +#include <common.h> +#include <asm/io.h> +#include <div64.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/syscounter.h> + +DECLARE_GLOBAL_DATA_PTR ; + +/* +* This function is intended for SHORT delays only. +* It will overflow at around 10 seconds @ 400MHz, +* or 20 seconds @ 200MHz. +*/ +unsigned long usec2ticks (unsigned long usec) { +ulong ticks; + +if (usec <1000 ) + ticks = ((usec * (get_tbclk ()/1000 )) +500 ) /1000 ; +else + ticks = ((usec /10 ) * (get_tbclk () /100000 )); + +return ticks; +} + +static inline unsigned long long tick_to_time (unsigned long long +tick) { +unsigned long freq; + + asmvolatile ("mrc p15, 0, %0, c14, c0, 0" :"=r" (freq)); + + tick *=CONFIG_SYS_HZ ; +do_div (tick, freq); + +return tick; +} + +static inline unsigned long long us_to_tick (unsigned long long usec) +{ +unsigned long freq; + + asmvolatile ("mrc p15, 0, %0, c14, c0, 0" :"=r" (freq)); + + usec = usec * freq +999999 ; +do_div (usec,1000000 ); + +return usec; +} + +int timer_init (void ) +{ +struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR ; +unsigned long val, freq; + + freq =CONFIG_SC_TIMER_CLK ; + asm("mcr p15, 0, %0, c14, c0, 0" : :"r" (freq)); + +writel (freq, &sctr->cntfid0); + +/* Enable system counter */ + val =readl (&sctr->cntcr); + val &= ~(SC_CNTCR_FREQ0 |SC_CNTCR_FREQ1 ); + val |=SC_CNTCR_FREQ0 |SC_CNTCR_ENABLE |SC_CNTCR_HDBG ; +writel (val, &sctr->cntcr); + + gd->arch.tbl =0 ; + gd->arch.tbu =0 ; + +return 0 ; +} + +unsigned long long get_ticks (void ) +{ +unsigned long long now; + + asm("mrrc p15, 0, %Q0, %R0, c14" :"=r" (now)); + + gd->arch.tbl = (unsigned long )(now &0xffffffff ); + gd->arch.tbu = (unsigned long )(now >>32 ); + +return now; +} + +ulong get_timer_masked (void ) +{ +return tick_to_time (get_ticks ()); +} + +ulong get_timer (ulong base) +{ +return get_timer_masked () - base; +} + +void __udelay (unsigned long usec) +{ +unsigned long long tmp; +ulong tmo; + + tmo =us_to_tick (usec); + tmp =get_ticks () + tmo;/* get current timestamp */ + +while (get_ticks () < tmp)/* loop till event */ +/*NOP*/ ; +} + +/* +* This function is derived from PowerPC code (timebase clock frequency). +* On ARM it returns the number of timer ticks per second. +*/ +ulong get_tbclk (void ) +{ +unsigned long freq; + + asmvolatile ("mrc p15, 0, %0, c14, c0, 0" :"=r" (freq)); + +return freq; +}arch/arm/include/asm/imx-common/syscounter.h new file +0
-0arch/arm/include/asm/imx-common/syscounter.h line 2
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arch/arm/include/asm/imx-common/syscounter.h new file +2
-0@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2014-2015 Freescale Semiconductor, Inc. Same here.
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arch/arm/include/asm/imx-common/syscounter.h new file +27
-0+* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef _ASM_ARCH_SYSTEM_COUNTER_H +#define _ASM_ARCH_SYSTEM_COUNTER_H + +/* System Counter */ +struct sctr_regs { +u32 cntcr; +u32 cntsr; +u32 cntcv1; +u32 cntcv2; +u32 resv1[4 ]; +u32 cntfid0; +u32 cntfid1; +u32 cntfid2; +u32 resv2[1001 ]; +u32 counterid[1 ]; +}; + +#define SC_CNTCR_ENABLE (1 << 0) +#define SC_CNTCR_HDBG (1 << 1) +#define SC_CNTCR_FREQ0 (1 << 8) +#define SC_CNTCR_FREQ1 (1 << 9) + +#endif (quoted diff) +0
-0
b/include/configs/mx6_common.hindex 54ab890..ed9f8fe 100644include/configs/mx6_common.h line 36
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include/configs/mx6_common.h +1
-0@@ -30,6 +30,7 @@#define CONFIG_MP #define CONFIG_MXC_GPT_HCLK +#define CONFIG_GPT_TIMER #define CONFIG_SYS_NO_FLASH Kind regards,
Nikolay
PATCH v4 7/13 imx: imx7d: initial arch level support
In reply to Adrian Alonso* Add system arch level header files
- imx-regs.h: iMX7D SoC system architecture registers
- crm_regs.h: Clock control module registers
- sys_proto.h: helper callback function for SoC setup
Signed-off-by Adrian Alonso <[email protected]>
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Ye.Li <[email protected]>
---
Changes for V2: Split patch to easier review process
- Add system arch register definitions Changes for V3: Resend
Changes for V4: Resend
arch/arm/include/asm/arch-mx7/crm_regs.h | 2813 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx7/imx-regs.h | 1303 +++++++++++++ arch/arm/include/asm/arch-mx7/sys_proto.h | 42 + 3 files changed, 4158 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx7/crm_regs.h create mode 100644 arch/arm/include/asm/arch-mx7/imx-regs.h create mode 100644 arch/arm/include/asm/arch-mx7/sys_proto.h
arch/arm/include/asm/arch-mx7/crm_regs.h new file +2813 -0
@@ -0,0 +1,2813 @@ +/* +* Copyright (C) 2015 Freescale Semiconductor, Inc. +* +* Author: +* Peng Fan <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ARCH_ARM_MACH_MX7_CCM_REGS_H__ +#define __ARCH_ARM_MACH_MX7_CCM_REGS_H__ + +#include <asm/arch/imx-regs.h> +#include <asm/io.h> + +#define CCM_GPR0_OFFSET 0x0 +#define CCM_OBSERVE0_OFFSET 0x0400 +#define CCM_SCTRL0_OFFSET 0x0800 +#define CCM_CCGR0_OFFSET 0x4000 +#define CCM_ROOT0_TARGET_OFFSET 0x8000 + +#ifndef __ASSEMBLY__ + +struct mxc_ccm_ccgr { +uint32_t ccgr; +uint32_t ccgr_set; +uint32_t ccgr_clr; +uint32_t ccgr_tog; +}; + +struct mxc_ccm_root_slice { +uint32_t target_root; +uint32_t target_root_set; +uint32_t target_root_clr; +uint32_t target_root_tog; +uint32_t reserved_0[4 ]; +uint32_t post; +uint32_t post_root_set; +uint32_t post_root_clr; +uint32_t post_root_tog; +uint32_t pre; +uint32_t pre_root_set; +uint32_t pre_root_clr; +uint32_t pre_root_tog; +uint32_t reserved_1[12 ]; +uint32_t access_ctrl; +uint32_t access_ctrl_root_set; +uint32_t access_ctrl_root_clr; +uint32_t access_ctrl_root_tog; +}; + +/** CCM - Peripheral register structure */ +struct mxc_ccm_reg { +uint32_t gpr0; +uint32_t gpr0_set; +uint32_t gpr0_clr; +uint32_t gpr0_tog; +uint32_t reserved_0[4092 ]; +struct mxc_ccm_ccgr ccgr_array[191 ];/* offset 0x4000 */ +uint32_t reserved_1[3332 ]; +struct mxc_ccm_root_slice root[121 ];/* offset 0x8000 */ + +}; + +struct mxc_ccm_anatop_reg { +uint32_t ctrl_24m;/* offset 0x0000 */ +uint32_t ctrl_24m_set; +uint32_t ctrl_24m_clr; +uint32_t ctrl_24m_tog; +uint32_t rcosc_config0;/* offset 0x0010 */ +uint32_t rcosc_config0_set; +uint32_t rcosc_config0_clr; +uint32_t rcosc_config0_tog; +uint32_t rcosc_config1;/* offset 0x0020 */ +uint32_t rcosc_config1_set; +uint32_t rcosc_config1_clr; +uint32_t rcosc_config1_tog; +uint32_t rcosc_config2;/* offset 0x0030 */ +uint32_t rcosc_config2_set; +uint32_t rcosc_config2_clr; +uint32_t rcosc_config2_tog; +uint8_t reserved_0[16 ]; +uint32_t osc_32k;/* offset 0x0050 */ +uint32_t osc_32k_set; +uint32_t osc_32k_clr; +uint32_t osc_32k_tog; +uint32_t pll_arm;/* offset 0x0060 */ +uint32_t pll_arm_set; +uint32_t pll_arm_clr; +uint32_t pll_arm_tog; +uint32_t pll_ddr;/* offset 0x0070 */ +uint32_t pll_ddr_set; +uint32_t pll_ddr_clr; +uint32_t pll_ddr_tog; +uint32_t pll_ddr_ss;/* offset 0x0080 */ +uint8_t reserved_1[12 ]; +uint32_t pll_ddr_num;/* offset 0x0090 */ +uint8_t reserved_2[12 ]; +uint32_t pll_ddr_denom;/* offset 0x00a0 */ +uint8_t reserved_3[12 ]; +uint32_t pll_480;/* offset 0x00b0 */ +uint32_t pll_480_set; +uint32_t pll_480_clr; +uint32_t pll_480_tog; +uint32_t pfd_480a;/* offset 0x00c0 */ +uint32_t pfd_480a_set; +uint32_t pfd_480a_clr; +uint32_t pfd_480a_tog; +uint32_t pfd_480b;/* offset 0x00d0 */ +uint32_t pfd_480b_set; +uint32_t pfd_480b_clr; +uint32_t pfd_480b_tog; +uint32_t pll_enet;/* offset 0x00e0 */ +uint32_t pll_enet_set; +uint32_t pll_enet_clr; +uint32_t pll_enet_tog; +uint32_t pll_audio;/* offset 0x00f0 */ +uint32_t pll_audio_set; +uint32_t pll_audio_clr; +uint32_t pll_audio_tog; +uint32_t pll_audio_ss;/* offset 0x0100 */ +uint8_t reserved_4[12 ]; +uint32_t pll_audio_num;/* offset 0x0110 */ +uint8_t reserved_5[12 ]; +uint32_t pll_audio_denom;/* offset 0x0120 */ +uint8_t reserved_6[12 ]; +uint32_t pll_video;/* offset 0x0130 */ +uint32_t pll_video_set; +uint32_t pll_video_clr; +uint32_t pll_video_tog; +uint32_t pll_video_ss;/* offset 0x0140 */ +uint8_t reserved_7[12 ]; +uint32_t pll_video_num;/* offset 0x0150 */ +uint8_t reserved_8[12 ]; +uint32_t pll_video_denom;/* offset 0x0160 */ +uint8_t reserved_9[12 ]; +uint32_t clk_misc0;/* offset 0x0170 */ +uint32_t clk_misc0_set; +uint32_t clk_misc0_clr; +uint32_t clk_misc0_tog; +uint32_t clk_rsvd;/* offset 0x0180 */ +uint8_t reserved_10[124 ]; +uint32_t reg_1p0a;/* offset 0x0200 */ +uint32_t reg_1p0a_set; +uint32_t reg_1p0a_clr; +uint32_t reg_1p0a_tog; +uint32_t reg_1p0d;/* offsest 0x0210 */ +uint32_t reg_1p0d_set; +uint32_t reg_1p0d_clr; +uint32_t reg_1p0d_tog; +uint32_t reg_hsic_1p2;/* offset 0x0220 */ +uint32_t reg_hsic_1p2_set; +uint32_t reg_hsic_1p2_clr; +uint32_t reg_hsic_1p2_tog; +uint32_t reg_lpsr_1p0;/* offset 0x0230 */ +uint32_t reg_lpsr_1p0_set; +uint32_t reg_lpsr_1p0_clr; +uint32_t reg_lpsr_1p0_tog; +uint32_t reg_3p0;/* offset 0x0240 */ +uint32_t reg_3p0_set; +uint32_t reg_3p0_clr; +uint32_t reg_3p0_tog; +uint32_t reg_snvs;/* offset 0x0250 */ +uint32_t reg_snvs_set; +uint32_t reg_snvs_clr; +uint32_t reg_snvs_tog; +uint32_t analog_debug_misc0;/* offset 0x0260 */ +uint32_t analog_debug_misc0_set; +uint32_t analog_debug_misc0_clr; +uint32_t analog_debug_misc0_tog; +uint32_t ref;/* offset 0x0270 */ +uint32_t ref_set; +uint32_t ref_clr; +uint32_t ref_tog; +uint8_t reserved_11[128 ]; +uint32_t tempsense0;/* offset 0x0300 */ +uint32_t tempsense0_set; +uint32_t tempsense0_clr; +uint32_t tempsense0_tog; +uint32_t tempsense1;/* offset 0x0310 */ +uint32_t tempsense1_set; +uint32_t tempsense1_clr; +uint32_t tempsense1_tog; +uint32_t tempsense_trim;/* offset 0x0320 */ +uint32_t tempsense_trim_set; +uint32_t tempsense_trim_clr; +uint32_t tempsense_trim_tog; +uint32_t lowpwr_ctrl;/* offset 0x0330 */ +uint32_t lowpwr_ctrl_set; +uint32_t lowpwr_ctrl_clr; +uint32_t lowpwr_ctrl_tog; +uint32_t snvs_tamper_offset_ctrl;/* offset 0x0340 */ +uint32_t snvs_tamper_offset_ctrl_set; +uint32_t snvs_tamper_offset_ctrl_clr; +uint32_t snvs_tamper_offset_ctrl_tog; +uint32_t snvs_tamper_pull_ctrl;/* offset 0x0350 */ +uint32_t snvs_tamper_pull_ctrl_set; +uint32_t snvs_tamper_pull_ctrl_clr; +uint32_t snvs_tamper_pull_ctrl_tog; +uint32_t snvs_test;/* offset 0x0360 */ +uint32_t snvs_test_set; +uint32_t snvs_test_clr; +uint32_t snvs_test_tog; +uint32_t snvs_tamper_trim_ctrl;/* offset 0x0370 */ +uint32_t snvs_tamper_trim_ctrl_set; +uint32_t snvs_tamper_trim_ctrl_ctrl; +uint32_t snvs_tamper_trim_ctrl_tog; +uint32_t snvs_misc_ctrl;/* offset 0x0380 */ +uint32_t snvs_misc_ctrl_set; +uint32_t snvs_misc_ctrl_clr; +uint32_t snvs_misc_ctrl_tog; +uint8_t reserved_12[112 ]; +uint32_t misc;/* offset 0x0400 */ +uint8_t reserved_13[252 ]; +uint32_t adc0;/* offset 0x0500 */ +uint8_t reserved_14[12 ]; +uint32_t adc1;/* offset 0x0510 */ +uint8_t reserved_15[748 ]; +uint32_t digprog;/* offset 0x0800 */ +}; +#endif + +#define ANADIG_CLK_MISC0_PFD_480_AUTOGATE_EN_MASK (0x01 << 17) + +#define ANADIG_PLL_LOCK 0x80000000 + +#define ANADIG_PLL_ARM_PWDN_MASK (0x01 << 12) +#define ANADIG_PLL_480_PWDN_MASK (0x01 << 12) +#define ANADIG_PLL_DDR_PWDN_MASK (0x01 << 20) +#define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5) +#define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12) + + +#define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f +#define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B +#define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016 +#define ANATOP_PFD480B_PFD4_FRAC_432M_VAL 0x00000014 + +/* PLL_ARM Bit Fields */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7F +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_ARM_HALF_LF_MASK 0x80 +#define CCM_ANALOG_PLL_ARM_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_MASK 0x100 +#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_ARM_HALF_CP_MASK 0x200 +#define CCM_ANALOG_PLL_ARM_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_MASK 0x400 +#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_MASK 0x800 +#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK 0x1000 +#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_MASK 0x2000 +#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK 0xC000 +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_ARM_BYPASS_MASK 0x10000 +#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK 0x20000 +#define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT 17 +#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK 0x40000 +#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT 18 +#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK 0x80000 +#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT 19 +#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_MASK 0x100000 +#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_SHIFT 20 +#define CCM_ANALOG_PLL_ARM_RSVD0_MASK 0x7FE00000 +#define CCM_ANALOG_PLL_ARM_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_ARM_LOCK_MASK 0x80000000 +#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT 31 + +/* PLL_DDR Bit Fields */ +#define CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK 0x7F +#define CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_DDR_HALF_LF_MASK 0x80 +#define CCM_ANALOG_PLL_DDR_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_MASK 0x100 +#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_DDR_HALF_CP_MASK 0x200 +#define CCM_ANALOG_PLL_DDR_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_MASK 0x400 +#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_MASK 0x800 +#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK 0x1000 +#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT 12 +#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_MASK 0x2000 +#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK 0xC000 +#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_DDR_BYPASS_MASK 0x10000 +#define CCM_ANALOG_PLL_DDR_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_MASK 0x20000 +#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_MASK 0x40000 +#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_MASK 0x80000 +#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_SHIFT 19 +#define CCM_ANALOG_PLL_DDR_POWERDOWN_MASK 0x100000 +#define CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT 20 +#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK 0x600000 +#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT 21 +#define CCM_ANALOG_PLL_DDR_RSVD1_MASK 0x7F800000 +#define CCM_ANALOG_PLL_DDR_RSVD1_SHIFT 23 +#define CCM_ANALOG_PLL_DDR_LOCK_MASK 0x80000000 +#define CCM_ANALOG_PLL_DDR_LOCK_SHIFT 31 + +/* PLL_480 Bit Fields */ +#define CCM_ANALOG_PLL_480_DIV_SELECT_MASK 0x1 +#define CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_480_RSVD0_MASK 0xE +#define CCM_ANALOG_PLL_480_RSVD0_SHIFT 1 +#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK 0x10 +#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT 4 +#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK 0x20 +#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT 5 +#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK 0x40 +#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT 6 +#define CCM_ANALOG_PLL_480_HALF_LF_MASK 0x80 +#define CCM_ANALOG_PLL_480_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_480_DOUBLE_LF_MASK 0x100 +#define CCM_ANALOG_PLL_480_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_480_HALF_CP_MASK 0x200 +#define CCM_ANALOG_PLL_480_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_480_DOUBLE_CP_MASK 0x400 +#define CCM_ANALOG_PLL_480_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_MASK 0x800 +#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_480_POWERDOWN_MASK 0x1000 +#define CCM_ANALOG_PLL_480_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_480_ENABLE_CLK_MASK 0x2000 +#define CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK 0xC000 +#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_480_BYPASS_MASK 0x10000 +#define CCM_ANALOG_PLL_480_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_MASK 0x20000 +#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_SHIFT 17 +#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_MASK 0x40000 +#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_SHIFT 18 +#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_MASK 0x80000 +#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_SHIFT 19 +#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_MASK 0x100000 +#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_SHIFT 20 +#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_MASK 0x200000 +#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_SHIFT 21 +#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_MASK 0x400000 +#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_SHIFT 22 +#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_MASK 0x800000 +#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_SHIFT 23 +#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_MASK 0x1000000 +#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_MASK 0x2000000 +#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_SHIFT 25 +#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK 0x4000000 +#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT 26 +#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK 0x8000000 +#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT 27 +#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK 0x10000000 +#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT 28 +#define CCM_ANALOG_PLL_480_RSVD1_MASK 0x60000000 +#define CCM_ANALOG_PLL_480_RSVD1_SHIFT 29 +#define CCM_ANALOG_PLL_480_LOCK_MASK 0x80000000 +#define CCM_ANALOG_PLL_480_LOCK_SHIFT 31 + +/* PFD_480A Bit Fields */ +#define CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK 0x3F +#define CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT 0 +#define CCM_ANALOG_PFD_480A_PFD0_STABLE_MASK 0x40 +#define CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT 6 +#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK 0x80 +#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT 7 +#define CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK 0x3F00 +#define CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT 8 +#define CCM_ANALOG_PFD_480A_PFD1_STABLE_MASK 0x4000 +#define CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT 14 +#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK 0x8000 +#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT 15 +#define CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK 0x3F0000 +#define CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT 16 +#define CCM_ANALOG_PFD_480A_PFD2_STABLE_MASK 0x400000 +#define CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT 22 +#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK 0x800000 +#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT 23 +#define CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK 0x3F000000 +#define CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT 24 +#define CCM_ANALOG_PFD_480A_PFD3_STABLE_MASK 0x40000000 +#define CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT 30 +#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK 0x80000000 +#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT 31 +/* PFD_480B Bit Fields */ +#define CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK 0x3F +#define CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT 0 +#define CCM_ANALOG_PFD_480B_PFD4_STABLE_MASK 0x40 +#define CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT 6 +#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK 0x80 +#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT 7 +#define CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK 0x3F00 +#define CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT 8 +#define CCM_ANALOG_PFD_480B_PFD5_STABLE_MASK 0x4000 +#define CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT 14 +#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK 0x8000 +#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT 15 +#define CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK 0x3F0000 +#define CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT 16 +#define CCM_ANALOG_PFD_480B_PFD6_STABLE_MASK 0x400000 +#define CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT 22 +#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK 0x800000 +#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT 23 +#define CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK 0x3F000000 +#define CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT 24 +#define CCM_ANALOG_PFD_480B_PFD7_STABLE_MASK 0x40000000 +#define CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT 30 +#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK 0x80000000 +#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT 31 + +/* PLL_ENET Bit Fields */ +#define CCM_ANALOG_PLL_ENET_HALF_LF_MASK 0x1 +#define CCM_ANALOG_PLL_ENET_HALF_LF_SHIFT 0 +#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_MASK 0x2 +#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_SHIFT 1 +#define CCM_ANALOG_PLL_ENET_HALF_CP_MASK 0x4 +#define CCM_ANALOG_PLL_ENET_HALF_CP_SHIFT 2 +#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_MASK 0x8 +#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_SHIFT 3 +#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_MASK 0x10 +#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_SHIFT 4 +#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK 0x20 +#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT 5 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK 0x40 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT 6 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK 0x80 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT 7 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK 0x100 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT 8 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK 0x200 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT 9 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK 0x400 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT 10 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK 0x800 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT 11 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK 0x1000 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT 12 +#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_MASK 0x2000 +#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_SHIFT 13 +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK 0xC000 +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_ENET_BYPASS_MASK 0x10000 +#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_MASK 0x20000 +#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK 0x40000 +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_ENET_RSVD1_MASK 0x7FF80000 +#define CCM_ANALOG_PLL_ENET_RSVD1_SHIFT 19 +#define CCM_ANALOG_PLL_ENET_LOCK_MASK 0x80000000 +#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT 31 + +/* PLL_AUDIO Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_AUDIO_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_AUDIO_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_AUDIO_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_AUDIO_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_AUDIO_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_AUDIO_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_RSVD1_MASK) +#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT 31 +/* PLL_AUDIO_SET Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT 31 +/* PLL_AUDIO_CLR Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT 31 +/* PLL_AUDIO_TOG Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT 31 +/* PLL_AUDIO_SS Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK 0x7FFFu +#define CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_SS_STEP (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK) +#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK 0x8000u +#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_SHIFT 15 +#define CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK 0xFFFF0000u +#define CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_SS_STOP (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK) +/* PLL_AUDIO_NUM Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK 0x3FFFFFFFu +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_NUM_A (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) +#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK 0xC0000000u +#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT 30 +#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK) +/* PLL_AUDIO_DENOM Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK 0x3FFFFFFFu +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_DENOM_B (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) +#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK 0xC0000000u +#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT 30 +#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK) +/* PLL_VIDEO Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_VIDEO_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_VIDEO_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_VIDEO_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_VIDEO_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_VIDEO_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_VIDEO_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_RSVD1_MASK) +#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT 31 +/* PLL_VIDEO_SET Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT 31 +/* PLL_VIDEO_CLR Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT 31 +/* PLL_VIDEO_TOG Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT 31 +/* PLL_VIDEO_SS Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK 0x7FFFu +#define CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_SS_STEP (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK) +#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK 0x8000u +#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_SHIFT 15 +#define CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK 0xFFFF0000u +#define CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_SS_STOP (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK) +/* PLL_VIDEO_NUM Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK 0x3FFFFFFFu +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_NUM_A (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) +#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK 0xC0000000u +#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT 30 +#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK) +/* PLL_VIDEO_DENOM Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK 0x3FFFFFFFu +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_DENOM_B (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) +#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK 0xC0000000u +#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT 30 +#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK) +/* CLK_MISC0 Bit Fields */ +#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK 0x1Fu +#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT 0 +#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_MASK 0x20u +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_SHIFT 5 +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_MASK 0x40u +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_SHIFT 6 +#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_MASK 0x80u +#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_SHIFT 7 +#define CCM_ANALOG_CLK_MISC0_RSVD0_MASK 0xFFFFFF00u +#define CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT 8 +#define CCM_ANALOG_CLK_MISC0_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_RSVD0_MASK) +/* CLK_MISC0_SET Bit Fields */ +#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK 0x1Fu +#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT 0 +#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_MASK 0x20u +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_SHIFT 5 +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_MASK 0x40u +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_SHIFT 6 +#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_MASK 0x80u +#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_SHIFT 7 +#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK 0xFFFFFF00u +#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT 8 +#define CCM_ANALOG_CLK_MISC0_SET_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK) +/* CLK_MISC0_CLR Bit Fields */ +#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK 0x1Fu +#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT 0 +#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_MASK 0x20u +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_SHIFT 5 +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_MASK 0x40u +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_SHIFT 6 +#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_MASK 0x80u +#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_SHIFT 7 +#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK 0xFFFFFF00u +#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT 8 +#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK) +/* CLK_MISC0_TOG Bit Fields */ +#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK 0x1Fu +#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT 0 +#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_MASK 0x20u +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_SHIFT 5 +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_MASK 0x40u +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_SHIFT 6 +#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_MASK 0x80u +#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_SHIFT 7 +#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK 0xFFFFFF00u +#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT 8 +#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK) + +/* REG_1P0A Bit Fields */ +#define PMU_REG_1P0A_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0A_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0A_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0A_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0A_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0A_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0A_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0A_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_BO_OFFSET_SHIFT))&PMU_REG_1P0A_BO_OFFSET_MASK) +#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0A_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0A_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0A_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_OUTPUT_TRG_MASK) +#define PMU_REG_1P0A_RSVD0_MASK 0xE000u +#define PMU_REG_1P0A_RSVD0_SHIFT 13 +#define PMU_REG_1P0A_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD0_SHIFT))&PMU_REG_1P0A_RSVD0_MASK) +#define PMU_REG_1P0A_BO_MASK 0x10000u +#define PMU_REG_1P0A_BO_SHIFT 16 +#define PMU_REG_1P0A_OK_MASK 0x20000u +#define PMU_REG_1P0A_OK_SHIFT 17 +#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0A_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0A_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0A_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0A_REG_TEST_SHIFT 20 +#define PMU_REG_1P0A_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_REG_TEST_SHIFT))&PMU_REG_1P0A_REG_TEST_MASK) +#define PMU_REG_1P0A_RSVD1_MASK 0xFF000000u +#define PMU_REG_1P0A_RSVD1_SHIFT 24 +#define PMU_REG_1P0A_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD1_SHIFT))&PMU_REG_1P0A_RSVD1_MASK) +/* REG_1P0A_SET Bit Fields */ +#define PMU_REG_1P0A_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0A_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0A_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0A_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0A_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0A_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0A_SET_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0A_SET_BO_OFFSET_MASK) +#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0A_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0A_SET_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_SET_OUTPUT_TRG_MASK) +#define PMU_REG_1P0A_SET_RSVD0_MASK 0xE000u +#define PMU_REG_1P0A_SET_RSVD0_SHIFT 13 +#define PMU_REG_1P0A_SET_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD0_SHIFT))&PMU_REG_1P0A_SET_RSVD0_MASK) +#define PMU_REG_1P0A_SET_BO_MASK 0x10000u +#define PMU_REG_1P0A_SET_BO_SHIFT 16 +#define PMU_REG_1P0A_SET_OK_MASK 0x20000u +#define PMU_REG_1P0A_SET_OK_SHIFT 17 +#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0A_SET_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0A_SET_REG_TEST_SHIFT 20 +#define PMU_REG_1P0A_SET_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_REG_TEST_SHIFT))&PMU_REG_1P0A_SET_REG_TEST_MASK) +#define PMU_REG_1P0A_SET_RSVD1_MASK 0xFF000000u +#define PMU_REG_1P0A_SET_RSVD1_SHIFT 24 +#define PMU_REG_1P0A_SET_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD1_SHIFT))&PMU_REG_1P0A_SET_RSVD1_MASK) +/* REG_1P0A_CLR Bit Fields */ +#define PMU_REG_1P0A_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0A_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0A_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0A_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0A_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0A_CLR_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0A_CLR_BO_OFFSET_MASK) +#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0A_CLR_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_1P0A_CLR_RSVD0_MASK 0xE000u +#define PMU_REG_1P0A_CLR_RSVD0_SHIFT 13 +#define PMU_REG_1P0A_CLR_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD0_SHIFT))&PMU_REG_1P0A_CLR_RSVD0_MASK) +#define PMU_REG_1P0A_CLR_BO_MASK 0x10000u +#define PMU_REG_1P0A_CLR_BO_SHIFT 16 +#define PMU_REG_1P0A_CLR_OK_MASK 0x20000u +#define PMU_REG_1P0A_CLR_OK_SHIFT 17 +#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0A_CLR_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0A_CLR_REG_TEST_SHIFT 20 +#define PMU_REG_1P0A_CLR_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_REG_TEST_SHIFT))&PMU_REG_1P0A_CLR_REG_TEST_MASK) +#define PMU_REG_1P0A_CLR_RSVD1_MASK 0xFF000000u +#define PMU_REG_1P0A_CLR_RSVD1_SHIFT 24 +#define PMU_REG_1P0A_CLR_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD1_SHIFT))&PMU_REG_1P0A_CLR_RSVD1_MASK) +/* REG_1P0A_TOG Bit Fields */ +#define PMU_REG_1P0A_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0A_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0A_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0A_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0A_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0A_TOG_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0A_TOG_BO_OFFSET_MASK) +#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0A_TOG_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_1P0A_TOG_RSVD0_MASK 0xE000u +#define PMU_REG_1P0A_TOG_RSVD0_SHIFT 13 +#define PMU_REG_1P0A_TOG_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD0_SHIFT))&PMU_REG_1P0A_TOG_RSVD0_MASK) +#define PMU_REG_1P0A_TOG_BO_MASK 0x10000u +#define PMU_REG_1P0A_TOG_BO_SHIFT 16 +#define PMU_REG_1P0A_TOG_OK_MASK 0x20000u +#define PMU_REG_1P0A_TOG_OK_SHIFT 17 +#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0A_TOG_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0A_TOG_REG_TEST_SHIFT 20 +#define PMU_REG_1P0A_TOG_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_REG_TEST_SHIFT))&PMU_REG_1P0A_TOG_REG_TEST_MASK) +#define PMU_REG_1P0A_TOG_RSVD1_MASK 0xFF000000u +#define PMU_REG_1P0A_TOG_RSVD1_SHIFT 24 +#define PMU_REG_1P0A_TOG_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD1_SHIFT))&PMU_REG_1P0A_TOG_RSVD1_MASK) +/* REG_1P0D Bit Fields */ +#define PMU_REG_1P0D_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0D_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0D_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0D_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0D_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0D_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0D_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0D_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0D_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0D_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0D_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_BO_OFFSET_SHIFT))&PMU_REG_1P0D_BO_OFFSET_MASK) +#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0D_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0D_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0D_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_OUTPUT_TRG_MASK) +#define PMU_REG_1P0D_RSVD0_MASK 0xE000u +#define PMU_REG_1P0D_RSVD0_SHIFT 13 +#define PMU_REG_1P0D_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD0_SHIFT))&PMU_REG_1P0D_RSVD0_MASK) +#define PMU_REG_1P0D_BO_MASK 0x10000u +#define PMU_REG_1P0D_BO_SHIFT 16 +#define PMU_REG_1P0D_OK_MASK 0x20000u +#define PMU_REG_1P0D_OK_SHIFT 17 +#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0D_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0D_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0D_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0D_REG_TEST_SHIFT 20 +#define PMU_REG_1P0D_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_REG_TEST_SHIFT))&PMU_REG_1P0D_REG_TEST_MASK) +#define PMU_REG_1P0D_RSVD1_MASK 0x7F000000u +#define PMU_REG_1P0D_RSVD1_SHIFT 24 +#define PMU_REG_1P0D_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD1_SHIFT))&PMU_REG_1P0D_RSVD1_MASK) +#define PMU_REG_1P0D_OVERRIDE_MASK 0x80000000u +#define PMU_REG_1P0D_OVERRIDE_SHIFT 31 +/* REG_1P0D_SET Bit Fields */ +#define PMU_REG_1P0D_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0D_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0D_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0D_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0D_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0D_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0D_SET_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0D_SET_BO_OFFSET_MASK) +#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0D_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0D_SET_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_SET_OUTPUT_TRG_MASK) +#define PMU_REG_1P0D_SET_RSVD0_MASK 0xE000u +#define PMU_REG_1P0D_SET_RSVD0_SHIFT 13 +#define PMU_REG_1P0D_SET_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD0_SHIFT))&PMU_REG_1P0D_SET_RSVD0_MASK) +#define PMU_REG_1P0D_SET_BO_MASK 0x10000u +#define PMU_REG_1P0D_SET_BO_SHIFT 16 +#define PMU_REG_1P0D_SET_OK_MASK 0x20000u +#define PMU_REG_1P0D_SET_OK_SHIFT 17 +#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0D_SET_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0D_SET_REG_TEST_SHIFT 20 +#define PMU_REG_1P0D_SET_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_REG_TEST_SHIFT))&PMU_REG_1P0D_SET_REG_TEST_MASK) +#define PMU_REG_1P0D_SET_RSVD1_MASK 0x7F000000u +#define PMU_REG_1P0D_SET_RSVD1_SHIFT 24 +#define PMU_REG_1P0D_SET_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD1_SHIFT))&PMU_REG_1P0D_SET_RSVD1_MASK) +#define PMU_REG_1P0D_SET_OVERRIDE_MASK 0x80000000u +#define PMU_REG_1P0D_SET_OVERRIDE_SHIFT 31 +/* REG_1P0D_CLR Bit Fields */ +#define PMU_REG_1P0D_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0D_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0D_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0D_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0D_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0D_CLR_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0D_CLR_BO_OFFSET_MASK) +#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0D_CLR_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_1P0D_CLR_RSVD0_MASK 0xE000u +#define PMU_REG_1P0D_CLR_RSVD0_SHIFT 13 +#define PMU_REG_1P0D_CLR_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD0_SHIFT))&PMU_REG_1P0D_CLR_RSVD0_MASK) +#define PMU_REG_1P0D_CLR_BO_MASK 0x10000u +#define PMU_REG_1P0D_CLR_BO_SHIFT 16 +#define PMU_REG_1P0D_CLR_OK_MASK 0x20000u +#define PMU_REG_1P0D_CLR_OK_SHIFT 17 +#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0D_CLR_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0D_CLR_REG_TEST_SHIFT 20 +#define PMU_REG_1P0D_CLR_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_REG_TEST_SHIFT))&PMU_REG_1P0D_CLR_REG_TEST_MASK) +#define PMU_REG_1P0D_CLR_RSVD1_MASK 0x7F000000u +#define PMU_REG_1P0D_CLR_RSVD1_SHIFT 24 +#define PMU_REG_1P0D_CLR_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD1_SHIFT))&PMU_REG_1P0D_CLR_RSVD1_MASK) +#define PMU_REG_1P0D_CLR_OVERRIDE_MASK 0x80000000u +#define PMU_REG_1P0D_CLR_OVERRIDE_SHIFT 31 +/* REG_1P0D_TOG Bit Fields */ +#define PMU_REG_1P0D_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0D_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0D_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0D_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0D_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0D_TOG_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0D_TOG_BO_OFFSET_MASK) +#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0D_TOG_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_1P0D_TOG_RSVD0_MASK 0xE000u +#define PMU_REG_1P0D_TOG_RSVD0_SHIFT 13 +#define PMU_REG_1P0D_TOG_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD0_SHIFT))&PMU_REG_1P0D_TOG_RSVD0_MASK) +#define PMU_REG_1P0D_TOG_BO_MASK 0x10000u +#define PMU_REG_1P0D_TOG_BO_SHIFT 16 +#define PMU_REG_1P0D_TOG_OK_MASK 0x20000u +#define PMU_REG_1P0D_TOG_OK_SHIFT 17 +#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0D_TOG_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0D_TOG_REG_TEST_SHIFT 20 +#define PMU_REG_1P0D_TOG_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_REG_TEST_SHIFT))&PMU_REG_1P0D_TOG_REG_TEST_MASK) +#define PMU_REG_1P0D_TOG_RSVD1_MASK 0x7F000000u +#define PMU_REG_1P0D_TOG_RSVD1_SHIFT 24 +#define PMU_REG_1P0D_TOG_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD1_SHIFT))&PMU_REG_1P0D_TOG_RSVD1_MASK) +#define PMU_REG_1P0D_TOG_OVERRIDE_MASK 0x80000000u +#define PMU_REG_1P0D_TOG_OVERRIDE_SHIFT 31 +/* REG_HSIC_1P2 Bit Fields */ +#define PMU_REG_HSIC_1P2_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_HSIC_1P2_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_HSIC_1P2_ENABLE_BO_MASK 0x2u +#define PMU_REG_HSIC_1P2_ENABLE_BO_SHIFT 1 +#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_HSIC_1P2_BO_OFFSET_MASK 0x70u +#define PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT 4 +#define PMU_REG_HSIC_1P2_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_BO_OFFSET_MASK) +#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_HSIC_1P2_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK) +#define PMU_REG_HSIC_1P2_RSVD0_MASK 0xE000u +#define PMU_REG_HSIC_1P2_RSVD0_SHIFT 13 +#define PMU_REG_HSIC_1P2_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_RSVD0_MASK) +#define PMU_REG_HSIC_1P2_BO_MASK 0x10000u +#define PMU_REG_HSIC_1P2_BO_SHIFT 16 +#define PMU_REG_HSIC_1P2_OK_MASK 0x20000u +#define PMU_REG_HSIC_1P2_OK_SHIFT 17 +#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_HSIC_1P2_REG_TEST_MASK 0xF00000u +#define PMU_REG_HSIC_1P2_REG_TEST_SHIFT 20 +#define PMU_REG_HSIC_1P2_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_REG_TEST_MASK) +#define PMU_REG_HSIC_1P2_RSVD1_MASK 0x7F000000u +#define PMU_REG_HSIC_1P2_RSVD1_SHIFT 24 +#define PMU_REG_HSIC_1P2_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_RSVD1_MASK) +#define PMU_REG_HSIC_1P2_OVERRIDE_MASK 0x80000000u +#define PMU_REG_HSIC_1P2_OVERRIDE_SHIFT 31 +/* REG_HSIC_1P2_SET Bit Fields */ +#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_HSIC_1P2_SET_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK) +#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK) +#define PMU_REG_HSIC_1P2_SET_RSVD0_MASK 0xE000u +#define PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT 13 +#define PMU_REG_HSIC_1P2_SET_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD0_MASK) +#define PMU_REG_HSIC_1P2_SET_BO_MASK 0x10000u +#define PMU_REG_HSIC_1P2_SET_BO_SHIFT 16 +#define PMU_REG_HSIC_1P2_SET_OK_MASK 0x20000u +#define PMU_REG_HSIC_1P2_SET_OK_SHIFT 17 +#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_HSIC_1P2_SET_REG_TEST_MASK 0xF00000u +#define PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT 20 +#define PMU_REG_HSIC_1P2_SET_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_SET_REG_TEST_MASK) +#define PMU_REG_HSIC_1P2_SET_RSVD1_MASK 0x7F000000u +#define PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT 24 +#define PMU_REG_HSIC_1P2_SET_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD1_MASK) +#define PMU_REG_HSIC_1P2_SET_OVERRIDE_MASK 0x80000000u +#define PMU_REG_HSIC_1P2_SET_OVERRIDE_SHIFT 31 +/* REG_HSIC_1P2_CLR Bit Fields */ +#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK) +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_HSIC_1P2_CLR_RSVD0_MASK 0xE000u +#define PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT 13 +#define PMU_REG_HSIC_1P2_CLR_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD0_MASK) +#define PMU_REG_HSIC_1P2_CLR_BO_MASK 0x10000u +#define PMU_REG_HSIC_1P2_CLR_BO_SHIFT 16 +#define PMU_REG_HSIC_1P2_CLR_OK_MASK 0x20000u +#define PMU_REG_HSIC_1P2_CLR_OK_SHIFT 17 +#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK 0xF00000u +#define PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT 20 +#define PMU_REG_HSIC_1P2_CLR_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK) +#define PMU_REG_HSIC_1P2_CLR_RSVD1_MASK 0x7F000000u +#define PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT 24 +#define PMU_REG_HSIC_1P2_CLR_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD1_MASK) +#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_MASK 0x80000000u +#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_SHIFT 31 +/* REG_HSIC_1P2_TOG Bit Fields */ +#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK) +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_HSIC_1P2_TOG_RSVD0_MASK 0xE000u +#define PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT 13 +#define PMU_REG_HSIC_1P2_TOG_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD0_MASK) +#define PMU_REG_HSIC_1P2_TOG_BO_MASK 0x10000u +#define PMU_REG_HSIC_1P2_TOG_BO_SHIFT 16 +#define PMU_REG_HSIC_1P2_TOG_OK_MASK 0x20000u +#define PMU_REG_HSIC_1P2_TOG_OK_SHIFT 17 +#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK 0xF00000u +#define PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT 20 +#define PMU_REG_HSIC_1P2_TOG_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK) +#define PMU_REG_HSIC_1P2_TOG_RSVD1_MASK 0x7F000000u +#define PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT 24 +#define PMU_REG_HSIC_1P2_TOG_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD1_MASK) +#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_MASK 0x80000000u +#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_SHIFT 31 +/* REG_LPSR_1P0 Bit Fields */ +#define PMU_REG_LPSR_1P0_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_LPSR_1P0_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_LPSR_1P0_ENABLE_BO_MASK 0x2u +#define PMU_REG_LPSR_1P0_ENABLE_BO_SHIFT 1 +#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_LPSR_1P0_BO_OFFSET_MASK 0x70u +#define PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT 4 +#define PMU_REG_LPSR_1P0_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_BO_OFFSET_MASK) +#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_LPSR_1P0_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK) +#define PMU_REG_LPSR_1P0_RSVD0_MASK 0xE000u +#define PMU_REG_LPSR_1P0_RSVD0_SHIFT 13 +#define PMU_REG_LPSR_1P0_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_RSVD0_MASK) +#define PMU_REG_LPSR_1P0_BO_MASK 0x10000u +#define PMU_REG_LPSR_1P0_BO_SHIFT 16 +#define PMU_REG_LPSR_1P0_OK_MASK 0x20000u +#define PMU_REG_LPSR_1P0_OK_SHIFT 17 +#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_LPSR_1P0_REG_TEST_MASK 0xF00000u +#define PMU_REG_LPSR_1P0_REG_TEST_SHIFT 20 +#define PMU_REG_LPSR_1P0_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_REG_TEST_MASK) +#define PMU_REG_LPSR_1P0_RSVD1_MASK 0xFF000000u +#define PMU_REG_LPSR_1P0_RSVD1_SHIFT 24 +#define PMU_REG_LPSR_1P0_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_RSVD1_MASK) +/* REG_LPSR_1P0_SET Bit Fields */ +#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_LPSR_1P0_SET_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK) +#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK) +#define PMU_REG_LPSR_1P0_SET_RSVD0_MASK 0xE000u +#define PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT 13 +#define PMU_REG_LPSR_1P0_SET_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD0_MASK) +#define PMU_REG_LPSR_1P0_SET_BO_MASK 0x10000u +#define PMU_REG_LPSR_1P0_SET_BO_SHIFT 16 +#define PMU_REG_LPSR_1P0_SET_OK_MASK 0x20000u +#define PMU_REG_LPSR_1P0_SET_OK_SHIFT 17 +#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_LPSR_1P0_SET_REG_TEST_MASK 0xF00000u +#define PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT 20 +#define PMU_REG_LPSR_1P0_SET_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_SET_REG_TEST_MASK) +#define PMU_REG_LPSR_1P0_SET_RSVD1_MASK 0xFF000000u +#define PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT 24 +#define PMU_REG_LPSR_1P0_SET_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD1_MASK) +/* REG_LPSR_1P0_CLR Bit Fields */ +#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK) +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_LPSR_1P0_CLR_RSVD0_MASK 0xE000u +#define PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT 13 +#define PMU_REG_LPSR_1P0_CLR_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD0_MASK) +#define PMU_REG_LPSR_1P0_CLR_BO_MASK 0x10000u +#define PMU_REG_LPSR_1P0_CLR_BO_SHIFT 16 +#define PMU_REG_LPSR_1P0_CLR_OK_MASK 0x20000u +#define PMU_REG_LPSR_1P0_CLR_OK_SHIFT 17 +#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK 0xF00000u +#define PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT 20 +#define PMU_REG_LPSR_1P0_CLR_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK) +#define PMU_REG_LPSR_1P0_CLR_RSVD1_MASK 0xFF000000u +#define PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT 24 +#define PMU_REG_LPSR_1P0_CLR_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD1_MASK) +/* REG_LPSR_1P0_TOG Bit Fields */ +#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK) +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_LPSR_1P0_TOG_RSVD0_MASK 0xE000u +#define PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT 13 +#define PMU_REG_LPSR_1P0_TOG_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD0_MASK) +#define PMU_REG_LPSR_1P0_TOG_BO_MASK 0x10000u +#define PMU_REG_LPSR_1P0_TOG_BO_SHIFT 16 +#define PMU_REG_LPSR_1P0_TOG_OK_MASK 0x20000u +#define PMU_REG_LPSR_1P0_TOG_OK_SHIFT 17 +#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK 0xF00000u +#define PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT 20 +#define PMU_REG_LPSR_1P0_TOG_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK) +#define PMU_REG_LPSR_1P0_TOG_RSVD1_MASK 0xFF000000u +#define PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT 24 +#define PMU_REG_LPSR_1P0_TOG_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD1_MASK) +/* REG_3P0 Bit Fields */ +#define PMU_REG_3P0_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_3P0_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_3P0_ENABLE_BO_MASK 0x2u +#define PMU_REG_3P0_ENABLE_BO_SHIFT 1 +#define PMU_REG_3P0_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_3P0_RSVD0_MASK 0x8u +#define PMU_REG_3P0_RSVD0_SHIFT 3 +#define PMU_REG_3P0_BO_OFFSET_MASK 0x70u +#define PMU_REG_3P0_BO_OFFSET_SHIFT 4 +#define PMU_REG_3P0_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_BO_OFFSET_SHIFT))&PMU_REG_3P0_BO_OFFSET_MASK) +#define PMU_REG_3P0_VBUS_SEL_MASK 0x80u +#define PMU_REG_3P0_VBUS_SEL_SHIFT 7 +#define PMU_REG_3P0_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_3P0_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_3P0_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_RSVD1_MASK 0xE000u +#define PMU_REG_3P0_RSVD1_SHIFT 13 +#define PMU_REG_3P0_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD1_SHIFT))&PMU_REG_3P0_RSVD1_MASK) +#define PMU_REG_3P0_BO_VDD3P0_MASK 0x10000u +#define PMU_REG_3P0_BO_VDD3P0_SHIFT 16 +#define PMU_REG_3P0_OK_VDD3P0_MASK 0x20000u +#define PMU_REG_3P0_OK_VDD3P0_SHIFT 17 +#define PMU_REG_3P0_REG_TEST_MASK 0x3C0000u +#define PMU_REG_3P0_REG_TEST_SHIFT 18 +#define PMU_REG_3P0_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_REG_TEST_SHIFT))&PMU_REG_3P0_REG_TEST_MASK) +#define PMU_REG_3P0_RSVD2_MASK 0xFFC00000u +#define PMU_REG_3P0_RSVD2_SHIFT 22 +#define PMU_REG_3P0_RSVD2 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD2_SHIFT))&PMU_REG_3P0_RSVD2_MASK) +/* REG_3P0_SET Bit Fields */ +#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_3P0_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_3P0_SET_RSVD0_MASK 0x8u +#define PMU_REG_3P0_SET_RSVD0_SHIFT 3 +#define PMU_REG_3P0_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_3P0_SET_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_BO_OFFSET_SHIFT))&PMU_REG_3P0_SET_BO_OFFSET_MASK) +#define PMU_REG_3P0_SET_VBUS_SEL_MASK 0x80u +#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT 7 +#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_3P0_SET_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_SET_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_SET_RSVD1_MASK 0xE000u +#define PMU_REG_3P0_SET_RSVD1_SHIFT 13 +#define PMU_REG_3P0_SET_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD1_SHIFT))&PMU_REG_3P0_SET_RSVD1_MASK) +#define PMU_REG_3P0_SET_BO_VDD3P0_MASK 0x10000u +#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT 16 +#define PMU_REG_3P0_SET_OK_VDD3P0_MASK 0x20000u +#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT 17 +#define PMU_REG_3P0_SET_REG_TEST_MASK 0x3C0000u +#define PMU_REG_3P0_SET_REG_TEST_SHIFT 18 +#define PMU_REG_3P0_SET_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_REG_TEST_SHIFT))&PMU_REG_3P0_SET_REG_TEST_MASK) +#define PMU_REG_3P0_SET_RSVD2_MASK 0xFFC00000u +#define PMU_REG_3P0_SET_RSVD2_SHIFT 22 +#define PMU_REG_3P0_SET_RSVD2 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD2_SHIFT))&PMU_REG_3P0_SET_RSVD2_MASK) +/* REG_3P0_CLR Bit Fields */ +#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_3P0_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_3P0_CLR_RSVD0_MASK 0x8u +#define PMU_REG_3P0_CLR_RSVD0_SHIFT 3 +#define PMU_REG_3P0_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_3P0_CLR_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_3P0_CLR_BO_OFFSET_MASK) +#define PMU_REG_3P0_CLR_VBUS_SEL_MASK 0x80u +#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT 7 +#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_3P0_CLR_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_CLR_RSVD1_MASK 0xE000u +#define PMU_REG_3P0_CLR_RSVD1_SHIFT 13 +#define PMU_REG_3P0_CLR_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD1_SHIFT))&PMU_REG_3P0_CLR_RSVD1_MASK) +#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK 0x10000u +#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT 16 +#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK 0x20000u +#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT 17 +#define PMU_REG_3P0_CLR_REG_TEST_MASK 0x3C0000u +#define PMU_REG_3P0_CLR_REG_TEST_SHIFT 18 +#define PMU_REG_3P0_CLR_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_REG_TEST_SHIFT))&PMU_REG_3P0_CLR_REG_TEST_MASK) +#define PMU_REG_3P0_CLR_RSVD2_MASK 0xFFC00000u +#define PMU_REG_3P0_CLR_RSVD2_SHIFT 22 +#define PMU_REG_3P0_CLR_RSVD2 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD2_SHIFT))&PMU_REG_3P0_CLR_RSVD2_MASK) +/* REG_3P0_TOG Bit Fields */ +#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_3P0_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_3P0_TOG_RSVD0_MASK 0x8u +#define PMU_REG_3P0_TOG_RSVD0_SHIFT 3 +#define PMU_REG_3P0_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_3P0_TOG_BO_OFFSET (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_3P0_TOG_BO_OFFSET_MASK) +#define PMU_REG_3P0_TOG_VBUS_SEL_MASK 0x80u +#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT 7 +#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_3P0_TOG_OUTPUT_TRG (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_TOG_RSVD1_MASK 0xE000u +#define PMU_REG_3P0_TOG_RSVD1_SHIFT 13 +#define PMU_REG_3P0_TOG_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD1_SHIFT))&PMU_REG_3P0_TOG_RSVD1_MASK) +#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK 0x10000u +#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT 16 +#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK 0x20000u +#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT 17 +#define PMU_REG_3P0_TOG_REG_TEST_MASK 0x3C0000u +#define PMU_REG_3P0_TOG_REG_TEST_SHIFT 18 +#define PMU_REG_3P0_TOG_REG_TEST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_REG_TEST_SHIFT))&PMU_REG_3P0_TOG_REG_TEST_MASK) +#define PMU_REG_3P0_TOG_RSVD2_MASK 0xFFC00000u +#define PMU_REG_3P0_TOG_RSVD2_SHIFT 22 +#define PMU_REG_3P0_TOG_RSVD2 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD2_SHIFT))&PMU_REG_3P0_TOG_RSVD2_MASK) +/* REF Bit Fields */ +#define PMU_REF_REFTOP_PWD_MASK 0x1u +#define PMU_REF_REFTOP_PWD_SHIFT 0 +#define PMU_REF_REFTOP_PWDVBGUP_MASK 0x2u +#define PMU_REF_REFTOP_PWDVBGUP_SHIFT 1 +#define PMU_REF_REFTOP_LOWPOWER_MASK 0x4u +#define PMU_REF_REFTOP_LOWPOWER_SHIFT 2 +#define PMU_REF_REFTOP_SELFBIASOFF_MASK 0x8u +#define PMU_REF_REFTOP_SELFBIASOFF_SHIFT 3 +#define PMU_REF_REFTOP_VBGADJ_MASK 0x70u +#define PMU_REF_REFTOP_VBGADJ_SHIFT 4 +#define PMU_REF_REFTOP_VBGADJ (x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_VBGADJ_SHIFT))&PMU_REF_REFTOP_VBGADJ_MASK) +#define PMU_REF_REFTOP_VBGUP_MASK 0x80u +#define PMU_REF_REFTOP_VBGUP_SHIFT 7 +#define PMU_REF_REFTOP_BIAS_TST_MASK 0x300u +#define PMU_REF_REFTOP_BIAS_TST_SHIFT 8 +#define PMU_REF_REFTOP_BIAS_TST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_BIAS_TST_SHIFT))&PMU_REF_REFTOP_BIAS_TST_MASK) +#define PMU_REF_LPBG_SEL_MASK 0x400u +#define PMU_REF_LPBG_SEL_SHIFT 10 +#define PMU_REF_LPBG_TEST_MASK 0x800u +#define PMU_REF_LPBG_TEST_SHIFT 11 +#define PMU_REF_REFTOP_IBIAS_OFF_MASK 0x1000u +#define PMU_REF_REFTOP_IBIAS_OFF_SHIFT 12 +#define PMU_REF_REFTOP_LINREGREF_EN_MASK 0x2000u +#define PMU_REF_REFTOP_LINREGREF_EN_SHIFT 13 +#define PMU_REF_RSVD1_MASK 0xFFFFC000u +#define PMU_REF_RSVD1_SHIFT 14 +#define PMU_REF_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_RSVD1_SHIFT))&PMU_REF_RSVD1_MASK) +/* REF_SET Bit Fields */ +#define PMU_REF_SET_REFTOP_PWD_MASK 0x1u +#define PMU_REF_SET_REFTOP_PWD_SHIFT 0 +#define PMU_REF_SET_REFTOP_PWDVBGUP_MASK 0x2u +#define PMU_REF_SET_REFTOP_PWDVBGUP_SHIFT 1 +#define PMU_REF_SET_REFTOP_LOWPOWER_MASK 0x4u +#define PMU_REF_SET_REFTOP_LOWPOWER_SHIFT 2 +#define PMU_REF_SET_REFTOP_SELFBIASOFF_MASK 0x8u +#define PMU_REF_SET_REFTOP_SELFBIASOFF_SHIFT 3 +#define PMU_REF_SET_REFTOP_VBGADJ_MASK 0x70u +#define PMU_REF_SET_REFTOP_VBGADJ_SHIFT 4 +#define PMU_REF_SET_REFTOP_VBGADJ (x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_VBGADJ_SHIFT))&PMU_REF_SET_REFTOP_VBGADJ_MASK) +#define PMU_REF_SET_REFTOP_VBGUP_MASK 0x80u +#define PMU_REF_SET_REFTOP_VBGUP_SHIFT 7 +#define PMU_REF_SET_REFTOP_BIAS_TST_MASK 0x300u +#define PMU_REF_SET_REFTOP_BIAS_TST_SHIFT 8 +#define PMU_REF_SET_REFTOP_BIAS_TST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_BIAS_TST_SHIFT))&PMU_REF_SET_REFTOP_BIAS_TST_MASK) +#define PMU_REF_SET_LPBG_SEL_MASK 0x400u +#define PMU_REF_SET_LPBG_SEL_SHIFT 10 +#define PMU_REF_SET_LPBG_TEST_MASK 0x800u +#define PMU_REF_SET_LPBG_TEST_SHIFT 11 +#define PMU_REF_SET_REFTOP_IBIAS_OFF_MASK 0x1000u +#define PMU_REF_SET_REFTOP_IBIAS_OFF_SHIFT 12 +#define PMU_REF_SET_REFTOP_LINREGREF_EN_MASK 0x2000u +#define PMU_REF_SET_REFTOP_LINREGREF_EN_SHIFT 13 +#define PMU_REF_SET_RSVD1_MASK 0xFFFFC000u +#define PMU_REF_SET_RSVD1_SHIFT 14 +#define PMU_REF_SET_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_RSVD1_SHIFT))&PMU_REF_SET_RSVD1_MASK) +/* REF_CLR Bit Fields */ +#define PMU_REF_CLR_REFTOP_PWD_MASK 0x1u +#define PMU_REF_CLR_REFTOP_PWD_SHIFT 0 +#define PMU_REF_CLR_REFTOP_PWDVBGUP_MASK 0x2u +#define PMU_REF_CLR_REFTOP_PWDVBGUP_SHIFT 1 +#define PMU_REF_CLR_REFTOP_LOWPOWER_MASK 0x4u +#define PMU_REF_CLR_REFTOP_LOWPOWER_SHIFT 2 +#define PMU_REF_CLR_REFTOP_SELFBIASOFF_MASK 0x8u +#define PMU_REF_CLR_REFTOP_SELFBIASOFF_SHIFT 3 +#define PMU_REF_CLR_REFTOP_VBGADJ_MASK 0x70u +#define PMU_REF_CLR_REFTOP_VBGADJ_SHIFT 4 +#define PMU_REF_CLR_REFTOP_VBGADJ (x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_VBGADJ_SHIFT))&PMU_REF_CLR_REFTOP_VBGADJ_MASK) +#define PMU_REF_CLR_REFTOP_VBGUP_MASK 0x80u +#define PMU_REF_CLR_REFTOP_VBGUP_SHIFT 7 +#define PMU_REF_CLR_REFTOP_BIAS_TST_MASK 0x300u +#define PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT 8 +#define PMU_REF_CLR_REFTOP_BIAS_TST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT))&PMU_REF_CLR_REFTOP_BIAS_TST_MASK) +#define PMU_REF_CLR_LPBG_SEL_MASK 0x400u +#define PMU_REF_CLR_LPBG_SEL_SHIFT 10 +#define PMU_REF_CLR_LPBG_TEST_MASK 0x800u +#define PMU_REF_CLR_LPBG_TEST_SHIFT 11 +#define PMU_REF_CLR_REFTOP_IBIAS_OFF_MASK 0x1000u +#define PMU_REF_CLR_REFTOP_IBIAS_OFF_SHIFT 12 +#define PMU_REF_CLR_REFTOP_LINREGREF_EN_MASK 0x2000u +#define PMU_REF_CLR_REFTOP_LINREGREF_EN_SHIFT 13 +#define PMU_REF_CLR_RSVD1_MASK 0xFFFFC000u +#define PMU_REF_CLR_RSVD1_SHIFT 14 +#define PMU_REF_CLR_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_RSVD1_SHIFT))&PMU_REF_CLR_RSVD1_MASK) +/* REF_TOG Bit Fields */ +#define PMU_REF_TOG_REFTOP_PWD_MASK 0x1u +#define PMU_REF_TOG_REFTOP_PWD_SHIFT 0 +#define PMU_REF_TOG_REFTOP_PWDVBGUP_MASK 0x2u +#define PMU_REF_TOG_REFTOP_PWDVBGUP_SHIFT 1 +#define PMU_REF_TOG_REFTOP_LOWPOWER_MASK 0x4u +#define PMU_REF_TOG_REFTOP_LOWPOWER_SHIFT 2 +#define PMU_REF_TOG_REFTOP_SELFBIASOFF_MASK 0x8u +#define PMU_REF_TOG_REFTOP_SELFBIASOFF_SHIFT 3 +#define PMU_REF_TOG_REFTOP_VBGADJ_MASK 0x70u +#define PMU_REF_TOG_REFTOP_VBGADJ_SHIFT 4 +#define PMU_REF_TOG_REFTOP_VBGADJ (x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_VBGADJ_SHIFT))&PMU_REF_TOG_REFTOP_VBGADJ_MASK) +#define PMU_REF_TOG_REFTOP_VBGUP_MASK 0x80u +#define PMU_REF_TOG_REFTOP_VBGUP_SHIFT 7 +#define PMU_REF_TOG_REFTOP_BIAS_TST_MASK 0x300u +#define PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT 8 +#define PMU_REF_TOG_REFTOP_BIAS_TST (x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT))&PMU_REF_TOG_REFTOP_BIAS_TST_MASK) +#define PMU_REF_TOG_LPBG_SEL_MASK 0x400u +#define PMU_REF_TOG_LPBG_SEL_SHIFT 10 +#define PMU_REF_TOG_LPBG_TEST_MASK 0x800u +#define PMU_REF_TOG_LPBG_TEST_SHIFT 11 +#define PMU_REF_TOG_REFTOP_IBIAS_OFF_MASK 0x1000u +#define PMU_REF_TOG_REFTOP_IBIAS_OFF_SHIFT 12 +#define PMU_REF_TOG_REFTOP_LINREGREF_EN_MASK 0x2000u +#define PMU_REF_TOG_REFTOP_LINREGREF_EN_SHIFT 13 +#define PMU_REF_TOG_RSVD1_MASK 0xFFFFC000u +#define PMU_REF_TOG_RSVD1_SHIFT 14 +#define PMU_REF_TOG_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_RSVD1_SHIFT))&PMU_REF_TOG_RSVD1_MASK) +/* LOWPWR_CTRL Bit Fields */ +#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK 0x3u +#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT 0 +#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK) +#define PMU_LOWPWR_CTRL_RSVD0_MASK 0xFCu +#define PMU_LOWPWR_CTRL_RSVD0_SHIFT 2 +#define PMU_LOWPWR_CTRL_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_RSVD0_MASK) +#define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK 0x100u +#define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT 8 +#define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK 0x200u +#define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT 9 +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK 0x400u +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT 10 +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK 0x800u +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT 11 +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK 0x1000u +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT 12 +#define PMU_LOWPWR_CTRL_GPU_PWRGATE_MASK 0x2000u +#define PMU_LOWPWR_CTRL_GPU_PWRGATE_SHIFT 13 +#define PMU_LOWPWR_CTRL_CONTROL0_MASK 0xFFC000u +#define PMU_LOWPWR_CTRL_CONTROL0_SHIFT 14 +#define PMU_LOWPWR_CTRL_CONTROL0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CONTROL0_MASK) +#define PMU_LOWPWR_CTRL_CONTROL1_MASK 0xFF000000u +#define PMU_LOWPWR_CTRL_CONTROL1_SHIFT 24 +#define PMU_LOWPWR_CTRL_CONTROL1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CONTROL1_MASK) +/* LOWPWR_CTRL_SET Bit Fields */ +#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK 0x3u +#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT 0 +#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK) +#define PMU_LOWPWR_CTRL_SET_RSVD0_MASK 0xFCu +#define PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT 2 +#define PMU_LOWPWR_CTRL_SET_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_SET_RSVD0_MASK) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK 0x100u +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT 8 +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK 0x200u +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT 9 +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK 0x400u +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT 10 +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11 +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK 0x1000u +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT 12 +#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK 0x2000u +#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT 13 +#define PMU_LOWPWR_CTRL_SET_CONTROL0_MASK 0xFFC000u +#define PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT 14 +#define PMU_LOWPWR_CTRL_SET_CONTROL0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL0_MASK) +#define PMU_LOWPWR_CTRL_SET_CONTROL1_MASK 0xFF000000u +#define PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT 24 +#define PMU_LOWPWR_CTRL_SET_CONTROL1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL1_MASK) +/* LOWPWR_CTRL_CLR Bit Fields */ +#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK 0x3u +#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT 0 +#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK) +#define PMU_LOWPWR_CTRL_CLR_RSVD0_MASK 0xFCu +#define PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT 2 +#define PMU_LOWPWR_CTRL_CLR_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_CLR_RSVD0_MASK) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK 0x100u +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT 8 +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK 0x200u +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT 9 +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK 0x400u +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT 10 +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11 +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK 0x1000u +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT 12 +#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK 0x2000u +#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT 13 +#define PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK 0xFFC000u +#define PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT 14 +#define PMU_LOWPWR_CTRL_CLR_CONTROL0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK) +#define PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK 0xFF000000u +#define PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT 24 +#define PMU_LOWPWR_CTRL_CLR_CONTROL1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK) +/* LOWPWR_CTRL_TOG Bit Fields */ +#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK 0x3u +#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT 0 +#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK) +#define PMU_LOWPWR_CTRL_TOG_RSVD0_MASK 0xFCu +#define PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT 2 +#define PMU_LOWPWR_CTRL_TOG_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_TOG_RSVD0_MASK) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK 0x100u +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT 8 +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK 0x200u +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT 9 +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK 0x400u +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT 10 +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11 +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK 0x1000u +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT 12 +#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK 0x2000u +#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT 13 +#define PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK 0xFFC000u +#define PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT 14 +#define PMU_LOWPWR_CTRL_TOG_CONTROL0 (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK) +#define PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK 0xFF000000u +#define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24 +#define PMU_LOWPWR_CTRL_TOG_CONTROL1 (x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK) + + +/* HW_ANADIG_TEMPSENSE0 Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK 0x3FE00u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK 0x7FC0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT 18 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK 0xF8000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT 27 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK) +/* HW_ANADIG_TEMPSENSE0_SET Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK 0x3FE00u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK 0x7FC0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT 18 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK 0xF8000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT 27 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK) +/* HW_ANADIG_TEMPSENSE0_CLR Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK 0x3FE00u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK 0x7FC0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT 18 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT 27 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK) +/* HW_ANADIG_TEMPSENSE0_TOG Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK 0x3FE00u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK 0x7FC0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT 18 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK 0xF8000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT 27 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK) +/* HW_ANADIG_TEMPSENSE1 Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK 0x200u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK 0x400u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_SHIFT 10 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK 0x800u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_SHIFT 11 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK 0xF000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT 12 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK 0xFFFF0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT 16 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK) +/* HW_ANADIG_TEMPSENSE1_SET Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_MASK 0x200u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_MASK 0x400u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_SHIFT 10 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_MASK 0x800u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_SHIFT 11 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK 0xF000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT 12 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFF0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT 16 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK) +/* HW_ANADIG_TEMPSENSE1_CLR Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_MASK 0x200u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_MASK 0x400u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_SHIFT 10 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_MASK 0x800u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_SHIFT 11 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK 0xF000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT 12 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFF0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT 16 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) +/* HW_ANADIG_TEMPSENSE1_TOG Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_MASK 0x200u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_MASK 0x400u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_SHIFT 10 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_MASK 0x800u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_SHIFT 11 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK 0xF000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT 12 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFF0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT 16 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) +/* HW_ANADIG_TEMPSENSE_TRIM Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK 0x1Fu +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK 0x60u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT 5 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_MASK 0x80u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_SHIFT 7 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK 0x1FF00u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT 8 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK 0xE0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT 17 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK 0xF00000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT 20 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK 0x1F000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT 24 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK 0xE0000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT 29 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK) +/* HW_ANADIG_TEMPSENSE_TRIM_SET Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK 0x1Fu +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK 0x60u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT 5 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_MASK 0x80u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_SHIFT 7 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK 0x1FF00u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT 8 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK 0xE0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT 17 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK 0xF00000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT 20 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK 0x1F000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT 24 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK 0xE0000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT 29 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK) +/* HW_ANADIG_TEMPSENSE_TRIM_CLR Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK 0x1Fu +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK 0x60u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT 5 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_MASK 0x80u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_SHIFT 7 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK 0x1FF00u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT 8 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK 0xE0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT 17 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK 0xF00000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT 20 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK 0x1F000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT 24 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK 0xE0000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT 29 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK) +/* HW_ANADIG_TEMPSENSE_TRIM_TOG Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK 0x1Fu +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK 0x60u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT 5 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_MASK 0x80u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_SHIFT 7 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK 0x1FF00u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT 8 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK 0xE0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT 17 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK 0xF00000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT 20 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK 0x1F000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT 24 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2 (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK 0xE0000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR (x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK) + + +#define CCM_GPR (i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i)) +#define CCM_OBSERVE (i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i)) +#define CCM_SCTRL (i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i)) +#define CCM_CCGR (i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i)) +#define CCM_ROOT_TARGET (i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i)) + +#define CCM_GPR_SET (i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 4) +#define CCM_OBSERVE_SET (i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4) +#define CCM_SCTRL_SET (i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4) +#define CCM_CCGR_SET (i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 4) +#define CCM_ROOT_TARGET_SET (i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4) + +#define CCM_GPR_CLR (i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 8) +#define CCM_OBSERVE_CLR (i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8) +#define CCM_SCTRL_CLR (i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8) +#define CCM_CCGR_CLR (i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 8) +#define CCM_ROOT_TARGET_CLR (i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8) + +#define CCM_GPR_TOGGLE (i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 12) +#define CCM_OBSERVE_TOGGLE (i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12) +#define CCM_SCTRL_TOGGLE (i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12) +#define CCM_CCGR_TOGGLE (i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 12) +#define CCM_ROOT_TARGET_TOGGLE (i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12) + +#define HW_CCM_GPR_WR (i, v) writel((v), CCM_GPR(i)) +#define HW_CCM_CCM_OBSERVE_WR (i, v) writel((v), CCM_OBSERVE(i)) +#define HW_CCM_SCTRL_WR (i, v) writel((v), CCM_SCTRL(i)) +#define HW_CCM_CCGR_WR (i, v) writel((v), CCM_CCGR(i)) +#define HW_CCM_ROOT_TARGET_WR (i, v) writel((v), CCM_ROOT_TARGET(i)) + +#define HW_CCM_GPR_RD (i) readl(CCM_GPR(i)) +#define HW_CCM_CCM_OBSERVE_RD (i) readl(CCM_OBSERVE(i)) +#define HW_CCM_SCTRL_RD (i) readl(CCM_SCTRL(i)) +#define HW_CCM_CCGR_RD (i) readl(CCM_CCGR(i)) +#define HW_CCM_ROOT_TARGET_RD (i) readl(CCM_ROOT_TARGET(i)) + +#define HW_CCM_GPR_SET (i, v) writel((v), CCM_GPR_SET(i)) +#define HW_CCM_CCM_OBSERVE_SET (i, v) writel((v), CCM_CCM_OBSERVE_SET(i)) +#define HW_CCM_SCTRL_SET (i, v) writel((v), CCM_SCTRL_SET(i)) +#define HW_CCM_CCGR_SET (i, v) writel((v), CCM_CCGR_SET(i)) +#define HW_CCM_ROOT_TARGET_SET (i, v) writel((v), CCM_ROOT_TARGET_SET(i)) + +#define HW_CCM_GPR_CLR (i, v) writel((v), CCM_GPR_CLR(i)) +#define HW_CCM_CCM_OBSERVE_CLR (i, v) writel((v), CCM_CCM_OBSERVE_CLR(i)) +#define HW_CCM_SCTRL_CLR (i, v) writel((v), CCM_SCTRL_CLR(i)) +#define HW_CCM_CCGR_CLR (i, v) writel((v), CCM_CCGR_CLR(i)) +#define HW_CCM_ROOT_TARGET_CLR (i, v) writel((v), CCM_ROOT_TARGET_CLR(i)) + +#define HW_CCM_GPR_TOGGLE (i, v) writel((v), CCM_GPR_TOGGLE(i)) +#define HW_CCM_CCM_OBSERVE_TOGGLE (i, v) writel((v), CCM_CCM_OBSERVE_TOGGLE(i)) +#define HW_CCM_SCTRL_TOGGLE (i, v) writel((v), CCM_SCTRL_TOGGLE(i)) +#define HW_CCM_CCGR_TOGGLE (i, v) writel((v), CCM_CCGR_TOGGLE(i)) +#define HW_CCM_ROOT_TARGET_TOGGLE (i, v) writel((v), CCM_ROOT_TARGET_TOGGLE(i)) + +#define CCM_CLK_ON_MSK 0x03 + +#define CCM_ROOT_TGT_POST_DIV_SHIFT 0 +#define CCM_ROOT_TGT_PRE_DIV_SHIFT 15 +#define CCM_ROOT_TGT_MUX_SHIFT 24 +#define CCM_ROOT_TGT_ENABLE_SHIFT 28 +#define CCM_ROOT_TGT_POST_DIV_MSK 0x3F +#define CCM_ROOT_TGT_PRE_DIV_MSK (0x07 << CCM_ROOT_TGT_PRE_DIV_SHIFT) +#define CCM_ROOT_TGT_MUX_MSK (0x07 << CCM_ROOT_TGT_MUX_SHIFT) +#define CCM_ROOT_TGT_ENABLE_MSK (0x01 << CCM_ROOT_TGT_ENABLE_SHIFT) + +#define CCM_ROOT_TGT_POST_DIV (x) ((((x) - 1) << CCM_ROOT_TGT_POST_DIV_SHIFT) & CCM_ROOT_TGT_POST_DIV_MSK) +#define CCM_ROOT_TGT_PRE_DIV (x) ((((x) - 1) << CCM_ROOT_TGT_PRE_DIV_SHIFT) & CCM_ROOT_TGT_PRE_DIV_MSK) +#define CCM_ROOT_TGT_MUX_TO (x) ((((x) - 1) << CCM_ROOT_TGT_MUX_SHIFT) & CCM_ROOT_TGT_MUX_MSK) + +/* +* Field values definition for clock slice TARGET register +*/ + +#define CLK_ROOT_ON 0x10000000 +#define CLK_ROOT_OFF 0x0 +#define CLK_ROOT_ENABLE_MASK 0x10000000 +#define CLK_ROOT_ENABLE_SHIFT 28 + +#define CLK_ROOT_ALT0 0x00000000 +#define CLK_ROOT_ALT1 0x01000000 +#define CLK_ROOT_ALT2 0x02000000 +#define CLK_ROOT_ALT3 0x03000000 +#define CLK_ROOT_ALT4 0x04000000 +#define CLK_ROOT_ALT5 0x05000000 +#define CLK_ROOT_ALT6 0x06000000 +#define CLK_ROOT_ALT7 0x07000000 + + +#define DRAM_CLK_ROOT_POST_DIV_MASK 0x00000007 +#define CLK_ROOT_POST_DIV_MASK 0x0000003f +#define CLK_ROOT_POST_DIV_SHIFT 0 +#define CLK_ROOT_POST_DIV (n) ((n << CLK_ROOT_POST_DIV_SHIFT) & CLK_ROOT_POST_DIV_MASK) + +#define CLK_ROOT_AUTO_DIV_MASK 0x00000700 +#define CLK_ROOT_AUTO_DIV_SHIFT 8 +#define CLK_ROOT_AUTO_DIV (n) ((n << CLK_ROOT_AUTO_DIV_SHIFT) & CLK_ROOT_AUTO_DIV_MASK) + +#define CLK_ROOT_AUTO_EN_MASK 0x00001000 +#define CLK_ROOT_AUTO_EN 0x00001000 + +#define CLK_ROOT_PRE_DIV_MASK 0x00070000 +#define CLK_ROOT_PRE_DIV_SHIFT 16 +#define CLK_ROOT_PRE_DIV (n) ((n << CLK_ROOT_PRE_DIV_SHIFT) & CLK_ROOT_PRE_DIV_MASK) + +#define CLK_ROOT_MUX_MASK 0x07000000 +#define CLK_ROOT_MUX_SHIFT 24 + +#define CLK_ROOT_EN_MASK 0x10000000 + +#define CLK_ROOT_AUTO_ON 0x00001000 +#define CLK_ROOT_AUTO_OFF 0x0 + +/* ARM_A7_CLK_ROOT */ +#define ARM_A7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ARM_A7_CLK_ROOT_FROM_PLL_ARM_MAIN_800M_CLK 0x01000000 +#define ARM_A7_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x03000000 +#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000 +#define ARM_A7_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000 +#define ARM_A7_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define ARM_A7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* ARM_M4_CLK_ROOT */ +#define ARM_M4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ARM_M4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 +#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000 +#define ARM_M4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x02000000 +#define ARM_M4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define ARM_M4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define ARM_M4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* ARM_M0_CLK_ROOT */ +#define ARM_M0_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ARM_M0_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 +#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x03000000 +#define ARM_M0_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x02000000 +#define ARM_M0_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define ARM_M0_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define ARM_M0_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* MAIN_AXI_CLK_ROOT */ +#define MAIN_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define MAIN_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 +#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000 +#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define MAIN_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 +#define MAIN_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define MAIN_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 + +/* DISP_AXI_CLK_ROOT */ +#define DISP_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define DISP_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 +#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x04000000 +#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000 +#define DISP_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 +#define DISP_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define DISP_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 + +/* ENET_AXI_CLK_ROOT */ +#define ENET_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 + +/* NAND_USDHC_BUS_CLK_ROOT */ +#define NAND_USDHC_BUS_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x03000000 +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000 +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x04000000 +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000 +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 + +/* AHB_CLK_ROOT */ +#define AHB_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define AHB_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000 +#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define AHB_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 +#define AHB_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define AHB_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define AHB_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 + +/* DRAM_PHYM_CLK_ROOT */ +#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000 +#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_PHYM_ALT_CLK_ROOT 0x01000000 + +/* DRAM_CLK_ROOT */ +#define DRAM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000 +#define DRAM_CLK_ROOT_FROM_PLL_DRAM_ALT_CLK_ROOT 0x01000000 + +/* DRAM_PHYM_ALT_CLK_ROOT */ +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000 +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000 +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000 +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 + +/* DRAM_ALT_CLK_ROOT */ +#define DRAM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define DRAM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000 +#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000 +#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000 +#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x07000000 +#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 +#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x04000000 +#define DRAM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 + +/* USB_HSIC_CLK_ROOT */ +#define USB_HSIC_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x03000000 +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x05000000 +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define USB_HSIC_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x02000000 + +/* PCIE_CTRL_CLK_ROOT */ +#define PCIE_CTRL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000 +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x06000000 +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000 +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x07000000 +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x01000000 + +/* PCIE_PHY_CLK_ROOT */ +#define PCIE_PHY_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define PCIE_PHY_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x07000000 +#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000 +#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 +#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 +#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 +#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 + +/* EPDC_PIXEL_CLK_ROOT */ +#define EPDC_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000 +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000 +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x06000000 +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 + +/* LCDIF_PIXEL_CLK_ROOT */ +#define LCDIF_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000 +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define LCDIF_PIXEL_CLK_ROOT_FROM_EXT_CLK_3 0x03000000 + +/* MIPI_DSI_EXTSER_CLK_ROOT */ +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000 +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000 +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000 +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000 +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 + +/* MIPI_CSI_WARP_CLK_ROOT */ +#define MIPI_CSI_WARP_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000 +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000 +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000 +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000 +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 + +/* MIPI_DPHY_REF_CLK_ROOT */ +#define MIPI_DPHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x03000000 +#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define MIPI_DPHY_REF_CLK_ROOT_FROM_REF_1M_CLK 0x04000000 +#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 + +/* SAI1_CLK_ROOT */ +#define SAI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define SAI1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define SAI1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 +#define SAI1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 +#define SAI1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define SAI1_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 + +/* SAI2_CLK_ROOT */ +#define SAI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define SAI2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define SAI2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 +#define SAI2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 +#define SAI2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define SAI2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 + +/* SAI3_CLK_ROOT */ +#define SAI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define SAI3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define SAI3_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 +#define SAI3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 +#define SAI3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define SAI3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 + +/* SPDIF_CLK_ROOT */ +#define SPDIF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define SPDIF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define SPDIF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 +#define SPDIF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 +#define SPDIF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define SPDIF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 + +/* ENET1_REF_CLK_ROOT */ +#define ENET1_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define ENET1_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 + +/* ENET1_TIME_CLK_ROOT */ +#define ENET1_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define ENET1_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 +#define ENET1_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 +#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 +#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 +#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 + +/* ENET2_REF_CLK_ROOT */ +#define ENET2_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ENET2_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000 +#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 +#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 +#define ENET2_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define ENET2_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define ENET2_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 + +/* ENET2_TIME_CLK_ROOT */ +#define ENET2_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define ENET2_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 +#define ENET2_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 +#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 +#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 +#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 + +/* ENET_PHY_REF_CLK_ROOT */ +#define ENET_PHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x07000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x03000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 + +/* EIM_CLK_ROOT */ +#define EIM_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define EIM_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x04000000 +#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x05000000 +#define EIM_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 +#define EIM_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* NAND_CLK_ROOT */ +#define NAND_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define NAND_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define NAND_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 +#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000 +#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000 +#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 +#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 +#define NAND_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 + +/* QSPI_CLK_ROOT */ +#define QSPI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define QSPI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000 +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000 +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define QSPI_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 + +/* USDHC1_CLK_ROOT */ +#define USDHC1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define USDHC1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define USDHC1_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 + +/* USDHC2_CLK_ROOT */ +#define USDHC2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define USDHC2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define USDHC2_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 + +/* USDHC3_CLK_ROOT */ +#define USDHC3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define USDHC3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define USDHC3_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 + +/* CAN1_CLK_ROOT */ +#define CAN1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define CAN1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 +#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define CAN1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000 +#define CAN1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 +#define CAN1_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 +#define CAN1_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 + +/* CAN2_CLK_ROOT */ +#define CAN2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define CAN2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 +#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define CAN2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000 +#define CAN2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 +#define CAN2_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 +#define CAN2_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 + +/* I2C1_CLK_ROOT */ +#define I2C1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define I2C1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define I2C1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 +#define I2C1_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define I2C1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define I2C1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 +#define I2C1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 + +/* I2C2_CLK_ROOT */ +#define I2C2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define I2C2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define I2C2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define I2C2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 +#define I2C2_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define I2C2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define I2C2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 +#define I2C2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 + +/* I2C3_CLK_ROOT */ +#define I2C3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define I2C3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define I2C3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define I2C3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 +#define I2C3_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define I2C3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define I2C3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 +#define I2C3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 + +/* I2C4_CLK_ROOT */ +#define I2C4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define I2C4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define I2C4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define I2C4_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 +#define I2C4_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define I2C4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define I2C4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 +#define I2C4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 + +/* UART1_CLK_ROOT */ +#define UART1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 +#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define UART1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define UART1_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define UART1_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 + +/* UART2_CLK_ROOT */ +#define UART2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 +#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define UART2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define UART2_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define UART2_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 + +/* UART3_CLK_ROOT */ +#define UART3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 +#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define UART3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define UART3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define UART3_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 + +/* UART4_CLK_ROOT */ +#define UART4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 +#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define UART4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define UART4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define UART4_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 + +/* UART5_CLK_ROOT */ +#define UART5_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 +#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define UART5_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define UART5_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define UART5_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 + +/* UART6_CLK_ROOT */ +#define UART6_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 +#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define UART6_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define UART6_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define UART6_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 + +/* UART7_CLK_ROOT */ +#define UART7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 +#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define UART7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define UART7_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define UART7_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 + +/* ECSPI1_CLK_ROOT */ +#define ECSPI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 +#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 +#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define ECSPI1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* ECSPI2_CLK_ROOT */ +#define ECSPI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 +#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 +#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define ECSPI2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* ECSPI3_CLK_ROOT */ +#define ECSPI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 +#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 +#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define ECSPI3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* ECSPI4_CLK_ROOT */ +#define ECSPI4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 +#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 +#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define ECSPI4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* PWM1_CLK_ROOT */ +#define PWM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define PWM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define PWM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define PWM1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define PWM1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 +#define PWM1_CLK_ROOT_FROM_EXT_CLK_1 0x05000000 + +/* PWM2_CLK_ROOT */ +#define PWM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define PWM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define PWM2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define PWM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define PWM2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 +#define PWM2_CLK_ROOT_FROM_EXT_CLK_1 0x05000000 + +/* PWM3_CLK_ROOT */ +#define PWM3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define PWM3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define PWM3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define PWM3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define PWM3_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 +#define PWM3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 + +/* PWM4_CLK_ROOT */ +#define PWM4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define PWM4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define PWM4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define PWM4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define PWM4_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 +#define PWM4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 + +/* FLEXTIMER1_CLK_ROOT */ +#define FLEXTIMER1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define FLEXTIMER1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 +#define FLEXTIMER1_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 + +/* FLEXTIMER2_CLK_ROOT */ +#define FLEXTIMER2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define FLEXTIMER2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 +#define FLEXTIMER2_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 + +/* SIM1_CLK_ROOT */ +#define SIM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define SIM1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define SIM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define SIM1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 +#define SIM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define SIM1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 + +/* SIM2_CLK_ROOT */ +#define SIM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define SIM2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define SIM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define SIM2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 +#define SIM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 +#define SIM2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 + +/* GPT1_CLK_ROOT */ +#define GPT1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define GPT1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 +#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define GPT1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define GPT1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define GPT1_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 +#define GPT1_CLK_ROOT_FROM_EXT_CLK_1 0x07000000 + +/* GPT2_CLK_ROOT */ +#define GPT2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define GPT2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 +#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define GPT2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define GPT2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define GPT2_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 +#define GPT2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 + +/* GPT3_CLK_ROOT */ +#define GPT3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define GPT3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 +#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define GPT3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define GPT3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define GPT3_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 +#define GPT3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 + +/* GPT4_CLK_ROOT */ +#define GPT4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define GPT4_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 +#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define GPT4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define GPT4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define GPT4_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 +#define GPT4_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 + +/* TRACE_CLK_ROOT */ +#define TRACE_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define TRACE_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define TRACE_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define TRACE_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define TRACE_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 +#define TRACE_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 +#define TRACE_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 +#define TRACE_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 + +/* WDOG_CLK_ROOT */ +#define WDOG_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define WDOG_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define WDOG_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD1_166M_CLK 0x07000000 +#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define WDOG_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 +#define WDOG_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 +#define WDOG_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 + +/* CSI_MCLK_CLK_ROOT */ +#define CSI_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define CSI_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define CSI_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 +#define CSI_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define CSI_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define CSI_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* AUDIO_MCLK_CLK_ROOT */ +#define AUDIO_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* WRCLK_CLK_ROOT */ +#define WRCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define WRCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define WRCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000 +#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 +#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x06000000 +#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x01000000 +#define WRCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x03000000 + +/* IPP_DO_CLKO1 */ +#define IPP_DO_CLKO1_FROM_OSC_24M_CLK 0x00000000 +#define IPP_DO_CLKO1_FROM_PLL_DRAM_MAIN_533M_CLK 0x06000000 +#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 +#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000 +#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD0_196M_CLK 0x03000000 +#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD3_CLK 0x04000000 +#define IPP_DO_CLKO1_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 +#define IPP_DO_CLKO1_FROM_REF_1M_CLK 0x07000000 + +/* IPP_DO_CLKO2 */ +#define IPP_DO_CLKO2_FROM_OSC_24M_CLK 0x00000000 +#define IPP_DO_CLKO2_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 +#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD1_166M_CLK 0x03000000 +#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD4_CLK 0x04000000 +#define IPP_DO_CLKO2_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define IPP_DO_CLKO2_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define IPP_DO_CLKO2_FROM_OSC_32K_CLK 0x07000000 + +#endif
arch/arm/include/asm/arch-mx7/imx-regs.h new file +1303 -0
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arch/arm/include/asm/arch-mx7/sys_proto.h new file +42 -0
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Signature · 1 line
2.1.4
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PATCH v4 8/13 imx: imx7d: clock control module support
In reply to Adrian Alonso* Add Clock control module (CCM) support
* iMX7D SoC introduces 3 main clock sysmtem abstraction for clock root frequency generation denominated clock slices. Core clock slice: hihg speed clock for ARM core
Bus clock slice: for bus clocks
IP clock slice: Peripheral clocks
* At system boot ROM enables PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET In u-boot, we have to:
- Configure PFD3- PFD7 for freq we needed in u-boot
- Set clock root for peripherals (ip channel)
Signed-off-by Adrian Alonso <[email protected]>
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Ye.Li <[email protected]>
---
Changes for V2: Split from patch imx: imx7d: initial arch level support Changes for V3: Resend
Changes for V4: Resend
arch/arm/cpu/armv7/mx7/clock.c | 1130 +++++++++++++++++++++++++++ arch/arm/cpu/armv7/mx7/clock_slice.c | 757 ++++++++++++++++++ arch/arm/include/asm/arch-mx7/clock.h | 348 +++++++++ arch/arm/include/asm/arch-mx7/clock_slice.h | 116 +++ 4 files changed, 2351 insertions(+) create mode 100644 arch/arm/cpu/armv7/mx7/clock.c create mode 100644 arch/arm/cpu/armv7/mx7/clock_slice.c create mode 100644 arch/arm/include/asm/arch-mx7/clock.h create mode 100644 arch/arm/include/asm/arch-mx7/clock_slice.h
arch/arm/cpu/armv7/mx7/clock.c new file +1130 -0
@@ -0,0 +1,1130 @@ +/* +* Copyright (C) 2015 Freescale Semiconductor, Inc. +* +* Author: +* Peng Fan <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <div64.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) +ANATOP_BASE_ADDR ; +struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR ; + +#ifdef CONFIG_FSL_ESDHC +DECLARE_GLOBAL_DATA_PTR ; +#endif + +int get_clocks (void ) +{ +#ifdef CONFIG_FSL_ESDHC +#if CONFIG_SYS_FSL_ESDHC_ADDR ==USDHC2_BASE_ADDR + gd->arch.sdhc_clk =mxc_get_clock (MXC_ESDHC2_CLK ); +#elif CONFIG_SYS_FSL_ESDHC_ADDR ==USDHC3_BASE_ADDR + gd->arch.sdhc_clk =mxc_get_clock (MXC_ESDHC3_CLK ); +#else + gd->arch.sdhc_clk =mxc_get_clock (MXC_ESDHC_CLK ); +#endif +#endif +return 0 ; +} + +u32 get_ahb_clk (void ) +{ +return get_root_clk (AHB_CLK_ROOT ); +} + +static u32 get_ipg_clk (void ) +{ +/* +* The AHB and IPG are fixed at 2:1 ratio, and synchronized to +* each other. +*/ +return get_ahb_clk () /2 ; +} + +u32 imx_get_uartclk (void ) +{ +return get_root_clk (UART1_CLK_ROOT ); +} + +u32 imx_get_fecclk (void ) +{ +return get_root_clk (ENET_AXI_CLK_ROOT ); +} + +#ifdef CONFIG_MXC_OCOTP +void enable_ocotp_clk (unsigned char enable) +{ +clock_enable (CCGR_OCOTP , enable); +} + +void enable_thermal_clk (void ) +{ +enable_ocotp_clk (1 ); +} +#endif + +void enable_usboh3_clk (unsigned char enable) +{ +u32 target; + +if (enable) { +/* disable the clock gate first */ +clock_enable (CCGR_USB_HSIC ,0 ); + +/* 120Mhz */ + target =CLK_ROOT_ON |USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV1 ); +clock_set_target_val (USB_HSIC_CLK_ROOT , target); + +/* enable the clock gate */ +clock_enable (CCGR_USB_CTRL ,1 ); +clock_enable (CCGR_USB_HSIC ,1 ); +clock_enable (CCGR_USB_PHY1 ,1 ); +clock_enable (CCGR_USB_PHY2 ,1 ); + }else { +clock_enable (CCGR_USB_CTRL ,0 ); +clock_enable (CCGR_USB_HSIC ,0 ); +clock_enable (CCGR_USB_PHY1 ,0 ); +clock_enable (CCGR_USB_PHY2 ,0 ); + } + +} + +static u32 decode_pll (enum pll_clocks pll,u32 infreq) +{ +u32 reg, div_sel; +u32 num, denom; + +/* +* Alought there are four choices for the bypass src, +* we choose OSC_24M which is the default set in ROM. +*/ +switch (pll) { +case PLL_CORE : + reg =readl (&ccm_anatop->pll_arm); + +if (reg &CCM_ANALOG_PLL_ARM_POWERDOWN_MASK ) +return 0 ; + +if (reg &CCM_ANALOG_PLL_ARM_BYPASS_MASK ) +return MXC_HCLK ; + + div_sel = (reg &CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK ) >> +CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT ; + +return (infreq * div_sel) /2 ; + +case PLL_SYS : + reg =readl (&ccm_anatop->pll_480); + +if (reg &CCM_ANALOG_PLL_480_POWERDOWN_MASK ) +return 0 ; + +if (reg &CCM_ANALOG_PLL_480_BYPASS_MASK ) +return MXC_HCLK ; + +if (((reg &CCM_ANALOG_PLL_480_DIV_SELECT_MASK ) >> +CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT ) ==0 ) +return 480000000u ; +else +return 528000000u ; + +case PLL_ENET : + reg =readl (&ccm_anatop->pll_enet); + +if (reg &CCM_ANALOG_PLL_ENET_POWERDOWN_MASK ) +return 0 ; + +if (reg &CCM_ANALOG_PLL_ENET_BYPASS_MASK ) +return MXC_HCLK ; + +return 1000000000u ; + +case PLL_DDR : + reg =readl (&ccm_anatop->pll_ddr); + +if (reg &CCM_ANALOG_PLL_DDR_POWERDOWN_MASK ) +return 0 ; + + num = ccm_anatop->pll_ddr_num; + denom = ccm_anatop->pll_ddr_denom; + +if (reg &CCM_ANALOG_PLL_DDR_BYPASS_MASK ) +return MXC_HCLK ; + + div_sel = (reg &CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK ) >> +CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT ; + +return infreq * (div_sel + num / denom); + +case PLL_USB : +return 480000000u ; + +default : +printf ("Unsupported pll clocks %d\n" , pll); +break ; + } + +return 0 ; +} + +static u32 mxc_get_pll_sys_derive (int derive) +{ +u32 freq, div, frac; +u32 reg; + + div =1 ; + reg =readl (&ccm_anatop->pll_480); + freq =decode_pll (PLL_SYS ,MXC_HCLK ); + +switch (derive) { +case PLL_SYS_MAIN_480M_CLK : +if (reg &CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK ) +return 0 ; +else +return freq; +case PLL_SYS_MAIN_240M_CLK : +if (reg &CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK ) +return 0 ; +else +return freq /2 ; +case PLL_SYS_MAIN_120M_CLK : +if (reg &CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK ) +return 0 ; +else +return freq /4 ; +case PLL_SYS_PFD0_392M_CLK : + reg =readl (&ccm_anatop->pfd_480a); +if (reg &CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK ) +return 0 ; + frac = (reg &CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK ) >> +CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT ; +break ; +case PLL_SYS_PFD0_196M_CLK : +if (reg &CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK ) +return 0 ; + reg =readl (&ccm_anatop->pfd_480a); + frac = (reg &CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK ) >> +CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT ; + div =2 ; +break ; +case PLL_SYS_PFD1_332M_CLK : + reg =readl (&ccm_anatop->pfd_480a); +if (reg &CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK ) +return 0 ; + frac = (reg &CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK ) >> +CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT ; +break ; +case PLL_SYS_PFD1_166M_CLK : +if (reg &CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK ) +return 0 ; + reg =readl (&ccm_anatop->pfd_480a); + frac = (reg &CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK ) >> +CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT ; + div =2 ; +break ; +case PLL_SYS_PFD2_270M_CLK : + reg =readl (&ccm_anatop->pfd_480a); +if (reg &CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK ) +return 0 ; + frac = (reg &CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK ) >> +CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT ; +break ; +case PLL_SYS_PFD2_135M_CLK : +if (reg &CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK ) +return 0 ; + reg =readl (&ccm_anatop->pfd_480a); + frac = (reg &CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK ) >> +CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT ; + div =2 ; +break ; +case PLL_SYS_PFD3_CLK : + reg =readl (&ccm_anatop->pfd_480a); +if (reg &CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK ) +return 0 ; + frac = (reg &CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK ) >> +CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT ; +break ; +case PLL_SYS_PFD4_CLK : + reg =readl (&ccm_anatop->pfd_480b); +if (reg &CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK ) +return 0 ; + frac = (reg &CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK ) >> +CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT ; +break ; +case PLL_SYS_PFD5_CLK : + reg =readl (&ccm_anatop->pfd_480b); +if (reg &CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK ) +return 0 ; + frac = (reg &CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK ) >> +CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT ; +break ; +case PLL_SYS_PFD6_CLK : + reg =readl (&ccm_anatop->pfd_480b); +if (reg &CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK ) +return 0 ; + frac = (reg &CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK ) >> +CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT ; +break ; +case PLL_SYS_PFD7_CLK : + reg =readl (&ccm_anatop->pfd_480b); +if (reg &CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK ) +return 0 ; + frac = (reg &CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK ) >> +CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT ; +break ; +default : +printf ("Error derived pll_sys clock %d\n" , derive); +return 0 ; + } + +return ((freq / frac) *18 ) / div; +} + +static u32 mxc_get_pll_enet_derive (int derive) +{ +u32 freq, reg; + + freq =decode_pll (PLL_ENET ,MXC_HCLK ); + reg =readl (&ccm_anatop->pll_enet); + +switch (derive) { +case PLL_ENET_MAIN_500M_CLK : +if (reg &CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK ) +return freq /2 ; +break ; +case PLL_ENET_MAIN_250M_CLK : +if (reg &CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK ) +return freq /4 ; +break ; +case PLL_ENET_MAIN_125M_CLK : +if (reg &CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK ) +return freq /8 ; +break ; +case PLL_ENET_MAIN_100M_CLK : +if (reg &CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK ) +return freq /10 ; +break ; +case PLL_ENET_MAIN_50M_CLK : +if (reg &CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK ) +return freq /20 ; +break ; +case PLL_ENET_MAIN_40M_CLK : +if (reg &CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK ) +return freq /25 ; +break ; +case PLL_ENET_MAIN_25M_CLK : +if (reg &CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK ) +return freq /40 ; +break ; +default : +printf ("Error derived pll_enet clock %d\n" , derive); +break ; + } + +return 0 ; +} + +static u32 mxc_get_pll_ddr_derive (int derive) +{ +u32 freq, reg; + + freq =decode_pll (PLL_DDR ,MXC_HCLK ); + reg =readl (&ccm_anatop->pll_ddr); + +switch (derive) { +case PLL_DRAM_MAIN_1066M_CLK : +return freq; +case PLL_DRAM_MAIN_533M_CLK : +if (reg &CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK ) +return freq /2 ; +break ; +default : +printf ("Error derived pll_ddr clock %d\n" , derive); +break ; + } + +return 0 ; +} + +static u32 mxc_get_pll_derive (enum pll_clocks pll,int derive) +{ +switch (pll) { +case PLL_SYS : +return mxc_get_pll_sys_derive (derive); +case PLL_ENET : +return mxc_get_pll_enet_derive (derive); +case PLL_DDR : +return mxc_get_pll_ddr_derive (derive); +default : +printf ("Error pll.\n" ); +return 0 ; + } +} + +static u32 get_root_src_clk (enum clk_root_src root_src) +{ +switch (root_src) { +case OSC_24M_CLK : +return 24000000u ; +case PLL_ARM_MAIN_800M_CLK : +return decode_pll (PLL_CORE ,MXC_HCLK ); + +case PLL_SYS_MAIN_480M_CLK : +case PLL_SYS_MAIN_240M_CLK : +case PLL_SYS_MAIN_120M_CLK : +case PLL_SYS_PFD0_392M_CLK : +case PLL_SYS_PFD0_196M_CLK : +case PLL_SYS_PFD1_332M_CLK : +case PLL_SYS_PFD1_166M_CLK : +case PLL_SYS_PFD2_270M_CLK : +case PLL_SYS_PFD2_135M_CLK : +case PLL_SYS_PFD3_CLK : +case PLL_SYS_PFD4_CLK : +case PLL_SYS_PFD5_CLK : +case PLL_SYS_PFD6_CLK : +case PLL_SYS_PFD7_CLK : +return mxc_get_pll_derive (PLL_SYS , root_src); + +case PLL_ENET_MAIN_500M_CLK : +case PLL_ENET_MAIN_250M_CLK : +case PLL_ENET_MAIN_125M_CLK : +case PLL_ENET_MAIN_100M_CLK : +case PLL_ENET_MAIN_50M_CLK : +case PLL_ENET_MAIN_40M_CLK : +case PLL_ENET_MAIN_25M_CLK : +return mxc_get_pll_derive (PLL_ENET , root_src); + +case PLL_DRAM_MAIN_1066M_CLK : +case PLL_DRAM_MAIN_533M_CLK : +return mxc_get_pll_derive (PLL_DDR , root_src); + +case PLL_AUDIO_MAIN_CLK : +return decode_pll (PLL_AUDIO ,MXC_HCLK ); +case PLL_VIDEO_MAIN_CLK : +return decode_pll (PLL_VIDEO ,MXC_HCLK ); + +case PLL_USB_MAIN_480M_CLK : +return decode_pll (PLL_USB ,MXC_HCLK ); + +case REF_1M_CLK : +return 1000000 ; +case OSC_32K_CLK : +return MXC_CLK32 ; + +case EXT_CLK_1 : +case EXT_CLK_2 : +case EXT_CLK_3 : +case EXT_CLK_4 : +printf ("No EXT CLK supported??\n" ); +break ; + }; + +return 0 ; +} + +u32 get_root_clk (enum clk_root_index clock_id) +{ +enum clk_root_src root_src; +u32 post_podf, pre_podf, auto_podf, root_src_clk; +int auto_en; + +if (clock_root_enabled (clock_id) <=0 ) +return 0 ; + +if (clock_get_prediv (clock_id, &pre_podf) <0 ) +return 0 ; + +if (clock_get_postdiv (clock_id, &post_podf) <0 ) +return 0 ; + +if (clock_get_autopostdiv (clock_id, &auto_podf, &auto_en) <0 ) +return 0 ; + +if (auto_en ==0 ) + auto_podf =0 ; + +if (clock_get_src (clock_id, &root_src) <0 ) +return 0 ; + + root_src_clk =get_root_src_clk (root_src); + +/* +* bypass clk is ignored. +*/ + +return root_src_clk / (post_podf +1 ) / (pre_podf +1 ) / + (auto_podf +1 ); +} + +static u32 get_ddrc_clk (void ) +{ +u32 reg, freq; +enum root_post_div post_div; + + reg =readl (&ccm_reg->root[DRAM_CLK_ROOT ].target_root); +if (reg &CLK_ROOT_MUX_MASK ) +/* DRAM_ALT_CLK_ROOT */ + freq =get_root_clk (DRAM_ALT_CLK_ROOT ); +else +/* PLL_DRAM_MAIN_1066M_CLK */ + freq =mxc_get_pll_derive (PLL_DDR ,PLL_DRAM_MAIN_1066M_CLK ); + + post_div = reg &DRAM_CLK_ROOT_POST_DIV_MASK ; + +return freq / (post_div +1 ) /2 ; +} + +unsigned int mxc_get_clock (enum mxc_clock clk) +{ +switch (clk) { +case MXC_ARM_CLK : +return get_root_clk (ARM_A7_CLK_ROOT ); +case MXC_AXI_CLK : +return get_root_clk (MAIN_AXI_CLK_ROOT ); +case MXC_AHB_CLK : +return get_root_clk (AHB_CLK_ROOT ); +case MXC_IPG_CLK : +return get_ipg_clk (); +case MXC_I2C_CLK : +return get_root_clk (I2C1_CLK_ROOT ); +case MXC_UART_CLK : +return get_root_clk (UART1_CLK_ROOT ); +case MXC_CSPI_CLK : +return get_root_clk (ECSPI1_CLK_ROOT ); +case MXC_DDR_CLK : +return get_ddrc_clk (); +case MXC_ESDHC_CLK : +return get_root_clk (USDHC1_CLK_ROOT ); +case MXC_ESDHC2_CLK : +return get_root_clk (USDHC2_CLK_ROOT ); +case MXC_ESDHC3_CLK : +return get_root_clk (USDHC3_CLK_ROOT ); +default : +printf ("Unsupported mxc_clock %d\n" , clk); +break ; + } + +return 0 ; +} + +#ifdef CONFIG_SYS_I2C_MXC +/* i2c_num can be 0 - 3 */ +int enable_i2c_clk (unsigned char enable,unsigned i2c_num) +{ +u32 target; + +if (i2c_num >=4 ) +return -EINVAL ; + +if (enable) { +clock_enable (CCGR_I2C1 + i2c_num,0 ); + +/* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */ + + target =CLK_ROOT_ON |I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV2 ); +clock_set_target_val (I2C1_CLK_ROOT + i2c_num, target); + +clock_enable (CCGR_I2C1 + i2c_num,1 ); + }else { +clock_enable (CCGR_I2C1 + i2c_num,0 ); + } + +return 0 ; +} +#endif + +static void init_clk_esdhc (void ) +{ +u32 target; + +/* disable the clock gate first */ +clock_enable (CCGR_USDHC1 ,0 ); +clock_enable (CCGR_USDHC2 ,0 ); +clock_enable (CCGR_USDHC3 ,0 ); + +/* 196: 392/2 */ + target =CLK_ROOT_ON |USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV2 ); +clock_set_target_val (USDHC1_CLK_ROOT , target); + + target =CLK_ROOT_ON |USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV2 ); +clock_set_target_val (USDHC2_CLK_ROOT , target); + + target =CLK_ROOT_ON |USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV2 ); +clock_set_target_val (USDHC3_CLK_ROOT , target); + +/* enable the clock gate */ +clock_enable (CCGR_USDHC1 ,1 ); +clock_enable (CCGR_USDHC2 ,1 ); +clock_enable (CCGR_USDHC3 ,1 ); + +} + +static void init_clk_uart (void ) +{ +u32 target; + +/* disable the clock gate first */ +clock_enable (CCGR_UART1 ,0 ); +clock_enable (CCGR_UART2 ,0 ); +clock_enable (CCGR_UART3 ,0 ); +clock_enable (CCGR_UART4 ,0 ); +clock_enable (CCGR_UART5 ,0 ); +clock_enable (CCGR_UART6 ,0 ); +clock_enable (CCGR_UART7 ,0 ); + +/* 24Mhz */ + target =CLK_ROOT_ON |UART1_CLK_ROOT_FROM_OSC_24M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV1 ); +clock_set_target_val (UART1_CLK_ROOT , target); + + target =CLK_ROOT_ON |UART2_CLK_ROOT_FROM_OSC_24M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV1 ); +clock_set_target_val (UART2_CLK_ROOT , target); + + target =CLK_ROOT_ON |UART3_CLK_ROOT_FROM_OSC_24M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV1 ); +clock_set_target_val (UART3_CLK_ROOT , target); + + target =CLK_ROOT_ON |UART4_CLK_ROOT_FROM_OSC_24M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV1 ); +clock_set_target_val (UART4_CLK_ROOT , target); + + target =CLK_ROOT_ON |UART5_CLK_ROOT_FROM_OSC_24M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV1 ); +clock_set_target_val (UART5_CLK_ROOT , target); + + target =CLK_ROOT_ON |UART6_CLK_ROOT_FROM_OSC_24M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV1 ); +clock_set_target_val (UART6_CLK_ROOT , target); + + target =CLK_ROOT_ON |UART7_CLK_ROOT_FROM_OSC_24M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV1 ); +clock_set_target_val (UART7_CLK_ROOT , target); + +/* enable the clock gate */ +clock_enable (CCGR_UART1 ,1 ); +clock_enable (CCGR_UART2 ,1 ); +clock_enable (CCGR_UART3 ,1 ); +clock_enable (CCGR_UART4 ,1 ); +clock_enable (CCGR_UART5 ,1 ); +clock_enable (CCGR_UART6 ,1 ); +clock_enable (CCGR_UART7 ,1 ); + +} + +static void init_clk_weim (void ) +{ +u32 target; + +/* disable the clock gate first */ +clock_enable (CCGR_WEIM ,0 ); + +/* 120Mhz */ + target =CLK_ROOT_ON |EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV1 ); +clock_set_target_val (EIM_CLK_ROOT , target); + +/* enable the clock gate */ +clock_enable (CCGR_WEIM ,1 ); +} + +static void init_clk_ecspi (void ) +{ +u32 target; + +/* disable the clock gate first */ +clock_enable (CCGR_ECSPI1 ,0 ); +clock_enable (CCGR_ECSPI2 ,0 ); +clock_enable (CCGR_ECSPI3 ,0 ); +clock_enable (CCGR_ECSPI4 ,0 ); + +/* 60Mhz: 240/4 */ + target =CLK_ROOT_ON |ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV4 ); +clock_set_target_val (ECSPI1_CLK_ROOT , target); + + target =CLK_ROOT_ON |ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV4 ); +clock_set_target_val (ECSPI2_CLK_ROOT , target); + + target =CLK_ROOT_ON |ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV4 ); +clock_set_target_val (ECSPI3_CLK_ROOT , target); + + target =CLK_ROOT_ON |ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV4 ); +clock_set_target_val (ECSPI4_CLK_ROOT , target); + +/* enable the clock gate */ +clock_enable (CCGR_ECSPI1 ,1 ); +clock_enable (CCGR_ECSPI2 ,1 ); +clock_enable (CCGR_ECSPI3 ,1 ); +clock_enable (CCGR_ECSPI4 ,1 ); +} + +static void init_clk_wdog (void ) +{ +u32 target; + +/* disable the clock gate first */ +clock_enable (CCGR_WDOG1 ,0 ); +clock_enable (CCGR_WDOG2 ,0 ); +clock_enable (CCGR_WDOG3 ,0 ); +clock_enable (CCGR_WDOG4 ,0 ); + +/* 24Mhz */ + target =CLK_ROOT_ON |WDOG_CLK_ROOT_FROM_OSC_24M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) |CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV1 ); +clock_set_target_val (WDOG_CLK_ROOT , target); + +/* enable the clock gate */ +clock_enable (CCGR_WDOG1 ,1 ); +clock_enable (CCGR_WDOG2 ,1 ); +clock_enable (CCGR_WDOG3 ,1 ); +clock_enable (CCGR_WDOG4 ,1 ); + +} + +#ifdef CONFIG_MXC_EPDC +static void init_clk_epdc (void ) +{ +u32 target; + +/* disable the clock gate first */ +clock_enable (CCGR_EPDC ,0 ); + +/* 24Mhz */ + target =CLK_ROOT_ON |EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV12 ); +clock_set_target_val (EPDC_PIXEL_CLK_ROOT , target); + +/* enable the clock gate */ +clock_enable (CCGR_EPDC ,1 ); +} +#endif + +static int enable_pll_enet (void ) +{ +u32 reg; +s32 timeout =100000 ; + + reg =readl (&ccm_anatop->pll_enet); +/* If pll_enet powered up, no need to set it again */ +if (reg &ANADIG_PLL_ENET_PWDN_MASK ) { + reg &= ~ANADIG_PLL_ENET_PWDN_MASK ; +writel (reg, &ccm_anatop->pll_enet); + +while (timeout--) { +if (readl (&ccm_anatop->pll_enet) &ANADIG_PLL_LOCK ) +break ; + } + +if (timeout <=0 ) { +/* If timeout, we set pwdn for pll_enet. */ + reg |=ANADIG_PLL_ENET_PWDN_MASK ; +return -ETIME ; + } + } + +/* Clear bypass */ +writel (CCM_ANALOG_PLL_ENET_BYPASS_MASK , &ccm_anatop->pll_enet_clr); + +writel ((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK + |CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK + |CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK + |CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK + |CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK + |CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK + |CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK ), + &ccm_anatop->pll_enet_set); + +return 0 ; +} +static int enable_pll_video (u32 pll_div,u32 pll_num,u32 pll_denom, +u32 post_div) +{ +u32 reg =0 ; +ulong start; + +debug ("pll5 div = %d, num = %d, denom = %d\n" , + pll_div, pll_num, pll_denom); + +/* Power up PLL5 video and disable its output */ +writel (CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK | +CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK | +CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK | +CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK | +CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK | +CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK , + &ccm_anatop->pll_video_clr); + +/* Set div, num and denom */ +switch (post_div) { +case 1 : +writel (CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT (pll_div) | +CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT (0x1 ) | +CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL (0x0 ), + &ccm_anatop->pll_video_set); +break ; +case 2 : +writel (CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT (pll_div) | +CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT (0x0 ) | +CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL (0x0 ), + &ccm_anatop->pll_video_set); +break ; +case 3 : +writel (CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT (pll_div) | +CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT (0x0 ) | +CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL (0x1 ), + &ccm_anatop->pll_video_set); +break ; +case 4 : +writel (CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT (pll_div) | +CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT (0x0 ) | +CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL (0x3 ), + &ccm_anatop->pll_video_set); +break ; +case 0 : +default : +writel (CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT (pll_div) | +CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT (0x2 ) | +CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL (0x0 ), + &ccm_anatop->pll_video_set); +break ; + } + +writel (CCM_ANALOG_PLL_VIDEO_NUM_A (pll_num), + &ccm_anatop->pll_video_num); + +writel (CCM_ANALOG_PLL_VIDEO_DENOM_B (pll_denom), + &ccm_anatop->pll_video_denom); + +/* Wait PLL5 lock */ + start =get_timer (0 );/* Get current timestamp */ + +do { + reg =readl (&ccm_anatop->pll_video); +if (reg &CCM_ANALOG_PLL_VIDEO_LOCK_MASK ) { +/* Enable PLL out */ +writel (CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK , + &ccm_anatop->pll_video_set); +return 0 ; + } + }while (get_timer (0 ) < (start +10 ));/* Wait 10ms */ + +printf ("Lock PLL5 timeout\n" ); + +return 1 ; + +} + +int set_clk_qspi (void ) +{ +u32 target; + +/* disable the clock gate first */ +clock_enable (CCGR_QSPI ,0 ); + +/* 49M: 392/2/4 */ + target =CLK_ROOT_ON |QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV2 ); +clock_set_target_val (QSPI_CLK_ROOT , target); + +/* enable the clock gate */ +clock_enable (CCGR_QSPI ,1 ); + +return 0 ; +} + +int set_clk_nand (void ) +{ +u32 target; + +/* disable the clock gate first */ +clock_enable (CCGR_RAWNAND ,0 ); + +enable_pll_enet (); +/* 100: 500/5 */ + target =CLK_ROOT_ON |NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV5 ); +clock_set_target_val (NAND_CLK_ROOT , target); + +/* enable the clock gate */ +clock_enable (CCGR_RAWNAND ,1 ); + +return 0 ; +} + +void mxs_set_lcdclk (uint32_t base_addr,uint32_t freq) +{ +u32 hck =MXC_HCLK /1000 ; +u32 min = hck *27 ; +u32 max = hck *54 ; +u32 temp, best =0 ; +u32 i, j, pred =1 , postd =1 ; +u32 pll_div, pll_num, pll_denom, post_div =0 ; +u32 target; + +debug ("mxs_set_lcdclk, freq = %d\n" , freq); + +clock_enable (CCGR_LCDIF ,0 ); + + temp = (freq *8 *8 ); +if (temp < min) { + +for (i =1 ; i <=4 ; i++) { +if ((temp * (1 << i)) > min) { + post_div = i; + freq = (freq * (1 << i)); +break ; + } + } + +if (5 == i) { +printf ("Fail to set rate to %dkhz" , freq); +return ; + } + } + +for (i =1 ; i <=8 ; i++) { +for (j =1 ; j <=8 ; j++) { + temp = freq * i * j; +if (temp > max || temp < min) +continue ; + +if (best ==0 || temp < best) { + best = temp; + pred = i; + postd = j; + } + } + } + +if (best ==0 ) { +printf ("Fail to set rate to %dkhz" , freq); +return ; + } + +debug ("best %d, pred = %d, postd = %d\n" , best, pred, postd); + + pll_div = best / hck; + pll_denom =1000000 ; + pll_num = (best - hck * pll_div) * pll_denom / hck; + +if (enable_pll_video (pll_div, pll_num, pll_denom, post_div)) +return ; + + target =CLK_ROOT_ON |LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK | +CLK_ROOT_PRE_DIV ((pred -1 )) |CLK_ROOT_POST_DIV ((postd -1 )); +clock_set_target_val (LCDIF_PIXEL_CLK_ROOT , target); + +clock_enable (CCGR_LCDIF ,1 ); +} + +#ifdef CONFIG_FEC_MXC +int set_clk_enet (enum enet_freq type) +{ +u32 target; +int ret; +u32 enet1_ref, enet2_ref; + +/* disable the clock first */ +clock_enable (CCGR_ENET1 ,0 ); +clock_enable (CCGR_ENET2 ,0 ); + +switch (type) { +case ENET_125MHz: + enet1_ref =ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK ; + enet2_ref =ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK ; +break ; +case ENET_50MHz: + enet1_ref =ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK ; + enet2_ref =ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK ; +break ; +case ENET_25MHz: + enet1_ref =ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK ; + enet2_ref =ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK ; +break ; +default : +return -EINVAL ; + } + + ret =enable_pll_enet (); +if (ret !=0 ) +return ret; + +/* set enet axi clock 196M: 392/2 */ + target =CLK_ROOT_ON |ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV2 ); +clock_set_target_val (ENET_AXI_CLK_ROOT , target); + + target =CLK_ROOT_ON | enet1_ref | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV1 ); +clock_set_target_val (ENET1_REF_CLK_ROOT , target); + + target =CLK_ROOT_ON |ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV4 ); +clock_set_target_val (ENET1_TIME_CLK_ROOT , target); + + target =CLK_ROOT_ON | enet2_ref | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV1 ); +clock_set_target_val (ENET2_REF_CLK_ROOT , target); + + target =CLK_ROOT_ON |ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV4 ); +clock_set_target_val (ENET2_TIME_CLK_ROOT , target); + +#ifdef CONFIG_FEC_MXC_25M_REF_CLK + target =CLK_ROOT_ON |ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV1 ) | +CLK_ROOT_POST_DIV (CLK_ROOT_POST_DIV1 ); +clock_set_target_val (ENET_PHY_REF_CLK_ROOT , target); +#endif +/* enable clock */ +clock_enable (CCGR_ENET1 ,1 ); +clock_enable (CCGR_ENET2 ,1 ); + +return 0 ; +} +#endif + +/* Configure PLL/PFD freq */ +void clock_init (void ) +{ +/* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET +* In u-boot, we have to: +* 1. Configure PFD3- PFD7 for freq we needed in u-boot +* 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate +* interface. The clocks for these peripherals are enabled after this intialization. +* 3. Other peripherals with set clock rate interface does not be set in this function. +*/ + +u32 reg; + +/* +* Configure PFD4 to 392M +* 480M * 18 / 0x16 = 392M +*/ + reg =readl (&ccm_anatop->pfd_480b); + + reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK | +CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK ); + reg |=ANATOP_PFD480B_PFD4_FRAC_392M_VAL ; + +writel (reg, &ccm_anatop->pfd_480b); + +init_clk_esdhc (); +init_clk_uart (); +init_clk_weim (); +init_clk_ecspi (); +init_clk_wdog (); +#ifdef CONFIG_MXC_EPDC +init_clk_epdc (); +#endif + +enable_usboh3_clk (1 ); + +clock_enable (CCGR_SNVS ,1 ); + +#ifdef CONFIG_NAND_MXS +clock_enable (CCGR_RAWNAND ,1 ); +#endif +} + +#ifdef CONFIG_SECURE_BOOT +void hab_caam_clock_enable (unsigned char enable) +{ +if (enable) +clock_enable (CCGR_CAAM ,1 ); +else +clock_enable (CCGR_CAAM ,0 ); +} +#endif + +#ifdef CONFIG_MXC_EPDC +void epdc_clock_enable (void ) +{ +clock_enable (CCGR_EPDC ,1 ); +} +void epdc_clock_disable (void ) +{ +clock_enable (CCGR_EPDC ,0 ); +} +#endif + +/* +* Dump some core clockes. +*/ +int do_mx7_showclocks (cmd_tbl_t *cmdtp,int flag,int argc,char *const argv[]) +{ +u32 freq; + freq =decode_pll (PLL_CORE ,MXC_HCLK ); +printf ("PLL_CORE %8d MHz\n" , freq /1000000 ); + freq =decode_pll (PLL_SYS ,MXC_HCLK ); +printf ("PLL_SYS %8d MHz\n" , freq /1000000 ); + freq =decode_pll (PLL_ENET ,MXC_HCLK ); +printf ("PLL_NET %8d MHz\n" , freq /1000000 ); + +printf ("\n" ); + +printf ("IPG %8d kHz\n" ,mxc_get_clock (MXC_IPG_CLK ) /1000 ); +printf ("UART %8d kHz\n" ,mxc_get_clock (MXC_UART_CLK ) /1000 ); +#ifdef CONFIG_MXC_SPI +printf ("CSPI %8d kHz\n" ,mxc_get_clock (MXC_CSPI_CLK ) /1000 ); +#endif +printf ("AHB %8d kHz\n" ,mxc_get_clock (MXC_AHB_CLK ) /1000 ); +printf ("AXI %8d kHz\n" ,mxc_get_clock (MXC_AXI_CLK ) /1000 ); +printf ("DDR %8d kHz\n" ,mxc_get_clock (MXC_DDR_CLK ) /1000 ); +printf ("USDHC1 %8d kHz\n" ,mxc_get_clock (MXC_ESDHC_CLK ) /1000 ); +printf ("USDHC2 %8d kHz\n" ,mxc_get_clock (MXC_ESDHC2_CLK ) /1000 ); +printf ("USDHC3 %8d kHz\n" ,mxc_get_clock (MXC_ESDHC3_CLK ) /1000 ); + +return 0 ; +} + +U_BOOT_CMD ( + clocks,CONFIG_SYS_MAXARGS ,1 , do_mx7_showclocks, +"display clocks" , +"" +);
arch/arm/cpu/armv7/mx7/clock_slice.c new file +757 -0
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arch/arm/include/asm/arch-mx7/clock.h new file +348 -0
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arch/arm/include/asm/arch-mx7/clock_slice.h new file +116 -0
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Signature · 1 line
2.1.4
PATCH v4 9/13 imx: imx7d: Add SoC system support
In reply to Adrian Alonso* Add SoC system support, Misc arch dependent functions for system bring up:
s_init: system init enable clock base settings
enable_caches: configures Cortex-A7 L2 caches
get_boot_device: identifies boot device
Signed-off-by Adrian Alonso <[email protected]>
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Ye.Li <[email protected]>
---
Changes for V2: Split from patch imx: imx7d: initial arch level support Changes for V3: Resend
Changes for V4: Resend
arch/arm/cpu/armv7/mx7/soc.c | 360 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/include/asm/imx-common/boot_mode.h | 21 ++ 3 files changed, 382 insertions(+) create mode 100644 arch/arm/cpu/armv7/mx7/soc.c
arch/arm/cpu/armv7/mx7/soc.c new file +360 -0
@@ -0,0 +1,360 @@ +/* +* Copyright (C) 2015 Freescale Semiconductor, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/armv7.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/dma.h> +#include <stdbool.h> +#include <asm/arch/crm_regs.h> +#include <dm.h> +#include <imx_thermal.h> +#ifdef CONFIG_VIDEO_MXS +#include <mxsfb.h> +#endif + +struct src *src_reg = (struct src *)SRC_BASE_ADDR ; + +#if defined(CONFIG_IMX_THERMAL ) +static const struct imx_thermal_plat imx7_thermal_plat = { + .regs = (void *)ANATOP_BASE_ADDR , + .fuse_bank =3 , + .fuse_word =3 , +}; + +U_BOOT_DEVICE (imx7_thermal) = { + .name ="imx_thermal" , + .platdata = &imx7_thermal_plat, +}; +#endif + +u32 get_cpu_rev (void ) +{ +struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) +ANATOP_BASE_ADDR ; +u32 reg =readl (&ccm_anatop->digprog); +u32 type = (reg >>16 ) &0xff ; + + reg &=0xff ; +return (type <<12 ) | reg; +} + +#ifdef CONFIG_REVISION_TAG +u32 __weak get_board_rev (void ) +{ +u32 cpurev =get_cpu_rev (); +u32 type = ((cpurev >>12 ) &0xff ); + +if (type ==MXC_CPU_MX7D ) + cpurev = (MXC_CPU_MX7D ) <<12 | (cpurev &0xFFF ); + +return cpurev; +} +#endif + +static void init_aips (void ) +{ +struct aipstz_regs *aips1, *aips2, *aips3; + + aips1 = (struct aipstz_regs *)AIPS1_ON_BASE_ADDR ; + aips2 = (struct aipstz_regs *)AIPS2_ON_BASE_ADDR ; + aips3 = (struct aipstz_regs *)AIPS3_ON_BASE_ADDR ; + +/* +* Set all MPROTx to be non-bufferable, trusted for R/W, +* not forced to user-mode. +*/ +writel (0x77777777 , &aips1->mprot0); +writel (0x77777777 , &aips1->mprot1); +writel (0x77777777 , &aips2->mprot0); +writel (0x77777777 , &aips2->mprot1); +writel (0x77777777 , &aips3->mprot0); +writel (0x77777777 , &aips3->mprot1); + +/* +* Set all OPACRx to be non-bufferable, not require +* supervisor privilege level for access,allow for +* write access and untrusted master access. +*/ +writel (0x00000000 , &aips1->opacr0); +writel (0x00000000 , &aips1->opacr1); +writel (0x00000000 , &aips1->opacr2); +writel (0x00000000 , &aips1->opacr3); +writel (0x00000000 , &aips1->opacr4); +writel (0x00000000 , &aips2->opacr0); +writel (0x00000000 , &aips2->opacr1); +writel (0x00000000 , &aips2->opacr2); +writel (0x00000000 , &aips2->opacr3); +writel (0x00000000 , &aips2->opacr4); +writel (0x00000000 , &aips3->opacr0); +writel (0x00000000 , &aips3->opacr1); +writel (0x00000000 , &aips3->opacr2); +writel (0x00000000 , &aips3->opacr3); +writel (0x00000000 , &aips3->opacr4); +} + +static void imx_set_pcie_phy_power_down (void ) +{ +/* TODO */ +} + +static void imx_set_wdog_powerdown (bool enable) +{ +struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR ; +struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR ; +struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR ; +struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR ; + +writew (enable, &wdog1->wmcr); +writew (enable, &wdog2->wmcr); +writew (enable, &wdog3->wmcr); +writew (enable, &wdog4->wmcr); +} + +static void set_epdc_qos (void ) +{ +#define REGS_QOS_BASE QOSC_IPS_BASE_ADDR +#define REGS_QOS_EPDC (QOSC_IPS_BASE_ADDR + 0x3400) +#define REGS_QOS_PXP0 (QOSC_IPS_BASE_ADDR + 0x2C00) +#define REGS_QOS_PXP1 (QOSC_IPS_BASE_ADDR + 0x3C00) + +writel (0 ,REGS_QOS_BASE );/* Disable clkgate & soft_reset */ +writel (0 ,REGS_QOS_BASE +0x60 );/* Enable all masters */ +writel (0 ,REGS_QOS_EPDC );/* Disable clkgate & soft_reset */ +writel (0 ,REGS_QOS_PXP0 );/* Disable clkgate & soft_reset */ +writel (0 ,REGS_QOS_PXP1 );/* Disable clkgate & soft_reset */ + +writel (0x0f020722 ,REGS_QOS_EPDC +0xd0 );/* WR, init = 7 with red flag */ +writel (0x0f020722 ,REGS_QOS_EPDC +0xe0 );/* RD, init = 7 with red flag */ + +writel (1 ,REGS_QOS_PXP0 );/* OT_CTRL_EN =1 */ +writel (1 ,REGS_QOS_PXP1 );/* OT_CTRL_EN =1 */ + +writel (0x0f020222 ,REGS_QOS_PXP0 +0x50 );/* WR, init = 2 with red flag */ +writel (0x0f020222 ,REGS_QOS_PXP1 +0x50 );/* WR, init = 2 with red flag */ +writel (0x0f020222 ,REGS_QOS_PXP0 +0x60 );/* rD, init = 2 with red flag */ +writel (0x0f020222 ,REGS_QOS_PXP1 +0x60 );/* rD, init = 2 with red flag */ +writel (0x0f020422 ,REGS_QOS_PXP0 +0x70 );/* tOTAL, init = 4 with red flag */ +writel (0x0f020422 ,REGS_QOS_PXP1 +0x70 );/* TOTAL, init = 4 with red flag */ + +writel (0xe080 ,IOMUXC_GPR_BASE_ADDR +0x0034 );/* EPDC AW/AR CACHE ENABLE */ +} + +int arch_cpu_init (void ) +{ +init_aips (); + +/* Disable PDE bit of WMCR register */ +imx_set_wdog_powerdown (false); + +imx_set_pcie_phy_power_down (); + +#ifdef CONFIG_APBH_DMA +/* Start APBH DMA */ +mxs_dma_init (); +#endif + +set_epdc_qos (); + +return 0 ; +} + +#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init (void ) +{ +/* +* We do not need to set LDO_SOC as i.mx6, since LDO_ARM and LDO_SOC +* does not exist. Check "Figure 7-9. i.MX7Dual Power Diagram" +*/ +return 0 ; +} +#endif + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial (struct tag_serialnr *serialnr) +{ +struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR ; +struct fuse_bank *bank = &ocotp->bank[0 ]; +struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + serialnr->low = fuse->tester0; + serialnr->high = fuse->tester1; +} +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches (void ) +{ +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH ) +enum dcache_option option =DCACHE_WRITETHROUGH ; +#else +enum dcache_option option =DCACHE_WRITEBACK ; +#endif + +/* Avoid random hang when download by usb */ +invalidate_dcache_all (); + +/* Enable D-cache. I-cache is already enabled in start.S */ +dcache_enable (); + +/* Enable caching on OCRAM and ROM */ +mmu_set_region_dcache_behaviour (ROMCP_ARB_BASE_ADDR , +ROMCP_ARB_END_ADDR , + option); +mmu_set_region_dcache_behaviour (IRAM_BASE_ADDR , +IRAM_SIZE , + option); +} +#endif + +#if defined(CONFIG_FEC_MXC ) +void imx_get_mac_from_fuse (int dev_id,unsigned char *mac) +{ +struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR ; +struct fuse_bank *bank = &ocotp->bank[9 ]; +struct fuse_bank9_regs *fuse = + (struct fuse_bank9_regs *)bank->fuse_regs; + +if (0 == dev_id) { +u32 value =readl (&fuse->mac_addr1); + mac[0 ] = (value >>8 ); + mac[1 ] = value; + + value =readl (&fuse->mac_addr0); + mac[2 ] = value >>24 ; + mac[3 ] = value >>16 ; + mac[4 ] = value >>8 ; + mac[5 ] = value; + }else { +u32 value =readl (&fuse->mac_addr2); + mac[0 ] = value >>24 ; + mac[1 ] = value >>16 ; + mac[2 ] = value >>8 ; + mac[3 ] = value; + + value =readl (&fuse->mac_addr1); + mac[4 ] = value >>24 ; + mac[5 ] = value >>16 ; + } +} +#endif + +void boot_mode_apply (uint32_t cfg_val) +{ +uint32_t reg; +writel (cfg_val, &src_reg->gpr9); + reg =readl (&src_reg->gpr10); +if (cfg_val) + reg |=1 <<28 ; +else + reg &= ~(1 <<28 ); +writel (reg, &src_reg->gpr10); +} + +void set_wdog_reset (struct wdog_regs *wdog) +{ +u32 reg =readw (&wdog->wcr); +/* +* Output WDOG_B signal to reset external pmic or POR_B decided by +* the board desgin. Without external reset, the peripherals/DDR/ +* PMIC are not reset, that may cause system working abnormal. +*/ + reg =readw (&wdog->wcr); + reg |=1 <<3 ; +/* +* WDZST bit is write-once only bit. Align this bit in kernel, +* otherwise kernel code will have no chance to set this bit. +*/ + reg |=1 <<0 ; +writew (reg, &wdog->wcr); +} + +/* +* cfg_val will be used for +* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] +* After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] +* to SBMR1, which will determine the boot device. +*/ +const struct boot_mode soc_boot_modes[] = { + {"ecspi1:0" ,MAKE_CFGVAL (0x00 ,0x60 ,0x00 ,0x00 )}, + {"ecspi1:1" ,MAKE_CFGVAL (0x40 ,0x62 ,0x00 ,0x00 )}, + {"ecspi1:2" ,MAKE_CFGVAL (0x80 ,0x64 ,0x00 ,0x00 )}, + {"ecspi1:3" ,MAKE_CFGVAL (0xc0 ,0x66 ,0x00 ,0x00 )}, + + {"weim" ,MAKE_CFGVAL (0x00 ,0x50 ,0x00 ,0x00 )}, + {"qspi1" ,MAKE_CFGVAL (0x10 ,0x40 ,0x00 ,0x00 )}, +/* 4 bit bus width */ + {"usdhc1" ,MAKE_CFGVAL (0x10 ,0x10 ,0x00 ,0x00 )}, + {"usdhc2" ,MAKE_CFGVAL (0x10 ,0x14 ,0x00 ,0x00 )}, + {"usdhc3" ,MAKE_CFGVAL (0x10 ,0x18 ,0x00 ,0x00 )}, + {"mmc1" ,MAKE_CFGVAL (0x10 ,0x20 ,0x00 ,0x00 )}, + {"mmc2" ,MAKE_CFGVAL (0x10 ,0x24 ,0x00 ,0x00 )}, + {"mmc3" ,MAKE_CFGVAL (0x10 ,0x28 ,0x00 ,0x00 )}, + {NULL ,0 }, +}; + +enum boot_device get_boot_device (void ) +{ +struct bootrom_sw_info **p = + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR ; + +enum boot_device boot_dev =SD1_BOOT ; +u8 boot_type = (*p)->boot_dev_type; +u8 boot_instance = (*p)->boot_dev_instance; + +switch (boot_type) { +case BOOT_TYPE_SD : + boot_dev = boot_instance +SD1_BOOT ; +break ; +case BOOT_TYPE_MMC : + boot_dev = boot_instance +MMC1_BOOT ; +break ; +case BOOT_TYPE_NAND : + boot_dev =NAND_BOOT ; +break ; +case BOOT_TYPE_QSPI : + boot_dev =QSPI_BOOT ; +break ; +case BOOT_TYPE_WEIM : + boot_dev =WEIM_NOR_BOOT ; +break ; +case BOOT_TYPE_SPINOR : + boot_dev =SPI_NOR_BOOT ; +break ; +default : +break ; + } + +return boot_dev; +} + +void s_init (void ) +{ +#if !definedCONFIG_SPL_BUILD +/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ + asmvolatile ( +"mrc p15, 0, r0, c1, c0, 1\n" +"orr r0, r0, #1 << 6\n" +"mcr p15, 0, r0, c1, c0, 1\n" ); +#endif +/* clock configuration. */ +clock_init (); + +return ; +} + +void reset_misc (void ) +{ +#ifdef CONFIG_VIDEO_MXS +lcdif_power_down (); +#endif +}
arch/arm/include/asm/arch-imx/cpu.h +1 -0
@@ -12,6 +12,7 @@#define MXC_CPU_MX6Q 0x63#define MXC_CPU_MX6D 0x64#define MXC_CPU_MX6SOLO 0x65/* dummy ID */ +#define MXC_CPU_MX7D 0x72#define CS0_128 0#define CS0_64M_CS1_64M 1
arch/arm/include/asm/imx-common/boot_mode.h +21 -0
@@ -9,6 +9,27 @@#define MAKE_CFGVAL (cfg1, cfg2, cfg3, cfg4) \ ((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1) +enum boot_device { +WEIM_NOR_BOOT , +ONE_NAND_BOOT , +PATA_BOOT , +SATA_BOOT , +I2C_BOOT , +SPI_NOR_BOOT , +SD1_BOOT , +SD2_BOOT , +SD3_BOOT , +SD4_BOOT , +MMC1_BOOT , +MMC2_BOOT , +MMC3_BOOT , +MMC4_BOOT , +NAND_BOOT , +QSPI_BOOT , +UNKNOWN_BOOT , +BOOT_DEV_NUM =UNKNOWN_BOOT , +}; +struct boot_mode {const char *name;unsigned cfg_val;
Signature · 1 line
2.1.4
PATCH v4 10/13 imx: imx7d: add hab secure boot support
In reply to Adrian Alonso* HAB secure boot support
- get_hab_status: checks if secure boot is enabled or not
- authenticate_image: verifies image properly signed based on CSF entry
* Uboot command for hab authenticate
- hab_auth_img: authenticate image via HAB
- hab_status: display HAB status
Signed-off-by Adrian Alonso <[email protected]>
---
Changes for V2: Split from patch imx: imx7d: initial arch level support Changes for V3: Resend
Changes for V4: Resend
arch/arm/cpu/armv7/mx7/Makefile | 9 ++ arch/arm/cpu/armv7/mx7/hab.c | 277 ++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx7/hab.h | 69 +++++++++ 3 files changed, 355 insertions(+) create mode 100644 arch/arm/cpu/armv7/mx7/Makefile create mode 100644 arch/arm/cpu/armv7/mx7/hab.c create mode 100644 arch/arm/include/asm/arch-mx7/hab.h
arch/arm/cpu/armv7/mx7/Makefile new file +9 -0
@@ -0,0 +1,9 @@ +# +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# + +obj-y := soc.o clock.o clock_slice.o +obj-$(CONFIG_SECURE_BOOT) += hab.o
arch/arm/cpu/armv7/mx7/hab.c new file +277 -0
277 lines not on this page · raw message
arch/arm/include/asm/arch-mx7/hab.h new file +69 -0
69 lines not on this page · raw message
Signature · 1 line
2.1.4
PATCH v4 11/13 imx: imx7d: add timer support for imx7d
In reply to Adrian Alonso* Add timer support for imx7d SoC
Signed-off-by Adrian Alonso <[email protected]>
---
Changes for V2: Split from patch imx: imx7d: initial arch level support Changes for V3: Resend
Changes for V4: Resend
arch/arm/imx-common/timer.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)
arch/arm/imx-common/timer.c +8 -1
@@ -49,6 +49,8 @@ static inline int gpt_has_clk_source_osc(void)return 1 ;return 0 ; +#elif defined(CONFIG_MX7 ) +return 1 ;#else return 0 ;#endif
@@ -56,6 +58,9 @@ static inline int gpt_has_clk_source_osc(void)static inline ulong gpt_get_clk (void ) { +#if defined(CONFIG_MX7 ) +return MXC_HCLK >>3 ; +#else #ifdef CONFIG_MXC_GPT_HCLK if (gpt_has_clk_source_osc ())return MXC_HCLK >>3 ;
@@ -64,6 +69,7 @@ static inline ulong gpt_get_clk(void)#else return MXC_CLK32 ;#endif +#endif }static inline unsigned long long tick_to_time (unsigned long long tick) {
@@ -106,7 +112,8 @@ int timer_init(void)/* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */ if (is_cpu_type (MXC_CPU_MX6DL ) ||is_cpu_type (MXC_CPU_MX6SOLO ) || -is_cpu_type (MXC_CPU_MX6SX )) { +is_cpu_type (MXC_CPU_MX6SX ) || +is_cpu_type (MXC_CPU_MX7D )) { i |=GPTCR_24MEN ;/* Produce 3Mhz clock */
Signature · 1 line
2.1.4
PATCH v4 12/13 imx: imx7d: add imx-common cpu support for imx7d
In reply to Adrian Alonso* Add imx-common cpu support for imx7d SoC
* Update reset_cause for imx7d
* Enable watchdog driver built for imx7d
Signed-off-by Adrian Alonso <[email protected]>
---
Changes for V2: Split from patch imx: imx7d: initial arch level support Changes for V3: Resend
Changes for V4: Resend
arch/arm/Makefile | 4 ++-- arch/arm/cpu/armv7/Makefile | 3 ++- arch/arm/imx-common/Makefile | 17 ++++++++++++++--- arch/arm/imx-common/cpu.c | 17 +++++++++++++++++ drivers/watchdog/Makefile | 2 +- 5 files changed, 36 insertions(+), 7 deletions(-)
arch/arm/Makefile +2 -2
@@ -78,11 +78,11 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35)) libs-y += arch/arm/imx-common/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35 mxs vf610)) libs-y += arch/arm/imx-common/ endif endif
arch/arm/cpu/armv7/Makefile +2 -1
@@ -12,7 +12,7 @@ obj-y += cache_v7.o obj-y += cpu.o cp15.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif
@@ -45,6 +45,7 @@ obj-$(CONFIG_ARCH_EXYNOS) += exynos/ obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/ obj-$(if $(filter mx5,$(SOC)),y) += mx5/ obj-$(CONFIG_MX6) += mx6/ +obj-$(CONFIG_MX7) += mx7/ obj-$(CONFIG_OMAP34XX) += omap3/ obj-$(CONFIG_OMAP44XX) += omap4/ obj-$(CONFIG_OMAP54XX) += omap5/
arch/arm/imx-common/Makefile +14 -3
@@ -7,20 +7,31 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610)) +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610)) obj-y = iomux-v3.o endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) -obj-y += timer.o cpu.o speed.o +obj-y += cpu.o speed.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif -ifeq ($(SOC),$(filter $(SOC),mx6 mxs)) +ifeq ($(SOC),$(filter $(SOC),mx5)) +obj-y += timer.o +endif +ifeq ($(SOC),$(filter $(SOC),mx7)) +obj-y += cpu.o +obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o +obj-$(CONFIG_GPT_TIMER) += timer.o +obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o +endif +ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs)) obj-y += misc.o obj-$(CONFIG_SPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx6)) obj-$(CONFIG_CMD_SATA) += sata.o obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o +obj-$(CONFIG_GPT_TIMER) += timer.o +obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o endif ifeq ($(SOC),$(filter $(SOC),vf610)) obj-y += ddrmc-vf610.o
arch/arm/imx-common/cpu.c +17 -0
@@ -46,13 +46,26 @@ static char *get_reset_cause(void)case 0x00008 :return "IPP USER" ;case 0x00010 : +#ifdef CONFIG_MX7 +return "WDOG1" ; +#else return "WDOG" ; +#endif case 0x00020 :return "JTAG HIGH-Z" ;case 0x00040 :return "JTAG SW" ; +#ifdef CONFIG_MX7 +case 0x00080 : +return "WDOG3" ; +case 0x00100 : +return "WDOG4" ; +case 0x00200 : +return "TEMPSENSE" ; +#else case 0x10000 :return "WARM BOOT" ; +#endif default :return "unknown reset" ; }
@@ -122,6 +135,8 @@ unsigned imx_ddr_size(void)const char *get_imx_type (u32 imxtype) {switch (imxtype) { +case MXC_CPU_MX7D : +return "7D" ;/* Dual-core version of the mx7 */ case MXC_CPU_MX6Q :return "6Q" ;/* Quad-core version of the mx6 */ case MXC_CPU_MX6D :
@@ -236,6 +251,7 @@ int cpu_mmc_init(bd_t *bis) }#endif +#ifndef CONFIG_MX7 u32 get_ahb_clk (void ) {struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR ;
@@ -247,6 +263,7 @@ u32 get_ahb_clk(void) return get_periph_clk() / (ahb_podf + 1); } +#endif void arch_preboot_os (void ) {
drivers/watchdog/Makefile +1 -1
@@ -7,7 +7,7 @@ obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o -ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa)) +ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610 ls102xa)) obj-y += imx_watchdog.o endif obj-$(CONFIG_S5P) += s5p_wdt.o
Signature · 1 line
2.1.4
PATCH v4 13/13 imx: mx7dsabresd: Add support for MX7D SABRESD board
In reply to Adrian Alonso* Add i.MX7D SABRESD target board support with enabled modules:
UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX.
Build target: mx7dsabresd_config
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Fugang Duan <[email protected]>
Signed-off-by Ye.Li <[email protected]>
Signed-off-by Adrian Alonso <[email protected]>
---
Changes for V2:
- Include arch/arm/Kconfig target config option Changes for V3:
- Update target board maintainer contact info Changes for V4: depends on patchs
- mmc: fsl_esdhc invalidate dcache before read
- imx: usb: ehci-mx6: add usb support for imx7d soc
arch/arm/Kconfig | 7 + board/freescale/mx7dsabresd/Kconfig | 15 + board/freescale/mx7dsabresd/MAINTAINERS | 6 + board/freescale/mx7dsabresd/Makefile | 6 + board/freescale/mx7dsabresd/imximage.cfg | 103 +++++ board/freescale/mx7dsabresd/mx7dsabresd.c | 642 ++++++++++++++++++++++++++++++ configs/mx7dsabresd_defconfig | 10 + include/configs/mx7_common.h | 22 + include/configs/mx7dsabresd.h | 355 +++++++++++++++++ 9 files changed, 1166 insertions(+) create mode 100644 board/freescale/mx7dsabresd/Kconfig create mode 100644 board/freescale/mx7dsabresd/MAINTAINERS create mode 100644 board/freescale/mx7dsabresd/Makefile create mode 100644 board/freescale/mx7dsabresd/imximage.cfg create mode 100644 board/freescale/mx7dsabresd/mx7dsabresd.c create mode 100644 configs/mx7dsabresd_defconfig create mode 100644 include/configs/mx7_common.h create mode 100644 include/configs/mx7dsabresd.h
arch/arm/Kconfig +7 -0
@@ -578,6 +578,12 @@ config TARGET_MX6SXSABRESD select DM select DM_THERMAL +config TARGET_MX7DSABRESD + bool "Support mx7dsabresd" + select CPU_V7 + select DM + select DM_THERMAL + config TARGET_GW_VENTANA bool "Support gw_ventana" select CPU_V7
@@ -920,6 +926,7 @@ source "board/freescale/mx6qsabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" source "board/freescale/mx6slevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" +source "board/freescale/mx7dsabresd/Kconfig" source "board/freescale/vf610twr/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/genesi/mx51_efikamx/Kconfig"
board/freescale/mx7dsabresd/Kconfig new file +15 -0
@@ -0,0 +1,15 @@ +if TARGET_MX7DSABRESD + +config SYS_BOARD + default "mx7dsabresd" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx7" + +config SYS_CONFIG_NAME + default "mx7dsabresd" + +endif
board/freescale/mx7dsabresd/MAINTAINERS new file +6 -0
@@ -0,0 +1,6 @@ +MX7DSABRESD BOARD +M: Adrian Alonso <[email protected]> +S: Maintained +F: board/freescale/mx7dsabresd +F: include/configs/mx7dsabresd.h +F: configs/mx7dsabresd_defconfig
board/freescale/mx7dsabresd/Makefile new file +6 -0
@@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7dsabresd.o
board/freescale/mx7dsabresd/imximage.cfg new file +103 -0
103 lines not on this page · raw message
board/freescale/mx7dsabresd/mx7dsabresd.c new file +642 -0
642 lines not on this page · raw message
configs/mx7dsabresd_defconfig new file +10 -0
@@ -0,0 +1,10 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D" +CONFIG_ARM=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set
include/configs/mx7_common.h new file +22 -0
@@ -0,0 +1,22 @@ +/* +* Copyright (C) 2015 Freescale Semiconductor, Inc. +* +* Configuration settings for the Freescale i.MX7. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + + +#ifndef __MX7_COMMON_H +#define __MX7_COMMON_H + +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_MXC_GPT_HCLK + +#define CONFIG_SYSCOUNTER_TIMER +#define CONFIG_SC_TIMER_CLK 8000000/* 8Mhz */ + +#define CONFIG_IOMUX_LPSR +#define CONFIG_IMX_FIXED_IVT_OFFSET + +#endif
include/configs/mx7dsabresd.h new file +355 -0
355 lines not on this page · raw message
Signature · 1 line
2.1.4
PATCH v4 1/13 power: pmic: add pfuze3000 support
In reply to Adrian AlonsoQuoted 6 lines · Adrian Alonso
* Add pmic pfuze3000 support, implement
power_pfuze3000_initto be used inpower_init_boardcallback function.Signed-off-by Adrian Alonso <[email protected]>Signed-off-by Peng Fan <[email protected]>---
Reviewed-by Stefano Babic <[email protected]>
Best regards,
Stefano Babic
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================
PATCH v4 1/13 power: pmic: add pfuze3000 support
In reply to Adrian AlonsoHello Adrian,
Quoted 5 lines · Adrian Alonso
* Add pmic pfuze3000 support, implement
power_pfuze3000_initto be used inpower_init_boardcallback function.Signed-off-by Adrian Alonso <[email protected]>Signed-off-by Peng Fan <[email protected]>
Quoted 8 lines
---
Changes for V2:
- Correct pfuze device name to pfuze3000; Freescale documentation uses Pfuze 3000 as product name for the pmic, align driver name with the actual product name.
Changes for V3: Resend
Changes for V4: Resend
How this driver is related to this work:
https://patchwork.ozlabs.org/patch/503337/
the mentioned above supports all pfuze 100/200/3000 versions, so maybe you can wait for it to be finished and merged?
Best regards,
Signature · 4 lines
Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marczak at samsung.com
PATCH v4 1/13 power: pmic: add pfuze3000 support
Hello Przemyslaw,
Quoted 17 lines · Przemyslaw Marczak
Hello Adrian,
Quoted 5 lines · Adrian Alonso
* Add pmic pfuze3000 support, implement
power_pfuze3000_initto be used inpower_init_boardcallback function.Signed-off-by Adrian Alonso <[email protected]>Signed-off-by Peng Fan <[email protected]>Quoted 8 lines
---
Changes for V2:
- Correct pfuze device name to pfuze3000; Freescale documentation uses Pfuze 3000 as product name for the pmic, align driver name with the actual product name.
Changes for V3: Resend
Changes for V4: Resend
Quoted 6 lines
How this driver is related to this work:
https://patchwork.ozlabs.org/patch/503337/
the mentioned above supports all pfuze 100/200/3000 versions, so maybe you can wait for it to be finished and merged?
The work I am doing now is to support all the current pfuze100/200/3000 using driver model with device tree support. It depends on device tree support and new power framework support.
The patch from Adrian is using original power framework. If using the new power framework support for pfuze100/200/3000 and regulator support, device tree will need to be added to mx7dsabresd board. This may delay i.MX7 upstream, and needs lots work to redo current patchset.
When the patchset from Adrian for i.MX7 and 7dsabresd is upstreamed, I can prepare to convert to support device tree and enable new power framework and regulator. So I prefer this patch can be merged first.
Regards,
Peng.
Quoted 7 lines
Best regards,
Signature · 4 lines
Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marczak at samsung.com
PATCH v4 1/13 power: pmic: add pfuze3000 support
Hello Peng,
Quoted 38 lines · Peng Fan
Hello Przemyslaw,
Quoted 17 lines · Przemyslaw Marczak
Hello Adrian,
Quoted 5 lines · Adrian Alonso
* Add pmic pfuze3000 support, implement
power_pfuze3000_initto be used inpower_init_boardcallback function.Signed-off-by Adrian Alonso <[email protected]>Signed-off-by Peng Fan <[email protected]>Quoted 8 lines
---
Changes for V2:
- Correct pfuze device name to pfuze3000; Freescale documentation uses Pfuze 3000 as product name for the pmic, align driver name with the actual product name.
Changes for V3: Resend
Changes for V4: ResendQuoted 6 lines
How this driver is related to this work:
https://patchwork.ozlabs.org/patch/503337/
the mentioned above supports all pfuze 100/200/3000 versions, so maybe you can wait for it to be finished and merged?
The work I am doing now is to support all the current pfuze100/200/3000 using driver model with device tree support. It depends on device tree support and new power framework support.
The patch from Adrian is using original power framework. If using the new power framework support for pfuze100/200/3000 and regulator support, device tree will need to be added to mx7dsabresd board. This may delay i.MX7 upstream, and needs lots work to redo current patchset.
When the patchset from Adrian for i.MX7 and 7dsabresd is upstreamed, I can prepare to convert to support device tree and enable new power framework and regulator. So I prefer this patch can be merged first.
Quoted 3 lines
Regards,
Peng.
Thank you for explanation.
Ok, I agree with your idea - we can remove it later.
Quoted 8 lines
Quoted 7 lines
Best regards,
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
Best regards,
Signature · 4 lines
Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marczak at samsung.com
PATCH v4 1/13 power: pmic: add pfuze3000 support
In reply to Adrian AlonsoHello Adrian,
Quoted 13 lines · Adrian Alonso
* Add pmic pfuze3000 support, implement
power_pfuze3000_initto be used inpower_init_boardcallback function.Signed-off-by Adrian Alonso <[email protected]>Signed-off-by Peng Fan <[email protected]>---
Changes for V2:
- Correct pfuze device name to pfuze3000; Freescale documentation uses Pfuze 3000 as product name for the pmic, align driver name with the actual product name.
Changes for V3: Resend
Changes for V4: Resend
Quoted 7 lines
drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_pfuze3000.c | 32 +++++++++++++++ include/power/pfuze3000_pmic.h | 78 +++++++++++++++++++++++++++++++++++++ 3 files changed, 111 insertions(+)create mode 100644
drivers/power/pmic/pmic_pfuze3000.ccreate mode 100644include/power/pfuze3000_pmic.h
Best regards,
Signature · 4 lines
Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marczak at samsung.com