arm: ls1021a: allow OCRAM access permission as R/W in SPL
PATCH 1/1 arm: ls1021a: allow OCRAM access permission as R/W in SPL
On LS1021A Rev2.0, OCRAM's security level needs to be changed to non-secure access for SD boot. This patch will allow OCRAM access permission as R/W in SPL.
Signed-off-by Alison Wang <[email protected]>
--- board/freescale/ls1021aqds/ls1021aqds.c | 178 +++++++++++++++++--------------- board/freescale/ls1021atwr/ls1021atwr.c | 177 ++++++++++++++++--------------- 2 files changed, 184 insertions(+), 171 deletions(-)
board/freescale/ls1021aqds/ls1021aqds.c +92 -86
@@ -54,6 +54,92 @@ enum { GE1_CLK125, }; +#ifdef CONFIG_LS102XA_NS_ACCESS +static struct csu_ns_dev ns_dev[] = { + {CSU_CSLX_PCIE2_IO ,CSU_ALL_RW }, + {CSU_CSLX_PCIE1_IO ,CSU_ALL_RW }, + {CSU_CSLX_MG2TPR_IP ,CSU_ALL_RW }, + {CSU_CSLX_IFC_MEM ,CSU_ALL_RW }, + {CSU_CSLX_OCRAM ,CSU_ALL_RW }, + {CSU_CSLX_GIC ,CSU_ALL_RW }, + {CSU_CSLX_PCIE1 ,CSU_ALL_RW }, + {CSU_CSLX_OCRAM2 ,CSU_ALL_RW }, + {CSU_CSLX_QSPI_MEM ,CSU_ALL_RW }, + {CSU_CSLX_PCIE2 ,CSU_ALL_RW }, + {CSU_CSLX_SATA ,CSU_ALL_RW }, + {CSU_CSLX_USB3 ,CSU_ALL_RW }, + {CSU_CSLX_SERDES ,CSU_ALL_RW }, + {CSU_CSLX_QDMA ,CSU_ALL_RW }, + {CSU_CSLX_LPUART2 ,CSU_ALL_RW }, + {CSU_CSLX_LPUART1 ,CSU_ALL_RW }, + {CSU_CSLX_LPUART4 ,CSU_ALL_RW }, + {CSU_CSLX_LPUART3 ,CSU_ALL_RW }, + {CSU_CSLX_LPUART6 ,CSU_ALL_RW }, + {CSU_CSLX_LPUART5 ,CSU_ALL_RW }, + {CSU_CSLX_DSPI2 ,CSU_ALL_RW }, + {CSU_CSLX_DSPI1 ,CSU_ALL_RW }, + {CSU_CSLX_QSPI ,CSU_ALL_RW }, + {CSU_CSLX_ESDHC ,CSU_ALL_RW }, + {CSU_CSLX_2D_ACE ,CSU_ALL_RW }, + {CSU_CSLX_IFC ,CSU_ALL_RW }, + {CSU_CSLX_I2C1 ,CSU_ALL_RW }, + {CSU_CSLX_USB2 ,CSU_ALL_RW }, + {CSU_CSLX_I2C3 ,CSU_ALL_RW }, + {CSU_CSLX_I2C2 ,CSU_ALL_RW }, + {CSU_CSLX_DUART2 ,CSU_ALL_RW }, + {CSU_CSLX_DUART1 ,CSU_ALL_RW }, + {CSU_CSLX_WDT2 ,CSU_ALL_RW }, + {CSU_CSLX_WDT1 ,CSU_ALL_RW }, + {CSU_CSLX_EDMA ,CSU_ALL_RW }, + {CSU_CSLX_SYS_CNT ,CSU_ALL_RW }, + {CSU_CSLX_DMA_MUX2 ,CSU_ALL_RW }, + {CSU_CSLX_DMA_MUX1 ,CSU_ALL_RW }, + {CSU_CSLX_DDR ,CSU_ALL_RW }, + {CSU_CSLX_QUICC ,CSU_ALL_RW }, + {CSU_CSLX_DCFG_CCU_RCPM ,CSU_ALL_RW }, + {CSU_CSLX_SECURE_BOOTROM ,CSU_ALL_RW }, + {CSU_CSLX_SFP ,CSU_ALL_RW }, + {CSU_CSLX_TMU ,CSU_ALL_RW }, + {CSU_CSLX_SECURE_MONITOR ,CSU_ALL_RW }, + {CSU_CSLX_RESERVED0 ,CSU_ALL_RW }, + {CSU_CSLX_ETSEC1 ,CSU_ALL_RW }, + {CSU_CSLX_SEC5_5 ,CSU_ALL_RW }, + {CSU_CSLX_ETSEC3 ,CSU_ALL_RW }, + {CSU_CSLX_ETSEC2 ,CSU_ALL_RW }, + {CSU_CSLX_GPIO2 ,CSU_ALL_RW }, + {CSU_CSLX_GPIO1 ,CSU_ALL_RW }, + {CSU_CSLX_GPIO4 ,CSU_ALL_RW }, + {CSU_CSLX_GPIO3 ,CSU_ALL_RW }, + {CSU_CSLX_PLATFORM_CONT ,CSU_ALL_RW }, + {CSU_CSLX_CSU ,CSU_ALL_RW }, + {CSU_CSLX_ASRC ,CSU_ALL_RW }, + {CSU_CSLX_SPDIF ,CSU_ALL_RW }, + {CSU_CSLX_FLEXCAN2 ,CSU_ALL_RW }, + {CSU_CSLX_FLEXCAN1 ,CSU_ALL_RW }, + {CSU_CSLX_FLEXCAN4 ,CSU_ALL_RW }, + {CSU_CSLX_FLEXCAN3 ,CSU_ALL_RW }, + {CSU_CSLX_SAI2 ,CSU_ALL_RW }, + {CSU_CSLX_SAI1 ,CSU_ALL_RW }, + {CSU_CSLX_SAI4 ,CSU_ALL_RW }, + {CSU_CSLX_SAI3 ,CSU_ALL_RW }, + {CSU_CSLX_FTM2 ,CSU_ALL_RW }, + {CSU_CSLX_FTM1 ,CSU_ALL_RW }, + {CSU_CSLX_FTM4 ,CSU_ALL_RW }, + {CSU_CSLX_FTM3 ,CSU_ALL_RW }, + {CSU_CSLX_FTM6 ,CSU_ALL_RW }, + {CSU_CSLX_FTM5 ,CSU_ALL_RW }, + {CSU_CSLX_FTM8 ,CSU_ALL_RW }, + {CSU_CSLX_FTM7 ,CSU_ALL_RW }, + {CSU_CSLX_COP_DCSR ,CSU_ALL_RW }, + {CSU_CSLX_EPU ,CSU_ALL_RW }, + {CSU_CSLX_GDI ,CSU_ALL_RW }, + {CSU_CSLX_DDI ,CSU_ALL_RW }, + {CSU_CSLX_RESERVED1 ,CSU_ALL_RW }, + {CSU_CSLX_USB3_PHY ,CSU_ALL_RW }, + {CSU_CSLX_RESERVED2 ,CSU_ALL_RW }, +}; +#endif +int checkboard (void ) {#ifndef CONFIG_QSPI_BOOT
@@ -289,6 +375,12 @@ void board_init_f(ulong dummy)dram_init (); +/* Allow OCRAM access permission as R/W */ +#ifdef CONFIG_LS102XA_NS_ACCESS +enable_devices_ns_access (&ns_dev[4 ],1 ); +enable_devices_ns_access (&ns_dev[7 ],1 ); +#endif + board_init_r(NULL, 0); }#endif
@@ -441,92 +533,6 @@ int misc_init_r(void)return 0 ; } -#ifdef CONFIG_LS102XA_NS_ACCESS -static struct csu_ns_dev ns_dev[] = { - {CSU_CSLX_PCIE2_IO ,CSU_ALL_RW }, - {CSU_CSLX_PCIE1_IO ,CSU_ALL_RW }, - {CSU_CSLX_MG2TPR_IP ,CSU_ALL_RW }, - {CSU_CSLX_IFC_MEM ,CSU_ALL_RW }, - {CSU_CSLX_OCRAM ,CSU_ALL_RW }, - {CSU_CSLX_GIC ,CSU_ALL_RW }, - {CSU_CSLX_PCIE1 ,CSU_ALL_RW }, - {CSU_CSLX_OCRAM2 ,CSU_ALL_RW }, - {CSU_CSLX_QSPI_MEM ,CSU_ALL_RW }, - {CSU_CSLX_PCIE2 ,CSU_ALL_RW }, - {CSU_CSLX_SATA ,CSU_ALL_RW }, - {CSU_CSLX_USB3 ,CSU_ALL_RW }, - {CSU_CSLX_SERDES ,CSU_ALL_RW }, - {CSU_CSLX_QDMA ,CSU_ALL_RW }, - {CSU_CSLX_LPUART2 ,CSU_ALL_RW }, - {CSU_CSLX_LPUART1 ,CSU_ALL_RW }, - {CSU_CSLX_LPUART4 ,CSU_ALL_RW }, - {CSU_CSLX_LPUART3 ,CSU_ALL_RW }, - {CSU_CSLX_LPUART6 ,CSU_ALL_RW }, - {CSU_CSLX_LPUART5 ,CSU_ALL_RW }, - {CSU_CSLX_DSPI2 ,CSU_ALL_RW }, - {CSU_CSLX_DSPI1 ,CSU_ALL_RW }, - {CSU_CSLX_QSPI ,CSU_ALL_RW }, - {CSU_CSLX_ESDHC ,CSU_ALL_RW }, - {CSU_CSLX_2D_ACE ,CSU_ALL_RW }, - {CSU_CSLX_IFC ,CSU_ALL_RW }, - {CSU_CSLX_I2C1 ,CSU_ALL_RW }, - {CSU_CSLX_USB2 ,CSU_ALL_RW }, - {CSU_CSLX_I2C3 ,CSU_ALL_RW }, - {CSU_CSLX_I2C2 ,CSU_ALL_RW }, - {CSU_CSLX_DUART2 ,CSU_ALL_RW }, - {CSU_CSLX_DUART1 ,CSU_ALL_RW }, - {CSU_CSLX_WDT2 ,CSU_ALL_RW }, - {CSU_CSLX_WDT1 ,CSU_ALL_RW }, - {CSU_CSLX_EDMA ,CSU_ALL_RW }, - {CSU_CSLX_SYS_CNT ,CSU_ALL_RW }, - {CSU_CSLX_DMA_MUX2 ,CSU_ALL_RW }, - {CSU_CSLX_DMA_MUX1 ,CSU_ALL_RW }, - {CSU_CSLX_DDR ,CSU_ALL_RW }, - {CSU_CSLX_QUICC ,CSU_ALL_RW }, - {CSU_CSLX_DCFG_CCU_RCPM ,CSU_ALL_RW }, - {CSU_CSLX_SECURE_BOOTROM ,CSU_ALL_RW }, - {CSU_CSLX_SFP ,CSU_ALL_RW }, - {CSU_CSLX_TMU ,CSU_ALL_RW }, - {CSU_CSLX_SECURE_MONITOR ,CSU_ALL_RW }, - {CSU_CSLX_RESERVED0 ,CSU_ALL_RW }, - {CSU_CSLX_ETSEC1 ,CSU_ALL_RW }, - {CSU_CSLX_SEC5_5 ,CSU_ALL_RW }, - {CSU_CSLX_ETSEC3 ,CSU_ALL_RW }, - {CSU_CSLX_ETSEC2 ,CSU_ALL_RW }, - {CSU_CSLX_GPIO2 ,CSU_ALL_RW }, - {CSU_CSLX_GPIO1 ,CSU_ALL_RW }, - {CSU_CSLX_GPIO4 ,CSU_ALL_RW }, - {CSU_CSLX_GPIO3 ,CSU_ALL_RW }, - {CSU_CSLX_PLATFORM_CONT ,CSU_ALL_RW }, - {CSU_CSLX_CSU ,CSU_ALL_RW }, - {CSU_CSLX_ASRC ,CSU_ALL_RW }, - {CSU_CSLX_SPDIF ,CSU_ALL_RW }, - {CSU_CSLX_FLEXCAN2 ,CSU_ALL_RW }, - {CSU_CSLX_FLEXCAN1 ,CSU_ALL_RW }, - {CSU_CSLX_FLEXCAN4 ,CSU_ALL_RW }, - {CSU_CSLX_FLEXCAN3 ,CSU_ALL_RW }, - {CSU_CSLX_SAI2 ,CSU_ALL_RW }, - {CSU_CSLX_SAI1 ,CSU_ALL_RW }, - {CSU_CSLX_SAI4 ,CSU_ALL_RW }, - {CSU_CSLX_SAI3 ,CSU_ALL_RW }, - {CSU_CSLX_FTM2 ,CSU_ALL_RW }, - {CSU_CSLX_FTM1 ,CSU_ALL_RW }, - {CSU_CSLX_FTM4 ,CSU_ALL_RW }, - {CSU_CSLX_FTM3 ,CSU_ALL_RW }, - {CSU_CSLX_FTM6 ,CSU_ALL_RW }, - {CSU_CSLX_FTM5 ,CSU_ALL_RW }, - {CSU_CSLX_FTM8 ,CSU_ALL_RW }, - {CSU_CSLX_FTM7 ,CSU_ALL_RW }, - {CSU_CSLX_COP_DCSR ,CSU_ALL_RW }, - {CSU_CSLX_EPU ,CSU_ALL_RW }, - {CSU_CSLX_GDI ,CSU_ALL_RW }, - {CSU_CSLX_DDI ,CSU_ALL_RW }, - {CSU_CSLX_RESERVED1 ,CSU_ALL_RW }, - {CSU_CSLX_USB3_PHY ,CSU_ALL_RW }, - {CSU_CSLX_RESERVED2 ,CSU_ALL_RW }, -}; -#endif -struct liodn_id_table sec_liodn_tbl[] = {SET_SEC_JR_LIODN_ENTRY (0 ,0x10 ,0x10 ),SET_SEC_JR_LIODN_ENTRY (1 ,0x10 ,0x10 ),
board/freescale/ls1021atwr/ls1021atwr.c +92 -85
193 lines not on this page · raw message
Signature · 1 line
2.1.0.27.g96db324
PATCH 1/1 arm: ls1021a: allow OCRAM access permission as R/W in SPL
Quoted 6 lines · Alison Wang
On LS1021A Rev2.0, OCRAM's security level needs to be changed to non-secure access for SD boot. This patch will allow OCRAM access permission as R/W in SPL.
Signed-off-by Alison Wang <[email protected]>---
Applied to u-boot-fsl-qoriq master after fixing subject. Thanks.
York