CAAM RNG fixes
cover CAAM RNG fixes
This set of patches fixes some issues identified with the usage of the RNG block of the CAAM in newer SoCs e.g. T2080.
Alex Porosanu (3):
crypto/fsl - disable RNG oscillator maximum frequency check crypto/fsl - change starting entropy delay value crypto/fsl - enable raw data instead of von Neumann data
drivers/crypto/fsl/jr.c | 15 ++++++++++++--- include/fsl_sec.h | 13 ++++++++++++- 2 files changed, 24 insertions(+), 4 deletions(-)
Signature · 1 line
1.9.1
PATCH 1/3 crypto/fsl - disable RNG oscillator maximum frequency check
The rtfrqmax & rtfrqmin set the bounds of the expected frequency of the oscillator, when SEC runs at its maximum frequency. For certain platforms (f.i. T2080), the oscillator is very fast and thus if the SEC runs at a lower than normal frequency, the ring oscillator is incorrectly detected as being out of bounds.
This patch effectively disables the maximum frequency check, by setting a high enough maximum allowable frequency for the oscillator. The reasoning behind this is that usually a broken oscillator will run too slow (i.e. not run at all) rather than run too fast.
--- drivers/crypto/fsl/jr.c | 4 ++-- include/fsl_sec.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-)
drivers/crypto/fsl/jr.c +2 -2
@@ -406,8 +406,8 @@ static void kick_trng(int ent_delay)sec_out32 (&rng->rtsdctl, val);/* min. freq. count, equal to 1/4 of the entropy sample length */ sec_out32 (&rng->rtfreqmin, ent_delay >>2 ); -/* max. freq. count, equal to 8 times the entropy sample length */ -sec_out32 (&rng->rtfreqmax, ent_delay <<3 ); +/* disable maximum frequency count */ +sec_out32 (&rng->rtfreqmax,RTFRQMAX_DISABLE );/* put RNG4 into run mode */ sec_clrbits32 (&rng->rtmctl,RTMCTL_PRGM ); }
include/fsl_sec.h +1 -0
@@ -49,6 +49,7 @@ struct rng4tst {u32 rttotsam;/* PRGM=0: total samples register */ };u32 rtfreqmin;/* frequency count min. limit register */ +#define RTFRQMAX_DISABLE (1 << 20)union {u32 rtfreqmax;/* PRGM=1: freq. count max. limit register */ u32 rtfreqcnt;/* PRGM=0: freq. count register */
Signature · 1 line
1.9.1
A message that is not in the archive (sent off-list or not yet received): [email protected]
PATCH 1/3 crypto/fsl - disable RNG oscillator maximum frequency check
Quoted 58 lines
-----Original Message-----
From: Sun York-R58495
Sent: Sunday, July 19, 2015 3:43 AM
To: Gupta Ruchika-R66431
Subject: Re: [PATCH 1/3]crypto/fsl- disable RNG oscillator maximum frequency checkRuchika,
Please comment/ack this patch and others in this set.
York
Quoted 43 lines · Alex Porosanu
The rtfrqmax & rtfrqmin set the bounds of the expected frequency of the oscillator, when SEC runs at its maximum frequency. For certain platforms (f.i. T2080), the oscillator is very fast and thus if the SEC runs at a lower than normal frequency, the ring oscillator is incorrectly detected as being out of bounds.
This patch effectively disables the maximum frequency check, by setting a high enough maximum allowable frequency for the oscillator. The reasoning behind this is that usually a broken oscillator will run too slow (i.e. not run at all) rather than run too fast.
Signed-off-by Alex Porosanu <[email protected]>--- drivers/crypto/fsl/jr.c | 4 ++-- include/fsl_sec.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-)drivers/crypto/fsl/jr.c index renamed from drivers/crypto/fsl/jr.c +0
-0f99d594..aa527ec 100644
drivers/crypto/fsl/jr.c +2
-2@@ -406,8 +406,8 @@ static void kick_trng(int ent_delay)sec_out32 (&rng->rtsdctl, val);/* min. freq. count, equal to 1/4 of the entropy sample length */ sec_out32 (&rng->rtfreqmin, ent_delay >>2 ); -/* max. freq. count, equal to 8 times the entropy sample length */ -sec_out32 (&rng->rtfreqmax, ent_delay <<3 ); +/* disable maximum frequency count */ +sec_out32 (&rng->rtfreqmax,RTFRQMAX_DISABLE );/* put RNG4 into run mode */ sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM); } diff --git
a/include/fsl_sec.hb/include/fsl_sec.hindex ebb1ac6..14f6633 100644include/fsl_sec.h +1
-0@@ -49,6 +49,7 @@ struct rng4tst {u32 rttotsam;/* PRGM=0: total samples register */ };u32 rtfreqmin;/* frequency count min. limit register */ +#define RTFRQMAX_DISABLE (1 << 20)union {u32 rtfreqmax;/* PRGM=1: freq. count max. limit register */ u32 rtfreqcnt;/* PRGM=0: freq. count register */
PATCH 1/3 crypto/fsl - disable RNG oscillator maximum frequency check
In reply to Alex PorosanuQuoted 6 lines · Alex Porosanu
The rtfrqmax & rtfrqmin set the bounds of the expected frequency of the oscillator, when SEC runs at its maximum frequency. For certain platforms (f.i. T2080), the oscillator is very fast and thus if the SEC runs at a lower than normal frequency, the ring oscillator is incorrectly detected as being out of bounds.
Quoted 7 lines
This patch effectively disables the maximum frequency check, by setting a high enough maximum allowable frequency for the oscillator. The reasoning behind this is that usually a broken oscillator will run too slow (i.e. not run at all) rather than run too fast.
Signed-off-by Alex Porosanu <[email protected]>---
Applied to u-boot-fsl-qoriq master with minor change in subject. Thanks.
York
PATCH 2/3 crypto/fsl - change starting entropy delay value
In reply to Alex PorosanuThe entropy delay (the length in system clocks of each entropy sample) for the RNG4 block of CAAM is dependent on the frequency of the SoC. By elaborate methods, it has been determined that a good starting value for all platforms integrating the CAAM IP is 3200. Using a higher value has additional benefit of speeding up the process of instantiating the RNG, since the entropy delay will be increased and instantiation of the RNG state handles will be reattempted by the driver. If the starting value is low, for certain platforms, this can lead to a quite lengthy process.
This patch changes the starting value of the length of the entropy sample to 3200 system clocks.
In addition to this change, the attempted entropy delay values are now printed on the console upon initialization of the RNG block.
--- include/fsl_sec.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
include/fsl_sec.h +1 -1
@@ -35,7 +35,7 @@ struct rng4tst {u32 rtmctl;/* misc. control register */ u32 rtscmisc;/* statistical check misc. register */ u32 rtpkrrng;/* poker range register */ -#define RTSDCTL_ENT_DLY_MIN 1200 +#define RTSDCTL_ENT_DLY_MIN 3200#define RTSDCTL_ENT_DLY_MAX 12800union {u32 rtpkrmax;/* PRGM=1: poker max. limit register */
Signature · 1 line
1.9.1
A message that is not in the archive (sent off-list or not yet received): [email protected]
PATCH 2/3 crypto/fsl - change starting entropy delay value
Quoted 46 lines
-----Original Message-----
From: Sun York-R58495
Sent: Sunday, July 19, 2015 3:43 AM
To: Gupta Ruchika-R66431
Subject: Re: [PATCH 2/3]crypto/fsl- change starting entropy delay valueRuchika,
Please comment/ack this patch and others in this set.
York
Quoted 33 lines · Alex Porosanu
The entropy delay (the length in system clocks of each entropy sample) for the RNG4 block of CAAM is dependent on the frequency of the SoC. By elaborate methods, it has been determined that a good starting value for all platforms integrating the CAAM IP is 3200. Using a higher value has additional benefit of speeding up the process of instantiating the RNG, since the entropy delay will be increased and instantiation of the RNG state handles will be reattempted by the driver. If the starting value is low, for certain platforms, this can lead to a quite lengthy process.
This patch changes the starting value of the length of the entropy sample to 3200 system clocks.
In addition to this change, the attempted entropy delay values are now printed on the console upon initialization of the RNG block.Signed-off-by Alex Porosanu <[email protected]>--- include/fsl_sec.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)include/fsl_sec.h index renamed from include/fsl_sec.h +0
-014f6633..c84b6ad 100644
include/fsl_sec.h +1
-1@@ -35,7 +35,7 @@ struct rng4tst {u32 rtmctl;/* misc. control register */ u32 rtscmisc;/* statistical check misc. register */ u32 rtpkrrng;/* poker range register */ -#define RTSDCTL_ENT_DLY_MIN 1200 +#define RTSDCTL_ENT_DLY_MIN 3200#define RTSDCTL_ENT_DLY_MAX 12800union {u32 rtpkrmax;/* PRGM=1: poker max. limit register */
PATCH 2/3 crypto/fsl - change starting entropy delay value
In reply to Alex PorosanuQuoted 17 lines · Alex Porosanu
The entropy delay (the length in system clocks of each entropy sample) for the RNG4 block of CAAM is dependent on the frequency of the SoC. By elaborate methods, it has been determined that a good starting value for all platforms integrating the CAAM IP is 3200. Using a higher value has additional benefit of speeding up the process of instantiating the RNG, since the entropy delay will be increased and instantiation of the RNG state handles will be reattempted by the driver. If the starting value is low, for certain platforms, this can lead to a quite lengthy process.
This patch changes the starting value of the length of the entropy sample to 3200 system clocks.
In addition to this change, the attempted entropy delay values are now printed on the console upon initialization of the RNG block.
Quoted 2 lines
Signed-off-by Alex Porosanu <[email protected]>---
Applied to u-boot-fsl-qoriq master with minor change in subject. Thanks.
York
PATCH 3/3 crypto/fsl - enable raw data instead of von Neumann data
In reply to Alex PorosanuThe sampling of the oscillator can be done in multiple modes for generating the entropy value. By default, this is set to von Neumann. This patch changes the sampling to raw data, since it has been discovered that the generated entropy has a better 'quality'.
--- drivers/crypto/fsl/jr.c | 11 ++++++++++- include/fsl_sec.h | 10 ++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-)
drivers/crypto/fsl/jr.c +10 -1
@@ -408,8 +408,17 @@ static void kick_trng(int ent_delay)sec_out32 (&rng->rtfreqmin, ent_delay >>2 );/* disable maximum frequency count */ sec_out32 (&rng->rtfreqmax,RTFRQMAX_DISABLE ); +/* read the control register */ + val =sec_in32 (&rng->rtmctl); +/* +* select raw sampling in both entropy shifter +* and statistical checker +*/ +sec_setbits32 (&val,RTMCTL_SAMP_MODE_RAW_ES_SC );/* put RNG4 into run mode */ -sec_clrbits32 (&rng->rtmctl,RTMCTL_PRGM ); +sec_clrbits32 (&val,RTMCTL_PRGM ); +/* write back the control register */ +sec_out32 (&rng->rtmctl, val); }static int rng_init (void )
include/fsl_sec.h +10 -0
@@ -32,6 +32,16 @@/* RNG4 TRNG test registers */ struct rng4tst {#define RTMCTL_PRGM 0x00010000/* 1 -> program mode, 0 -> run mode */ +#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0/* use von Neumann data in +both entropy shifter and +statistical checker */ +#define RTMCTL_SAMP_MODE_RAW_ES_SC 1/* use raw data in both +entropy shifter and +statistical checker */ +#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2/* use von Neumann data in +entropy shifter, raw data +in statistical checker */ +#define RTMCTL_SAMP_MODE_INVALID 3/* invalid combination */ u32 rtmctl;/* misc. control register */ u32 rtscmisc;/* statistical check misc. register */ u32 rtpkrrng;/* poker range register */
Signature · 1 line
1.9.1
A message that is not in the archive (sent off-list or not yet received): [email protected]
PATCH 3/3 crypto/fsl - enable raw data instead of von Neumann data
Quoted 75 lines
-----Original Message-----
From: Sun York-R58495
Sent: Sunday, July 19, 2015 3:43 AM
To: Gupta Ruchika-R66431
Subject: Re: [PATCH 3/3]crypto/fsl- enable raw data instead of von Neumann dataRuchika,
Please comment/ack.
York
Quoted 39 lines · Alex Porosanu
The sampling of the oscillator can be done in multiple modes for generating the entropy value. By default, this is set to von Neumann. This patch changes the sampling to raw data, since it has been discovered that the generated entropy has a better 'quality'.
Signed-off-by Alex Porosanu <[email protected]>--- drivers/crypto/fsl/jr.c | 11 ++++++++++- include/fsl_sec.h | 10 ++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-)drivers/crypto/fsl/jr.c index renamed from drivers/crypto/fsl/jr.c +0
-0aa527ec..3560668 100644
drivers/crypto/fsl/jr.c +10
-1@@ -408,8 +408,17 @@ static void kick_trng(int ent_delay)sec_out32 (&rng->rtfreqmin, ent_delay >>2 );/* disable maximum frequency count */ sec_out32 (&rng->rtfreqmax,RTFRQMAX_DISABLE ); +/* read the control register */ + val =sec_in32 (&rng->rtmctl); +/* +* select raw sampling in both entropy shifter +* and statistical checker +*/ +sec_setbits32 (&val,RTMCTL_SAMP_MODE_RAW_ES_SC );/* put RNG4 into run mode */ -sec_clrbits32 (&rng->rtmctl,RTMCTL_PRGM ); +sec_clrbits32 (&val,RTMCTL_PRGM ); +/* write back the control register */ +sec_out32 (&rng->rtmctl, val); }static int rng_init (void )include/fsl_sec.h index renamed from include/fsl_sec.h +0
-0c84b6ad..672bcef 100644
include/fsl_sec.h line 34
Quoted 3 lines
include/fsl_sec.h +0
-0@@ -32,6 +32,16 @@/* RNG4 TRNG test registers */ struct rng4tst {#define RTMCTL_PRGM 0x00010000/* 1 -> program mode, 0 -> run mode */
include/fsl_sec.h line 35
Quoted 1 line
include/fsl_sec.h +1
-0+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0/* use von Neumann data in
include/fsl_sec.h
Quoted 3 lines
include/fsl_sec.h +3
-0+both entropy shifter and +statistical checker */ +#define RTMCTL_SAMP_MODE_RAW_ES_SC 1/* use raw data in both
include/fsl_sec.h
Quoted 3 lines
include/fsl_sec.h +3
-0+entropy shifter and +statistical checker */ +#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2/* use von Neumann data in
include/fsl_sec.h
Quoted 3 lines
include/fsl_sec.h +3
-0+entropy shifter, raw data +in statistical checker */ +#define RTMCTL_SAMP_MODE_INVALID 3/* invalid combination */
Quoted 4 lines
include/fsl_sec.h +0
-0u32 rtmctl;/* misc. control register */ u32 rtscmisc;/* statistical check misc. register */ u32 rtpkrrng;/* poker range register */
PATCH 3/3 crypto/fsl - enable raw data instead of von Neumann data
In reply to Alex PorosanuQuoted 8 lines · Alex Porosanu
The sampling of the oscillator can be done in multiple modes for generating the entropy value. By default, this is set to von Neumann. This patch changes the sampling to raw data, since it has been discovered that the generated entropy has a better 'quality'.
Signed-off-by Alex Porosanu <[email protected]>---
Applied to u-boot-fsl-qoriq master with minor change in subject. Thanks.
York