crypto/fsl: fix "era" property value on LE platforms
PATCH 1/3 crypto/fsl: fix "era" property value on LE platforms
Use fdt_setprop_u32() instead of fdt_setprop().
--- drivers/crypto/fsl/sec.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
drivers/crypto/fsl/sec.c +1 -2
@@ -155,8 +155,7 @@ static void fdt_fixup_crypto_era(void *blob, u32 era)return ; } - err =fdt_setprop (blob, crypto_node,"fsl,sec-era" , &era, -sizeof (era)); + err =fdt_setprop_u32 (blob, crypto_node,"fsl,sec-era" , era);if (err <0 ) {printf ("ERROR: could not set fsl,sec-era property: %s\n" ,fdt_strerror (err));
Signature · 1 line
2.4.4
PATCH 2/3 crypto/fsl: fix snooping for write transactions
HW coherency won't work properly for CAAM write transactions if AWCACHE is left to default (POR) value - 4'b0001. It has to be programmed to 4'b0010.
For platforms that have HW coherency support:
-PPC-based: the update has no effect; CAAM coherency already works due to the IOMMU (PAMU) driver setting the correct memory coherency attributes
-ARM-based: the update fixes cache coherency issues,
since IOMMU (SMMU) driver is not programmed to behave similar to PAMU
--- drivers/crypto/fsl/jr.c | 10 ++++++---- drivers/crypto/fsl/jr.h | 2 ++ 2 files changed, 8 insertions(+), 4 deletions(-)
drivers/crypto/fsl/jr.c +6 -4
@@ -459,14 +459,16 @@ static int rng_init(void)int sec_init (void ) { -int ret =0 ; - -#ifdef CONFIG_PHYS_64BIT ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR ;uint32_t mcr =sec_in32 (&sec->mcfgr); +int ret =0 ; -sec_out32 (&sec->mcfgr, mcr |1 <<MCFGR_PS_SHIFT ); + mcr = (mcr & ~MCFGR_AWCACHE_MASK ) | (0x2 <<MCFGR_AWCACHE_SHIFT ); +#ifdef CONFIG_PHYS_64BIT + mcr |= (1 <<MCFGR_PS_SHIFT );#endif +sec_out32 (&sec->mcfgr, mcr); + ret =jr_init ();if (ret <0 ) {printf ("SEC initialization failed\n" );
drivers/crypto/fsl/jr.h +2 -0
@@ -21,6 +21,8 @@#define MCFGR_SWRST ((uint32_t)(1)<<31)/* Software Reset */ #define MCFGR_DMA_RST ((uint32_t)(1)<<28)/* DMA Reset */ #define MCFGR_PS_SHIFT 16 +#define MCFGR_AWCACHE_SHIFT 8 +#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)#define JR_INTMASK 0x00000001#define JRCR_RESET 0x01#define JRINT_ERR_HALT_INPROGRESS 0x4
Signature · 1 line
2.4.4
A message that is not in the archive (sent off-list or not yet received): [email protected]
PATCH 2/3 crypto/fsl: fix snooping for write transactions
Quoted 74 lines
-----Original Message-----
From: Sun York-R58495
Sent: Sunday, July 19, 2015 3:44 AM
To: Gupta Ruchika-R66431
Subject: Re: [PATCH 2/3]crypto/fsl: fix snooping for write transactionsRuchika,
Please comment/ack.
York
Quoted 28 lines · Horia Geant?
HW coherency won't work properly for CAAM write transactions if AWCACHE is left to default (POR) value - 4'b0001.
It has to be programmed to 4'b0010.For platforms that have HW coherency support:
-PPC-based: the update has no effect; CAAM coherency already works due to the IOMMU (PAMU) driver setting the correct memory coherency attributes
-ARM-based: the update fixes cache coherency issues, since IOMMU (SMMU) driver is not programmed to behave similar to PAMUFixes b9eebfade974c ("fsl_sec: Add hardware accelerated SHA256 andSHA1")
Signed-off-by Horia Geant? <[email protected]>Reviewed-by Aneesh Bansal <[email protected]>Reviewed-by Mingkai Hu <[email protected]>--- drivers/crypto/fsl/jr.c | 10 ++++++---- drivers/crypto/fsl/jr.h | 2 ++ 2 files changed, 8 insertions(+), 4 deletions(-)drivers/crypto/fsl/jr.c index renamed from drivers/crypto/fsl/jr.c +0
-0
f99d59480c81..e2bd913aa259100644drivers/crypto/fsl/jr.c +0
-0@@ -459,14 +459,16 @@ static int rng_init(void)int sec_init (void )drivers/crypto/fsl/jr.c static int rng_init(void) · line 466
Quoted 10 lines
drivers/crypto/fsl/jr.c +2
-4{ -int ret =0 ; - -#ifdef CONFIG_PHYS_64BIT ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR ;uint32_t mcr =sec_in32 (&sec->mcfgr); +int ret =0 ; -sec_out32 (&sec->mcfgr, mcr |1 <<MCFGR_PS_SHIFT ); + mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 <<
MCFGR_AWCACHE_SHIFT);Quoted 22 lines
drivers/crypto/fsl/jr.c +4
-0+#ifdef CONFIG_PHYS_64BIT + mcr |= (1 <<MCFGR_PS_SHIFT );#endif +sec_out32 (&sec->mcfgr, mcr); + ret =jr_init ();if (ret <0 ) { printf("SEC initialization failed\n"); diff --git
a/drivers/crypto/fsl/jr.hb/drivers/crypto/fsl/jr.hindex cce2c589ce0b..152606008845 100644drivers/crypto/fsl/jr.h +2
-0@@ -21,6 +21,8 @@#define MCFGR_SWRST ((uint32_t)(1)<<31)/* Software Reset */ #define MCFGR_DMA_RST ((uint32_t)(1)<<28)/* DMA Reset */ #define MCFGR_PS_SHIFT 16 +#define MCFGR_AWCACHE_SHIFT 8 +#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)#define JR_INTMASK 0x00000001#define JRCR_RESET 0x01#define JRINT_ERR_HALT_INPROGRESS 0x4
PATCH 2/3 crypto/fsl: fix snooping for write transactions
In reply to Horia GeantăQuoted 11 lines · Horia Geant?
HW coherency won't work properly for CAAM write transactions if AWCACHE is left to default (POR) value - 4'b0001. It has to be programmed to 4'b0010.
For platforms that have HW coherency support:
-PPC-based: the update has no effect; CAAM coherency already works due to the IOMMU (PAMU) driver setting the correct memory coherency attributes
-ARM-based: the update fixes cache coherency issues,
since IOMMU (SMMU) driver is not programmed to behave similar to PAMU
Quoted 5 lines
Fixes b9eebfade974c ("fsl_sec: Add hardware accelerated SHA256 and SHA1")Signed-off-by Horia Geant? <[email protected]>Reviewed-by Aneesh Bansal <[email protected]>Reviewed-by Mingkai Hu <[email protected]>---
Applied to u-boot-fsl-qoriq master with minor change in subject. Thanks.
York
PATCH 3/3 crypto/fsl: clean-up - use fdt_setprop_u32 helper
In reply to Horia Geantă--- drivers/crypto/fsl/sec.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-)
drivers/crypto/fsl/sec.c +8 -9
@@ -60,27 +60,26 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)return ; } - val =cpu_to_fdt32 (sec_rev_prop_list[sec_idx].num_channels); - err =fdt_setprop (blob, crypto_node,"fsl,num-channels" , &val,4 ); + err =fdt_setprop_u32 (blob, crypto_node,"fsl,num-channels" , + sec_rev_prop_list[sec_idx].num_channels);if (err <0 )printf ("WARNING: could not set crypto property: %s\n" ,fdt_strerror (err)); - val =cpu_to_fdt32 (sec_rev_prop_list[sec_idx].descriptor_types_mask); - err =fdt_setprop (blob, crypto_node,"fsl,descriptor-types-mask" , - &val,4 ); + err =fdt_setprop_u32 (blob, crypto_node,"fsl,descriptor-types-mask" , + sec_rev_prop_list[sec_idx].descriptor_types_mask);if (err <0 )printf ("WARNING: could not set crypto property: %s\n" ,fdt_strerror (err)); - val =cpu_to_fdt32 (sec_rev_prop_list[sec_idx].exec_units_mask); - err =fdt_setprop (blob, crypto_node,"fsl,exec-units-mask" , &val,4 ); + err =fdt_setprop_u32 (blob, crypto_node,"fsl,exec-units-mask" , + sec_rev_prop_list[sec_idx].exec_units_mask);if (err <0 )printf ("WARNING: could not set crypto property: %s\n" ,fdt_strerror (err)); - val =cpu_to_fdt32 (sec_rev_prop_list[sec_idx].channel_fifo_len); - err =fdt_setprop (blob, crypto_node,"fsl,channel-fifo-len" , &val,4 ); + err =fdt_setprop_u32 (blob, crypto_node,"fsl,channel-fifo-len" , + sec_rev_prop_list[sec_idx].channel_fifo_len);if (err <0 )printf ("WARNING: could not set crypto property: %s\n" ,fdt_strerror (err));
Signature · 1 line
2.4.4
A message that is not in the archive (sent off-list or not yet received): [email protected]
PATCH 3/3 crypto/fsl: clean-up - use fdt_setprop_u32 helper
Quoted 63 lines
-----Original Message-----
From: Sun York-R58495
Sent: Sunday, July 19, 2015 3:44 AM
To: Gupta Ruchika-R66431
Subject: Re: [PATCH 3/3]crypto/fsl: clean-up - usefdt_setprop_u32helperRuchika,
Please comment/ack.
York
drivers/crypto/fsl/sec.c void fdt_fixup_crypto_node(void *blob, int
Quoted 10 lines · Horia Geant?
Signed-off-by Horia Geant? <[email protected]>--- drivers/crypto/fsl/sec.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-)drivers/crypto/fsl/sec.c index renamed from drivers/crypto/fsl/sec.c +0
-0
b25b1a4052d2..0940faf768cc100644drivers/crypto/fsl/sec.c +0
-0@@ -60,27 +60,26 @@ void fdt_fixup_crypto_node(void *blob, int
sec_rev)drivers/crypto/fsl/sec.c void fdt_fixup_crypto_node(void *blob, int sec_rev)
Quoted 12 lines
drivers/crypto/fsl/sec.c +2
-3return ; } - val =cpu_to_fdt32 (sec_rev_prop_list[sec_idx].num_channels); - err =fdt_setprop (blob, crypto_node,"fsl,num-channels" , &val,4 ); + err =fdt_setprop_u32 (blob, crypto_node,"fsl,num-channels" , + sec_rev_prop_list[sec_idx].num_channels);if (err <0 )printf ("WARNING: could not set crypto property: %s\n" ,fdt_strerror (err)); - val =
cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask);drivers/crypto/fsl/sec.c void fdt_fixup_crypto_node(void *blob, int sec_rev)
Quoted 3 lines
drivers/crypto/fsl/sec.c +1
-2- err =fdt_setprop (blob, crypto_node,"fsl,descriptor-types-mask" , - &val,4 ); + err = fdt_setprop_u32(blob, crypto_node, "fsl,descriptor-types-mask",
drivers/crypto/fsl/sec.c void fdt_fixup_crypto_node(void *blob, int · line 70
Quoted 1 line
drivers/crypto/fsl/sec.c +1
-0+sec_rev_prop_list[sec_idx].descriptor_types_mask);
Quoted 20 lines
drivers/crypto/fsl/sec.c +4
-4if (err <0 )printf ("WARNING: could not set crypto property: %s\n" ,fdt_strerror (err)); - val =cpu_to_fdt32 (sec_rev_prop_list[sec_idx].exec_units_mask); - err =fdt_setprop (blob, crypto_node,"fsl,exec-units-mask" , &val,4 ); + err =fdt_setprop_u32 (blob, crypto_node,"fsl,exec-units-mask" , + sec_rev_prop_list[sec_idx].exec_units_mask);if (err <0 )printf ("WARNING: could not set crypto property: %s\n" ,fdt_strerror (err)); - val =cpu_to_fdt32 (sec_rev_prop_list[sec_idx].channel_fifo_len); - err =fdt_setprop (blob, crypto_node,"fsl,channel-fifo-len" , &val,4 ); + err =fdt_setprop_u32 (blob, crypto_node,"fsl,channel-fifo-len" , + sec_rev_prop_list[sec_idx].channel_fifo_len);if (err <0 )printf ("WARNING: could not set crypto property: %s\n" ,fdt_strerror (err));
PATCH 3/3 crypto/fsl: clean-up - use fdt_setprop_u32 helper
In reply to Horia GeantăQuoted 2 lines · Horia Geant?
Signed-off-by Horia Geant? <[email protected]>---
Applied to u-boot-fsl-qoriq master with minor change in subject. Thanks.
York
A message that is not in the archive (sent off-list or not yet received): [email protected]
PATCH 1/3 crypto/fsl: fix "era" property value on LE platforms
Quoted 38 lines
-----Original Message-----
From: Sun York-R58495
Sent: Sunday, July 19, 2015 3:44 AM
To: Gupta Ruchika-R66431
Subject: Re: [PATCH 1/3]crypto/fsl: fix "era" property value on LE platformsRuchika,
Please comment/ack.
York
drivers/crypto/fsl/sec.c static void fdt_fixup_crypto_era(void *blob, u32
Quoted 14 lines · Horia Geant?
Use
fdt_setprop_u32()instead offdt_setprop().Fixes 0181937fa371a ("crypto/fsl: Add fixup for crypto node")Signed-off-by Horia Geant? <[email protected]>Reviewed-by Mingkai Hu <[email protected]>--- drivers/crypto/fsl/sec.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)drivers/crypto/fsl/sec.c index renamed from drivers/crypto/fsl/sec.c +0
-0
443ee964feae..b25b1a4052d2100644drivers/crypto/fsl/sec.c +0
-0@@ -155,8 +155,7 @@ static void fdt_fixup_crypto_era(void *blob, u32era)
Quoted 10 lines
drivers/crypto/fsl/sec.c +1
-2return ; } - err =fdt_setprop (blob, crypto_node,"fsl,sec-era" , &era, -sizeof (era)); + err =fdt_setprop_u32 (blob, crypto_node,"fsl,sec-era" , era);if (err <0 ) {printf ("ERROR: could not set fsl,sec-era property: %s\n" ,fdt_strerror (err));
PATCH 1/3 crypto/fsl: fix "era" property value on LE platforms
In reply to Horia GeantăQuoted 6 lines · Horia Geant?
Use
fdt_setprop_u32()instead offdt_setprop().Fixes 0181937fa371a ("crypto/fsl: Add fixup for crypto node")Signed-off-by Horia Geant? <[email protected]>Reviewed-by Mingkai Hu <[email protected]>---
Applied to u-boot-fsl-qoriq master with minor change in subject. Thanks.
York