Skip to contentSkip to conversation

config: lsch3: Define USB XHCI controller base address for LS2085A

PATCH New Nikhil Badola 2 participants 2 messages Jun 26, 2015 – Aug 4, 2015 Arm (32-bit)

lore
Share & tools
lore

Nikhil Badola

author
#0 lore raw

PATCH v2 2/4 config: lsch3: Define USB XHCI controller base address for LS2085A

Define base address of both usb xhci controllers in lsch3 config in the format (IMMR + offset) for LS2085A

Signed-off-by Nikhil Badola <[email protected]>

---
Changes for v2 :
- Descriptive commit message

 arch/arm/include/asm/arch-fsl-lsch3/config.h | 3 +++
 1 file changed, 3 insertions(+)
arch/arm/include/asm/arch-fsl-lsch3/config.h +3 -0
index 02332dc..992dc11 100644
@@ -64,6 +64,9 @@
 #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
 #define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)
 
+#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02110000)
+
 /* TZ Protection Controller Definitions */
 #define TZPC_BASE				0x02200000
 #define TZPCR0SIZE_BASE				(TZPC_BASE)
Signature · 1 line
2.1.0
#1 lore raw

PATCH v2 2/4 config: lsch3: Define USB XHCI controller base address for LS2085A

Quoted 8 lines · Nikhil Badola

Define base address of both usb xhci controllers in lsch3 config in the format (IMMR + offset) for LS2085A

Signed-off-by Nikhil Badola <[email protected]>

---
Changes for v2 :
- Descriptive commit message

Applied to u-boot-fsl-qoriq master with minor change in subject. Thanks.

York