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ARM: Fix the secondary_startup function in Big Endian case

PATCH New Gregory CLEMENT 2 participants 3 messages Aug 6, 2015 Arm (32-bit)

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Gregory CLEMENT

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PATCH 1/1 ARM: Fix the secondary_startup function in Big Endian case

Since the commit "b2c3e38a5471 ARM: redo TTBR setup code for LPAE", the setup code had been reworked. As a result the secondary CPUs failed to come online in Big Endian.

As explained by Russell, the new code expected the value in r4/r5 to be the least significant 32bits in r4 and the most significant 32bits in r5. However, in the secondary code, we load this using ldrd, which on BE reverses that.

This patch swap r4/r5 after the ldrd. It is done using the xor instructions in order to not use a temporary register.

Signed-off-by Gregory CLEMENT <[email protected]>
---
 arch/arm/kernel/head.S | 3 +++
 1 file changed, 3 insertions(+)
arch/arm/kernel/head.S +3 -0
index bd755d97e459..75cbcf34c2e9 100644
@@ -399,6 +399,9 @@ ENTRY(secondary_startup)
 	sub	lr, r4, r5			@ mmu has been enabled
 	add	r3, r7, lr
 	ldrd	r4, [r3, #0]			@ get secondary_data.pgdir
+ARM_BE8(eor	r4, r4, r5)			@ swap r5 and r4 in BE
+ARM_BE8(eor	r5, r4, r5)			@ it can be done in 3 step
+ARM_BE8(eor	r4, r4, r5)			@ without using an temp reg
 	ldr	r8, [r3, #8]			@ get secondary_data.swapper_pg_dir
 	badr	lr, __enable_mmu		@ return address
 	mov	r13, r12			@ __secondary_switched address
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2.1.0
#1 lore raw

PATCH 1/1 ARM: Fix the secondary_startup function in Big Endian case

Quoted 11 lines · Gregory CLEMENT

Since the commit "b2c3e38a5471 ARM: redo TTBR setup code for LPAE", the setup code had been reworked. As a result the secondary CPUs failed to come online in Big Endian.

As explained by Russell, the new code expected the value in r4/r5 to be the least significant 32bits in r4 and the most significant 32bits in r5. However, in the secondary code, we load this using ldrd, which on BE reverses that.

This patch swap r4/r5 after the ldrd. It is done using the xor instructions in order to not use a temporary register.

Patch looks good to me, thanks.

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#2 lore raw

PATCH 1/1 ARM: Fix the secondary_startup function in Big Endian case

Quoted 10 lines · Russell King - ARM Linux
Quoted 9 lines · Gregory CLEMENT

Since the commit "b2c3e38a5471 ARM: redo TTBR setup code for LPAE", the setup code had been reworked. As a result the secondary CPUs failed to come online in Big Endian.

As explained by Russell, the new code expected the value in r4/r5 to be the least significant 32bits in r4 and the most significant 32bits in r5. However, in the secondary code, we load this using ldrd, which on BE reverses that.

Quoted 5 lines
Quoted 2 lines

This patch swap r4/r5 after the ldrd. It is done using the xor instructions in order to not use a temporary register.

Patch looks good to me, thanks.

So I am going to submit it to your patch system and in the same time I will fix the typo in my comment:

- @ it can be done in 3 step
- @ without using an temp reg
+ @ it can be done in 3 steps
+ @ without using a temp reg.

Thanks,

Gregory

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Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com