beagle_x15/omap5: Add dwc3 peripheral support

index 46af109..ac9a856 100644
@@ -91,6 +91,16 @@
 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL		(1 << 3)
 #define USBOTGSS_IRQMISC_IDPULLUP_FALL		(1 << 0)
 
+#define USBOTGSS_INTERRUPTS (USBOTGSS_IRQMISC_OEVT | \
+			     USBOTGSS_IRQMISC_DRVVBUS_RISE | \
+			     USBOTGSS_IRQMISC_CHRGVBUS_RISE | \
+			     USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | \
+			     USBOTGSS_IRQMISC_IDPULLUP_RISE | \
+			     USBOTGSS_IRQMISC_DRVVBUS_FALL | \
+			     USBOTGSS_IRQMISC_CHRGVBUS_FALL | \
+			     USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | \
+			     USBOTGSS_IRQMISC_IDPULLUP_FALL)
+
 /* UTMI_OTG_CTRL REGISTER */
 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS		(1 << 5)
 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS		(1 << 4)

@@ -187,6 +197,18 @@ static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
 						omap->irq0_offset, value);
 }
 
+static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
+{
+	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
+						omap->irqmisc_offset, value);
+}
+
+static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
+{
+	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
+						omap->irq0_offset, value);
+}
+
 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
 	enum omap_dwc3_vbus_id_status status)
 {

@@ -285,30 +307,18 @@ static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
 
 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
 {
-	u32			reg;
-
 	/* enable all IRQs */
-	reg = USBOTGSS_IRQO_COREIRQ_ST;
-	dwc3_omap_write_irq0_set(omap, reg);
-
-	reg = (USBOTGSS_IRQMISC_OEVT |
-			USBOTGSS_IRQMISC_DRVVBUS_RISE |
-			USBOTGSS_IRQMISC_CHRGVBUS_RISE |
-			USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
-			USBOTGSS_IRQMISC_IDPULLUP_RISE |
-			USBOTGSS_IRQMISC_DRVVBUS_FALL |
-			USBOTGSS_IRQMISC_CHRGVBUS_FALL |
-			USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
-			USBOTGSS_IRQMISC_IDPULLUP_FALL);
-
-	dwc3_omap_write_irqmisc_set(omap, reg);
+	dwc3_omap_write_irq0_set(omap, USBOTGSS_IRQO_COREIRQ_ST);
+
+	dwc3_omap_write_irqmisc_set(omap, USBOTGSS_INTERRUPTS);
 }
 
 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
 {
 	/* disable all IRQs */
-	dwc3_omap_write_irqmisc_set(omap, 0x00);
-	dwc3_omap_write_irq0_set(omap, 0x00);
+	dwc3_omap_write_irq0_clr(omap, USBOTGSS_IRQO_COREIRQ_ST);
+
+	dwc3_omap_write_irqmisc_clr(omap, USBOTGSS_INTERRUPTS);
 }
 
 static void dwc3_omap_map_offset(struct dwc3_omap *omap)

index 141ff8b..850ba02 100644
@@ -15,6 +15,7 @@
 #include <linux/usb/cdc.h>
 #include <linux/usb/gadget.h>
 #include <net.h>
+#include <usb.h>
 #include <malloc.h>
 #include <linux/ctype.h>
 

@@ -2312,6 +2313,8 @@ static int usb_eth_init(struct eth_device *netdev, bd_t *bd)
 		goto fail;
 	}
 
+	board_usb_init(0, USB_INIT_DEVICE);
+
 	/* Configure default mac-addresses for the USB ethernet device */
 #ifdef CONFIG_USBNET_DEV_ADDR
 	strlcpy(dev_addr, CONFIG_USBNET_DEV_ADDR, sizeof(dev_addr));

@@ -2492,6 +2495,7 @@ void usb_eth_halt(struct eth_device *netdev)
 	}
 
 	usb_gadget_unregister_driver(&eth_driver);
+	board_usb_cleanup(0, USB_INIT_DEVICE);
 }
 
 static struct usb_gadget_driver eth_driver = {

index 3a723ca..11440ac 100644
@@ -463,6 +463,9 @@ void enable_basic_clocks(void)
 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 		(*prcm)->cm_l3init_ocp2scp1_clkctrl,
 		(*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+		(*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
+#endif
 #endif
 		0
 	};

@@ -503,6 +506,19 @@ void enable_basic_clocks(void)
 	/* Enable 32 KHz clock for dwc3 */
 	setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
 		     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+	/* Enable 960 MHz clock for dwc3 */
+	setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
+		     OPTFCLKEN_REFCLK960M);
+
+	/* Enable 32 KHz clock for dwc3 */
+	setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
+		     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+	/* Enable 60 MHz clock for USB2PHY2 */
+	setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
+		     L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
+#endif
 #endif
 
 	/* Set the correct clock dividers for mmc */

index cd51fe7..99f847b 100644
@@ -809,6 +809,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_clkmode_dpll_gmac			= 0x4a0052a8,
 	.cm_coreaon_usb_phy1_core_clkctrl	= 0x4a008640,
 	.cm_coreaon_usb_phy2_core_clkctrl	= 0x4a008688,
+	.cm_coreaon_l3init_60m_gfclk_clkctrl	= 0x4a0086c0,
 
 	/* cm1.mpu */
 	.cm_mpu_mpu_clkctrl			= 0x4a005320,

@@ -919,6 +920,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_l3init_ocp2scp1_clkctrl		= 0x4a0093e0,
 	.cm_l3init_ocp2scp3_clkctrl		= 0x4a0093e8,
 	.cm_l3init_usb_otg_ss1_clkctrl		= 0x4a0093f0,
+	.cm_l3init_usb_otg_ss2_clkctrl		= 0x4a009340,
 
 	/* cm2.l4per */
 	.cm_l4per_clkstctrl			= 0x4a009700,

index f8e5630..38d50d6 100644
@@ -172,6 +172,9 @@
 /* CM_COREAON_USB_PHY_CORE_CLKCTRL */
 #define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K	(1 << 8)
 
+/* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */
+#define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK	(1 << 8)
+
 /* CM_L3INIT_USB_OTG_SS_CLKCTRL */
 #define OTG_SS_CLKCTRL_MODULEMODE_HW	(1 << 0)
 #define OPTFCLKEN_REFCLK960M			(1 << 8)

index 056affc..462a9ee 100644
@@ -145,6 +145,7 @@ struct prcm_regs {
 	u32 cm_ssc_modfreqdiv_dpll_unipro;
 	u32 cm_coreaon_usb_phy1_core_clkctrl;
 	u32 cm_coreaon_usb_phy2_core_clkctrl;
+	u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
 
 	/* cm2.core */
 	u32 cm_coreaon_bandgap_clkctrl;

@@ -231,6 +232,7 @@ struct prcm_regs {
 	u32 cm_l3init_ocp2scp1_clkctrl;
 	u32 cm_l3init_ocp2scp3_clkctrl;
 	u32 cm_l3init_usb_otg_ss1_clkctrl;
+	u32 cm_l3init_usb_otg_ss2_clkctrl;
 
 	u32 prm_irqstatus_mpu_2;
 

index e6048eb..4159e5a 100644
@@ -193,8 +193,11 @@ void ti_usb2_phy_power(struct ti_usb_phy *phy, int on)
 	val = readl(phy->usb2_phy_power);
 
 	if (on) {
-#ifdef CONFIG_DRA7XX
-		val &= ~OMAP_CTRL_DEV_PHY_PD;
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+		if (phy->index == 1)
+			val &= ~OMAP_CTRL_USB2_PHY_PD;
+		else
+			val &= ~OMAP_CTRL_DEV_PHY_PD;
 #elif defined(CONFIG_AM43XX)
 		val &= ~(AM437X_CTRL_USB2_PHY_PD |
 			 AM437X_CTRL_USB2_OTG_PD);

@@ -202,8 +205,12 @@ void ti_usb2_phy_power(struct ti_usb_phy *phy, int on)
 			AM437X_CTRL_USB2_OTGSESSEND_EN);
 #endif
 	} else {
-#ifdef CONFIG_DRA7XX
-		val |= OMAP_CTRL_DEV_PHY_PD;
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+		if (phy->index == 1)
+			val |= OMAP_CTRL_USB2_PHY_PD;
+		else
+			val |= OMAP_CTRL_DEV_PHY_PD;
+
 #elif defined(CONFIG_AM43XX)
 		val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
 			 AM437X_CTRL_USB2_OTGSESSEND_EN);

index 524fae4..9b66877 100644
@@ -33,7 +33,7 @@
 #define CONTROL_ID_CODE		CONTROL_CORE_ID_CODE
 #endif
 
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 #define DRA7_USB_OTG_SS1_BASE		0x48890000
 #define DRA7_USB_OTG_SS1_GLUE_BASE	0x48880000
 #define DRA7_USB3_PHY1_PLL_CTRL		0x4A084C00

124 lines not on this page · raw message

index 9b66877..bf5afbd 100644
@@ -43,6 +43,12 @@
 #define DRA7_USB_OTG_SS2_BASE		0x488D0000
 #define DRA7_USB_OTG_SS2_GLUE_BASE	0x488C0000
 #define DRA7_USB2_PHY2_POWER		0x4A002E74
+#else
+#define OMAP5XX_USB_OTG_SS_BASE		0x4A030000
+#define OMAP5XX_USB_OTG_SS_GLUE_BASE	0x4A020000
+#define OMAP5XX_USB3_PHY_PLL_CTRL	0x4A084C00
+#define OMAP5XX_USB3_PHY_POWER		0x4A002370
+#define OMAP5XX_USB2_PHY_POWER		0x4A002300
 #endif
 
 /* To be verified */

90 lines not on this page · raw message

index 7499447..78a2c25 100644
@@ -47,47 +47,6 @@
 	"uuid_disk=${uuid_gpt_disk};" \
 	"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
 
-#define DFU_ALT_INFO_MMC \
-	"dfu_alt_info_mmc=" \
-	"boot part 0 1;" \
-	"rootfs part 0 2;" \
-	"MLO fat 0 1;" \
-	"MLO.raw raw 0x100 0x100;" \
-	"u-boot.img.raw raw 0x300 0x400;" \
-	"spl-os-args.raw raw 0x80 0x80;" \
-	"spl-os-image.raw raw 0x900 0x2000;" \
-	"spl-os-args fat 0 1;" \
-	"spl-os-image fat 0 1;" \
-	"u-boot.img fat 0 1;" \
-	"uEnv.txt fat 0 1\0"
-
-#define DFU_ALT_INFO_EMMC \
-	"dfu_alt_info_emmc=" \
-	"rawemmc raw 0 3751936;" \
-	"boot part 1 1;" \
-	"rootfs part 1 2;" \
-	"MLO fat 1 1;" \
-	"MLO.raw raw 0x100 0x100;" \
-	"u-boot.img.raw raw 0x300 0x400;" \
-	"spl-os-args.raw raw 0x80 0x80;" \
-	"spl-os-image.raw raw 0x900 0x2000;" \
-	"spl-os-args fat 1 1;" \
-	"spl-os-image fat 1 1;" \
-	"u-boot.img fat 1 1;" \
-	"uEnv.txt fat 1 1\0"
-
-#define DFU_ALT_INFO_RAM \
-	"dfu_alt_info_ram=" \
-	"kernel ram 0x80200000 0x4000000;" \
-	"fdt ram 0x80f80000 0x80000;" \
-	"ramdisk ram 0x81000000 0x4000000\0"
-
-#define DFUARGS \
-	"dfu_bufsiz=0x10000\0" \
-	DFU_ALT_INFO_MMC \
-	DFU_ALT_INFO_EMMC \
-	DFU_ALT_INFO_RAM
-
 /* Fastboot */
 #define CONFIG_USB_FUNCTION_FASTBOOT
 #define CONFIG_CMD_FASTBOOT

@@ -184,28 +143,6 @@
 #define CONFIG_OMAP_USB_PHY
 #define CONFIG_OMAP_USB2PHY2_HOST
 
-/* USB GADGET */
-#define CONFIG_USB_DWC3_PHY_OMAP
-#define CONFIG_USB_DWC3_OMAP
-#define CONFIG_USB_DWC3
-#define CONFIG_USB_DWC3_GADGET
-
-#define CONFIG_USB_GADGET
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
-#define CONFIG_G_DNL_VENDOR_NUM 0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM 0xd022
-#define CONFIG_USB_GADGET_DUALSPEED
-
-/* USB Device Firmware Update support */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_RAM
-#define CONFIG_CMD_DFU
-
-#define CONFIG_DFU_MMC
-#define CONFIG_DFU_RAM
-
 /* SATA */
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_CMD_SCSI

80 lines not on this page · raw message

index c94a807..e28b795 100644
@@ -648,6 +648,14 @@ static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
 	debug("Enable clock domain - %x\n", clkctrl_reg);
 }
 
+static inline void disable_clock_domain(u32 const clkctrl_reg)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Disable clock domain - %x\n", clkctrl_reg);
+}
+
 static inline void wait_for_clk_enable(u32 clkctrl_addr)
 {
 	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;

@@ -677,6 +685,34 @@ static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
 		wait_for_clk_enable(clkctrl_addr);
 }
 
+static inline void wait_for_clk_disable(u32 clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
+	u32 bound = LDELAY;
+
+	while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock disable failed for 0x%x idlest 0x%x\n",
+			       clkctrl_addr, clkctrl);
+			return;
+		}
+	}
+}
+
+static inline void disable_clock_module(u32 const clkctrl_addr,
+					u32 wait_for_disable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Disable clock module - %x\n", clkctrl_addr);
+	if (wait_for_disable)
+		wait_for_clk_disable(clkctrl_addr);
+}
+
 void freq_update_core(void)
 {
 	u32 freq_config1 = 0;

@@ -800,6 +836,23 @@ void do_enable_clocks(u32 const *clk_domains,
 	}
 }
 
+void do_disable_clocks(u32 const *clk_domains,
+			    u32 const *clk_modules_disable,
+			    u8 wait_for_disable)
+{
+	u32 i, max = 100;
+
+
+	/* Clock modules that need to be put in SW_DISABLE */
+	for (i = 0; (i < max) && clk_modules_disable[i]; i++)
+		disable_clock_module(clk_modules_disable[i],
+				     wait_for_disable);
+
+	/* Put the clock domains in SW_SLEEP mode */
+	for (i = 0; (i < max) && clk_domains[i]; i++)
+		disable_clock_domain(clk_domains[i]);
+}
+
 void prcm_init(void)
 {
 	switch (omap_hw_init_context()) {

index 462a9ee..224fbf0 100644
@@ -577,6 +577,10 @@ void do_enable_clocks(u32 const *clk_domains,
 		      u32 const *clk_modules_explicit_en,
 		      u8 wait_for_enable);
 
+void do_disable_clocks(u32 const *clk_domains,
+		       u32 const *clk_modules_disable,
+		       u8 wait_for_disable);
+
 void setup_post_dividers(u32 const base,
 			const struct dpll_params *params);
 u32 omap_ddr_clk(void);

index 11440ac..1085bb3 100644
@@ -581,6 +581,103 @@ void enable_basic_uboot_clocks(void)
 			 1);
 }
 
+#ifdef CONFIG_USB_DWC3
+void enable_usb_clocks(int index)
+{
+	u32 cm_l3init_usb_otg_ss_clkctrl = 0;
+
+	if (index == 0) {
+		cm_l3init_usb_otg_ss_clkctrl =
+			(*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
+		/* Enable 960 MHz clock for dwc3 */
+		setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
+			     OPTFCLKEN_REFCLK960M);
+
+		/* Enable 32 KHz clock for dwc3 */
+		setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
+			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+	} else if (index == 1) {
+		cm_l3init_usb_otg_ss_clkctrl =
+			(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
+		/* Enable 960 MHz clock for dwc3 */
+		setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
+			     OPTFCLKEN_REFCLK960M);
+
+		/* Enable 32 KHz clock for dwc3 */
+		setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
+			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+		/* Enable 60 MHz clock for USB2PHY2 */
+		setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
+			     L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
+	}
+
+	u32 const clk_domains_usb[] = {
+		0
+	};
+
+	u32 const clk_modules_hw_auto_usb[] = {
+		(*prcm)->cm_l3init_ocp2scp1_clkctrl,
+		cm_l3init_usb_otg_ss_clkctrl,
+		0
+	};
+
+	u32 const clk_modules_explicit_en_usb[] = {
+		0
+	};
+
+	do_enable_clocks(clk_domains_usb,
+			 clk_modules_hw_auto_usb,
+			 clk_modules_explicit_en_usb,
+			 1);
+}
+
+void disable_usb_clocks(int index)
+{
+	u32 cm_l3init_usb_otg_ss_clkctrl = 0;
+
+	if (index == 0) {
+		cm_l3init_usb_otg_ss_clkctrl =
+			(*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
+		/* Disable 960 MHz clock for dwc3 */
+		clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
+			     OPTFCLKEN_REFCLK960M);
+
+		/* Disable 32 KHz clock for dwc3 */
+		clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
+			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+	} else if (index == 1) {
+		cm_l3init_usb_otg_ss_clkctrl =
+			(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
+		/* Disable 960 MHz clock for dwc3 */
+		clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
+			     OPTFCLKEN_REFCLK960M);
+
+		/* Disable 32 KHz clock for dwc3 */
+		clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
+			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+		/* Disable 60 MHz clock for USB2PHY2 */
+		clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
+			     L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
+	}
+
+	u32 const clk_domains_usb[] = {
+		0
+	};
+
+	u32 const clk_modules_disable[] = {
+		(*prcm)->cm_l3init_ocp2scp1_clkctrl,
+		cm_l3init_usb_otg_ss_clkctrl,
+		0
+	};
+
+	do_disable_clocks(clk_domains_usb,
+			  clk_modules_disable,
+			  1);
+}
+#endif
+
 const struct ctrl_ioregs ioregs_omap5430 = {
 	.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
 	.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,

index 224fbf0..527e143 100644
@@ -587,6 +587,12 @@ u32 omap_ddr_clk(void);
 u32 get_sys_clk_index(void);
 void enable_basic_clocks(void);
 void enable_basic_uboot_clocks(void);
+
+#ifdef CONFIG_USB_DWC3
+void enable_usb_clocks(int index);
+void disable_usb_clocks(int index);
+#endif
+
 void scale_vcores(struct vcores_data const *);
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);

index ec7d468..f6a4cee 100644
@@ -144,6 +144,34 @@ static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
 		wait_for_clk_enable(clkctrl_addr);
 }
 
+static inline void wait_for_clk_disable(u32 *clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
+	u32 bound = LDELAY;
+
+	while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock disable failed for 0x%p idlest 0x%x\n",
+			       clkctrl_addr, clkctrl);
+			return;
+		}
+	}
+}
+
+static inline void disable_clock_module(u32 *const clkctrl_addr,
+					u32 wait_for_disable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Disable clock module - %p\n", clkctrl_addr);
+	if (wait_for_disable)
+		wait_for_clk_disable(clkctrl_addr);
+}
+
 static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
 {
 	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,

@@ -151,6 +179,14 @@ static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
 	debug("Enable clock domain - %p\n", clkctrl_reg);
 }
 
+static inline void disable_clock_domain(u32 *const clkctrl_reg)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Disable clock domain - %p\n", clkctrl_reg);
+}
+
 void do_enable_clocks(u32 *const *clk_domains,
 		      u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
 {

@@ -170,6 +206,23 @@ void do_enable_clocks(u32 *const *clk_domains,
 	};
 }
 
+void do_disable_clocks(u32 *const *clk_domains,
+			    u32 *const *clk_modules_disable,
+			    u8 wait_for_disable)
+{
+	u32 i, max = 100;
+
+
+	/* Clock modules that need to be put in SW_DISABLE */
+	for (i = 0; (i < max) && clk_modules_disable[i]; i++)
+		disable_clock_module(clk_modules_disable[i],
+				     wait_for_disable);
+
+	/* Put the clock domains in SW_SLEEP mode */
+	for (i = 0; (i < max) && clk_domains[i]; i++)
+		disable_clock_domain(clk_domains[i]);
+}
+
 /*
  * Before scaling up the clocks we need to have the PMIC scale up the
  * voltages first.  This will be dependent on which PMIC is in use

index 4af6b57..a6d2419 100644
@@ -112,5 +112,6 @@ void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
 void prcm_init(void);
 void enable_basic_clocks(void);
 void do_enable_clocks(u32 *const *, u32 *const *, u8);
+void do_disable_clocks(u32 *const *, u32 *const *, u8);
 
 #endif

index b1c0025..cd8931e 100644
@@ -134,3 +134,73 @@ void enable_basic_clocks(void)
 	/* For OPP100 the mac clock should be /5. */
 	writel(0x4, &cmdpll->clkselmacclk);
 }
+
+#ifdef CONFIG_USB_DWC3
+void enable_usb_clocks(int index)
+{
+	u32 *usbclkctrl = 0;
+	u32 *usbphyocp2scpclkctrl = 0;
+
+	if (index == 0) {
+		usbclkctrl = &cmper->usb0clkctrl;
+		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
+		setbits_le32(&cmper->usb0clkctrl,
+			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+		setbits_le32(&cmwkup->usbphy0clkctrl,
+			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
+	} else if (index == 1) {
+		usbclkctrl = &cmper->usb1clkctrl;
+		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
+		setbits_le32(&cmper->usb1clkctrl,
+			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+		setbits_le32(&cmwkup->usbphy1clkctrl,
+			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
+	}
+
+	u32 *const clk_domains_usb[] = {
+		0
+	};
+
+	u32 *const clk_modules_explicit_en_usb[] = {
+		usbclkctrl,
+		usbphyocp2scpclkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains_usb, clk_modules_explicit_en_usb, 1);
+}
+
+void disable_usb_clocks(int index)
+{
+	u32 *usbclkctrl = 0;
+	u32 *usbphyocp2scpclkctrl = 0;
+
+	if (index == 0) {
+		usbclkctrl = &cmper->usb0clkctrl;
+		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
+		clrbits_le32(&cmper->usb0clkctrl,
+			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+		clrbits_le32(&cmwkup->usbphy0clkctrl,
+			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
+	} else if (index == 1) {
+		usbclkctrl = &cmper->usb1clkctrl;
+		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
+		clrbits_le32(&cmper->usb1clkctrl,
+			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+		clrbits_le32(&cmwkup->usbphy1clkctrl,
+			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
+	}
+
+	u32 *const clk_domains_usb[] = {
+		0
+	};
+
+	u32 *const clk_modules_disable_usb[] = {
+		usbclkctrl,
+		usbphyocp2scpclkctrl,
+		0
+	};
+
+	do_disable_clocks(clk_domains_usb, clk_modules_disable_usb, 1);
+}
+#endif

index 91b614a..275cf7b 100644
@@ -42,3 +42,8 @@ void am33xx_spl_board_init(void);
 int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
 int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
 #endif
+
+#ifdef CONFIG_USB_DWC3
+void enable_usb_clocks(int index);
+void disable_usb_clocks(int index);
+#endif

index d7b9e5a..54f250a 100644
@@ -715,6 +715,7 @@ static struct ti_usb_phy_device usb_phy2_device = {
 
 int board_usb_init(int index, enum usb_init_type init)
 {
+	enable_usb_clocks(index);
 	switch (index) {
 	case 0:
 		if (init == USB_INIT_DEVICE) {

@@ -761,6 +762,7 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 	default:
 		printf("Invalid Controller Index\n");
 	}
+	disable_usb_clocks(index);
 
 	return 0;
 }

index b0c5ccd..c9a48bc 100644
@@ -356,10 +356,12 @@ static struct ti_usb_phy_device usb_phy2_device = {
 
 int board_usb_init(int index, enum usb_init_type init)
 {
+	enable_usb_clocks(index);
 	switch (index) {
 	case 0:
 		if (init == USB_INIT_DEVICE) {
 			printf("port %d can't be used as device\n", index);
+			disable_usb_clocks(index);
 			return -EINVAL;
 		} else {
 			usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;

@@ -379,6 +381,7 @@ int board_usb_init(int index, enum usb_init_type init)
 			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 		} else {
 			printf("port %d can't be used as host\n", index);
+			disable_usb_clocks(index);
 			return -EINVAL;
 		}
 

@@ -405,6 +408,7 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 	default:
 		printf("Invalid Controller Index\n");
 	}
+	disable_usb_clocks(index);
 	return 0;
 }
 

index 94a1a8c..30ef34b 100644
@@ -146,6 +146,7 @@ static struct ti_usb_phy_device usb_phy2_device = {
 
 int board_usb_init(int index, enum usb_init_type init)
 {
+	enable_usb_clocks(index);
 	switch (index) {
 	case 0:
 		if (init == USB_INIT_DEVICE) {

@@ -192,6 +193,7 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 	default:
 		printf("Invalid Controller Index\n");
 	}
+	disable_usb_clocks(index);
 	return 0;
 }
 

index d0d0e0e..659877c 100644
@@ -95,6 +95,7 @@ int board_usb_init(int index, enum usb_init_type init)
 		usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 	}
 
+	enable_usb_clocks(index);
 	ti_usb_phy_uboot_init(&usb_phy_device);
 	dwc3_omap_uboot_init(&usb_otg_ss_glue);
 	dwc3_uboot_init(&usb_otg_ss);

@@ -112,6 +113,7 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 	ti_usb_phy_uboot_exit(index);
 	dwc3_uboot_exit(index);
 	dwc3_omap_uboot_exit(index);
+	disable_usb_clocks(index);
 
 	return 0;
 }

index cd8931e..30b4867 100644
@@ -111,21 +111,9 @@ void enable_basic_clocks(void)
 		&cmper->emifclkctrl,
 		&cmper->otfaemifclkctrl,
 		&cmper->qspiclkctrl,
-		&cmper->usb0clkctrl,
-		&cmper->usbphyocp2scp0clkctrl,
-		&cmper->usb1clkctrl,
-		&cmper->usbphyocp2scp1clkctrl,
 		0
 	};
 
-	setbits_le32(&cmper->usb0clkctrl,
-		     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
-	setbits_le32(&cmwkup->usbphy0clkctrl,
-		     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
-	setbits_le32(&cmper->usb1clkctrl,
-		     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
-	setbits_le32(&cmwkup->usbphy1clkctrl,
-		     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
 	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 
 	/* Select the Master osc clk as Timer2 clock source */

index 1085bb3..19f2c43 100644
@@ -460,13 +460,6 @@ void enable_basic_clocks(void)
 		(*prcm)->cm_l4per_gpio6_clkctrl,
 		(*prcm)->cm_l4per_gpio7_clkctrl,
 		(*prcm)->cm_l4per_gpio8_clkctrl,
-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
-		(*prcm)->cm_l3init_ocp2scp1_clkctrl,
-		(*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
-		(*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
-#endif
-#endif
 		0
 	};
 

@@ -498,29 +491,6 @@ void enable_basic_clocks(void)
 	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 			HSMMC_CLKCTRL_CLKSEL_MASK);
 
-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
-	/* Enable 960 MHz clock for dwc3 */
-	setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
-		     OPTFCLKEN_REFCLK960M);
-
-	/* Enable 32 KHz clock for dwc3 */
-	setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
-		     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
-	/* Enable 960 MHz clock for dwc3 */
-	setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
-		     OPTFCLKEN_REFCLK960M);
-
-	/* Enable 32 KHz clock for dwc3 */
-	setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
-		     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
-	/* Enable 60 MHz clock for USB2PHY2 */
-	setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
-		     L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
-#endif
-#endif
-
 	/* Set the correct clock dividers for mmc */
 	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 			HSMMC_CLKCTRL_CLKSEL_DIV_MASK);

index 54f250a..770726c 100644
@@ -685,7 +685,6 @@ static struct dwc3_device usb_otg_ss1 = {
 static struct dwc3_omap_device usb_otg_ss1_glue = {
 	.base = (void *)USB_OTG_SS1_GLUE_BASE,
 	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
-	.vbus_id_status = OMAP_DWC3_VBUS_VALID,
 	.index = 0,
 };
 

@@ -704,7 +703,6 @@ static struct dwc3_device usb_otg_ss2 = {
 static struct dwc3_omap_device usb_otg_ss2_glue = {
 	.base = (void *)USB_OTG_SS2_GLUE_BASE,
 	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
-	.vbus_id_status = OMAP_DWC3_VBUS_VALID,
 	.index = 1,
 };
 

index 30ef34b..04fc8ed 100644
@@ -114,7 +114,6 @@ static struct dwc3_device usb_otg_ss1 = {
 static struct dwc3_omap_device usb_otg_ss1_glue = {
 	.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
-	.vbus_id_status = OMAP_DWC3_VBUS_VALID,
 	.index = 0,
 };
 

@@ -135,7 +134,6 @@ static struct dwc3_device usb_otg_ss2 = {
 static struct dwc3_omap_device usb_otg_ss2_glue = {
 	.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
-	.vbus_id_status = OMAP_DWC3_VBUS_VALID,
 	.index = 1,
 };
 

index 3a55208..104e7a7 100644
@@ -96,4 +96,5 @@ void xhci_hcd_stop(int index)
 	struct omap_xhci *ctx = &omap;
 
 	omap_xhci_core_exit(ctx);
+	board_usb_cleanup(index, USB_INIT_HOST);
 }

index d148169..15fa3e3 100644
@@ -292,6 +292,8 @@
 				"bootz ${loadaddr} - ${fdtaddr}; " \
 			"fi;" \
 		"fi\0" \
+		"fi;" \
+		"usb stop ${usbdev};\0" \
 	"findfdt="\
 		"if test $board_name = AM43EPOS; then " \
 			"setenv fdtfile am43x-epos-evm.dtb; fi; " \

index 770726c..8125c9f 100644
@@ -777,8 +777,8 @@ int usb_gadget_handle_interrupts(int index)
 }
 #endif
 
-#ifdef CONFIG_DRIVER_TI_CPSW
-
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 static void cpsw_control(int enabled)
 {
 	/* Additional controls can be added here */

@@ -816,7 +816,24 @@ static struct cpsw_platform_data cpsw_data = {
 	.host_port_num		= 0,
 	.version		= CPSW_CTRL_VERSION_2,
 };
+#endif
 
+/*
+ * This function will:
+ * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
+ * in the environment
+ * Perform fixups to the PHY present on certain boards.  We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \
+	defined(CONFIG_SPL_USBETH_SUPPORT)) && \
+	defined(CONFIG_SPL_BUILD)) || \
+	((defined(CONFIG_DRIVER_TI_CPSW) || \
+	  defined(CONFIG_USB_ETHER)) && !defined(CONFIG_SPL_BUILD))
 int board_eth_init(bd_t *bis)
 {
 	int rv;

@@ -833,12 +850,15 @@ int board_eth_init(bd_t *bis)
 	mac_addr[4] = mac_lo & 0xFF;
 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 	if (!getenv("ethaddr")) {
 		puts("<ethaddr> not set. Validating first E-fuse MAC\n");
 		if (is_valid_ethaddr(mac_addr))
 			eth_setenv_enetaddr("ethaddr", mac_addr);
 	}
 
+#ifndef CONFIG_SPL_BUILD
 	mac_lo = readl(&cdev->macid1l);
 	mac_hi = readl(&cdev->macid1h);
 	mac_addr[0] = mac_hi & 0xFF;

@@ -852,6 +872,7 @@ int board_eth_init(bd_t *bis)
 		if (is_valid_ethaddr(mac_addr))
 			eth_setenv_enetaddr("eth1addr", mac_addr);
 	}
+#endif
 
 	if (board_is_eposevm()) {
 		writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);

@@ -873,8 +894,20 @@ int board_eth_init(bd_t *bis)
 	}
 
 	rv = cpsw_register(&cpsw_data);
-	if (rv < 0)
+	if (rv < 0) {
 		printf("Error %d registering CPSW switch\n", rv);
+		return rv;
+	}
+#endif
+#if defined(CONFIG_USB_ETHER) && \
+	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
+	if (is_valid_ethaddr(mac_addr))
+		eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
+
+	rv = usb_eth_initialize(bis);
+	if (rv < 0)
+		printf("Error %d registering USB_ETHER\n", rv);
+#endif
 
 	return rv;
 }

index e9811c3..9c2232e 100644
@@ -231,5 +231,7 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
 		return 0x21;
 	else if (gadget_is_fotg210(gadget))
 		return 0x22;
+	else if (gadget_is_dwc3(gadget))
+		return 0x23;
 	return -ENOENT;
 }

index 15fa3e3..f0040e8 100644
@@ -122,12 +122,17 @@
 /* USB GADGET */
 #if !defined(CONFIG_SPL_BUILD) || \
 	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT))
+#undef CONFIG_ENV_IS_IN_FAT
+#define CONFIG_ENV_IS_NOWHERE
 #define CONFIG_USB_DWC3_PHY_OMAP
 #define CONFIG_USB_DWC3_OMAP
 #define CONFIG_USB_DWC3
 #define CONFIG_USB_DWC3_GADGET
 
 #define CONFIG_USB_GADGET
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_GADGET_VBUS_DRAW 2
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"

@@ -136,6 +141,10 @@
 #define CONFIG_USB_GADGET_DUALSPEED
 #endif
 
+#if defined(CONFIG_SPL_USBETH_SUPPORT) || defined(CONFIG_SPL_ETH_SUPPORT)
+#define CONFIG_SPL_NET_SUPPORT
+#endif
+
 #ifndef CONFIG_SPL_BUILD
 /* USB Device Firmware Update support */
 #define CONFIG_USB_FUNCTION_DFU

index 850ba02..53f4672 100644
@@ -2505,6 +2505,7 @@ static struct usb_gadget_driver eth_driver = {
 	.unbind		= eth_unbind,
 
 	.setup		= eth_setup,
+	.reset		= eth_disconnect,
 	.disconnect	= eth_disconnect,
 
 	.suspend	= eth_suspend,

index 4ed8597..f8fdace 100644
@@ -56,8 +56,8 @@
 #define BOOT_DEVICE_MMC1	0x07
 #define BOOT_DEVICE_MMC2	0x08
 #define BOOT_DEVICE_SPI		0x0A
+#define BOOT_DEVICE_USB		0x0D
 #define BOOT_DEVICE_UART	0x41
-#define BOOT_DEVICE_USB		0x45
 #define BOOT_DEVICE_CPGMAC	0x47
 
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1

index f8fdace..edf589e 100644
@@ -58,6 +58,7 @@
 #define BOOT_DEVICE_SPI		0x0A
 #define BOOT_DEVICE_USB		0x0D
 #define BOOT_DEVICE_UART	0x41
+#define BOOT_DEVICE_USBETH	0x45
 #define BOOT_DEVICE_CPGMAC	0x47
 
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1