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thermal: rockhip: fix setting thermal shutdown polarity

PATCH In review Dmitry Torokhov 2 participants 3 messages Aug 7, 2015 – Aug 10, 2015

Subsystems (2)
Arm Rockchip Thermal
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Dmitry Torokhov

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#0 lore raw

PATCH 1/1 thermal: rockhip: fix setting thermal shutdown polarity

When requested thermal shutdown signal polarity is low we need to make sure that the bit representing high level of signal is reset, and not set all other bits in that register.

Also rename TSADCV2_INT_PD_CLEAR to TSADCV2_INT_PD_CLEAR_MASK to better reflect its nature.

Signed-off-by Dmitry Torokhov <[email protected]>
---
 drivers/thermal/rockchip_thermal.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)
drivers/thermal/rockchip_thermal.c +4 -6
index 93ee307..4d5b7d4 100644
@@ -106,16 +106,14 @@ struct rockchip_thermal_data {
 #define TSADCV2_AUTO_PERIOD_HT			0x6c
 
 #define TSADCV2_AUTO_EN				BIT(0)
-#define TSADCV2_AUTO_DISABLE			~BIT(0)
 #define TSADCV2_AUTO_SRC_EN(chn)		BIT(4 + (chn))
 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH	BIT(8)
-#define TSADCV2_AUTO_TSHUT_POLARITY_LOW		~BIT(8)
 
 #define TSADCV2_INT_SRC_EN(chn)			BIT(chn)
 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn)		BIT(4 + (chn))
 #define TSADCV2_SHUT_2CRU_SRC_EN(chn)		BIT(8 + (chn))
 
-#define TSADCV2_INT_PD_CLEAR			~BIT(8)
+#define TSADCV2_INT_PD_CLEAR_MASK		~BIT(8)
 
 #define TSADCV2_DATA_MASK			0xfff
 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT	4

@@ -244,10 +242,10 @@ static void rk_tsadcv2_initialize(void __iomem *regs,
 				  enum tshut_polarity tshut_polarity)
 {
 	if (tshut_polarity == TSHUT_HIGH_ACTIVE)
-		writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_HIGH),
+		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
 			       regs + TSADCV2_AUTO_CON);
 	else
-		writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_LOW),
+		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
 			       regs + TSADCV2_AUTO_CON);
 
 	writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);

@@ -264,7 +262,7 @@ static void rk_tsadcv2_irq_ack(void __iomem *regs)
 	u32 val;
 
 	val = readl_relaxed(regs + TSADCV2_INT_PD);
-	writel_relaxed(val & TSADCV2_INT_PD_CLEAR, regs + TSADCV2_INT_PD);
+	writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
 }
 
 static void rk_tsadcv2_control(void __iomem *regs, bool enable)
Signature · 5 lines
2.5.0.rc2.392.g76e840b


-- 
Dmitry
Acked-by on v1 1/1
#1 lore raw

Dear Dmitry,

Thanks to work for it.

? 2015?08?08? 05:00, Dmitry Torokhov ??:

Quoted 8 lines

When requested thermal shutdown signal polarity is low we need to make sure that the bit representing high level of signal is reset, and not set all other bits in that register.

Also rename TSADCV2_INT_PD_CLEAR to TSADCV2_INT_PD_CLEAR_MASK to better reflect its nature.

Signed-off-by Dmitry Torokhov <[email protected]>
Acked-by Caesar Wang <[email protected]>

--
Thanks,
Caesar

Quoted 48 lines
---
  drivers/thermal/rockchip_thermal.c | 10 ++++------
  1 file changed, 4 insertions(+), 6 deletions(-)
drivers/thermal/rockchip_thermal.c +4 -6
index 93ee307..4d5b7d4 100644
@@ -106,16 +106,14 @@ struct rockchip_thermal_data {
  #define TSADCV2_AUTO_PERIOD_HT			0x6c
 
  #define TSADCV2_AUTO_EN				BIT(0)
-#define TSADCV2_AUTO_DISABLE			~BIT(0)
  #define TSADCV2_AUTO_SRC_EN(chn)		BIT(4 + (chn))
  #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH	BIT(8)
-#define TSADCV2_AUTO_TSHUT_POLARITY_LOW		~BIT(8)
 
  #define TSADCV2_INT_SRC_EN(chn)			BIT(chn)
  #define TSADCV2_SHUT_2GPIO_SRC_EN(chn)		BIT(4 + (chn))
  #define TSADCV2_SHUT_2CRU_SRC_EN(chn)		BIT(8 + (chn))
 
-#define TSADCV2_INT_PD_CLEAR			~BIT(8)
+#define TSADCV2_INT_PD_CLEAR_MASK		~BIT(8)
 
  #define TSADCV2_DATA_MASK			0xfff
  #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT	4

@@ -244,10 +242,10 @@ static void rk_tsadcv2_initialize(void __iomem *regs,
  				  enum tshut_polarity tshut_polarity)
  {
  	if (tshut_polarity == TSHUT_HIGH_ACTIVE)
-		writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_HIGH),
+		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
  			       regs + TSADCV2_AUTO_CON);
  	else
-		writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_LOW),
+		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
  			       regs + TSADCV2_AUTO_CON);
 
  	writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);

@@ -264,7 +262,7 @@ static void rk_tsadcv2_irq_ack(void __iomem *regs)
  	u32 val;
 
  	val = readl_relaxed(regs + TSADCV2_INT_PD);
-	writel_relaxed(val & TSADCV2_INT_PD_CLEAR, regs + TSADCV2_INT_PD);
+	writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
  }
 
  static void rk_tsadcv2_control(void __iomem *regs, bool enable)
#2 lore raw

Sorry, forgot it!
\s 'rockhip' to 'rockchip' :-)

? 2015?08?10? 14:34, Caesar Wang ??:

Quoted 66 lines

Dear Dmitry,

Thanks to work for it.

? 2015?08?08? 05:00, Dmitry Torokhov ??:

Quoted 8 lines

When requested thermal shutdown signal polarity is low we need to make sure that the bit representing high level of signal is reset, and not set all other bits in that register.

Also rename TSADCV2_INT_PD_CLEAR to TSADCV2_INT_PD_CLEAR_MASK to better reflect its nature.

Signed-off-by Dmitry Torokhov <[email protected]>
Acked-by Caesar Wang <[email protected]>
Signature · 2 lines
Thanks,
Caesar
Quoted 45 lines
---
  drivers/thermal/rockchip_thermal.c | 10 ++++------
  1 file changed, 4 insertions(+), 6 deletions(-)
drivers/thermal/rockchip_thermal.c +3 -4
index 93ee307..4d5b7d4 100644
@@ -106,16 +106,14 @@ struct rockchip_thermal_data {
  #define TSADCV2_AUTO_PERIOD_HT            0x6c
    #define TSADCV2_AUTO_EN                BIT(0)
-#define TSADCV2_AUTO_DISABLE            ~BIT(0)
  #define TSADCV2_AUTO_SRC_EN(chn)        BIT(4 + (chn))
  #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH    BIT(8)
-#define TSADCV2_AUTO_TSHUT_POLARITY_LOW        ~BIT(8)
    #define TSADCV2_INT_SRC_EN(chn)            BIT(chn)
  #define TSADCV2_SHUT_2GPIO_SRC_EN(chn)        BIT(4 + (chn))
  #define TSADCV2_SHUT_2CRU_SRC_EN(chn)        BIT(8 + (chn))
  -#define TSADCV2_INT_PD_CLEAR            ~BIT(8)
+#define TSADCV2_INT_PD_CLEAR_MASK        ~BIT(8)
    #define TSADCV2_DATA_MASK            0xfff
  #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT    4

@@ -244,10 +242,10 @@ static void rk_tsadcv2_initialize(void __iomem 
 *regs,
                    enum tshut_polarity tshut_polarity)
  {
      if (tshut_polarity == TSHUT_HIGH_ACTIVE)
-        writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_HIGH),
+        writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
                     regs + TSADCV2_AUTO_CON);
      else
-        writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_LOW),
+        writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
                     regs + TSADCV2_AUTO_CON);
        writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs +

TSADCV2_AUTO_PERIOD);

drivers/thermal/rockchip_thermal.c +1 -1
@@ -264,7 +262,7 @@ static void rk_tsadcv2_irq_ack(void __iomem *regs)
      u32 val;
        val = readl_relaxed(regs + TSADCV2_INT_PD);
-    writel_relaxed(val & TSADCV2_INT_PD_CLEAR, regs + TSADCV2_INT_PD);
+    writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + 
 TSADCV2_INT_PD);
  }
    static void rk_tsadcv2_control(void __iomem *regs, bool enable)