Enable edma support for ti-qspi

---
 common/cmd_sf.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

common/cmd_sf.c +3 -3

index 3746e0d9644f..ac7f5dfb8181 100644
@@ -223,7 +223,7 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,
 
 	if (end - buf >= 200)
 		scale = (end - buf) / 100;
-	cmp_buf = malloc(flash->sector_size);
+	cmp_buf = memalign(ARCH_DMA_MINALIGN, flash->sector_size);
 	if (cmp_buf) {
 		ulong last_update = get_timer(0);

@@ -484,12 +484,12 @@ static int do_spi_flash_test(int argc, char * const argv[])
 	if (*argv[2] == 0 || *endp != 0)
 		return -1;
 
-	vbuf = malloc(len);
+	vbuf = memalign(ARCH_DMA_MINALIGN, len);
 	if (!vbuf) {
 		printf("Cannot allocate memory (%lu bytes)\n", len);
 		return 1;
 	}
-	buf = malloc(len);
+	buf = memalign(ARCH_DMA_MINALIGN, len);
 	if (!buf) {
 		free(vbuf);
 		printf("Cannot allocate memory (%lu bytes)\n", len);

Signature · 1 line

2.5.0

Jagan Teki

2015-08-17 17:19 UTC #2 lore raw

PATCH RESEND v2 1/10 sf: allocate cache aligned buffers to copy from flash

Quoted 10 lines · Vignesh R

From: Ravi Babu <[email protected]>
Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.
Signed-off-by Ravi Babu <[email protected]>
Signed-off-by Vignesh R <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---

Quoted 32 lines

 common/cmd_sf.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

common/cmd_sf.c +3 -4

index 3746e0d9644f..ac7f5dfb8181 100644
@@ -223,7 +223,7 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,
 
        if (end - buf >= 200)
                scale = (end - buf) / 100;
-       cmp_buf = malloc(flash->sector_size);
+       cmp_buf = memalign(ARCH_DMA_MINALIGN, flash->sector_size);
        if (cmp_buf) {
                ulong last_update = get_timer(0);

@@ -484,12 +484,12 @@ static int do_spi_flash_test(int argc, char * const argv[])
        if (*argv[2] == 0 || *endp != 0)
                return -1;
 
-       vbuf = malloc(len);
+       vbuf = memalign(ARCH_DMA_MINALIGN, len);
        if (!vbuf) {
                printf("Cannot allocate memory (%lu bytes)\n", len);
                return 1;
        }
-       buf = malloc(len);
+       buf = memalign(ARCH_DMA_MINALIGN, len);
        if (!buf) {
                free(vbuf);
                printf("Cannot allocate memory (%lu bytes)\n", len);
--

Quoted 2 lines

2.5.0

thanks!

Signature · 1 line

Jagan | openedev.

Vignesh R

author maintainer

2015-08-17 07:59 UTC #3 lore raw

PATCH RESEND v2 2/10 env: use cache line aligned memory for flash read

From: Ravi Babu <[email protected]>

Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.

Signed-off-by Ravi Babu <[email protected]>

Signed-off-by Vignesh R <[email protected]>

---
 common/env_sf.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

common/env_sf.c +6 -5

index e928f5752cc7..940983124fbb 100644
@@ -79,7 +79,7 @@ int saveenv(void)
 	if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) {
 		saved_size = CONFIG_ENV_SECT_SIZE - CONFIG_ENV_SIZE;
 		saved_offset = env_new_offset + CONFIG_ENV_SIZE;
-		saved_buffer = malloc(saved_size);
+		saved_buffer = memalign(ARCH_DMA_MINALIGN, saved_size);
 		if (!saved_buffer) {
 			ret = 1;
 			goto done;

@@ -142,9 +142,10 @@ void env_relocate_spec(void)
 	env_t *tmp_env2 = NULL;
 	env_t *ep = NULL;
 
-	tmp_env1 = (env_t *)malloc(CONFIG_ENV_SIZE);
-	tmp_env2 = (env_t *)malloc(CONFIG_ENV_SIZE);
-
+	tmp_env1 = (env_t *)memalign(ARCH_DMA_MINALIGN,
+			CONFIG_ENV_SIZE);
+	tmp_env2 = (env_t *)memalign(ARCH_DMA_MINALIGN,
+			CONFIG_ENV_SIZE);
 	if (!tmp_env1 || !tmp_env2) {
 		set_default_env("!malloc() failed");
 		goto out;

@@ -295,7 +296,7 @@ void env_relocate_spec(void)
 	int ret;
 	char *buf = NULL;
 
-	buf = (char *)malloc(CONFIG_ENV_SIZE);
+	buf = (char *)memalign(ARCH_DMA_MINALIGN, CONFIG_ENV_SIZE);
 	env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
 			CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
 	if (!env_flash) {

Signature · 1 line

2.5.0

Vignesh R

author maintainer

2015-08-17 07:59 UTC #4 lore raw

PATCH RESEND v2 3/10 ARM: AM43xx: Add support for disabling clocks in uboot

From: Kishon Vijay Abraham I <[email protected]>

Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks().

Signed-off-by Kishon Vijay Abraham I <[email protected]>

Signed-off-by Vignesh R <[email protected]>

---
 arch/arm/cpu/armv7/am33xx/clock.c        | 52 ++++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-am33xx/clock.h |  1 +
 2 files changed, 53 insertions(+)

arch/arm/cpu/armv7/am33xx/clock.c +52 -0

index ec7d46838b74..595c951ed245 100644
@@ -144,6 +144,33 @@ static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
 		wait_for_clk_enable(clkctrl_addr);
 }
 
+static inline void wait_for_clk_disable(u32 *clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
+	u32 bound = LDELAY;
+
+	while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			  MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock disable failed for 0x%p idlest 0x%x\n",
+			       clkctrl_addr, clkctrl);
+			 return;
+		}
+	}
+}
+static inline void disable_clock_module(u32 *const clkctrl_addr,
+					u32 wait_for_disable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Disable clock module - %p\n", clkctrl_addr);
+	if (wait_for_disable)
+		wait_for_clk_disable(clkctrl_addr);
+}
+
 static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
 {
 	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,

@@ -151,6 +178,14 @@ static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
 	debug("Enable clock domain - %p\n", clkctrl_reg);
 }
 
+static inline void disable_clock_domain(u32 *const clkctrl_reg)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Disable clock domain - %p\n", clkctrl_reg);
+}
+
 void do_enable_clocks(u32 *const *clk_domains,
 		      u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
 {

@@ -170,6 +205,23 @@ void do_enable_clocks(u32 *const *clk_domains,
 	};
 }
 
+void do_disable_clocks(u32 *const *clk_domains,
+			u32 *const *clk_modules_disable,
+			u8 wait_for_disable)
+{
+	u32 i, max = 100;
+
+
+	/* Clock modules that need to be put in SW_DISABLE */
+	for (i = 0; (i < max) && clk_modules_disable[i]; i++)
+		disable_clock_module(clk_modules_disable[i],
+				     wait_for_disable);
+
+	/* Put the clock domains in SW_SLEEP mode */
+	for (i = 0; (i < max) && clk_domains[i]; i++)
+		disable_clock_domain(clk_domains[i]);
+}
+
 /*
  * Before scaling up the clocks we need to have the PMIC scale up the
  * voltages first.  This will be dependent on which PMIC is in use

arch/arm/include/asm/arch-am33xx/clock.h +1 -0

index 4af6b57e42f5..a6d2419fb843 100644
@@ -112,5 +112,6 @@ void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
 void prcm_init(void);
 void enable_basic_clocks(void);
 void do_enable_clocks(u32 *const *, u32 *const *, u8);
+void do_disable_clocks(u32 *const *, u32 *const *, u8);
 
 #endif

Signature · 1 line

2.5.0

Vignesh R

author maintainer

2015-08-17 07:59 UTC #5 lore raw

PATCH RESEND v2 4/10 ARM: OMAP5: Add support for disabling clocks in uboot

From: Kishon Vijay Abraham I <[email protected]>

Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks().

Signed-off-by Kishon Vijay Abraham I <[email protected]>

Signed-off-by Vignesh R <[email protected]>

---
 arch/arm/cpu/armv7/omap-common/clocks-common.c | 53 ++++++++++++++++++++++++++
 arch/arm/include/asm/omap_common.h             |  4 ++
 2 files changed, 57 insertions(+)

arch/arm/cpu/armv7/omap-common/clocks-common.c +53 -0

index c94a80781931..e28b79568d1d 100644
@@ -648,6 +648,14 @@ static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
 	debug("Enable clock domain - %x\n", clkctrl_reg);
 }
 
+static inline void disable_clock_domain(u32 const clkctrl_reg)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Disable clock domain - %x\n", clkctrl_reg);
+}
+
 static inline void wait_for_clk_enable(u32 clkctrl_addr)
 {
 	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;

@@ -677,6 +685,34 @@ static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
 		wait_for_clk_enable(clkctrl_addr);
 }
 
+static inline void wait_for_clk_disable(u32 clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
+	u32 bound = LDELAY;
+
+	while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock disable failed for 0x%x idlest 0x%x\n",
+			       clkctrl_addr, clkctrl);
+			return;
+		}
+	}
+}
+
+static inline void disable_clock_module(u32 const clkctrl_addr,
+					u32 wait_for_disable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Disable clock module - %x\n", clkctrl_addr);
+	if (wait_for_disable)
+		wait_for_clk_disable(clkctrl_addr);
+}
+
 void freq_update_core(void)
 {
 	u32 freq_config1 = 0;

@@ -800,6 +836,23 @@ void do_enable_clocks(u32 const *clk_domains,
 	}
 }
 
+void do_disable_clocks(u32 const *clk_domains,
+			    u32 const *clk_modules_disable,
+			    u8 wait_for_disable)
+{
+	u32 i, max = 100;
+
+
+	/* Clock modules that need to be put in SW_DISABLE */
+	for (i = 0; (i < max) && clk_modules_disable[i]; i++)
+		disable_clock_module(clk_modules_disable[i],
+				     wait_for_disable);
+
+	/* Put the clock domains in SW_SLEEP mode */
+	for (i = 0; (i < max) && clk_domains[i]; i++)
+		disable_clock_domain(clk_domains[i]);
+}
+
 void prcm_init(void)
 {
 	switch (omap_hw_init_context()) {

arch/arm/include/asm/omap_common.h +4 -0

index 056affc3fabd..87cdaad1d60f 100644
@@ -575,6 +575,10 @@ void do_enable_clocks(u32 const *clk_domains,
 		      u32 const *clk_modules_explicit_en,
 		      u8 wait_for_enable);
 
+void do_disable_clocks(u32 const *clk_domains,
+		       u32 const *clk_modules_disable,
+		       u8 wait_for_disable);
+
 void setup_post_dividers(u32 const base,
 			const struct dpll_params *params);
 u32 omap_ddr_clk(void);

Signature · 1 line

2.5.0

Vignesh R

author maintainer

2015-08-17 07:59 UTC #6 lore raw

PATCH RESEND v2 5/10 ARM: OMAP5: Add functions to enable and disable EDMA3 clocks

Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks.

Signed-off-by Vignesh R <[email protected]>

---
* dropped #ifdefs in header file.

 arch/arm/cpu/armv7/omap5/hw_data.c   | 41 ++++++++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap5/prcm-regs.c |  4 ++++
 arch/arm/include/asm/omap_common.h   |  7 ++++++
 3 files changed, 52 insertions(+)

arch/arm/cpu/armv7/omap5/hw_data.c +41 -0

index 3a723cace71a..33f92b7e225d 100644
@@ -565,6 +565,47 @@ void enable_basic_uboot_clocks(void)
 			 1);
 }
 
+#ifdef CONFIG_TI_EDMA3
+void enable_edma3_clocks(void)
+{
+	u32 const clk_domains_edma3[] = {
+		0
+	};
+
+	u32 const clk_modules_hw_auto_edma3[] = {
+		(*prcm)->cm_l3main1_tptc1_clkctrl,
+		(*prcm)->cm_l3main1_tptc2_clkctrl,
+		0
+	};
+
+	u32 const clk_modules_explicit_en_edma3[] = {
+		0
+	};
+
+	do_enable_clocks(clk_domains_edma3,
+			 clk_modules_hw_auto_edma3,
+			 clk_modules_explicit_en_edma3,
+			 1);
+}
+
+void disable_edma3_clocks(void)
+{
+	u32 const clk_domains_edma3[] = {
+		0
+	};
+
+	u32 const clk_modules_disable_edma3[] = {
+		(*prcm)->cm_l3main1_tptc1_clkctrl,
+		(*prcm)->cm_l3main1_tptc2_clkctrl,
+		0
+	};
+
+	do_disable_clocks(clk_domains_edma3,
+			  clk_modules_disable_edma3,
+			  1);
+}
+#endif
+
 const struct ctrl_ioregs ioregs_omap5430 = {
 	.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
 	.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,

arch/arm/cpu/armv7/omap5/prcm-regs.c +4 -0

index cd51fe7678be..d01ce88306ee 100644
@@ -989,4 +989,8 @@ struct prcm_regs const dra7xx_prcm = {
 
 	.prm_abbldo_mpu_setup			= 0x4AE07DDC,
 	.prm_abbldo_mpu_ctrl			= 0x4AE07DE0,
+
+	/*l3main1 edma*/
+	.cm_l3main1_tptc1_clkctrl               = 0x4a008778,
+	.cm_l3main1_tptc2_clkctrl               = 0x4a008780,
 };

arch/arm/include/asm/omap_common.h +7 -0

index 87cdaad1d60f..b67d4b673d99 100644
@@ -349,6 +349,10 @@ struct prcm_regs {
 	/* IPU */
 	u32 cm_ipu_clkstctrl;
 	u32 cm_ipu_i2c5_clkctrl;
+
+	/*l3main1 edma*/
+	u32 cm_l3main1_tptc1_clkctrl;
+	u32 cm_l3main1_tptc2_clkctrl;
 };
 
 struct omap_sys_ctrl_regs {

@@ -598,6 +602,9 @@ void recalibrate_iodelay(void);
 
 void omap_smc1(u32 service, u32 val);
 
+void enable_edma3_clocks(void);
+void disable_edma3_clocks(void);
+
 /* ABB */
 #define OMAP_ABB_NOMINAL_OPP		0
 #define OMAP_ABB_FAST_OPP		1

Signature · 1 line

2.5.0

Vignesh R

author maintainer

2015-08-17 07:59 UTC #7 lore raw

PATCH RESEND v2 6/10 ARM: AM43XX: Add functions to enable and disable EDMA3 clocks

Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks.

Signed-off-by Vignesh R <[email protected]>

---
 arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 36 ++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

arch/arm/cpu/armv7/am33xx/clock_am43xx.c +36 -0

index b6396942bbff..35c431eb292d 100644
@@ -135,3 +135,39 @@ void enable_basic_clocks(void)
 	/* For OPP100 the mac clock should be /5. */
 	writel(0x4, &cmdpll->clkselmacclk);
 }
+
+#ifdef CONFIG_TI_EDMA3
+void enable_edma3_clocks(void)
+{
+	u32 *const clk_domains_edma3[] = {
+		0
+	};
+
+	u32 *const clk_modules_explicit_en_edma3[] = {
+		&cmper->tpccclkctrl,
+		&cmper->tptc0clkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains_edma3,
+			 clk_modules_explicit_en_edma3,
+			 1);
+}
+
+void disable_edma3_clocks(void)
+{
+	u32 *const clk_domains_edma3[] = {
+		0
+	};
+
+	u32 *const clk_modules_disable_edma3[] = {
+		&cmper->tpccclkctrl,
+		&cmper->tptc0clkctrl,
+		0
+	};
+
+	do_disable_clocks(clk_domains_edma3,
+			  clk_modules_disable_edma3,
+			  1);
+}
+#endif

Signature · 1 line

2.5.0

Vignesh R

author maintainer

2015-08-17 07:59 UTC #8 lore raw

PATCH RESEND v2 7/10 sf: ops: Add spi_flash_copy_mmap function

From: Tom Rini <[email protected]>

When doing a memory mapped copy we may have DMA available and thus need to have this copy abstracted so that the driver can do it, rather than a simple memcpy.

Signed-off-by Tom Rini <[email protected]>

Signed-off-by Vignesh R <[email protected]>

---
 drivers/mtd/spi/sf_ops.c | 8 +++++++-
 include/spi.h            | 3 +++
 2 files changed, 10 insertions(+), 1 deletion(-)

drivers/mtd/spi/sf_ops.c +7 -1

index 38592f518b72..900ec1f2a9ce 100644
@@ -14,6 +14,7 @@
 #include <spi.h>
 #include <spi_flash.h>
 #include <watchdog.h>
+#include <linux/compiler.h>
 
 #include "sf_internal.h"

@@ -378,6 +379,11 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 	return ret;
 }
 
+void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len)
+{
+	memcpy(data, offset, len);
+}
+
 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 		size_t len, void *data)
 {

@@ -394,7 +400,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 			return ret;
 		}
 		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
-		memcpy(data, flash->memory_map + offset, len);
+		spi_flash_copy_mmap(data, flash->memory_map + offset, len);
 		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
 		spi_release_bus(flash->spi);
 		return 0;

include/spi.h +3 -0

index 18362364cf0e..51fdfd6d7360 100644
@@ -272,6 +272,9 @@ int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen);
 int  spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 		void *din, unsigned long flags);
 
+/* Copy memory mapped data */
+void spi_flash_copy_mmap(void *data, void *offset, size_t len);
+
 /**
  * Determine if a SPI chipselect is valid.
  * This function is provided by the board if the low-level SPI driver

Signature · 1 line

2.5.0

Vignesh R

author maintainer

2015-08-17 07:59 UTC #9 lore raw

PATCH RESEND v2 8/10 dma: ti-edma3: Add helper function to support edma3 transfer

Signed-off-by Vignesh R <[email protected]>

---
 arch/arm/include/asm/ti-common/ti-edma3.h |  2 +
 drivers/dma/ti-edma3.c                    | 78 +++++++++++++++++++++++++++++++
 2 files changed, 80 insertions(+)

arch/arm/include/asm/ti-common/ti-edma3.h +2 -0

index 5adc1dac0e65..6a7a321c1bdf 100644
@@ -117,5 +117,7 @@ void edma3_set_src_addr(u32 base, int slot, u32 src);
 void edma3_set_transfer_params(u32 base, int slot, int acnt,
 			       int bcnt, int ccnt, u16 bcnt_rld,
 			       enum edma3_sync_dimension sync_mode);
+void edma3_transfer(unsigned long edma3_base_addr, unsigned int
+		edma_slot_num, void *dst, void *src, size_t len);
 
 #endif

drivers/dma/ti-edma3.c +78 -0

81 lines not on this page · raw message

Signature · 1 line

2.5.0

Vignesh R

author maintainer

2015-08-17 07:59 UTC #10 lore raw

PATCH RESEND v2 9/10 spi: ti_qspi: Use DMA to read from qspi flash

ti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM.

Signed-off-by Vignesh R <[email protected]>

---
 drivers/spi/ti_qspi.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

drivers/spi/ti_qspi.c +23 -0

index 3356c0f072e5..753d68980bd6 100644
@@ -13,6 +13,8 @@
 #include <spi.h>
 #include <asm/gpio.h>
 #include <asm/omap_gpio.h>
+#include <asm/omap_common.h>
+#include <asm/ti-common/ti-edma3.h>
 
 /* ti qpsi register bit masks */
 #define QSPI_TIMEOUT                    2000000

@@ -347,3 +349,24 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 
 	return 0;
 }
+#ifdef CONFIG_TI_EDMA3
+void spi_flash_copy_mmap(void *data, void *offset, size_t len)
+{
+	unsigned int			addr = (unsigned int) (data);
+	unsigned int			edma_slot_num = 1;
+
+	/* Invalidate the area, so no writeback into the RAM races with DMA */
+	invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
+
+	/* enable edma3 clocks */
+	enable_edma3_clocks();
+
+	/* Call edma3 api to do actual DMA transfer	*/
+	edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
+
+	/* disable edma3 clocks */
+	disable_edma3_clocks();
+
+	*((unsigned int *)offset) += len;
+}
+#endif

Signature · 1 line

2.5.0

Jagan Teki

2015-08-17 08:18 UTC #11 lore raw

PATCH RESEND v2 9/10 spi: ti_qspi: Use DMA to read from qspi flash

Quoted 23 lines · Vignesh R

ti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM.
Signed-off-by Vignesh R <[email protected]>
Reviewed-by Jagan Teki <[email protected]>
---
 drivers/spi/ti_qspi.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
drivers/spi/ti_qspi.c +2 -0
index 3356c0f072e5..753d68980bd6 100644
@@ -13,6 +13,8 @@
 #include <spi.h>
 #include <asm/gpio.h>
 #include <asm/omap_gpio.h>
+#include <asm/omap_common.h>
+#include <asm/ti-common/ti-edma3.h>
 
 /* ti qpsi register bit masks */
 #define QSPI_TIMEOUT                    2000000

drivers/spi/ti_qspi.c int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, · line 351

Quoted 3 lines

drivers/spi/ti_qspi.c +0 -0

@@ -347,3 +349,24 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 
        return 0;
 }

Please add below comment here, I have asked the same on previous version patch this will track us to the work future.

/* TODO: control from sf layer to here through dm-spi */

Quoted 22 lines

drivers/spi/ti_qspi.c +21 -1

+#ifdef CONFIG_TI_EDMA3
+void spi_flash_copy_mmap(void *data, void *offset, size_t len)
+{
+       unsigned int                    addr = (unsigned int) (data);
+       unsigned int                    edma_slot_num = 1;
+
+       /* Invalidate the area, so no writeback into the RAM races with DMA */
+       invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
+
+       /* enable edma3 clocks */
+       enable_edma3_clocks();
+
+       /* Call edma3 api to do actual DMA transfer     */
+       edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
+
+       /* disable edma3 clocks */
+       disable_edma3_clocks();
+
+       *((unsigned int *)offset) += len;
+}
+#endif
--

Quoted 1 line

2.5.0

thanks!

Signature · 1 line

Jagan | openedev.

R

2015-08-17 08:22 UTC #12 lore raw

PATCH RESEND v2 9/10 spi: ti_qspi: Use DMA to read from qspi flash

Quoted 25 lines · Jagan Teki

Quoted 24 lines · Vignesh R
ti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM.
Signed-off-by Vignesh R <[email protected]>
Reviewed-by Jagan Teki <[email protected]>
---
 drivers/spi/ti_qspi.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
drivers/spi/ti_qspi.c +2 -0
index 3356c0f072e5..753d68980bd6 100644
@@ -13,6 +13,8 @@
 #include <spi.h>
 #include <asm/gpio.h>
 #include <asm/omap_gpio.h>
+#include <asm/omap_common.h>
+#include <asm/ti-common/ti-edma3.h>
 
 /* ti qpsi register bit masks */
 #define QSPI_TIMEOUT                    2000000
@@ -347,3 +349,24 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 

Quoted 6 lines

drivers/spi/ti_qspi.c int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, · line 351
Quoted 2 lines
drivers/spi/ti_qspi.c +0 -0
        return 0;
 }
Please add below comment here, I have asked the same on previous version patch this will track us to the work future.
/* TODO: control from sf layer to here through dm-spi */

Oops.. Sorry, I overlooked it.. Will add the comment and send it soon. Thanks!

Quoted 26 lines

Quoted 22 lines

drivers/spi/ti_qspi.c +21 -1

+#ifdef CONFIG_TI_EDMA3
+void spi_flash_copy_mmap(void *data, void *offset, size_t len)
+{
+       unsigned int                    addr = (unsigned int) (data);
+       unsigned int                    edma_slot_num = 1;
+
+       /* Invalidate the area, so no writeback into the RAM races with DMA */
+       invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
+
+       /* enable edma3 clocks */
+       enable_edma3_clocks();
+
+       /* Call edma3 api to do actual DMA transfer     */
+       edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
+
+       /* disable edma3 clocks */
+       disable_edma3_clocks();
+
+       *((unsigned int *)offset) += len;
+}
+#endif
--

Quoted 1 line

2.5.0

thanks!

Vignesh R

author maintainer

2015-08-17 09:50 UTC #13 lore raw

PATCH RESEND v2 9/10 spi: ti_qspi: Use DMA to read from qspi flash

ti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM.

Signed-off-by Vignesh R <[email protected]>

---
* Added a TODO comment

 drivers/spi/ti_qspi.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

drivers/spi/ti_qspi.c +25 -0

index 3356c0f072e5..c148d1cadfbd 100644
@@ -13,6 +13,8 @@
 #include <spi.h>
 #include <asm/gpio.h>
 #include <asm/omap_gpio.h>
+#include <asm/omap_common.h>
+#include <asm/ti-common/ti-edma3.h>
 
 /* ti qpsi register bit masks */
 #define QSPI_TIMEOUT                    2000000

@@ -347,3 +349,26 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 
 	return 0;
 }
+
+/* TODO: control from sf layer to here through dm-spi */
+#ifdef CONFIG_TI_EDMA3
+void spi_flash_copy_mmap(void *data, void *offset, size_t len)
+{
+	unsigned int			addr = (unsigned int) (data);
+	unsigned int			edma_slot_num = 1;
+
+	/* Invalidate the area, so no writeback into the RAM races with DMA */
+	invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
+
+	/* enable edma3 clocks */
+	enable_edma3_clocks();
+
+	/* Call edma3 api to do actual DMA transfer	*/
+	edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
+
+	/* disable edma3 clocks */
+	disable_edma3_clocks();
+
+	*((unsigned int *)offset) += len;
+}
+#endif

Signature · 1 line

2.5.0

Vignesh R

author maintainer

2015-08-17 07:59 UTC #14 lore raw

PATCH RESEND v2 10/10 ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi

Enable TI_EDMA3 and SPL_DMA support, so as to reduce boot time. With DMA enabled there is almost 3x improvement in read performance. This helps in reducing boot time in qspiboot mode

Also add EDMA3 base address for DRA7XX and AM57XX.

Signed-off-by Vignesh R <[email protected]>

---
 arch/arm/include/asm/arch-omap5/hardware.h | 5 +++++
 include/configs/dra7xx_evm.h               | 2 ++
 2 files changed, 7 insertions(+)

arch/arm/include/asm/arch-omap5/hardware.h +5 -0

index f7011b4e904a..a5bd60009289 100644
@@ -23,4 +23,9 @@
 /* GPMC Base address */
 #define GPMC_BASE			0x50000000
 
+/* EDMA3 Base address for DRA7XX and AM57XX */
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#define EDMA3_BASE			0x43300000
+#endif
+
 #endif

include/configs/dra7xx_evm.h +2 -0

index 74994479e60b..6e32de854619 100644
@@ -166,6 +166,8 @@
 
 /* SPI SPL */
 #define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_DMA_SUPPORT
+#define CONFIG_TI_EDMA3
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x40000

Signature · 1 line

2.5.0

Jagan Teki

2015-08-17 18:02 UTC #15 lore raw

v2 cover Enable edma support for ti-qspi