arm/ls1021a: Add sata support on qds and twr board
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
From: Tang Yuantian <[email protected]>
Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.
---
v2:
- rebase to latest git tree
- use micro SATA_ECC_REG_ADDR instead of hard coding
arch/arm/include/asm/arch-ls102xa/config.h | 15 ++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 24 +++++++++ board/freescale/ls1021aqds/ls1021aqds.c | 61 +++++++++++++++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 61 +++++++++++++++++++++++ 4 files changed, 161 insertions(+)
arch/arm/include/asm/arch-ls102xa/config.h +15 -0
@@ -79,6 +79,21 @@#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ CONFIG_SYS_PCIE2_VIRT_ADDR) +/* SATA */ +#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_FSL_ERRATUM_A008407 +#ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +24 -0
@@ -397,4 +397,28 @@ struct ccsr_cci400 { u8 res_e004[0x10000 - 0xe004]; }; +/* AHCI (sata) register map */ +struct ccsr_ahci { +u32 res1[0xa4 /4 ];/* 0x0 - 0xa4 */ +u32 pcfg;/* port config */ +u32 ppcfg;/* port phy1 config */ +u32 pp2c;/* port phy2 config */ +u32 pp3c;/* port phy3 config */ +u32 pp4c;/* port phy4 config */ +u32 pp5c;/* port phy5 config */ +u32 paxic;/* port AXI config */ +u32 axicc;/* AXI cache control */ +u32 axipc;/* AXI PROT control */ +u32 ptc;/* port Trans Config */ +u32 pts;/* port Trans Status */ +u32 plc;/* port link config */ +u32 plc1;/* port link config1 */ +u32 plc2;/* port link config2 */ +u32 pls;/* port link status */ +u32 pls1;/* port link status1 */ +u32 pcmdc;/* port CMD config */ +u32 ppcs;/* port phy control status */ +u32 pberr;/* port 0/1 BIST error */ +u32 cmds;/* port 0/1 CMD status error */ +};#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
board/freescale/ls1021aqds/ls1021aqds.c +61 -0
85 lines not on this page · raw message
board/freescale/ls1021atwr/ls1021atwr.c +61 -0
82 lines not on this page · raw message
Signature · 1 line
2.1.0.27.g96db324
PATCH v2 1/1 arm/ls2085a: Add sata support on qds and rdb board
From: Tang Yuantian <[email protected]>
Freescale ARM-based Layerscape LS2085A contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification.
This patch adds SATA feature on ls2085aqds and ls2085ardb boards.
---
v2:
- rebase to the latest git tree
arch/arm/cpu/armv8/fsl-lsch3/soc.c | 41 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/config.h | 20 +++++++++++ arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 25 ++++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/soc.h | 2 +- board/freescale/ls2085aqds/ls2085aqds.c | 11 ++++++ board/freescale/ls2085ardb/ls2085ardb.c | 11 ++++++ 6 files changed, 109 insertions(+), 1 deletion(-)
arch/arm/cpu/armv8/fsl-lsch3/soc.c +41 -0
@@ -11,6 +11,9 @@#include <asm/arch-fsl-lsch3/soc.h> #include <asm/io.h> #include <asm/global_data.h> +#include <asm/arch-fsl-lsch3/immap_lsch3.h> +#include <ahci.h> +#include <scsi.h> DECLARE_GLOBAL_DATA_PTR ;
@@ -70,12 +73,50 @@ static void erratum_a009203(void)#endif } +void ls2085a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ahci_base; + + ahci_base = (void __iomem *)CONFIG_SYS_SATA2 ; +out_le32 (&ahci_base->ppcfg,0xa003fffe ); + + ahci_base = (void __iomem *)CONFIG_SYS_SATA1 ; +out_le32 (&ahci_base->ppcfg,0xa003fffe ); +} + +#ifdef CONFIG_SCSI_AHCI_PLAT +int ls2085a_sata_start (void ) +{ +struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR ); +u32 cfg; +int rc =-1 ; + + cfg =in_le32 (&gur->rcwsr[28 ]) &FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK ; + cfg >>=FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT ; + +if ((cfg !=0x41 ) && (cfg !=0x42 ) && (cfg !=0x43 ) && + (cfg !=0x44 ) && (cfg !=0x49 ) && (cfg !=0x4A )) { +printf ("SATA disabled: serdes protocol doesn't support\n" ); +return rc; + } + + rc =ahci_init ((void __iomem *)CONFIG_SYS_SATA1 ); +if (rc) +return rc; + +scsi_scan (0 ); + +return 0 ; +} +#endif +void fsl_lsch3_early_init_f (void ) {erratum_a008751 ();erratum_rcw_src ();init_early_memctl_regs ();/* tighten IFC timing */ erratum_a009203 (); +ls2085a_sata_init (); }#ifdef CONFIG_SPL_BUILD
arch/arm/include/asm/arch-fsl-lsch3/config.h +20 -0
@@ -64,6 +64,26 @@#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + 0x02200000) +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + 0x02210000) + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h +25 -0
@@ -180,4 +180,29 @@ struct ccsr_reset {u32 ip_rev1;/* 0xbf8 */ u32 ip_rev2; /* 0xbfc */ }; + +/* AHCI (sata) register map */ +struct ccsr_ahci { +u32 res1[0xa4 /4 ];/* 0x0 - 0xa4 */ +u32 pcfg;/* port config */ +u32 ppcfg;/* port phy1 config */ +u32 pp2c;/* port phy2 config */ +u32 pp3c;/* port phy3 config */ +u32 pp4c;/* port phy4 config */ +u32 pp5c;/* port phy5 config */ +u32 paxic;/* port AXI config */ +u32 axicc;/* AXI cache control */ +u32 axipc;/* AXI PROT control */ +u32 ptc;/* port Trans Config */ +u32 pts;/* port Trans Status */ +u32 plc;/* port link config */ +u32 plc1;/* port link config1 */ +u32 plc2;/* port link config2 */ +u32 pls;/* port link status */ +u32 pls1;/* port link status1 */ +u32 pcmdc;/* port CMD config */ +u32 ppcs;/* port phy control status */ +u32 pberr;/* port 0/1 BIST error */ +u32 cmds;/* port 0/1 CMD status error */ +};#endif /* __ARCH_FSL_LSCH3_IMMAP_H */
arch/arm/include/asm/arch-fsl-lsch3/soc.h +1 -1
@@ -25,4 +25,4 @@ struct cpu_type {void fsl_lsch3_early_init_f (void );void cpu_name (char *name); - +int ls2085a_sata_start (void );
board/freescale/ls2085aqds/ls2085aqds.c +11 -0
@@ -249,6 +249,17 @@ int arch_misc_init(void) }#endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init (void ) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT +ls2085a_sata_start (); +#endif + +return 0 ; +} +#endif +unsigned long get_dram_size_to_hide (void ) {unsigned long dram_to_hide =0 ;
board/freescale/ls2085ardb/ls2085ardb.c +11 -0
@@ -217,6 +217,17 @@ int arch_misc_init(void) }#endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init (void ) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT +ls2085a_sata_start (); +#endif + +return 0 ; +} +#endif +unsigned long get_dram_size_to_hide (void ) {unsigned long dram_to_hide =0 ;
Signature · 1 line
2.1.0.27.g96db324
PATCH v2 1/1 arm/ls2085a: Add sata support on qds and rdb board
Quoted 35 lines · Yuantian.Tang at freescale.com
From: Tang Yuantian <[email protected]>
Freescale ARM-based Layerscape LS2085A contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification.
This patch adds SATA feature on ls2085aqds and ls2085ardb boards.Signed-off-by Tang Yuantian <[email protected]>---
v2:
- rebase to the latest git treearch/arm/cpu/armv8/fsl-lsch3/soc.c | 41 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/config.h | 20 +++++++++++ arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 25 ++++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/soc.h | 2 +- board/freescale/ls2085aqds/ls2085aqds.c | 11 ++++++ board/freescale/ls2085ardb/ls2085ardb.c | 11 ++++++ 6 files changed, 109 insertions(+), 1 deletion(-)arch/arm/cpu/armv8/fsl-lsch3/soc.c +3
-0@@ -11,6 +11,9 @@#include <asm/arch-fsl-lsch3/soc.h> #include <asm/io.h> #include <asm/global_data.h> +#include <asm/arch-fsl-lsch3/immap_lsch3.h> +#include <ahci.h> +#include <scsi.h> DECLARE_GLOBAL_DATA_PTR ;
arch/arm/cpu/armv8/fsl-lsch3/soc.c static void erratum_a009203(void) · line 81
Quoted 9 lines
arch/arm/cpu/armv8/fsl-lsch3/soc.c +6
-0@@ -70,12 +73,50 @@ static void erratum_a009203(void)#endif } +void ls2085a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ahci_base; + + ahci_base = (void __iomem *)CONFIG_SYS_SATA2 ; +out_le32 (&ahci_base->ppcfg,0xa003fffe );
Please put a comment to explain what this does and avoid using magic numbers.
arch/arm/cpu/armv8/fsl-lsch3/soc.c static void erratum_a009203(void) · line 84
Quoted 3 lines
arch/arm/cpu/armv8/fsl-lsch3/soc.c +3
-0+ + ahci_base = (void __iomem *)CONFIG_SYS_SATA1 ; +out_le32 (&ahci_base->ppcfg,0xa003fffe );
Same here.
York
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
In reply to Yuantian.Tang at freescale.comQuoted 100 lines · Yuantian.Tang at freescale.com
From: Tang Yuantian <[email protected]>
Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.Signed-off-by Tang Yuantian <[email protected]>---
v2:
- rebase to latest git tree
- use microSATA_ECC_REG_ADDRinstead of hard codingarch/arm/include/asm/arch-ls102xa/config.h | 15 ++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 24 +++++++++ board/freescale/ls1021aqds/ls1021aqds.c | 61 +++++++++++++++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 61 +++++++++++++++++++++++ 4 files changed, 161 insertions(+)arch/arm/include/asm/arch-ls102xa/config.h +15
-0@@ -79,6 +79,21 @@#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ CONFIG_SYS_PCIE2_VIRT_ADDR) +/* SATA */ +#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_FSL_ERRATUM_A008407 +#ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +24
-0@@ -397,4 +397,28 @@ struct ccsr_cci400 { u8 res_e004[0x10000 - 0xe004]; }; +/* AHCI (sata) register map */ +struct ccsr_ahci { +u32 res1[0xa4 /4 ];/* 0x0 - 0xa4 */ +u32 pcfg;/* port config */ +u32 ppcfg;/* port phy1 config */ +u32 pp2c;/* port phy2 config */ +u32 pp3c;/* port phy3 config */ +u32 pp4c;/* port phy4 config */ +u32 pp5c;/* port phy5 config */ +u32 paxic;/* port AXI config */ +u32 axicc;/* AXI cache control */ +u32 axipc;/* AXI PROT control */ +u32 ptc;/* port Trans Config */ +u32 pts;/* port Trans Status */ +u32 plc;/* port link config */ +u32 plc1;/* port link config1 */ +u32 plc2;/* port link config2 */ +u32 pls;/* port link status */ +u32 pls1;/* port link status1 */ +u32 pcmdc;/* port CMD config */ +u32 ppcs;/* port phy control status */ +u32 pberr;/* port 0/1 BIST error */ +u32 cmds;/* port 0/1 CMD status error */ +};#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ board/freescale/ls1021aqds/ls1021aqds.c +7
-0@@ -18,6 +18,8 @@#include <fsl_ifc.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #include "../common/qixis.h" @@ -54,6 +56,52 @@ enum { GE1_CLK125, }; +static void ls1021a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR ; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 73
Quoted 10 lines
board/freescale/ls1021aqds/ls1021aqds.c +10
-0+#define SATA_ECC_REG_ADDR 0x20220520 +unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR ; +#endif + +out_le32 (&ccsr_ahci->ppcfg,0xa003fffe ); +out_le32 (&ccsr_ahci->pp2c,0x28183411 ); +out_le32 (&ccsr_ahci->pp3c,0x0e081004 ); +out_le32 (&ccsr_ahci->pp4c,0x00480811 ); +out_le32 (&ccsr_ahci->pp5c,0x192c96a4 ); +out_le32 (&ccsr_ahci->ptc,0x08000025 );
What are these numbers?
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 77
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +4
-0+ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +out_le32 (ecc_reg,0x00020000 ); +#endif
Same here.
Quoted 31 lines
board/freescale/ls1021aqds/ls1021aqds.c +27
-0+} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start (void ) +{ +struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR ; +u32 cfg; +int rc =-1 ; + + cfg =in_be32 (&gur->rcwsr[4 ]) &RCWSR4_SRDS1_PRTCL_MASK ; + cfg >>=RCWSR4_SRDS1_PRTCL_SHIFT ; + +if (cfg !=0x30 && cfg !=0x70 ) { +printf ("SATA disabled: serdes protocol doesn't support\n" ); +return rc; + } + + rc =ahci_init ((void __iomem *)AHCI_BASE_ADDR ); +if (rc) +return rc; + +scsi_scan (0 ); + +return 0 ; +} +#endif +#ifdef CONFIG_LS102XA_NS_ACCESS static struct csu_ns_dev ns_dev[] = { { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
board/freescale/ls1021aqds/ls1021aqds.c int board_early_init_f(void) · line 378
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +1
-0@@ -327,6 +375,8 @@ int board_early_init_f(void)fsl_dp_disable_console ();#endif +ls1021a_sata_init ();
Is it OK to run this init regardless SerDes protocol?
Quoted 36 lines
board/freescale/ls1021aqds/ls1021aqds.c +12
-0+return 0 ; }@@ -388,6 +438,17 @@ void board_init_f(ulong dummy) }#endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init (void ) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT +ls1021a_sata_start (); +#endif + +return 0 ; +} +#endif +void config_etseccm_source (int etsec_gtx_125_mux) {struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR ;board/freescale/ls1021atwr/ls1021atwr.c +2
-0@@ -22,6 +22,8 @@#include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h"
board/freescale/ls1021atwr/ls1021atwr.c struct cpld_data { · line 182
Quoted 8 lines
board/freescale/ls1021atwr/ls1021atwr.c +5
-0@@ -173,6 +175,52 @@ struct cpld_data {u8 rev2;/* Reserved */ }; +static void ls1021a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR ; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be in board file.
York
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 65
Quoted 3 lines
board/freescale/ls1021aqds/ls1021aqds.c +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 +unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR ;#endif
Quoted 10 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 73
Quoted 7 lines
board/freescale/ls1021aqds/ls1021aqds.c +7
-0+ +out_le32 (&ccsr_ahci->ppcfg,0xa003fffe ); +out_le32 (&ccsr_ahci->pp2c,0x28183411 ); +out_le32 (&ccsr_ahci->pp3c,0x0e081004 ); +out_le32 (&ccsr_ahci->pp4c,0x00480811 ); +out_le32 (&ccsr_ahci->pp5c,0x192c96a4 ); +out_le32 (&ccsr_ahci->ptc,0x08000025 );What are these numbers?
I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for sata. They are gotten from validation team. Their meanings are documented in RM. Is it necessary to re-explain bit by bit again?
Same reasons for ls2085.
Regards,
Yuantian
Quoted 94 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 77
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +4
-0+ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +out_le32 (ecc_reg,0x00020000 ); +#endif Same here.
board/freescale/ls1021aqds/ls1021aqds.c enum {
Quoted 6 lines
board/freescale/ls1021aqds/ls1021aqds.c +6
-0+} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start (void ) +{ + struct ccsr_gur *gur = (struct ccsr_gur*)CONFIG_SYS_FSL_GUTS_ADDR;
Quoted 25 lines
board/freescale/ls1021aqds/ls1021aqds.c +21
-0+u32 cfg; +int rc =-1 ; + + cfg =in_be32 (&gur->rcwsr[4 ]) &RCWSR4_SRDS1_PRTCL_MASK ; + cfg >>=RCWSR4_SRDS1_PRTCL_SHIFT ; + +if (cfg !=0x30 && cfg !=0x70 ) { +printf ("SATA disabled: serdes protocol doesn't support\n" ); +return rc; + } + + rc =ahci_init ((void __iomem *)AHCI_BASE_ADDR ); +if (rc) +return rc; + +scsi_scan (0 ); + +return 0 ; +} +#endif +#ifdef CONFIG_LS102XA_NS_ACCESS static struct csu_ns_dev ns_dev[] = { { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },board/freescale/ls1021aqds/ls1021aqds.c int board_early_init_f(void) · line 378
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +1
-0@@ -327,6 +375,8 @@ int board_early_init_f(void)fsl_dp_disable_console ();#endif +ls1021a_sata_init ();Is it OK to run this init regardless SerDes protocol?
Quoted 35 lines
board/freescale/ls1021aqds/ls1021aqds.c +12
-0+return 0 ; }@@ -388,6 +438,17 @@ void board_init_f(ulong dummy) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init (void ) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT +ls1021a_sata_start (); +#endif + +return 0 ; +} +#endif +void config_etseccm_source (int etsec_gtx_125_mux) {struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
a/board/freescale/ls1021atwr/ls1021atwr.cb/board/freescale/ls1021atwr/ls1021atwr.c
index b7458a9..6a964c3 100644board/freescale/ls1021atwr/ls1021atwr.c +2
-0@@ -22,6 +22,8 @@#include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" board/freescale/ls1021atwr/ls1021atwr.c struct cpld_data { · line 182
Quoted 8 lines
board/freescale/ls1021atwr/ls1021atwr.c +5
-0@@ -173,6 +175,52 @@ struct cpld_data {u8 rev2;/* Reserved */ }; +static void ls1021a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR ; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be in board file.
York
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
Sorry for top posting, replying from my phone.
Please use macros instead of numbers. It's still better than putting magic numbers in the code. And please move it out of board files.
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot at lists.denx.de, Kushwaha Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Quoted 12 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 65
Quoted 3 lines
board/freescale/ls1021aqds/ls1021aqds.c +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 +unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR ;#endif
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 73
Quoted 7 lines
board/freescale/ls1021aqds/ls1021aqds.c +7
-0+ +out_le32 (&ccsr_ahci->ppcfg,0xa003fffe ); +out_le32 (&ccsr_ahci->pp2c,0x28183411 ); +out_le32 (&ccsr_ahci->pp3c,0x0e081004 ); +out_le32 (&ccsr_ahci->pp4c,0x00480811 ); +out_le32 (&ccsr_ahci->pp5c,0x192c96a4 ); +out_le32 (&ccsr_ahci->ptc,0x08000025 );
Quoted 2 lines
What are these numbers?
I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for sata. They are gotten from validation team. Their meanings are documented in RM. Is it necessary to re-explain bit by bit again?
Same reasons for ls2085.
Regards,
Yuantian
Quoted 94 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 77
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +4
-0+ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +out_le32 (ecc_reg,0x00020000 ); +#endif Same here.
board/freescale/ls1021aqds/ls1021aqds.c enum {
Quoted 6 lines
board/freescale/ls1021aqds/ls1021aqds.c +6
-0+} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start (void ) +{ + struct ccsr_gur *gur = (struct ccsr_gur*)CONFIG_SYS_FSL_GUTS_ADDR;
Quoted 25 lines
board/freescale/ls1021aqds/ls1021aqds.c +21
-0+u32 cfg; +int rc =-1 ; + + cfg =in_be32 (&gur->rcwsr[4 ]) &RCWSR4_SRDS1_PRTCL_MASK ; + cfg >>=RCWSR4_SRDS1_PRTCL_SHIFT ; + +if (cfg !=0x30 && cfg !=0x70 ) { +printf ("SATA disabled: serdes protocol doesn't support\n" ); +return rc; + } + + rc =ahci_init ((void __iomem *)AHCI_BASE_ADDR ); +if (rc) +return rc; + +scsi_scan (0 ); + +return 0 ; +} +#endif +#ifdef CONFIG_LS102XA_NS_ACCESS static struct csu_ns_dev ns_dev[] = { { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },board/freescale/ls1021aqds/ls1021aqds.c int board_early_init_f(void) · line 378
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +1
-0@@ -327,6 +375,8 @@ int board_early_init_f(void)fsl_dp_disable_console ();#endif +ls1021a_sata_init ();Is it OK to run this init regardless SerDes protocol?
Quoted 35 lines
board/freescale/ls1021aqds/ls1021aqds.c +12
-0+return 0 ; }@@ -388,6 +438,17 @@ void board_init_f(ulong dummy) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init (void ) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT +ls1021a_sata_start (); +#endif + +return 0 ; +} +#endif +void config_etseccm_source (int etsec_gtx_125_mux) {struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
a/board/freescale/ls1021atwr/ls1021atwr.cb/board/freescale/ls1021atwr/ls1021atwr.c
index b7458a9..6a964c3 100644board/freescale/ls1021atwr/ls1021atwr.c +2
-0@@ -22,6 +22,8 @@#include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" board/freescale/ls1021atwr/ls1021atwr.c struct cpld_data { · line 182
Quoted 8 lines
board/freescale/ls1021atwr/ls1021atwr.c +5
-0@@ -173,6 +175,52 @@ struct cpld_data {u8 rev2;/* Reserved */ }; +static void ls1021a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR ; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be in board file.
York
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
OK, I will updated this patch.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Sorry for top posting, replying from my phone.
Please use macros instead of numbers. It's still better than putting magic numbers in the code. And please move it out of board files.
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>, Kushwaha Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Quoted 12 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 65
Quoted 3 lines
board/freescale/ls1021aqds/ls1021aqds.c +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 +unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR ;#endif
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 73
Quoted 7 lines
board/freescale/ls1021aqds/ls1021aqds.c +7
-0+ +out_le32 (&ccsr_ahci->ppcfg,0xa003fffe ); +out_le32 (&ccsr_ahci->pp2c,0x28183411 ); +out_le32 (&ccsr_ahci->pp3c,0x0e081004 ); +out_le32 (&ccsr_ahci->pp4c,0x00480811 ); +out_le32 (&ccsr_ahci->pp5c,0x192c96a4 ); +out_le32 (&ccsr_ahci->ptc,0x08000025 );
Quoted 2 lines
What are these numbers?
I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for sata. They are gotten from validation team. Their meanings are documented in RM. Is it necessary to re-explain bit by bit again?
Same reasons for ls2085.
Regards,
Yuantian
Quoted 94 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 77
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +4
-0+ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +out_le32 (ecc_reg,0x00020000 ); +#endif Same here.
board/freescale/ls1021aqds/ls1021aqds.c enum {
Quoted 6 lines
board/freescale/ls1021aqds/ls1021aqds.c +6
-0+} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start (void ) +{ + struct ccsr_gur *gur = (struct ccsr_gur*)CONFIG_SYS_FSL_GUTS_ADDR;
Quoted 25 lines
board/freescale/ls1021aqds/ls1021aqds.c +21
-0+u32 cfg; +int rc =-1 ; + + cfg =in_be32 (&gur->rcwsr[4 ]) &RCWSR4_SRDS1_PRTCL_MASK ; + cfg >>=RCWSR4_SRDS1_PRTCL_SHIFT ; + +if (cfg !=0x30 && cfg !=0x70 ) { +printf ("SATA disabled: serdes protocol doesn't support\n" ); +return rc; + } + + rc =ahci_init ((void __iomem *)AHCI_BASE_ADDR ); +if (rc) +return rc; + +scsi_scan (0 ); + +return 0 ; +} +#endif +#ifdef CONFIG_LS102XA_NS_ACCESS static struct csu_ns_dev ns_dev[] = { { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },board/freescale/ls1021aqds/ls1021aqds.c int board_early_init_f(void) · line 378
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +1
-0@@ -327,6 +375,8 @@ int board_early_init_f(void)fsl_dp_disable_console ();#endif +ls1021a_sata_init ();Is it OK to run this init regardless SerDes protocol?
Quoted 35 lines
board/freescale/ls1021aqds/ls1021aqds.c +12
-0+return 0 ; }@@ -388,6 +438,17 @@ void board_init_f(ulong dummy) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init (void ) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT +ls1021a_sata_start (); +#endif + +return 0 ; +} +#endif +void config_etseccm_source (int etsec_gtx_125_mux) {struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
a/board/freescale/ls1021atwr/ls1021atwr.cb/board/freescale/ls1021atwr/ls1021atwr.c
index b7458a9..6a964c3 100644board/freescale/ls1021atwr/ls1021atwr.c +2
-0@@ -22,6 +22,8 @@#include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" board/freescale/ls1021atwr/ls1021atwr.c struct cpld_data { · line 182
Quoted 8 lines
board/freescale/ls1021atwr/ls1021atwr.c +5
-0@@ -173,6 +175,52 @@ struct cpld_data {u8 rev2;/* Reserved */ }; +static void ls1021a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR ; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be in board file.
York
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
In reply to York SunFrom: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Sorry for top posting, replying from my phone.
Please use macros instead of numbers. It's still better than putting magic numbers in the code. And please move it out of board files.
Yuantian:
Please move what out of board files, these magic numbers or sata init function?
Regards,
Yuantian
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>, Kushwaha Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Quoted 12 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 65
Quoted 3 lines
board/freescale/ls1021aqds/ls1021aqds.c +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 +unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR ;#endif
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 73
Quoted 7 lines
board/freescale/ls1021aqds/ls1021aqds.c +7
-0+ +out_le32 (&ccsr_ahci->ppcfg,0xa003fffe ); +out_le32 (&ccsr_ahci->pp2c,0x28183411 ); +out_le32 (&ccsr_ahci->pp3c,0x0e081004 ); +out_le32 (&ccsr_ahci->pp4c,0x00480811 ); +out_le32 (&ccsr_ahci->pp5c,0x192c96a4 ); +out_le32 (&ccsr_ahci->ptc,0x08000025 );
Quoted 2 lines
What are these numbers?
I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for sata. They are gotten from validation team. Their meanings are documented in RM. Is it necessary to re-explain bit by bit again?
Same reasons for ls2085.
Regards,
Yuantian
Quoted 94 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 77
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +4
-0+ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +out_le32 (ecc_reg,0x00020000 ); +#endif Same here.
board/freescale/ls1021aqds/ls1021aqds.c enum {
Quoted 6 lines
board/freescale/ls1021aqds/ls1021aqds.c +6
-0+} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start (void ) +{ + struct ccsr_gur *gur = (struct ccsr_gur*)CONFIG_SYS_FSL_GUTS_ADDR;
Quoted 25 lines
board/freescale/ls1021aqds/ls1021aqds.c +21
-0+u32 cfg; +int rc =-1 ; + + cfg =in_be32 (&gur->rcwsr[4 ]) &RCWSR4_SRDS1_PRTCL_MASK ; + cfg >>=RCWSR4_SRDS1_PRTCL_SHIFT ; + +if (cfg !=0x30 && cfg !=0x70 ) { +printf ("SATA disabled: serdes protocol doesn't support\n" ); +return rc; + } + + rc =ahci_init ((void __iomem *)AHCI_BASE_ADDR ); +if (rc) +return rc; + +scsi_scan (0 ); + +return 0 ; +} +#endif +#ifdef CONFIG_LS102XA_NS_ACCESS static struct csu_ns_dev ns_dev[] = { { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },board/freescale/ls1021aqds/ls1021aqds.c int board_early_init_f(void) · line 378
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +1
-0@@ -327,6 +375,8 @@ int board_early_init_f(void)fsl_dp_disable_console ();#endif +ls1021a_sata_init ();Is it OK to run this init regardless SerDes protocol?
Quoted 35 lines
board/freescale/ls1021aqds/ls1021aqds.c +12
-0+return 0 ; }@@ -388,6 +438,17 @@ void board_init_f(ulong dummy) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init (void ) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT +ls1021a_sata_start (); +#endif + +return 0 ; +} +#endif +void config_etseccm_source (int etsec_gtx_125_mux) {struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
a/board/freescale/ls1021atwr/ls1021atwr.cb/board/freescale/ls1021atwr/ls1021atwr.c
index b7458a9..6a964c3 100644board/freescale/ls1021atwr/ls1021atwr.c +2
-0@@ -22,6 +22,8 @@#include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" board/freescale/ls1021atwr/ls1021atwr.c struct cpld_data { · line 182
Quoted 8 lines
board/freescale/ls1021atwr/ls1021atwr.c +5
-0@@ -173,6 +175,52 @@ struct cpld_data {u8 rev2;/* Reserved */ }; +static void ls1021a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR ; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be in board file.
York
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
The soc workarounds belongs to soc file, not board file, so you don't have to copy the code to every board. Our boards are not the only boards with this SoC.
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 20:34 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot at lists.denx.de, Kushwaha Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Sorry for top posting, replying from my phone.
Please use macros instead of numbers. It's still better than putting magic numbers in the code. And please move it out of board files.
Yuantian:
Please move what out of board files, these magic numbers or sata init function?
Regards,
Yuantian
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>, Kushwaha Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Quoted 12 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 65
Quoted 3 lines
board/freescale/ls1021aqds/ls1021aqds.c +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 +unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR ;#endif
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 73
Quoted 7 lines
board/freescale/ls1021aqds/ls1021aqds.c +7
-0+ +out_le32 (&ccsr_ahci->ppcfg,0xa003fffe ); +out_le32 (&ccsr_ahci->pp2c,0x28183411 ); +out_le32 (&ccsr_ahci->pp3c,0x0e081004 ); +out_le32 (&ccsr_ahci->pp4c,0x00480811 ); +out_le32 (&ccsr_ahci->pp5c,0x192c96a4 ); +out_le32 (&ccsr_ahci->ptc,0x08000025 );
Quoted 2 lines
What are these numbers?
I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for sata. They are gotten from validation team. Their meanings are documented in RM. Is it necessary to re-explain bit by bit again?
Same reasons for ls2085.
Regards,
Yuantian
Quoted 94 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 77
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +4
-0+ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +out_le32 (ecc_reg,0x00020000 ); +#endif Same here.
board/freescale/ls1021aqds/ls1021aqds.c enum {
Quoted 6 lines
board/freescale/ls1021aqds/ls1021aqds.c +6
-0+} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start (void ) +{ + struct ccsr_gur *gur = (struct ccsr_gur*)CONFIG_SYS_FSL_GUTS_ADDR;
Quoted 25 lines
board/freescale/ls1021aqds/ls1021aqds.c +21
-0+u32 cfg; +int rc =-1 ; + + cfg =in_be32 (&gur->rcwsr[4 ]) &RCWSR4_SRDS1_PRTCL_MASK ; + cfg >>=RCWSR4_SRDS1_PRTCL_SHIFT ; + +if (cfg !=0x30 && cfg !=0x70 ) { +printf ("SATA disabled: serdes protocol doesn't support\n" ); +return rc; + } + + rc =ahci_init ((void __iomem *)AHCI_BASE_ADDR ); +if (rc) +return rc; + +scsi_scan (0 ); + +return 0 ; +} +#endif +#ifdef CONFIG_LS102XA_NS_ACCESS static struct csu_ns_dev ns_dev[] = { { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },board/freescale/ls1021aqds/ls1021aqds.c int board_early_init_f(void) · line 378
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +1
-0@@ -327,6 +375,8 @@ int board_early_init_f(void)fsl_dp_disable_console ();#endif +ls1021a_sata_init ();Is it OK to run this init regardless SerDes protocol?
Quoted 35 lines
board/freescale/ls1021aqds/ls1021aqds.c +12
-0+return 0 ; }@@ -388,6 +438,17 @@ void board_init_f(ulong dummy) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init (void ) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT +ls1021a_sata_start (); +#endif + +return 0 ; +} +#endif +void config_etseccm_source (int etsec_gtx_125_mux) {struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
a/board/freescale/ls1021atwr/ls1021atwr.cb/board/freescale/ls1021atwr/ls1021atwr.c
index b7458a9..6a964c3 100644board/freescale/ls1021atwr/ls1021atwr.c +2
-0@@ -22,6 +22,8 @@#include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" board/freescale/ls1021atwr/ls1021atwr.c struct cpld_data { · line 182
Quoted 8 lines
board/freescale/ls1021atwr/ls1021atwr.c +5
-0@@ -173,6 +175,52 @@ struct cpld_data {u8 rev2;/* Reserved */ }; +static void ls1021a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR ; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be in board file.
York
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
I don't understand. This workaround is our board specific and actually ls1021 specific. I thought about merging all the LS SATA initialization into one file, but that didn't reduce many code. So I add this one by one board.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:38 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
The soc workarounds belongs to soc file, not board file, so you don't have to copy the code to every board. Our boards are not the only boards with this SoC.
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 20:34 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>, Kushwaha Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Sorry for top posting, replying from my phone.
Please use macros instead of numbers. It's still better than putting magic numbers in the code. And please move it out of board files.
Yuantian:
Please move what out of board files, these magic numbers or sata init function?
Regards,
Yuantian
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>, Kushwaha Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Quoted 12 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 65
Quoted 3 lines
board/freescale/ls1021aqds/ls1021aqds.c +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 +unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR ;#endif
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 73
Quoted 7 lines
board/freescale/ls1021aqds/ls1021aqds.c +7
-0+ +out_le32 (&ccsr_ahci->ppcfg,0xa003fffe ); +out_le32 (&ccsr_ahci->pp2c,0x28183411 ); +out_le32 (&ccsr_ahci->pp3c,0x0e081004 ); +out_le32 (&ccsr_ahci->pp4c,0x00480811 ); +out_le32 (&ccsr_ahci->pp5c,0x192c96a4 ); +out_le32 (&ccsr_ahci->ptc,0x08000025 );
Quoted 2 lines
What are these numbers?
I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for sata. They are gotten from validation team. Their meanings are documented in RM. Is it necessary to re-explain bit by bit again?
Same reasons for ls2085.
Regards,
Yuantian
Quoted 94 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 77
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +4
-0+ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +out_le32 (ecc_reg,0x00020000 ); +#endif Same here.
board/freescale/ls1021aqds/ls1021aqds.c enum {
Quoted 6 lines
board/freescale/ls1021aqds/ls1021aqds.c +6
-0+} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start (void ) +{ + struct ccsr_gur *gur = (struct ccsr_gur*)CONFIG_SYS_FSL_GUTS_ADDR;
Quoted 25 lines
board/freescale/ls1021aqds/ls1021aqds.c +21
-0+u32 cfg; +int rc =-1 ; + + cfg =in_be32 (&gur->rcwsr[4 ]) &RCWSR4_SRDS1_PRTCL_MASK ; + cfg >>=RCWSR4_SRDS1_PRTCL_SHIFT ; + +if (cfg !=0x30 && cfg !=0x70 ) { +printf ("SATA disabled: serdes protocol doesn't support\n" ); +return rc; + } + + rc =ahci_init ((void __iomem *)AHCI_BASE_ADDR ); +if (rc) +return rc; + +scsi_scan (0 ); + +return 0 ; +} +#endif +#ifdef CONFIG_LS102XA_NS_ACCESS static struct csu_ns_dev ns_dev[] = { { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },board/freescale/ls1021aqds/ls1021aqds.c int board_early_init_f(void) · line 378
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +1
-0@@ -327,6 +375,8 @@ int board_early_init_f(void)fsl_dp_disable_console ();#endif +ls1021a_sata_init ();Is it OK to run this init regardless SerDes protocol?
Quoted 35 lines
board/freescale/ls1021aqds/ls1021aqds.c +12
-0+return 0 ; }@@ -388,6 +438,17 @@ void board_init_f(ulong dummy) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init (void ) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT +ls1021a_sata_start (); +#endif + +return 0 ; +} +#endif +void config_etseccm_source (int etsec_gtx_125_mux) {struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
a/board/freescale/ls1021atwr/ls1021atwr.cb/board/freescale/ls1021atwr/ls1021atwr.c
index b7458a9..6a964c3 100644board/freescale/ls1021atwr/ls1021atwr.c +2
-0@@ -22,6 +22,8 @@#include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" board/freescale/ls1021atwr/ls1021atwr.c struct cpld_data { · line 182
Quoted 8 lines
board/freescale/ls1021atwr/ls1021atwr.c +5
-0@@ -173,6 +175,52 @@ struct cpld_data {u8 rev2;/* Reserved */ }; +static void ls1021a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR ; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be in board file.
York
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
Yuantian,
In your patch, you are using CONFIG_SYS_FSL_ERRATUM_A008407. Are you saying this is a board erratum, not an SoC erratum?
York
________________________________
From: Tang Yuantian-B29983
Sent: Tuesday, August 18, 2015 8:47 PM
To: Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
I don?t understand. This workaround is our board specific and actually ls1021 specific. I thought about merging all the LS SATA initialization into one file, but that didn?t reduce many code. So I add this one by one board.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:38 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
The soc workarounds belongs to soc file, not board file, so you don't have to copy the code to every board. Our boards are not the only boards with this SoC.
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 20:34 (GMT-08:00)
To: Sun York-R58495
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Sorry for top posting, replying from my phone.
Please use macros instead of numbers. It's still better than putting magic numbers in the code. And please move it out of board files.
Yuantian:
Please move what out of board files, these magic numbers or sata init function?
Regards,
Yuantian
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun York-R58495
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Quoted 12 lines
Review
Quoted 3 lines
(quoted diff) +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 + unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;#endif
Review
Quoted 7 lines
(quoted diff) +7
-0+ + out_le32(&ccsr_ahci->ppcfg, 0xa003fffe); + out_le32(&ccsr_ahci->pp2c, 0x28183411); + out_le32(&ccsr_ahci->pp3c, 0x0e081004); + out_le32(&ccsr_ahci->pp4c, 0x00480811); + out_le32(&ccsr_ahci->pp5c, 0x192c96a4); + out_le32(&ccsr_ahci->ptc, 0x08000025);
Quoted 2 lines
What are these numbers?
I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for sata. They are gotten from validation team. Their meanings are documented in RM. Is it necessary to re-explain bit by bit again?
Same reasons for ls2085.
Regards,
Yuantian
Quoted 94 lines
Review
Quoted 4 lines
(quoted diff) +4
-0+ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 + out_le32(ecc_reg, 0x00020000); +#endifSame here.
Review
Quoted 6 lines
(quoted diff) +6
-0+} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start(void) +{ + struct ccsr_gur *gur = (struct ccsr_gur*)CONFIG_SYS_FSL_GUTS_ADDR;
Quoted 25 lines
(quoted diff) +21
-0+ u32 cfg; + int rc = -1; + + cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; + + if (cfg != 0x30 && cfg != 0x70) { + printf("SATA disabled: serdes protocol doesn't support\n"); + return rc; + } + + rc = ahci_init((void __iomem *)AHCI_BASE_ADDR); + if (rc) + return rc; + + scsi_scan(0); + + return 0; +} +#endif + #ifdef CONFIG_LS102XA_NS_ACCESS static struct csu_ns_dev ns_dev[] = { { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },Review int board_early_init_f(void) · line 378
Quoted 4 lines
(quoted diff) +1
-0@@ -327,6 +375,8 @@ int board_early_init_f(void) fsl_dp_disable_console(); #endif + ls1021a_sata_init();Is it OK to run this init regardless SerDes protocol?
Quoted 35 lines
(quoted diff) +12
-0+ return 0; }@@ -388,6 +438,17 @@ void board_init_f(ulong dummy) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls1021a_sata_start(); +#endif + + return 0; +} +#endif + void config_etseccm_source(int etsec_gtx_125_mux) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
a/board/freescale/ls1021atwr/ls1021atwr.cb/board/freescale/ls1021atwr/ls1021atwr.c
index b7458a9..6a964c3 100644board/freescale/ls1021atwr/ls1021atwr.c +2
-0@@ -22,6 +22,8 @@#include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" board/freescale/ls1021atwr/ls1021atwr.c struct cpld_data { · line 182
Quoted 8 lines
board/freescale/ls1021atwr/ls1021atwr.c +5
-0@@ -173,6 +175,52 @@ struct cpld_data {u8 rev2;/* Reserved */ }; +static void ls1021a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR ; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be in board file.
York
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
Yes, this is a ls1021 specific errata.
Maybe we need to name the errata micro better.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:57 AM
To: Tang Yuantian-B29983
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: Re: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Yuantian,
In your patch, you are using CONFIG_SYS_FSL_ERRATUM_A008407. Are you saying this is a board erratum, not an SoC erratum?
York
________________________________
From: Tang Yuantian-B29983
Sent: Tuesday, August 18, 2015 8:47 PM
To: Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
I don't understand. This workaround is our board specific and actually ls1021 specific. I thought about merging all the LS SATA initialization into one file, but that didn't reduce many code. So I add this one by one board.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:38 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
The soc workarounds belongs to soc file, not board file, so you don't have to copy the code to every board. Our boards are not the only boards with this SoC.
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 20:34 (GMT-08:00)
To: Sun York-R58495
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Sorry for top posting, replying from my phone.
Please use macros instead of numbers. It's still better than putting magic numbers in the code. And please move it out of board files.
Yuantian:
Please move what out of board files, these magic numbers or sata init function?
Regards,
Yuantian
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun York-R58495
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Quoted 12 lines
Review
Quoted 3 lines
(quoted diff) +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 + unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;#endif
Review
Quoted 7 lines
(quoted diff) +7
-0+ + out_le32(&ccsr_ahci->ppcfg, 0xa003fffe); + out_le32(&ccsr_ahci->pp2c, 0x28183411); + out_le32(&ccsr_ahci->pp3c, 0x0e081004); + out_le32(&ccsr_ahci->pp4c, 0x00480811); + out_le32(&ccsr_ahci->pp5c, 0x192c96a4); + out_le32(&ccsr_ahci->ptc, 0x08000025);
Quoted 2 lines
What are these numbers?
I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for sata. They are gotten from validation team. Their meanings are documented in RM. Is it necessary to re-explain bit by bit again?
Same reasons for ls2085.
Regards,
Yuantian
Quoted 94 lines
Review
Quoted 4 lines
(quoted diff) +4
-0+ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 + out_le32(ecc_reg, 0x00020000); +#endifSame here.
Review
Quoted 6 lines
(quoted diff) +6
-0+} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start(void) +{ + struct ccsr_gur *gur = (struct ccsr_gur*)CONFIG_SYS_FSL_GUTS_ADDR;
Quoted 25 lines
(quoted diff) +21
-0+ u32 cfg; + int rc = -1; + + cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; + + if (cfg != 0x30 && cfg != 0x70) { + printf("SATA disabled: serdes protocol doesn't support\n"); + return rc; + } + + rc = ahci_init((void __iomem *)AHCI_BASE_ADDR); + if (rc) + return rc; + + scsi_scan(0); + + return 0; +} +#endif + #ifdef CONFIG_LS102XA_NS_ACCESS static struct csu_ns_dev ns_dev[] = { { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },Review int board_early_init_f(void) · line 378
Quoted 4 lines
(quoted diff) +1
-0@@ -327,6 +375,8 @@ int board_early_init_f(void) fsl_dp_disable_console(); #endif + ls1021a_sata_init();Is it OK to run this init regardless SerDes protocol?
Quoted 35 lines
(quoted diff) +12
-0+ return 0; }@@ -388,6 +438,17 @@ void board_init_f(ulong dummy) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls1021a_sata_start(); +#endif + + return 0; +} +#endif + void config_etseccm_source(int etsec_gtx_125_mux) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
a/board/freescale/ls1021atwr/ls1021atwr.cb/board/freescale/ls1021atwr/ls1021atwr.c
index b7458a9..6a964c3 100644board/freescale/ls1021atwr/ls1021atwr.c +2
-0@@ -22,6 +22,8 @@#include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" board/freescale/ls1021atwr/ls1021atwr.c struct cpld_data { · line 182
Quoted 8 lines
board/freescale/ls1021atwr/ls1021atwr.c +5
-0@@ -173,6 +175,52 @@ struct cpld_data {u8 rev2;/* Reserved */ }; +static void ls1021a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR ; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be in board file.
York
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
That's exactly what I mean. It is ls1021 soc erratum, not board specific.
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 21:36 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot at lists.denx.de, Kushwaha Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Yes, this is a ls1021 specific errata.
Maybe we need to name the errata micro better.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:57 AM
To: Tang Yuantian-B29983
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: Re: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Yuantian,
In your patch, you are using CONFIG_SYS_FSL_ERRATUM_A008407. Are you saying this is a board erratum, not an SoC erratum?
York
________________________________
From: Tang Yuantian-B29983
Sent: Tuesday, August 18, 2015 8:47 PM
To: Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
I don?t understand. This workaround is our board specific and actually ls1021 specific. I thought about merging all the LS SATA initialization into one file, but that didn?t reduce many code. So I add this one by one board.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:38 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
The soc workarounds belongs to soc file, not board file, so you don't have to copy the code to every board. Our boards are not the only boards with this SoC.
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 20:34 (GMT-08:00)
To: Sun York-R58495
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Sorry for top posting, replying from my phone.
Please use macros instead of numbers. It's still better than putting magic numbers in the code. And please move it out of board files.
Yuantian:
Please move what out of board files, these magic numbers or sata init function?
Regards,
Yuantian
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun York-R58495
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Quoted 12 lines
Review
Quoted 3 lines
(quoted diff) +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 + unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;#endif
Review
Quoted 7 lines
(quoted diff) +7
-0+ + out_le32(&ccsr_ahci->ppcfg, 0xa003fffe); + out_le32(&ccsr_ahci->pp2c, 0x28183411); + out_le32(&ccsr_ahci->pp3c, 0x0e081004); + out_le32(&ccsr_ahci->pp4c, 0x00480811); + out_le32(&ccsr_ahci->pp5c, 0x192c96a4); + out_le32(&ccsr_ahci->ptc, 0x08000025);
Quoted 2 lines
What are these numbers?
I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for sata. They are gotten from validation team. Their meanings are documented in RM. Is it necessary to re-explain bit by bit again?
Same reasons for ls2085.
Regards,
Yuantian
Quoted 94 lines
Review
Quoted 4 lines
(quoted diff) +4
-0+ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 + out_le32(ecc_reg, 0x00020000); +#endifSame here.
Review
Quoted 6 lines
(quoted diff) +6
-0+} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start(void) +{ + struct ccsr_gur *gur = (struct ccsr_gur*)CONFIG_SYS_FSL_GUTS_ADDR;
Quoted 25 lines
(quoted diff) +21
-0+ u32 cfg; + int rc = -1; + + cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; + + if (cfg != 0x30 && cfg != 0x70) { + printf("SATA disabled: serdes protocol doesn't support\n"); + return rc; + } + + rc = ahci_init((void __iomem *)AHCI_BASE_ADDR); + if (rc) + return rc; + + scsi_scan(0); + + return 0; +} +#endif + #ifdef CONFIG_LS102XA_NS_ACCESS static struct csu_ns_dev ns_dev[] = { { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },Review int board_early_init_f(void) · line 378
Quoted 4 lines
(quoted diff) +1
-0@@ -327,6 +375,8 @@ int board_early_init_f(void) fsl_dp_disable_console(); #endif + ls1021a_sata_init();Is it OK to run this init regardless SerDes protocol?
Quoted 35 lines
(quoted diff) +12
-0+ return 0; }@@ -388,6 +438,17 @@ void board_init_f(ulong dummy) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls1021a_sata_start(); +#endif + + return 0; +} +#endif + void config_etseccm_source(int etsec_gtx_125_mux) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
a/board/freescale/ls1021atwr/ls1021atwr.cb/board/freescale/ls1021atwr/ls1021atwr.c
index b7458a9..6a964c3 100644board/freescale/ls1021atwr/ls1021atwr.c +2
-0@@ -22,6 +22,8 @@#include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" board/freescale/ls1021atwr/ls1021atwr.c struct cpld_data { · line 182
Quoted 8 lines
board/freescale/ls1021atwr/ls1021atwr.c +5
-0@@ -173,6 +175,52 @@ struct cpld_data {u8 rev2;/* Reserved */ }; +static void ls1021a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR ; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be in board file.
York
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
On ls2085 we had a soc file which can put all the soc specific function in it. But on ls1021, there is no such file unless I create one for SATA.
Please see the patch I first submit. Do you prefer this way?
http://patchwork.ozlabs.org/patch/497983/
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 12:39 PM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
That's exactly what I mean. It is ls1021 soc erratum, not board specific.
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 21:36 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>, Kushwaha Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Yes, this is a ls1021 specific errata.
Maybe we need to name the errata micro better.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:57 AM
To: Tang Yuantian-B29983
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: Re: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Yuantian,
In your patch, you are using CONFIG_SYS_FSL_ERRATUM_A008407. Are you saying this is a board erratum, not an SoC erratum?
York
________________________________
From: Tang Yuantian-B29983
Sent: Tuesday, August 18, 2015 8:47 PM
To: Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
I don't understand. This workaround is our board specific and actually ls1021 specific. I thought about merging all the LS SATA initialization into one file, but that didn't reduce many code. So I add this one by one board.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:38 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
The soc workarounds belongs to soc file, not board file, so you don't have to copy the code to every board. Our boards are not the only boards with this SoC.
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 20:34 (GMT-08:00)
To: Sun York-R58495
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Sorry for top posting, replying from my phone.
Please use macros instead of numbers. It's still better than putting magic numbers in the code. And please move it out of board files.
Yuantian:
Please move what out of board files, these magic numbers or sata init function?
Regards,
Yuantian
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun York-R58495
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Quoted 12 lines
Review
Quoted 3 lines
(quoted diff) +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 + unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;#endif
Review
Quoted 7 lines
(quoted diff) +7
-0+ + out_le32(&ccsr_ahci->ppcfg, 0xa003fffe); + out_le32(&ccsr_ahci->pp2c, 0x28183411); + out_le32(&ccsr_ahci->pp3c, 0x0e081004); + out_le32(&ccsr_ahci->pp4c, 0x00480811); + out_le32(&ccsr_ahci->pp5c, 0x192c96a4); + out_le32(&ccsr_ahci->ptc, 0x08000025);
Quoted 2 lines
What are these numbers?
I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for sata. They are gotten from validation team. Their meanings are documented in RM. Is it necessary to re-explain bit by bit again?
Same reasons for ls2085.
Regards,
Yuantian
Quoted 94 lines
Review
Quoted 4 lines
(quoted diff) +4
-0+ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 + out_le32(ecc_reg, 0x00020000); +#endifSame here.
Review
Quoted 6 lines
(quoted diff) +6
-0+} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start(void) +{ + struct ccsr_gur *gur = (struct ccsr_gur*)CONFIG_SYS_FSL_GUTS_ADDR;
Quoted 25 lines
(quoted diff) +21
-0+ u32 cfg; + int rc = -1; + + cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; + + if (cfg != 0x30 && cfg != 0x70) { + printf("SATA disabled: serdes protocol doesn't support\n"); + return rc; + } + + rc = ahci_init((void __iomem *)AHCI_BASE_ADDR); + if (rc) + return rc; + + scsi_scan(0); + + return 0; +} +#endif + #ifdef CONFIG_LS102XA_NS_ACCESS static struct csu_ns_dev ns_dev[] = { { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },Review int board_early_init_f(void) · line 378
Quoted 4 lines
(quoted diff) +1
-0@@ -327,6 +375,8 @@ int board_early_init_f(void) fsl_dp_disable_console(); #endif + ls1021a_sata_init();Is it OK to run this init regardless SerDes protocol?
Quoted 35 lines
(quoted diff) +12
-0+ return 0; }@@ -388,6 +438,17 @@ void board_init_f(ulong dummy) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls1021a_sata_start(); +#endif + + return 0; +} +#endif + void config_etseccm_source(int etsec_gtx_125_mux) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
a/board/freescale/ls1021atwr/ls1021atwr.cb/board/freescale/ls1021atwr/ls1021atwr.c
index b7458a9..6a964c3 100644board/freescale/ls1021atwr/ls1021atwr.c +2
-0@@ -22,6 +22,8 @@#include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" board/freescale/ls1021atwr/ls1021atwr.c struct cpld_data { · line 182
Quoted 8 lines
board/freescale/ls1021atwr/ls1021atwr.c +5
-0@@ -173,6 +175,52 @@ struct cpld_data {u8 rev2;/* Reserved */ }; +static void ls1021a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR ; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be in board file.
York
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
No, the old patch still use board files. Even it is a common board file, it is not common for other than freescale boards.
ls2085 didn't have an soc file to start with. When you have a situation like this, you create one. I will be out in next few days, please work with Prabhakar.
York
________________________________
From: Tang Yuantian-B29983
Sent: Tuesday, August 18, 2015 9:43 PM
To: Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
On ls2085 we had a soc file which can put all the soc specific function in it.
But on ls1021, there is no such file unless I create one for SATA.
Please see the patch I first submit. Do you prefer this way?
http://patchwork.ozlabs.org/patch/497983/
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 12:39 PM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
That's exactly what I mean. It is ls1021 soc erratum, not board specific.
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 21:36 (GMT-08:00)
To: Sun York-R58495
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Yes, this is a ls1021 specific errata.
Maybe we need to name the errata micro better.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:57 AM
To: Tang Yuantian-B29983
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: Re: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Yuantian,
In your patch, you are using CONFIG_SYS_FSL_ERRATUM_A008407. Are you saying this is a board erratum, not an SoC erratum?
York
________________________________
From: Tang Yuantian-B29983
Sent: Tuesday, August 18, 2015 8:47 PM
To: Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
I don?t understand. This workaround is our board specific and actually ls1021 specific. I thought about merging all the LS SATA initialization into one file, but that didn?t reduce many code. So I add this one by one board.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:38 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
The soc workarounds belongs to soc file, not board file, so you don't have to copy the code to every board. Our boards are not the only boards with this SoC.
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 20:34 (GMT-08:00)
To: Sun York-R58495
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Sorry for top posting, replying from my phone.
Please use macros instead of numbers. It's still better than putting magic numbers in the code. And please move it out of board files.
Yuantian:
Please move what out of board files, these magic numbers or sata init function?
Regards,
Yuantian
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun York-R58495
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Quoted 12 lines
Review
Quoted 3 lines
(quoted diff) +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 + unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;#endif
Review
Quoted 7 lines
(quoted diff) +7
-0+ + out_le32(&ccsr_ahci->ppcfg, 0xa003fffe); + out_le32(&ccsr_ahci->pp2c, 0x28183411); + out_le32(&ccsr_ahci->pp3c, 0x0e081004); + out_le32(&ccsr_ahci->pp4c, 0x00480811); + out_le32(&ccsr_ahci->pp5c, 0x192c96a4); + out_le32(&ccsr_ahci->ptc, 0x08000025);
Quoted 2 lines
What are these numbers?
I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for sata. They are gotten from validation team. Their meanings are documented in RM. Is it necessary to re-explain bit by bit again?
Same reasons for ls2085.
Regards,
Yuantian
Quoted 94 lines
Review
Quoted 4 lines
(quoted diff) +4
-0+ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 + out_le32(ecc_reg, 0x00020000); +#endifSame here.
Review
Quoted 6 lines
(quoted diff) +6
-0+} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start(void) +{ + struct ccsr_gur *gur = (struct ccsr_gur*)CONFIG_SYS_FSL_GUTS_ADDR;
Quoted 25 lines
(quoted diff) +21
-0+ u32 cfg; + int rc = -1; + + cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; + + if (cfg != 0x30 && cfg != 0x70) { + printf("SATA disabled: serdes protocol doesn't support\n"); + return rc; + } + + rc = ahci_init((void __iomem *)AHCI_BASE_ADDR); + if (rc) + return rc; + + scsi_scan(0); + + return 0; +} +#endif + #ifdef CONFIG_LS102XA_NS_ACCESS static struct csu_ns_dev ns_dev[] = { { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },Review int board_early_init_f(void) · line 378
Quoted 4 lines
(quoted diff) +1
-0@@ -327,6 +375,8 @@ int board_early_init_f(void) fsl_dp_disable_console(); #endif + ls1021a_sata_init();Is it OK to run this init regardless SerDes protocol?
Quoted 35 lines
(quoted diff) +12
-0+ return 0; }@@ -388,6 +438,17 @@ void board_init_f(ulong dummy) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls1021a_sata_start(); +#endif + + return 0; +} +#endif + void config_etseccm_source(int etsec_gtx_125_mux) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
a/board/freescale/ls1021atwr/ls1021atwr.cb/board/freescale/ls1021atwr/ls1021atwr.c
index b7458a9..6a964c3 100644board/freescale/ls1021atwr/ls1021atwr.c +2
-0@@ -22,6 +22,8 @@#include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" board/freescale/ls1021atwr/ls1021atwr.c struct cpld_data { · line 182
Quoted 8 lines
board/freescale/ls1021atwr/ls1021atwr.c +5
-0@@ -173,6 +175,52 @@ struct cpld_data {u8 rev2;/* Reserved */ }; +static void ls1021a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR ; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be in board file.
York
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
OK, I will work with Prabhakar on this.
This is freescale specific settings and workaround. Other boards out of freescale don't use this.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 12:47 PM
To: Tang Yuantian-B29983
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: Re: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
No, the old patch still use board files. Even it is a common board file, it is not common for other than freescale boards.
ls2085 didn't have an soc file to start with. When you have a situation like this, you create one. I will be out in next few days, please work with Prabhakar.
York
________________________________
From: Tang Yuantian-B29983
Sent: Tuesday, August 18, 2015 9:43 PM
To: Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
On ls2085 we had a soc file which can put all the soc specific function in it.
But on ls1021, there is no such file unless I create one for SATA.
Please see the patch I first submit. Do you prefer this way?
http://patchwork.ozlabs.org/patch/497983/
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 12:39 PM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
That's exactly what I mean. It is ls1021 soc erratum, not board specific.
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 21:36 (GMT-08:00)
To: Sun York-R58495
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Yes, this is a ls1021 specific errata.
Maybe we need to name the errata micro better.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:57 AM
To: Tang Yuantian-B29983
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: Re: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Yuantian,
In your patch, you are using CONFIG_SYS_FSL_ERRATUM_A008407. Are you saying this is a board erratum, not an SoC erratum?
York
________________________________
From: Tang Yuantian-B29983
Sent: Tuesday, August 18, 2015 8:47 PM
To: Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
I don't understand. This workaround is our board specific and actually ls1021 specific. I thought about merging all the LS SATA initialization into one file, but that didn't reduce many code. So I add this one by one board.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:38 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
The soc workarounds belongs to soc file, not board file, so you don't have to copy the code to every board. Our boards are not the only boards with this SoC.
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 20:34 (GMT-08:00)
To: Sun York-R58495
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de<mailto:[email protected]>; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Sorry for top posting, replying from my phone.
Please use macros instead of numbers. It's still better than putting magic numbers in the code. And please move it out of board files.
Yuantian:
Please move what out of board files, these magic numbers or sata init function?
Regards,
Yuantian
York
-------- Original message --------
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun York-R58495
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Quoted 12 lines
Review
Quoted 3 lines
(quoted diff) +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 + unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;#endif
Review
Quoted 7 lines
(quoted diff) +7
-0+ + out_le32(&ccsr_ahci->ppcfg, 0xa003fffe); + out_le32(&ccsr_ahci->pp2c, 0x28183411); + out_le32(&ccsr_ahci->pp3c, 0x0e081004); + out_le32(&ccsr_ahci->pp4c, 0x00480811); + out_le32(&ccsr_ahci->pp5c, 0x192c96a4); + out_le32(&ccsr_ahci->ptc, 0x08000025);
Quoted 2 lines
What are these numbers?
I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for sata. They are gotten from validation team. Their meanings are documented in RM. Is it necessary to re-explain bit by bit again?
Same reasons for ls2085.
Regards,
Yuantian
Quoted 94 lines
Review
Quoted 4 lines
(quoted diff) +4
-0+ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 + out_le32(ecc_reg, 0x00020000); +#endifSame here.
Review
Quoted 6 lines
(quoted diff) +6
-0+} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start(void) +{ + struct ccsr_gur *gur = (struct ccsr_gur*)CONFIG_SYS_FSL_GUTS_ADDR;
Quoted 25 lines
(quoted diff) +21
-0+ u32 cfg; + int rc = -1; + + cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; + + if (cfg != 0x30 && cfg != 0x70) { + printf("SATA disabled: serdes protocol doesn't support\n"); + return rc; + } + + rc = ahci_init((void __iomem *)AHCI_BASE_ADDR); + if (rc) + return rc; + + scsi_scan(0); + + return 0; +} +#endif + #ifdef CONFIG_LS102XA_NS_ACCESS static struct csu_ns_dev ns_dev[] = { { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },Review int board_early_init_f(void) · line 378
Quoted 4 lines
(quoted diff) +1
-0@@ -327,6 +375,8 @@ int board_early_init_f(void) fsl_dp_disable_console(); #endif + ls1021a_sata_init();Is it OK to run this init regardless SerDes protocol?
Quoted 35 lines
(quoted diff) +12
-0+ return 0; }@@ -388,6 +438,17 @@ void board_init_f(ulong dummy) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls1021a_sata_start(); +#endif + + return 0; +} +#endif + void config_etseccm_source(int etsec_gtx_125_mux) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
a/board/freescale/ls1021atwr/ls1021atwr.cb/board/freescale/ls1021atwr/ls1021atwr.c
index b7458a9..6a964c3 100644board/freescale/ls1021atwr/ls1021atwr.c +2
-0@@ -22,6 +22,8 @@#include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" board/freescale/ls1021atwr/ls1021atwr.c struct cpld_data { · line 182
Quoted 8 lines
board/freescale/ls1021atwr/ls1021atwr.c +5
-0@@ -173,6 +175,52 @@ struct cpld_data {u8 rev2;/* Reserved */ }; +static void ls1021a_sata_init (void ) +{ +struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR ; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be in board file.
York
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
In reply to Yuantian TangQuoted 20 lines
-----Original Message-----
From: Tang Yuantian-B29983
Sent: Wednesday, August 19, 2015 8:01 AM
To: Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardQuoted 12 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 65
Quoted 3 lines
board/freescale/ls1021aqds/ls1021aqds.c +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 +unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR ;#endif
Quoted 7 lines
board/freescale/ls1021aqds/ls1021aqds.c +7
-0+ +out_le32 (&ccsr_ahci->ppcfg,0xa003fffe ); +out_le32 (&ccsr_ahci->pp2c,0x28183411 ); +out_le32 (&ccsr_ahci->pp3c,0x0e081004 ); +out_le32 (&ccsr_ahci->pp4c,0x00480811 ); +out_le32 (&ccsr_ahci->pp5c,0x192c96a4 ); +out_le32 (&ccsr_ahci->ptc,0x08000025 );
It looks to be SoC specific configuration. It should be in soc files not in board files.
--prabhakar
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
Quoted 32 lines
-----Original Message-----
From: Kushwaha Prabhakar-B32579
Sent: Wednesday, August 19, 2015 12:15 PM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardQuoted 5 lines
-----Original Message-----
From: Tang Yuantian-B29983
Sent: Wednesday, August 19, 2015 8:01 AM
To: Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Quoted 1 line
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr
board
Quoted 5 lines
Quoted 5 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 65
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 +unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR ;#endif
Quoted 8 lines
Quoted 8 lines
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 73
Quoted 7 lines
board/freescale/ls1021aqds/ls1021aqds.c +7
-0+ +out_le32 (&ccsr_ahci->ppcfg,0xa003fffe ); +out_le32 (&ccsr_ahci->pp2c,0x28183411 ); +out_le32 (&ccsr_ahci->pp3c,0x0e081004 ); +out_le32 (&ccsr_ahci->pp4c,0x00480811 ); +out_le32 (&ccsr_ahci->pp5c,0x192c96a4 ); +out_le32 (&ccsr_ahci->ptc,0x08000025 );
Quoted 3 lines
It looks to be SoC specific configuration. It should be in soc files not in board files.
On other LS platforms we only need to set one register which is out_le32(&ccsr_ahci->ppcfg, 0xa003fffe). There are did much same settings about sata between LS platforms.
I thought about merging all the LS sata initialization together.
Please see the patch:
http://patchwork.ozlabs.org/patch/497983/
But I didn't see much benefit this way. So I send the sata patch one platform to another.
Regards,
Yuantian
Quoted 1 line
--prabhakar
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
Regards,
Prabhakar
Quoted 44 lines
-----Original Message-----
From: Tang Yuantian-B29983
Sent: Wednesday, August 19, 2015 10:17 AM
To: Kushwaha Prabhakar-B32579; Sun York-R58495
Cc: u-boot at lists.denx.de; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardQuoted 14 lines
-----Original Message-----
From: Kushwaha Prabhakar-B32579
Sent: Wednesday, August 19, 2015 12:15 PM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardQuoted 5 lines
-----Original Message-----
From: Tang Yuantian-B29983
Sent: Wednesday, August 19, 2015 8:01 AM
To: Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-Quoted 7 lines
B18965
Quoted 1 line
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr
board
Quoted 4 lines
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c enum {
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 + unsigned int __iomem *ecc_reg = (void*)SATA_ECC_REG_ADDR;
Quoted 10 lines
Quoted 9 lines
Quoted 9 lines
#endif
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 73
Quoted 7 lines
board/freescale/ls1021aqds/ls1021aqds.c +7
-0+ +out_le32 (&ccsr_ahci->ppcfg,0xa003fffe ); +out_le32 (&ccsr_ahci->pp2c,0x28183411 ); +out_le32 (&ccsr_ahci->pp3c,0x0e081004 ); +out_le32 (&ccsr_ahci->pp4c,0x00480811 ); +out_le32 (&ccsr_ahci->pp5c,0x192c96a4 ); +out_le32 (&ccsr_ahci->ptc,0x08000025 );Quoted 3 lines
It looks to be SoC specific configuration. It should be in soc files not in board files.
Quoted 9 lines
On other LS platforms we only need to set one register which is
out_le32(&ccsr_ahci->ppcfg, 0xa003fffe).
There are did much same settings about sata between LS platforms. I thought about merging all the LS sata initialization together. Please see the patch:
http://patchwork.ozlabs.org/patch/497983/
But I didn't see much benefit this way. So I send the sata patch one platform to another.
Problem is not with solution. Problem is with the place.
This SoC errata fix but in board file. It should be in arch/arm/cpu/armv7
--prabhakar
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
Quoted 71 lines
-----Original Message-----
From: Kushwaha Prabhakar-B32579
Sent: Wednesday, August 19, 2015 8:54 PM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardRegards,
PrabhakarQuoted 46 lines
-----Original Message-----
From: Tang Yuantian-B29983
Sent: Wednesday, August 19, 2015 10:17 AM
To: Kushwaha Prabhakar-B32579; Sun York-R58495
Cc: u-boot at lists.denx.de; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardQuoted 14 lines
-----Original Message-----
From: Kushwaha Prabhakar-B32579
Sent: Wednesday, August 19, 2015 12:15 PM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardQuoted 5 lines
-----Original Message-----
From: Tang Yuantian-B29983
Sent: Wednesday, August 19, 2015 8:01 AM
To: Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-Quoted 8 lines
B18965
Quoted 2 lines
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr
board
Quoted 4 lines
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c enum {
Quoted 4 lines
board/freescale/ls1021aqds/ls1021aqds.c +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 + unsigned int __iomem *ecc_reg = (void*)SATA_ECC_REG_ADDR;
Quoted 10 lines
Quoted 9 lines
Quoted 9 lines
#endif
board/freescale/ls1021aqds/ls1021aqds.c enum { · line 73
Quoted 7 lines
board/freescale/ls1021aqds/ls1021aqds.c +7
-0+ +out_le32 (&ccsr_ahci->ppcfg,0xa003fffe ); +out_le32 (&ccsr_ahci->pp2c,0x28183411 ); +out_le32 (&ccsr_ahci->pp3c,0x0e081004 ); +out_le32 (&ccsr_ahci->pp4c,0x00480811 ); +out_le32 (&ccsr_ahci->pp5c,0x192c96a4 ); +out_le32 (&ccsr_ahci->ptc,0x08000025 );Quoted 3 lines
It looks to be SoC specific configuration. It should be in soc files not in board files.
Quoted 9 lines
On other LS platforms we only need to set one register which is
out_le32(&ccsr_ahci->ppcfg, 0xa003fffe).
There are did much same settings about sata between LS platforms. I thought about merging all the LS sata initialization together. Please see the patch:
http://patchwork.ozlabs.org/patch/497983/
But I didn't see much benefit this way. So I send the sata patch one platform to another.
Quoted 3 lines
Problem is not with solution. Problem is with the place.
This SoC errata fix but in board file. It should be inarch/arm/cpu/armv7
OK, I will put it under arch/arm/cpu/armv7/, just like what I did in SDK.
Regards,
Yuantian
Quoted 1 line
--prabhakar
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
Quoted 80 lines
-----Original Message-----
From: Tang Yuantian-B29983
Sent: Thursday, August 20, 2015 6:52 AM
To: Kushwaha Prabhakar-B32579 <[email protected]>; Sun York- R58495 <[email protected]>
Cc: u-boot at lists.denx.de; Wang Huan-B18965 <[email protected]>
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardQuoted 70 lines
-----Original Message-----
From: Kushwaha Prabhakar-B32579
Sent: Wednesday, August 19, 2015 8:54 PM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardRegards,
PrabhakarQuoted 55 lines
-----Original Message-----
From: Tang Yuantian-B29983
Sent: Wednesday, August 19, 2015 10:17 AM
To: Kushwaha Prabhakar-B32579; Sun York-R58495
Cc: u-boot at lists.denx.de; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardQuoted 14 lines
-----Original Message-----
From: Kushwaha Prabhakar-B32579
Sent: Wednesday, August 19, 2015 12:15 PM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardQuoted 5 lines
-----Original Message-----
From: Tang Yuantian-B29983
Sent: Wednesday, August 19, 2015 8:01 AM
To: Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-Quoted 8 lines
B18965
Quoted 2 lines
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr
board
Quoted 4 lines
Quoted 4 lines
Review
Quoted 4 lines
(quoted diff) +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 + unsigned int __iomem *ecc_reg = (void*)SATA_ECC_REG_ADDR;
Quoted 10 lines
Quoted 9 lines
Quoted 9 lines
#endif
Review
Quoted 7 lines
(quoted diff) +7
-0+ + out_le32(&ccsr_ahci->ppcfg, 0xa003fffe); + out_le32(&ccsr_ahci->pp2c, 0x28183411); + out_le32(&ccsr_ahci->pp3c, 0x0e081004); + out_le32(&ccsr_ahci->pp4c, 0x00480811); + out_le32(&ccsr_ahci->pp5c, 0x192c96a4); + out_le32(&ccsr_ahci->ptc, 0x08000025);Quoted 3 lines
It looks to be SoC specific configuration. It should be in soc files not in board files.
On other LS platforms we only need to set one register which is
out_le32(&ccsr_ahci->ppcfg, 0xa003fffe).
There are did much same settings about sata between LS platforms. I thought about merging all the LS sata initialization together. Please see the patch:
http://patchwork.ozlabs.org/patch/497983/
But I didn't see much benefit this way. So I send the sata patch one platform to another.
Quoted 9 lines
Quoted 4 lines
Problem is not with solution. Problem is with the place. This SoC errata fix but in board file. It should be in
arch/arm/cpu/armv7OK, I will put it under
arch/arm/cpu/armv7/, just like what I did in SDK.Regards,
Yuantian
This workaround can also go in FSL-SATA driver.
--prabhakar
PATCH v2 1/1 arm/ls1021a: Add sata support on qds and twr board
Quoted 96 lines
-----Original Message-----
From: Kushwaha Prabhakar-B32579
Sent: Thursday, August 20, 2015 9:33 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardQuoted 6 lines
-----Original Message-----
From: Tang Yuantian-B29983
Sent: Thursday, August 20, 2015 6:52 AM
To: Kushwaha Prabhakar-B32579 <[email protected]>; Sun York- R58495 <[email protected]>
Cc: u-boot at lists.denx.de; Wang Huan-B18965Quoted 80 lines
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Quoted 75 lines
-----Original Message-----
From: Kushwaha Prabhakar-B32579
Sent: Wednesday, August 19, 2015 8:54 PM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardRegards,
PrabhakarQuoted 47 lines
-----Original Message-----
From: Tang Yuantian-B29983
Sent: Wednesday, August 19, 2015 10:17 AM
To: Kushwaha Prabhakar-B32579; Sun York-R58495
Cc: u-boot at lists.denx.de; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardQuoted 15 lines
-----Original Message-----
From: Kushwaha Prabhakar-B32579
Sent: Wednesday, August 19, 2015 12:15 PM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot at lists.denx.de; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr boardQuoted 6 lines
-----Original Message-----
From: Tang Yuantian-B29983
Sent: Wednesday, August 19, 2015 8:01 AM
To: Sun York-R58495
Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-Quoted 8 lines
B18965
Quoted 2 lines
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr
board
Quoted 4 lines
Quoted 4 lines
Review
Quoted 4 lines
(quoted diff) +3
-0+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 + unsigned int __iomem *ecc_reg = (void*)SATA_ECC_REG_ADDR;
Quoted 10 lines
Quoted 9 lines
Quoted 9 lines
#endif
Review
Quoted 7 lines
(quoted diff) +7
-0+ + out_le32(&ccsr_ahci->ppcfg, 0xa003fffe); + out_le32(&ccsr_ahci->pp2c, 0x28183411); + out_le32(&ccsr_ahci->pp3c, 0x0e081004); + out_le32(&ccsr_ahci->pp4c, 0x00480811); + out_le32(&ccsr_ahci->pp5c, 0x192c96a4); + out_le32(&ccsr_ahci->ptc, 0x08000025);Quoted 3 lines
It looks to be SoC specific configuration. It should be in soc files not in board files.
Quoted 9 lines
On other LS platforms we only need to set one register which is
out_le32(&ccsr_ahci->ppcfg, 0xa003fffe).
There are did much same settings about sata between LS platforms. I thought about merging all the LS sata initialization together. Please see the patch:
http://patchwork.ozlabs.org/patch/497983/
But I didn't see much benefit this way. So I send the sata patch one platform to another.Problem is not with solution. Problem is with the place. This SoC errata fix but in board file. It should be in
arch/arm/cpu/armv7
Quoted 8 lines
Quoted 5 lines
OK, I will put it under
arch/arm/cpu/armv7/, just like what I did in SDK.Regards,
YuantianThis workaround can also go in FSL-SATA driver.
There is no fsl-sata driver for ls sata. This patch just added the stub before ahci driver is called. So I will put this workaround and sata configuration together.
If there are any impropriate please inform me.
Regards,
Yuantian
Quoted 1 line
--prabhakar