armv7/fsl-ls102xa: Workaround for DDR erratum A008514
PATCH 1/3 armv7/fsl-ls102xa: Workaround for DDR erratum A008514
Affects: DDR
Description: Memory controller performance is not optimal with default internal target queue register values.
Impact: Memory controller performance is not optimal.
Workaround: Write a value of 63b2_0002h to address: 157_020Ch.
--- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- board/freescale/ls1021aqds/ls1021aqds.c | 10 ++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 10 ++++++++++ 3 files changed, 21 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +1 -1
@@ -221,7 +221,7 @@ struct ccsr_scfg {u32 scfgrevcr;u32 coresrencr;u32 pex2pmrdsr; -u32 ddrc1cr; +u32 eddrtqcfg;u32 ddrc2cr;u32 ddrc3cr;u32 ddrc4cr;
board/freescale/ls1021aqds/ls1021aqds.c +10 -0
@@ -299,6 +299,16 @@ int board_early_init_f(void)out_be32 (&scfg->endiancr,SCFG_ENDIANCR_LE );/* +* Memory controller require a register write before being enabled. +* Affects: DDR +* Register: EDDRTQCFG +* Description: Memory controller performance is not optimal with +* default internal target queue register values. +* Workaround: Write a value of 63b2_0002h to address: 157_020Ch. +*/ +out_be32 (&scfg->eddrtqcfg,0x63b20002 ); + +/* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */
board/freescale/ls1021atwr/ls1021atwr.c +10 -0
@@ -501,6 +501,16 @@ int board_early_init_f(void)out_be32 (&scfg->endiancr,SCFG_ENDIANCR_LE );/* +* Memory controller require a register write before being enabled. +* Affects: DDR +* Register: EDDRTQCFG +* Description: Memory controller performance is not optimal with +* default internal target queue register values. +* Workaround: Write a value of 63b2_0002h to address: 157_020Ch. +*/ +out_be32 (&scfg->eddrtqcfg,0x63b20002 ); + +/* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */
Signature · 1 line
2.1.0.27.g96db324
PATCH 2/3 LS102XA:workaround:disable priorities within DDR
EDDRTQCFG Registers are Integration Strap values which controls performance parameters for DDR Controller.
The bit 25 is used to disable priorities within DDR since DDR are connected backwards on silicon Rev2.0.
--- board/freescale/ls1021aqds/ls1021aqds.c | 13 ++++++++++++- board/freescale/ls1021atwr/ls1021atwr.c | 13 ++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-)
board/freescale/ls1021aqds/ls1021aqds.c +12 -1
@@ -277,7 +277,7 @@ int board_early_init_f(void) {struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR ;struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR ; -unsigned int major; +unsigned int major, reg;#ifdef CONFIG_TSEC_ENET out_be32 (&scfg->etsecdmamcr,SCFG_ETSECDMAMCR_LE_BD_FR );
@@ -309,6 +309,17 @@ int board_early_init_f(void)out_be32 (&scfg->eddrtqcfg,0x63b20002 );/* +* EDDRTQCFG Registers are Integration Strap values which controls +* performance parameters for DDR Controller. +* The bit 25(0x40) is used for disable priorities within DDR. +* This is a workaround because of the DDR are connected backwards +* on Rev2.0. +*/ + reg =in_be32 (&scfg->eddrtqcfg); + reg |=0x40 ; +out_be32 (&scfg->eddrtqcfg, reg); + +/* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */
board/freescale/ls1021atwr/ls1021atwr.c +12 -1
@@ -478,7 +478,7 @@ int board_early_init_f(void) {struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR ;struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR ; -unsigned int major; +unsigned int major, reg;#ifdef CONFIG_TSEC_ENET out_be32 (&scfg->etsecdmamcr,SCFG_ETSECDMAMCR_LE_BD_FR );
@@ -511,6 +511,17 @@ int board_early_init_f(void)out_be32 (&scfg->eddrtqcfg,0x63b20002 );/* +* EDDRTQCFG Registers are Integration Strap values which controls +* performance parameters for DDR Controller. +* The bit 25(0x40) is used for disable priorities within DDR. +* This is a workaround because of the DDR are connected backwards +* on Rev2.0. +*/ + reg =in_be32 (&scfg->eddrtqcfg); + reg |=0x40 ; +out_be32 (&scfg->eddrtqcfg, reg); + +/* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */
Signature · 1 line
2.1.0.27.g96db324
PATCH 2/3 LS102XA:workaround:disable priorities within DDR
Hi Yuan
Quoted 26 lines · Yuan Yao
EDDRTQCFG Registers are Integration Strap values which controls performance parameters for DDR Controller.
The bit 25 is used to disable priorities within DDR since DDR are connected backwards on silicon Rev2.0.
Signed-off-by Yuan Yao <[email protected]>--- board/freescale/ls1021aqds/ls1021aqds.c | 13 ++++++++++++- board/freescale/ls1021atwr/ls1021atwr.c | 13 ++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-)board/freescale/ls1021aqds/ls1021aqds.c +1
-1@@ -277,7 +277,7 @@ int board_early_init_f(void) {struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR ;struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR ; -unsigned int major; +unsigned int major, reg;#ifdef CONFIG_TSEC_ENET out_be32 (&scfg->etsecdmamcr,SCFG_ETSECDMAMCR_LE_BD_FR );
board/freescale/ls1021aqds/ls1021aqds.c int board_early_init_f(void) · line 313
Quoted 5 lines
board/freescale/ls1021aqds/ls1021aqds.c +2
-0@@ -309,6 +309,17 @@ int board_early_init_f(void)out_be32 (&scfg->eddrtqcfg,0x63b20002 );/* +* EDDRTQCFG Registers are Integration Strap values which controls +* performance parameters for DDR Controller.
Would this comment not be better placed in your patch 1/2. Please
see my comments there.
Quoted 34 lines
board/freescale/ls1021aqds/ls1021aqds.c +9
-0+* The bit 25(0x40) is used for disable priorities within DDR. +* This is a workaround because of the DDR are connected backwards +* on Rev2.0. +*/ + reg =in_be32 (&scfg->eddrtqcfg); + reg |=0x40 ; +out_be32 (&scfg->eddrtqcfg, reg); + +/* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */ board/freescale/ls1021atwr/ls1021atwr.c +5
-1@@ -478,7 +478,7 @@ int board_early_init_f(void) {struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR ;struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR ; -unsigned int major; +unsigned int major, reg;#ifdef CONFIG_TSEC_ENET out_be32 (&scfg->etsecdmamcr,SCFG_ETSECDMAMCR_LE_BD_FR );@@ -511,6 +511,17 @@ int board_early_init_f(void)out_be32 (&scfg->eddrtqcfg,0x63b20002 );/* +* EDDRTQCFG Registers are Integration Strap values which controls +* performance parameters for DDR Controller. +* The bit 25(0x40) is used for disable priorities within DDR. +* This is a workaround because of the DDR are connected backwards
board/freescale/ls1021atwr/ls1021atwr.c int board_early_init_f(void) · line 527
Quoted 10 lines
board/freescale/ls1021atwr/ls1021atwr.c +7
-0+* on Rev2.0. +*/ + reg =in_be32 (&scfg->eddrtqcfg); + reg |=0x40 ; +out_be32 (&scfg->eddrtqcfg, reg); + +/* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */
Regards
Sinan Akman
PATCH 2/3 LS102XA:workaround:disable priorities within DDR
In reply to Yuan YaoQuoted 11 lines · Yuan Yao
EDDRTQCFG Registers are Integration Strap values which controls performance parameters for DDR Controller.
The bit 25 is used to disable priorities within DDR since DDR are connected backwards on silicon Rev2.0.
Signed-off-by Yuan Yao <[email protected]>--- board/freescale/ls1021aqds/ls1021aqds.c | 13 ++++++++++++- board/freescale/ls1021atwr/ls1021atwr.c | 13 ++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-)
Yuan,
SoC erratum workaround shouldn't be put into board file.
York
PATCH 3/3 ls102xa: Enable snoop and DVM message requests.
In reply to Yuan YaoFor LS1021A Rev2.0 have already fixed the snoop silicon issue, So enable snoop requests and DVM message requests for all the slave insterfaces.
--- board/freescale/ls1021aqds/ls1021aqds.c | 8 +++++++- board/freescale/ls1021atwr/ls1021atwr.c | 8 +++++++- 2 files changed, 14 insertions(+), 2 deletions(-)
board/freescale/ls1021aqds/ls1021aqds.c +7 -1
@@ -321,8 +321,14 @@ int board_early_init_f(void)/* * Enable snoop requests and DVM message requests for -* Slave insterface S4 (A7 core cluster) +* All the slave insterfaces. */ +out_le32 (&cci->slave[0 ].snoop_ctrl, +CCI400_DVM_MESSAGE_REQ_EN |CCI400_SNOOP_REQ_EN ); +out_le32 (&cci->slave[1 ].snoop_ctrl, +CCI400_DVM_MESSAGE_REQ_EN |CCI400_SNOOP_REQ_EN ); +out_le32 (&cci->slave[2 ].snoop_ctrl, +CCI400_DVM_MESSAGE_REQ_EN |CCI400_SNOOP_REQ_EN );out_le32 (&cci->slave[4 ].snoop_ctrl,CCI400_DVM_MESSAGE_REQ_EN |CCI400_SNOOP_REQ_EN );
board/freescale/ls1021atwr/ls1021atwr.c +7 -1
@@ -523,8 +523,14 @@ int board_early_init_f(void)/* * Enable snoop requests and DVM message requests for -* Slave insterface S4 (A7 core cluster) +* All the slave insterfaces. */ +out_le32 (&cci->slave[0 ].snoop_ctrl, +CCI400_DVM_MESSAGE_REQ_EN |CCI400_SNOOP_REQ_EN ); +out_le32 (&cci->slave[1 ].snoop_ctrl, +CCI400_DVM_MESSAGE_REQ_EN |CCI400_SNOOP_REQ_EN ); +out_le32 (&cci->slave[2 ].snoop_ctrl, +CCI400_DVM_MESSAGE_REQ_EN |CCI400_SNOOP_REQ_EN );out_le32 (&cci->slave[4 ].snoop_ctrl,CCI400_DVM_MESSAGE_REQ_EN |CCI400_SNOOP_REQ_EN );
Signature · 1 line
2.1.0.27.g96db324
PATCH 3/3 ls102xa: Enable snoop and DVM message requests.
Quoted 8 lines · Yuan Yao
For LS1021A Rev2.0 have already fixed the snoop silicon issue, So enable snoop requests and DVM message requests for all the slave insterfaces.
Signed-off-by Yuan Yao <[email protected]>--- board/freescale/ls1021aqds/ls1021aqds.c | 8 +++++++- board/freescale/ls1021atwr/ls1021atwr.c | 8 +++++++- 2 files changed, 14 insertions(+), 2 deletions(-)
Yuan,
Do not put SoC specific code into board file, please.
York
PATCH 1/3 armv7/fsl-ls102xa: Workaround for DDR erratum A008514
In reply to Yuan YaoHi Yuan
Quoted 18 lines · Yuan Yao
Affects: DDR
Description: Memory controller performance is not optimal with default internal target queue register values.
Impact: Memory controller performance is not optimal.
Workaround: Write a value of 63b2_0002h to address: 157_020Ch.Signed-off-by Yuan Yao <[email protected]>--- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- board/freescale/ls1021aqds/ls1021aqds.c | 10 ++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 10 ++++++++++ 3 files changed, 21 insertions(+), 1 deletion(-)arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +0
-0
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h struct ccsr_scfg { · line 224
Quoted 5 lines
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +1
-1@@ -221,7 +221,7 @@ struct ccsr_scfg {u32 scfgrevcr;u32 coresrencr;u32 pex2pmrdsr; -u32 ddrc1cr; +u32 eddrtqcfg;
Is this a simple name change on the register, that ddrc1cr
is not needed/used anywhere else ?
Quoted 9 lines
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +0
-0u32 ddrc2cr;u32 ddrc3cr;u32 ddrc4cr;board/freescale/ls1021aqds/ls1021aqds.c +0
-0@@ -299,6 +299,16 @@ int board_early_init_f(void)out_be32 (&scfg->endiancr,SCFG_ENDIANCR_LE );
board/freescale/ls1021aqds/ls1021aqds.c int board_early_init_f(void) · line 309
Quoted 10 lines
board/freescale/ls1021aqds/ls1021aqds.c +8
-0/* +* Memory controller require a register write before being enabled. +* Affects: DDR +* Register: EDDRTQCFG +* Description: Memory controller performance is not optimal with +* default internal target queue register values. +* Workaround: Write a value of 63b2_0002h to address: 157_020Ch. +*/ +out_be32 (&scfg->eddrtqcfg,0x63b20002 );
Can you perhaps bring the comment from your 2/3 patch that
explains EDDRTQCFG Registers are so that the reader sees it before its first usage.
Also, is it possible to explain here what that magic
value 0x63b20002 corresponds to and perhaps use a #define that explains its function ?
Quoted 11 lines
board/freescale/ls1021aqds/ls1021aqds.c +2
-0+ +/* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */ board/freescale/ls1021atwr/ls1021atwr.c +0
-0@@ -501,6 +501,16 @@ int board_early_init_f(void)out_be32 (&scfg->endiancr,SCFG_ENDIANCR_LE );
board/freescale/ls1021atwr/ls1021atwr.c int board_early_init_f(void) · line 511
Quoted 10 lines
board/freescale/ls1021atwr/ls1021atwr.c +8
-0/* +* Memory controller require a register write before being enabled. +* Affects: DDR +* Register: EDDRTQCFG +* Description: Memory controller performance is not optimal with +* default internal target queue register values. +* Workaround: Write a value of 63b2_0002h to address: 157_020Ch. +*/ +out_be32 (&scfg->eddrtqcfg,0x63b20002 );
Same here.
board/freescale/ls1021atwr/ls1021atwr.c int board_early_init_f(void) · line 516
Quoted 6 lines
board/freescale/ls1021atwr/ls1021atwr.c +2
-0+ +/* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */
Regards
Sinan Akman
PATCH 1/3 armv7/fsl-ls102xa: Workaround for DDR erratum A008514
Hi Sinan,
Thanks for your review.
Please see my comments.
Best Regards,
Yuan Yao
Quoted 25 lines
-----Original Message-----
From: Sinan Akman [mailto:sinan at writeme.com]
Sent: Saturday, August 15, 2015 12:28 AM
To: Yuan Yao-B46683; Sun York-R58495; Wang Huan-B18965
Cc: u-boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH 1/3] armv7/fsl-ls102xa: Workaround for DDR erratum A008514Hi Yuan
Quoted 13 lines · Yuan Yao
Affects: DDR
Description: Memory controller performance is not optimal with default internal target queue register values.
Impact: Memory controller performance is not optimal.
Workaround: Write a value of 63b2_0002h to address: 157_020Ch.Signed-off-by Yuan Yao <[email protected]>--- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- board/freescale/ls1021aqds/ls1021aqds.c | 10 ++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 10 ++++++++++ 3 files changed, 21 insertions(+), 1 deletion(-)
Quoted 14 lines
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h struct ccsr_scfg { · line 224
Quoted 11 lines
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +1
-1@@ -221,7 +221,7 @@ struct ccsr_scfg {u32 scfgrevcr;u32 coresrencr;u32 pex2pmrdsr; -u32 ddrc1cr; +u32 eddrtqcfg;Is this a simple name change on the register, that ddrc1cr is not needed/used
anywhere else ?
[Yuan Yao]
Yes, there is no ddrc1cr in ls102xa, the register on 0x157020c is named eddrtqcfg.
Quoted 24 lines
Quoted 10 lines
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +0
-0u32 ddrc2cr;u32 ddrc3cr;u32 ddrc4cr;board/freescale/ls1021aqds/ls1021aqds.c +0
-0@@ -299,6 +299,16 @@ int board_early_init_f(void)out_be32 (&scfg->endiancr,SCFG_ENDIANCR_LE );board/freescale/ls1021aqds/ls1021aqds.c int board_early_init_f(void) · line 309
Quoted 10 lines
board/freescale/ls1021aqds/ls1021aqds.c +8
-0/* +* Memory controller require a register write before being enabled. +* Affects: DDR +* Register: EDDRTQCFG +* Description: Memory controller performance is not optimal with +* default internal target queue register values. +* Workaround: Write a value of 63b2_0002h to address: 157_020Ch. +*/ +out_be32 (&scfg->eddrtqcfg,0x63b20002 );Can you perhaps bring the comment from your 2/3 patch that explains
EDDRTQCFG Registers are so that the reader sees it before its first usage.
Quoted 2 lines
Also, is it possible to explain here what that magic value
0x63b20002
corresponds to and perhaps use a #define that explains its function ?
[Yuan Yao]
Sorry for here, I also don't sure what's the means of the magic value about 0x63b20002.
Also I'm not suggest to use the #define. Because the 0x63b20002 is just a silicon erratum workaround. I just get the information for the document for silicon erratum. There is no more information for software. The register eddrtqcfg is a reserve register for software. It should not open for developer as silicon team said.
Quoted 13 lines
Quoted 13 lines
board/freescale/ls1021aqds/ls1021aqds.c +2
-0+ +/* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */ board/freescale/ls1021atwr/ls1021atwr.c +0
-0@@ -501,6 +501,16 @@ int board_early_init_f(void)out_be32 (&scfg->endiancr,SCFG_ENDIANCR_LE );
Quoted 11 lines
board/freescale/ls1021atwr/ls1021atwr.c int board_early_init_f(void) · line 511
Quoted 9 lines
board/freescale/ls1021atwr/ls1021atwr.c +8
-0/* +* Memory controller require a register write before being enabled. +* Affects: DDR +* Register: EDDRTQCFG +* Description: Memory controller performance is not optimal with +* default internal target queue register values. +* Workaround: Write a value of 63b2_0002h to address: 157_020Ch. +*/ +out_be32 (&scfg->eddrtqcfg,0x63b20002 );Same here.
[Yuan Yao]
The same here.
Quoted 9 lines
board/freescale/ls1021atwr/ls1021atwr.c int board_early_init_f(void) · line 516
Quoted 6 lines
board/freescale/ls1021atwr/ls1021atwr.c +2
-0+ +/* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */ Regards
Sinan Akman
PATCH 1/3 armv7/fsl-ls102xa: Workaround for DDR erratum A008514
In reply to Yuan YaoQuoted 6 lines · Yuan Yao
Affects: DDR
Description: Memory controller performance is not optimal with default internal target queue register values.
Impact: Memory controller performance is not optimal.
Workaround: Write a value of 63b2_0002h to address: 157_020Ch.
Quoted 6 lines
Signed-off-by Yuan Yao <[email protected]>--- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- board/freescale/ls1021aqds/ls1021aqds.c | 10 ++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 10 ++++++++++ 3 files changed, 21 insertions(+), 1 deletion(-)
Yuan,
This is a wrong place to implement this workaround. It is a SoC erratum, not a board erratum. This erratum applies to both LS1021A and LS2085A. The workaround for LS2085A is already implemented in drivers/ddr/fsl/fsl_ddr_gen4.c. LS1021A supports both DDR3 and DDR4 modes. I started a discussion (CC'ed you) with the designer to clarify if both modes are impacted. If yes, you can add the workaround in drivers/ddr/fsl/arm_ddr_gen3.c, and make sure to add proper address offset in drivers/ddr/fsl/fsl_ddr_gen4.c.
York