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armv8: Add framework for CCN-504 interconnect configuration

PATCH RESEND New Bhupesh Sharma 2 participants 4 messages Jul 1, 2015 – Sep 2, 2015

Subsystems (2)
Arm (32-bit) Arm/actions semi architecture
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Bhupesh Sharma

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PATCH RESEND 1/1 armv8: Add framework for CCN-504 interconnect configuration

This patch adds a minimal framework for Dickens CCN-504 interconnect configuration - mainly related to adding Clusters/cores to snoop/DVM domain and setting QoS of the RN-I ports.

LS2085A platform makes use of these configurations to support better network data performance and to boot a SMP Linux.

Signed-off-by Bhupesh Sharma <[email protected]>
---
 arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S      |   72 +++++++++++++++++++++++---
 arch/arm/include/asm/arch-fsl-lsch3/config.h |   11 ++++
 arch/arm/lib/Makefile                        |    1 +
 arch/arm/lib/ccn504.S                        |   61 ++++++++++++++++++++++
 4 files changed, 138 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/lib/ccn504.S
arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +65 -7
index 018c617..6b19d36 100644
@@ -16,13 +16,71 @@ ENTRY(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 
 	/* Add fully-coherent masters to DVM domain */
-	ldr	x1, =CCI_MN_BASE
-	ldr	x2, [x1, #CCI_MN_RNF_NODEID_LIST]
-	str	x2, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET]
-1:	ldr	x3, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET]
-	mvn	x0, x3
-	tst	x0, x3		/* Wait for domain addition to complete */
-	b.ne	1b
+	ldr	x0, =CCI_MN_BASE
+	ldr	x1, =CCI_MN_RNF_NODEID_LIST
+	ldr	x2, =CCI_MN_DVM_DOMAIN_CTL_SET
+	bl	ccn504_add_masters_to_dvm
+
+	/* Set all RN-I ports to QoS of 15 */
+	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(0)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(0)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(0)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+
+	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(2)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(2)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(2)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+
+	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(6)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(6)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(6)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+
+	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(12)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(12)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(12)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+
+	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(16)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(16)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(16)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+
+	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(20)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(20)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
+	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(20)
+	ldr	x1, =0x00FF000C
+	bl	ccn504_set_qos
 
 	/* Set the SMMU page size in the sACR register */
 	ldr	x1, =SMMU_BASE
arch/arm/include/asm/arch-fsl-lsch3/config.h +11 -0
index ca8d38c..c47950c 100644
@@ -132,6 +132,17 @@
 #define CCI_MN_DVM_DOMAIN_CTL		0x200
 #define CCI_MN_DVM_DOMAIN_CTL_SET	0x210
 
+#define CCI_RN_I_0_BASE			(CCI_MN_BASE + 0x800000)
+#define CCI_RN_I_2_BASE			(CCI_MN_BASE + 0x820000)
+#define CCI_RN_I_6_BASE			(CCI_MN_BASE + 0x860000)
+#define CCI_RN_I_12_BASE		(CCI_MN_BASE + 0x8C0000)
+#define CCI_RN_I_16_BASE		(CCI_MN_BASE + 0x900000)
+#define CCI_RN_I_20_BASE		(CCI_MN_BASE + 0x940000)
+
+#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
+#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
+#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
+
 /* Device Configuration */
 #define DCFG_BASE		0x01e00000
 #define DCFG_PORSR1			0x000
arch/arm/lib/Makefile +1 -0
index 31a5c8d..51497cc 100644
@@ -42,6 +42,7 @@ obj-y	+= stack.o
 ifdef CONFIG_CPU_V7M
 obj-y	+= interrupts_m.o
 else ifdef CONFIG_ARM64
+obj-y	+= ccn504.o
 obj-y	+= gic_64.o
 obj-y	+= interrupts_64.o
 else
arch/arm/lib/ccn504.S new file +61 -0

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Signature · 1 line
1.7.9.5
#1 lore raw

PATCH RESEND 1/1 armv8: Add framework for CCN-504 interconnect configuration

Quoted 7 lines · Bhupesh Sharma

This patch adds a minimal framework for Dickens CCN-504 interconnect configuration - mainly related to adding Clusters/cores to snoop/DVM domain and setting QoS of the RN-I ports.

LS2085A platform makes use of these configurations to support better network data performance and to boot a SMP Linux.

Quoted 9 lines
Signed-off-by Bhupesh Sharma <[email protected]>
---
 arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S      |   72 +++++++++++++++++++++++---
 arch/arm/include/asm/arch-fsl-lsch3/config.h |   11 ++++
 arch/arm/lib/Makefile                        |    1 +
 arch/arm/lib/ccn504.S                        |   61 ++++++++++++++++++++++
 4 files changed, 138 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/lib/ccn504.S

There is no feedback on this patch. I presume we are OK with it. We may move other CCN-504 related code into the new framework.

York

author
#2 lore raw

PATCH RESEND 1/1 armv8: Add framework for CCN-504 interconnect configuration

Quoted 18 lines

From: Sun York-R58495
Sent: Thursday, August 13, 2015 11:10 PM

Quoted 10 lines · Bhupesh Sharma

This patch adds a minimal framework for Dickens CCN-504 interconnect configuration - mainly related to adding Clusters/cores to snoop/DVM domain and setting QoS of the RN-I ports.

LS2085A platform makes use of these configurations to support better network data performance and to boot a SMP Linux.

Signed-off-by Bhupesh Sharma <[email protected]>
---
 arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S      |   72

+++++++++++++++++++++++---

Quoted 3 lines
 arch/arm/include/asm/arch-fsl-lsch3/config.h |   11 ++++
 arch/arm/lib/Makefile                        |    1 +
 arch/arm/lib/ccn504.S                        |   61
Quoted 7 lines

++++++++++++++++++++++

Quoted 3 lines
 4 files changed, 138 insertions(+), 7 deletions(-)  create mode

100644 arch/arm/lib/ccn504.S

There is no feedback on this patch. I presume we are OK with it. We may move other CCN-504 related code into the new framework.

Sure. I didn't see any feedback on this either. @ Mark, Albert - Do you have any feedback on this?

Regards,
Bhupesh

Quoted 1 line

York

Applied
#3 lore raw

PATCH RESEND 1/1 armv8: Add framework for CCN-504 interconnect configuration

In reply to Bhupesh Sharma
Quoted 9 lines · Bhupesh Sharma

This patch adds a minimal framework for Dickens CCN-504 interconnect configuration - mainly related to adding Clusters/cores to snoop/DVM domain and setting QoS of the RN-I ports.

LS2085A platform makes use of these configurations to support better network data performance and to boot a SMP Linux.

Signed-off-by Bhupesh Sharma <[email protected]>

---

Applied to fsl-qoriq master branch. Awaiting upstream.

York