dts/ls2085a: Update DTSI to add support of various peripherals
Subsystems (3)
PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
This patch updates the LS2085a DTSI (DTS Include) file to add support for various peripherals supported by FSL LS2085a SoC, for e.g.:
- USB 3.0 Host
- PMU
- CCN-504
- Watchdog
- SATA
- SPI
- PCIe
- etc.
--- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 469 +++++++++++++++++++++++- 1 file changed, 459 insertions(+), 10 deletions(-)
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +459 -10
@@ -20,11 +20,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person
@@ -71,48 +66,56 @@ device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; }; cpu at 1 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x1>; + clocks = <&clockgen 1 0>; }; cpu at 100 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x100>; + clocks = <&clockgen 1 1>; }; cpu at 101 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x101>; + clocks = <&clockgen 1 1>; }; cpu at 200 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x200>; + clocks = <&clockgen 1 2>; }; cpu at 201 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x201>; + clocks = <&clockgen 1 2>; }; cpu at 300 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x300>; + clocks = <&clockgen 1 3>; }; cpu at 301 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x301>; + clocks = <&clockgen 1 3>; }; };
@@ -122,13 +125,44 @@ /* DRAM space - 1, size : 2 GB DRAM */ }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ + }; + gic: interrupt-controller at 6000000 { compatible = "arm,gic-v3"; reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ + <0x0 0x0c0c0000 0 0x2000>, /* GICC */ + <0x0 0x0c0d0000 0 0x1000>, /* GICH */ + <0x0 0x0c0e0000 0 0x20000>; /* GICV */ #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; interrupt-controller; interrupts = <1 9 0x4>; + + its: gic-its at 6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; + }; + + clockgen: clocking at 1300000 { + compatible = "fsl,ls2080a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; }; timer {
@@ -139,25 +173,440 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */ }; + amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster1_core1_watchdog: wdt at c010000 { + compatible = "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster2_core0_watchdog: wdt at c100000 { + compatible = "arm,primecell"; + reg = <0x0 0xc100000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster2_core1_watchdog: wdt at c110000 { + compatible = "arm,primecell"; + reg = <0x0 0xc110000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster3_core0_watchdog: wdt at c200000 { + compatible = "arm,primecell"; + reg = <0x0 0xc200000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster3_core1_watchdog: wdt at c210000 { + compatible = "arm,primecell"; + reg = <0x0 0xc210000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster4_core0_watchdog: wdt at c300000 { + compatible = "arm,primecell"; + reg = <0x0 0xc300000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster4_core1_watchdog: wdt at c310000 { + compatible = "arm,primecell"; + reg = <0x0 0xc310000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + }; + serial0: serial at 21c0500 { device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0500 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ + clocks = <&clockgen 4 3>; + interrupts = <0 32 0x4>; /* Level high type */ }; serial1: serial at 21c0600 { device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ + clocks = <&clockgen 4 3>; + interrupts = <0 32 0x4>; /* Level high type */ }; fsl_mc: fsl-mc at 80c000000 { compatible = "fsl,qoriq-mc"; + #stream-id-cells = <2>; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + lpi-parent = <&its>; + }; + + smmu: iommu at 5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #global-interrupts = <12>; + interrupts = <0 13 4>, /* global secure fault */ + <0 14 4>, /* combined secure interrupt */ + <0 15 4>, /* global non-secure fault */ + <0 16 4>, /* combined non-secure interrupt */ + /* performance counter interrupts 0-7 */ + <0 211 4>, + <0 212 4>, + <0 213 4>, + <0 214 4>, + <0 215 4>, + <0 216 4>, + <0 217 4>, + <0 218 4>, + /* per context interrupt, 64 interrupts */ + <0 146 4>, + <0 147 4>, + <0 148 4>, + <0 149 4>, + <0 150 4>, + <0 151 4>, + <0 152 4>, + <0 153 4>, + <0 154 4>, + <0 155 4>, + <0 156 4>, + <0 157 4>, + <0 158 4>, + <0 159 4>, + <0 160 4>, + <0 161 4>, + <0 162 4>, + <0 163 4>, + <0 164 4>, + <0 165 4>, + <0 166 4>, + <0 167 4>, + <0 168 4>, + <0 169 4>, + <0 170 4>, + <0 171 4>, + <0 172 4>, + <0 173 4>, + <0 174 4>, + <0 175 4>, + <0 176 4>, + <0 177 4>, + <0 178 4>, + <0 179 4>, + <0 180 4>, + <0 181 4>, + <0 182 4>, + <0 183 4>, + <0 184 4>, + <0 185 4>, + <0 186 4>, + <0 187 4>, + <0 188 4>, + <0 189 4>, + <0 190 4>, + <0 191 4>, + <0 192 4>, + <0 193 4>, + <0 194 4>, + <0 195 4>, + <0 196 4>, + <0 197 4>, + <0 198 4>, + <0 199 4>, + <0 200 4>, + <0 201 4>, + <0 202 4>, + <0 203 4>, + <0 204 4>, + <0 205 4>, + <0 206 4>, + <0 207 4>, + <0 208 4>, + <0 209 4>; + mmu-masters = <&fsl_mc 0x300 0>; + }; + + dspi: dspi at 2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; /* Level high type */ + tcfq-mode; + clocks = <&clockgen 4 3>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <0>; + spi-cpol; + spi-cpha; + }; + + esdhc: esdhc at 2140000 { + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + clock-frequency = <0>; /* Updated by bootloader */ + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; + bus-width = <4>; + }; + + gpio0: gpio at 2300000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio at 2310000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio at 2320000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 37 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio at 2330000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 37 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2c0: i2c at 2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c1: i2c at 2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c2: i2c at 2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c3: i2c at 2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + ifc: ifc at 2240000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x2240000 0x0 0x20000>; + interrupts = <0 21 0x4>; /* Level high type */ + little-endian; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0 0 0x5 0x80000000 0x08000000 + 2 0 0x5 0x30000000 0x00010000 + 3 0 0x5 0x20000000 0x00010000>; + }; + + qspi: quadspi at 20c0000 { + compatible = "fsl,vf610-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <0 25 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "qspi_en", "qspi"; + }; + + pcie at 3400000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x10 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 108 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, + <0000 0 0 2 &gic 0 0 0 110 4>, + <0000 0 0 3 &gic 0 0 0 111 4>, + <0000 0 0 4 &gic 0 0 0 112 4>; + }; + + pcie at 3500000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x12 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 113 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, + <0000 0 0 2 &gic 0 0 0 115 4>, + <0000 0 0 3 &gic 0 0 0 116 4>, + <0000 0 0 4 &gic 0 0 0 117 4>; + }; + + pcie at 3600000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x14 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 118 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, + <0000 0 0 2 &gic 0 0 0 120 4>, + <0000 0 0 3 &gic 0 0 0 121 4>, + <0000 0 0 4 &gic 0 0 0 122 4>; + }; + + pcie at 3700000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x16 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 123 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, + <0000 0 0 2 &gic 0 0 0 125 4>, + <0000 0 0 3 &gic 0 0 0 126 4>, + <0000 0 0 4 &gic 0 0 0 127 4>; + }; + + sata0: sata at 3200000 { + compatible = "fsl,ls2080a-ahci", "fsl,ls1021a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>; + }; + + sata1: sata at 3210000 { + compatible = "fsl,ls2080a-ahci", "fsl,ls1021a-ahci"; + reg = <0x0 0x3210000 0x0 0x10000>; + interrupts = <0 136 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>; + }; + + usb0: usb3 at 3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + usb1: usb3 at 3110000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + ccn at 4000000 { + compatible = "arm,ccn-504"; + reg = <0x0 0x04000000 0x0 0x01000000>; + interrupts = <0 12 4>; }; };
Signature · 1 line
1.7.9.5
PATCH v2 8/10 dts/ls2085a: Update Simulator DTS to add support of various peripherals
This patch updates the LS2085a simulator DTS to add support of various peripherals which are supported on the simulator platform and explicitly disables those which are yet not supported on the platform.
--- arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 54 ++++++++++++++++++-- 1 file changed, 49 insertions(+), 5 deletions(-)
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts +49 -5
@@ -20,11 +20,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person
@@ -63,3 +58,52 @@ interrupts = <0 58 0x1>; }; }; + +&esdhc { + status = "disabled"; +}; + +&ifc { + status = "okay"; +}; + +&i2c0 { + status = "disabled"; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&dspi { + status = "disabled"; +}; + +&qspi { + status = "disabled"; +}; + +&sata0 { + status = "disabled"; +}; + +&sata1 { + status = "disabled"; +}; + +&usb0 { + status = "disabled"; +}; + +&usb1 { + status = "disabled"; +}; +
Signature · 1 line
1.7.9.5
PATCH v2 8/10 dts/ls2085a: Update Simulator DTS to add support of various peripherals
Quoted 1 line · Bhupesh Sharma
This patch updates the LS2085a simulator DTS to add support of various
LS2080...
Quoted 2 lines
peripherals which are supported on the simulator platform and explicitly disables those which are yet not supported on the platform.
I don't know if there will be any people outside Freescale would get this simulator. If not, we should just remove this file.
Quoted 5 lines
Signed-off-by Bhupesh Sharma <[email protected]>--- arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 54 ++++++++++++++++++-- 1 file changed, 49 insertions(+), 5 deletions(-)
PATCH v2 8/10 dts/ls2085a: Update Simulator DTS to add support of various peripherals
Quoted 7 lines
From: pku.leo at gmail.com [mailto:pku.leo at gmail.com]
Sent: Saturday, September 05, 2015 3:01 AMQuoted 1 line · Bhupesh Sharma
This patch updates the LS2085a simulator DTS to add support of various
LS2080...
Ok.
Quoted 5 lines
Quoted 2 lines
peripherals which are supported on the simulator platform and explicitly disables those which are yet not supported on the platform.
I don't know if there will be any people outside Freescale would get this simulator. If not, we should just remove this file.
As conveyed by program management, Code Warrior for freescale will continue to support LS2080A. So, the simulator DTS support will continue till there is change in that strategy.
Regards,
Bhupesh
PATCH v2 9/10 dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards
In reply to Bhupesh SharmaThis patch adds the LS2080a DTS files for QDS and RDB boards which support the LS2080a SoC.
--- arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 198 +++++++++++++++++++++ arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 161 +++++++++++++++++ 2 files changed, 359 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts new file +198 -0
@@ -0,0 +1,198 @@ +/* + * Device Tree file for Freescale LS2080a QDS Board. + * + * Copyright (C) 2015, Freescale Semiconductor + * + * Bhupesh Sharma <[email protected]> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +/include/ "fsl-ls2080a.dtsi" + +/ { + model = "Freescale Layerscape 2080a QDS Board"; + compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; +}; + +&esdhc { + status = "okay"; +}; + +&ifc { + status = "okay"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x0 0x0 0x5 0x80000000 0x08000000 + 0x2 0x0 0x5 0x30000000 0x00010000 + 0x3 0x0 0x5 0x20000000 0x00010000>; + + nor at 0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand at 2,0 { + compatible = "fsl,ifc-nand"; + reg = <0x2 0x0 0x10000>; + }; + + cpld at 3,0 { + reg = <0x3 0x0 0x10000>; + compatible = "fsl,ls2080a-qds-qixis", "fsl,fpga-qixis"; + }; +}; + +&i2c0 { + status = "okay"; + pca9547 at 77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c at 0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + rtc at 68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; + }; + + i2c at 2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x02>; + + ina220 at 40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <500>; + }; + + ina220 at 41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c at 3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + adt7481 at 4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + }; + }; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&dspi { + status = "okay"; + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80"; + spi-max-frequency = <3000000>; + reg = <0>; + }; + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80"; + spi-max-frequency = <3000000>; + reg = <1>; + }; + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80"; + spi-max-frequency = <3000000>; + reg = <2>; + }; +}; + +&qspi { + status = "okay"; + qflash0: s25fl008k { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +};
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts new file +161 -0
161 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH v2 10/10 dts/Makefile: Add build support for LS2080a QDS & RDB board DTS
In reply to Bhupesh SharmaThis patch adds build support for LS2080a QDS & RDB board DTS files in the arm64 DTS Makefile.
--- arch/arm64/boot/dts/freescale/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/freescale/Makefile +1 -1
@@ -1,4 +1,4 @@ -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb fsl-ls2080a-rdb.dtb fsl-ls2080a-simu.dtb always := $(dtb-y) subdir-y := $(dts-dirs)
Signature · 1 line
1.7.9.5
PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
In reply to Bhupesh SharmaQuoted 28 lines · Bhupesh Sharma
This patch updates the LS2085a DTSI (DTS Include) file to add support for various peripherals supported by FSL LS2085a SoC, for e.g.:
- USB 3.0 Host
- PMU
- CCN-504
- Watchdog
- SATA
- SPI
- PCIe
- etc.Signed-off-by Bhupesh Sharma <[email protected]>Signed-off-by Jaiprakash Singh <[email protected]>Signed-off-by Alison Wang <[email protected]>Signed-off-by Liu Gang <[email protected]>Signed-off-by Minghuan Lian <[email protected]>Signed-off-by Shaohui Xie <[email protected]>Signed-off-by Nikhil Badola <[email protected]>Signed-off-by Yangbo Lu <[email protected]>Signed-off-by Scott Wood <[email protected]>--- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 469 +++++++++++++++++++++++- 1 file changed, 459 insertions(+), 10 deletions(-)arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +0
-0
[...]
Quoted 21 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +14
-1gic: interrupt-controller at 6000000 { compatible = "arm,gic-v3"; reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ + <0x0 0x0c0c0000 0 0x2000>, /* GICC */ + <0x0 0x0c0d0000 0 0x1000>, /* GICH */ + <0x0 0x0c0e0000 0 0x20000>; /* GICV */ #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; interrupt-controller; interrupts = <1 9 0x4>; + + its: gic-its at 6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; + };
[...]
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 268
Quoted 6 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +2
-0fsl_mc: fsl-mc at 80c000000 { compatible = "fsl,qoriq-mc"; + #stream-id-cells = <2>; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + lpi-parent = <&its>;
I'm afraid there is no such thing as "lpi_parent" as a property. We have msi_parent, which is (I think) what you want, and is dealt with in the ITS driver. Also, you'll need to describe the DeviceIDs that can be generated by this device so that the ITS can be correctly programmed.
Thanks,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
Quoted 2 lines
From: Marc Zyngier [mailto:marc.zyngier at arm.com]
Sent: Friday, September 04, 2015 4:25 PM
[snip] ..
Quoted 43 lines
Quoted 9 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 469 +++++++++++++++++++++++- 1 file changed, 459 insertions(+), 10 deletions(-)arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +0
-0[...]
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
Quoted 4 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +0
-1gic: interrupt-controller at 6000000 { compatible = "arm,gic-v3"; reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06100000 0 0x100000>; /* GICR (RD_base +
SGI_base) */arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
Quoted 1 line
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +1
-0+ <0x0 0x06100000 0 0x100000>, /* GICR (RD_base +
SGI_base) */Quoted 16 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +13
-0+ <0x0 0x0c0c0000 0 0x2000>, /* GICC */ + <0x0 0x0c0d0000 0 0x1000>, /* GICH */ + <0x0 0x0c0e0000 0 0x20000>; /* GICV */ #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; interrupt-controller; interrupts = <1 9 0x4>; + + its: gic-its at 6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; + };[...]
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
Quoted 4 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +1
-0fsl_mc: fsl-mc at 80c000000 { compatible = "fsl,qoriq-mc"; + #stream-id-cells = <2>; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base*/
Quoted 7 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 268
Quoted 2 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +1
-0<0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + lpi-parent = <&its>;I'm afraid there is no such thing as "
lpi_parent" as a property. We havemsi_parent, which is (I think) what you want, and is dealt with in the ITS driver. Also, you'll need to describe the DeviceIDs that can be generated by this device so that the ITS can be correctly programmed.
Oops. This should be 'msi_parent' as you point out, Marc.
I will address these comments in v3 of the patchset.
Regards,
Bhupesh
PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
In reply to Bhupesh SharmaQuoted 2 lines · Bhupesh Sharma
This patch updates the LS2085a DTSI (DTS Include) file to add support for various peripherals supported by FSL LS2085a SoC, for e.g.:
The title and description here are still using the old LS2085 name.
Quoted 143 lines
- USB 3.0 Host
- PMU
- CCN-504
- Watchdog
- SATA
- SPI
- PCIe
- etc.Signed-off-by Bhupesh Sharma <[email protected]>Signed-off-by Jaiprakash Singh <[email protected]>Signed-off-by Alison Wang <[email protected]>Signed-off-by Liu Gang <[email protected]>Signed-off-by Minghuan Lian <[email protected]>Signed-off-by Shaohui Xie <[email protected]>Signed-off-by Nikhil Badola <[email protected]>Signed-off-by Yangbo Lu <[email protected]>Signed-off-by Scott Wood <[email protected]>--- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 469 +++++++++++++++++++++++- 1 file changed, 459 insertions(+), 10 deletions(-)arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +40
-6@@ -20,11 +20,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person@@ -71,48 +66,56 @@ device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; }; cpu at 1 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x1>; + clocks = <&clockgen 1 0>; }; cpu at 100 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x100>; + clocks = <&clockgen 1 1>; }; cpu at 101 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x101>; + clocks = <&clockgen 1 1>; }; cpu at 200 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x200>; + clocks = <&clockgen 1 2>; }; cpu at 201 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x201>; + clocks = <&clockgen 1 2>; }; cpu at 300 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x300>; + clocks = <&clockgen 1 3>; }; cpu at 301 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x301>; + clocks = <&clockgen 1 3>; }; };@@ -122,13 +125,44 @@ /* DRAM space - 1, size : 2 GB DRAM */ }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ + }; + gic: interrupt-controller at 6000000 { compatible = "arm,gic-v3"; reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ + <0x0 0x0c0c0000 0 0x2000>, /* GICC */ + <0x0 0x0c0d0000 0 0x1000>, /* GICH */ + <0x0 0x0c0e0000 0 0x20000>; /* GICV */ #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; interrupt-controller; interrupts = <1 9 0x4>; + + its: gic-its at 6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; + }; + + clockgen: clocking at 1300000 { + compatible = "fsl,ls2080a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; }; timer {@@ -139,25 +173,440 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 183
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +8
-0}; + amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,primecell";
Binding of Primecell requires a specific name for the device instead of just a "arm,primecell".
Quoted 164 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +144
-4+ reg = <0x0 0xc000000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster1_core1_watchdog: wdt at c010000 { + compatible = "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster2_core0_watchdog: wdt at c100000 { + compatible = "arm,primecell"; + reg = <0x0 0xc100000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster2_core1_watchdog: wdt at c110000 { + compatible = "arm,primecell"; + reg = <0x0 0xc110000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster3_core0_watchdog: wdt at c200000 { + compatible = "arm,primecell"; + reg = <0x0 0xc200000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster3_core1_watchdog: wdt at c210000 { + compatible = "arm,primecell"; + reg = <0x0 0xc210000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster4_core0_watchdog: wdt at c300000 { + compatible = "arm,primecell"; + reg = <0x0 0xc300000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster4_core1_watchdog: wdt at c310000 { + compatible = "arm,primecell"; + reg = <0x0 0xc310000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + }; + serial0: serial at 21c0500 { device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0500 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ + clocks = <&clockgen 4 3>; + interrupts = <0 32 0x4>; /* Level high type */ }; serial1: serial at 21c0600 { device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ + clocks = <&clockgen 4 3>; + interrupts = <0 32 0x4>; /* Level high type */ }; fsl_mc: fsl-mc at 80c000000 { compatible = "fsl,qoriq-mc"; + #stream-id-cells = <2>; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + lpi-parent = <&its>; + }; + + smmu: iommu at 5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #global-interrupts = <12>; + interrupts = <0 13 4>, /* global secure fault */ + <0 14 4>, /* combined secure interrupt */ + <0 15 4>, /* global non-secure fault */ + <0 16 4>, /* combined non-secure interrupt */ + /* performance counter interrupts 0-7 */ + <0 211 4>, + <0 212 4>, + <0 213 4>, + <0 214 4>, + <0 215 4>, + <0 216 4>, + <0 217 4>, + <0 218 4>, + /* per context interrupt, 64 interrupts */ + <0 146 4>, + <0 147 4>, + <0 148 4>, + <0 149 4>, + <0 150 4>, + <0 151 4>, + <0 152 4>, + <0 153 4>, + <0 154 4>, + <0 155 4>, + <0 156 4>, + <0 157 4>, + <0 158 4>, + <0 159 4>, + <0 160 4>, + <0 161 4>, + <0 162 4>, + <0 163 4>, + <0 164 4>, + <0 165 4>, + <0 166 4>, + <0 167 4>, + <0 168 4>, + <0 169 4>, + <0 170 4>, + <0 171 4>, + <0 172 4>, + <0 173 4>, + <0 174 4>, + <0 175 4>, + <0 176 4>, + <0 177 4>, + <0 178 4>, + <0 179 4>, + <0 180 4>, + <0 181 4>, + <0 182 4>, + <0 183 4>, + <0 184 4>, + <0 185 4>, + <0 186 4>, + <0 187 4>, + <0 188 4>, + <0 189 4>, + <0 190 4>, + <0 191 4>, + <0 192 4>, + <0 193 4>, + <0 194 4>, + <0 195 4>, + <0 196 4>, + <0 197 4>, + <0 198 4>, + <0 199 4>, + <0 200 4>,
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 353
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ <0 201 4>, + <0 202 4>, + <0 203 4>, + <0 204 4>, + <0 205 4>, + <0 206 4>, + <0 207 4>, + <0 208 4>, + <0 209 4>; + mmu-masters = <&fsl_mc 0x300 0>;
Are we really only having one mmu-master?
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 362
Quoted 9 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +9
-0+ }; + + dspi: dspi at 2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; /* Level high type */ + tcfq-mode;
Can not find this property in the binding.
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 368
Quoted 6 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +6
-0+ clocks = <&clockgen 4 3>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <0>; + spi-cpol; + spi-cpha;
These two are not defined either.
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 378
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ }; + + esdhc: esdhc at 2140000 { + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + clock-frequency = <0>; /* Updated by bootloader */ + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian;
The patch for defining this property is still pending.
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 383
Quoted 5 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +5
-0+ bus-width = <4>; + }; + + gpio0: gpio at 2300000 { + compatible = "fsl,ls2080a-gpio";
Maybe you should add a more generic compatible string here. It's not clear which driver/binding you are actually using, mpc8xxx, imx or vf610?
Quoted 114 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +114
-0+ reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio at 2310000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio at 2320000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 37 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio at 2330000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 37 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2c0: i2c at 2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c1: i2c at 2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c2: i2c at 2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c3: i2c at 2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + ifc: ifc at 2240000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x2240000 0x0 0x20000>; + interrupts = <0 21 0x4>; /* Level high type */ + little-endian; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0 0 0x5 0x80000000 0x08000000 + 2 0 0x5 0x30000000 0x00010000 + 3 0 0x5 0x20000000 0x00010000>; + }; + + qspi: quadspi at 20c0000 { + compatible = "fsl,vf610-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <0 25 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "qspi_en", "qspi"; + }; + + pcie at 3400000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x10 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 108 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>;
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 507
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, + <0000 0 0 2 &gic 0 0 0 110 4>, + <0000 0 0 3 &gic 0 0 0 111 4>, + <0000 0 0 4 &gic 0 0 0 112 4>;
Binding shows it requires clocks and clock-names property.
Quoted 63 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +63
-0+ }; + + pcie at 3500000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x12 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 113 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, + <0000 0 0 2 &gic 0 0 0 115 4>, + <0000 0 0 3 &gic 0 0 0 116 4>, + <0000 0 0 4 &gic 0 0 0 117 4>; + }; + + pcie at 3600000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x14 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 118 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, + <0000 0 0 2 &gic 0 0 0 120 4>, + <0000 0 0 3 &gic 0 0 0 121 4>, + <0000 0 0 4 &gic 0 0 0 122 4>; + }; + + pcie at 3700000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x16 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 123 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>;
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 580
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, + <0000 0 0 2 &gic 0 0 0 125 4>, + <0000 0 0 3 &gic 0 0 0 126 4>, + <0000 0 0 4 &gic 0 0 0 127 4>; + }; + + sata0: sata at 3200000 { + compatible = "fsl,ls2080a-ahci", "fsl,ls1021a-ahci";
Binding requires a more general compatible fsl,qoriq-ahci
Quoted 7 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +7
-0+ reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>; + }; + + sata1: sata at 3210000 { + compatible = "fsl,ls2080a-ahci", "fsl,ls1021a-ahci";
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 597
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ reg = <0x0 0x3210000 0x0 0x10000>; + interrupts = <0 136 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>; + }; + + usb0: usb3 at 3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host";
dr_mode not defined in dwc3 binding.
Quoted 24 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +13
-1+ }; + + usb1: usb3 at 3110000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + ccn at 4000000 { + compatible = "arm,ccn-504"; + reg = <0x0 0x04000000 0x0 0x01000000>; + interrupts = <0 12 4>; }; }; --1.7.9.5
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Signature · 1 line
- Leo
PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
Quoted 8 lines
From: pku.leo at gmail.com [mailto:pku.leo at gmail.com]
Sent: Saturday, September 05, 2015 2:33 AMQuoted 2 lines · Bhupesh Sharma
This patch updates the LS2085a DTSI (DTS Include) file to add support for various peripherals supported by FSL LS2085a SoC, for e.g.:
The title and description here are still using the old LS2085 name.
Ok.
[snip] ..
Quoted 11 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 183
Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +8
-0+ amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,primecell";Binding of Primecell requires a specific name for the device instead of just a "arm,primecell".
The sp805 driver doesn't have a compatible string like arm, sp805.
You can refer to 'Documentation/devicetree/bindings/wdt' for details - there is no entry for sp805 here. Instead it relies on the 'drivers/amba/bus.c' framework to invoke the probe function of the sp805 wdt driver using the unique PRIMECELL identifiers of the sp805 wdt IP.
See Appendix A of 'devicetree/usage-model.txt' for details:
http://lxr.free-electrons.com/source/Documentation/devicetree/usage-model.txt#L398
Quoted 85 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +8
-0+ smmu: iommu at 5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #global-interrupts = <12>; + interrupts = <0 13 4>, /* global secure fault */ + <0 14 4>, /* combined secure interrupt */ + <0 15 4>, /* global non-secure fault */ + <0 16 4>, /* combined non-secure interrupt*/
Quoted 65 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +65
-0+ /* performance counter interrupts 0-7 */ + <0 211 4>, + <0 212 4>, + <0 213 4>, + <0 214 4>, + <0 215 4>, + <0 216 4>, + <0 217 4>, + <0 218 4>, + /* per context interrupt, 64 interrupts */ + <0 146 4>, + <0 147 4>, + <0 148 4>, + <0 149 4>, + <0 150 4>, + <0 151 4>, + <0 152 4>, + <0 153 4>, + <0 154 4>, + <0 155 4>, + <0 156 4>, + <0 157 4>, + <0 158 4>, + <0 159 4>, + <0 160 4>, + <0 161 4>, + <0 162 4>, + <0 163 4>, + <0 164 4>, + <0 165 4>, + <0 166 4>, + <0 167 4>, + <0 168 4>, + <0 169 4>, + <0 170 4>, + <0 171 4>, + <0 172 4>, + <0 173 4>, + <0 174 4>, + <0 175 4>, + <0 176 4>, + <0 177 4>, + <0 178 4>, + <0 179 4>, + <0 180 4>, + <0 181 4>, + <0 182 4>, + <0 183 4>, + <0 184 4>, + <0 185 4>, + <0 186 4>, + <0 187 4>, + <0 188 4>, + <0 189 4>, + <0 190 4>, + <0 191 4>, + <0 192 4>, + <0 193 4>, + <0 194 4>, + <0 195 4>, + <0 196 4>, + <0 197 4>, + <0 198 4>, + <0 199 4>, + <0 200 4>,arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 353
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ <0 201 4>, + <0 202 4>, + <0 203 4>, + <0 204 4>, + <0 205 4>, + <0 206 4>, + <0 207 4>, + <0 208 4>, + <0 209 4>; + mmu-masters = <&fsl_mc 0x300 0>;
Quoted 1 line
Are we really only having one mmu-master?
So far only this one is tested. Later on others can be added when we have tested them with SMMU APIs as well.
Quoted 11 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 362
Quoted 9 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +9
-0+ }; + + dspi: dspi at 2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; /* Level high type */ + tcfq-mode;Can not find this property in the binding.
Xiaobo, can you please answer Leo's comment here. Thanks.
Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 368
Quoted 6 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +6
-0+ clocks = <&clockgen 4 3>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <0>; + spi-cpol; + spi-cpha;These two are not defined either.
Xiaobo, can you please answer Leo's comment here. Thanks.
Quoted 11 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 378
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ }; + + esdhc: esdhc at 2140000 { + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + clock-frequency = <0>; /* Updated by bootloader */ + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian;
Quoted 1 line
The patch for defining this property is still pending.
Xiaobo, can you please answer Leo's comment here. Thanks.
Quoted 9 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 383
Quoted 6 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +5
-0+ bus-width = <4>; + }; + + gpio0: gpio at 2300000 { + compatible = "fsl,ls2080a-gpio";Maybe you should add a more generic compatible string here. It's not clear which driver/binding you are actually using, mpc8xxx, imx or vf610?
Liu Gang, can you please answer Leo's comment here. Thanks.
Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 391
Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +8
-0+ reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +
[snip] ..
Quoted 26 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
Quoted 3 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +3
-0+ pcie at 3400000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controllerregisters */
Quoted 1 line
+
0x100x000000000x00x00001000>; /*configuration space */
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
Quoted 9 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +9
-0+ reg-names = "regs", "config"; + interrupts = <0 108 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0
0x00010000/* downstream I/O */Quoted 1 line
+
0x820000000x00x400000000x100x400000000x0
0x40000000>; /* non-prefetchable memory */arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 507
Quoted 7 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +7
-0+ msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, + <0000 0 0 2 &gic 0 0 0 110 4>, + <0000 0 0 3 &gic 0 0 0 111 4>, + <0000 0 0 4 &gic 0 0 0 112 4>;
Quoted 1 line
Binding shows it requires clocks and clock-names property.
Minghuan, can you please answer Leo's comment here. Thanks.
Quoted 2 lines
Review
Quoted 2 lines
(quoted diff) +2
-0+ }; +
[snip] ..
Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 597
Quoted 6 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +6
-0+ + usb0: usb3 at 3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host";
dr_modenot defined in dwc3 binding.
Nikhil, I think you have already sent out a patch which addresses the same. Can you please update this thread with the link of the same? Thanks.
[snip] ..
Regards,
Bhupesh
PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
Quoted 22 lines · Sharma Bhupesh
Quoted 8 lines
From: pku.leo at gmail.com [mailto:pku.leo at gmail.com]
Sent: Saturday, September 05, 2015 2:33 AMQuoted 2 lines · Bhupesh Sharma
This patch updates the LS2085a DTSI (DTS Include) file to add support for various peripherals supported by FSL LS2085a SoC, for e.g.:
The title and description here are still using the old LS2085 name.
Ok.
[snip] ..
Quoted 9 lines
Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +8
-0+ amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,primecell";
Quoted 5 lines
Quoted 2 lines
Binding of Primecell requires a specific name for the device instead of just a "arm,primecell".
The sp805 driver doesn't have a compatible string like arm, sp805.
You can refer to 'Documentation/devicetree/bindings/wdt' for details - there is no entry for sp805 here.
Because no one wrote it yet. Please read Documentation/devicetree/bindings/arm/primecell.txt. If sp805 has no binding doc, please write one.
Quoted 2 lines
Instead it relies on the '
drivers/amba/bus.c' framework to invoke the probe function of the sp805 wdt driver using the unique PRIMECELL identifiers of the sp805 wdt IP.
Whether the kernel chooses to bind with the ID registers or compatible strings is up to the kernel. That is independent of the bindings.
Rob
PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
Quoted 37 lines
From: Rob Herring [mailto:robherring2 at gmail.com]
Sent: Monday, September 07, 2015 2:27 AMQuoted 5 lines · Sharma Bhupesh
Quoted 5 lines
From: pku.leo at gmail.com [mailto:pku.leo at gmail.com]
Sent: Saturday, September 05, 2015 2:33 AM On Fri, Sep 4, 2015 atQuoted 2 lines · Bhupesh Sharma
This patch updates the LS2085a DTSI (DTS Include) file to add support for various peripherals supported by FSL LS2085a SoC, for
e.g.:
Quoted 16 lines
Quoted 2 lines
The title and description here are still using the old LS2085 name.
Ok.
[snip] ..
Quoted 9 lines
Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +8
-0+ amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,primecell";Quoted 5 lines
Quoted 2 lines
Binding of Primecell requires a specific name for the device instead of just a "arm,primecell".
The sp805 driver doesn't have a compatible string like arm, sp805. You can refer to '
Documentation/devicetree/bindings/wdt' for details -there is no entry for sp805 here.
Because no one wrote it yet. Please read
Documentation/devicetree/bindings/arm/primecell.txt. If sp805 has no binding doc, please write one.
Quoted 8 lines
Quoted 3 lines
Instead it relies on the '
drivers/amba/bus.c' framework to invoke the probe function of the
sp805 wdt driver using the unique PRIMECELL identifiers of the sp805wdt IP.
Whether the kernel chooses to bind with the ID registers or compatible strings is up to the kernel. That is independent of the bindings.
Right. But wouldn't the driver require DTS awareness to handle the compatible string then. Shouldn't the DTS awareness added both in terms of bindings and driver handling?
Regards,
Bhupesh
PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
Quoted 40 lines · Sharma Bhupesh
Quoted 40 lines
From: Rob Herring [mailto:robherring2 at gmail.com]
Sent: Monday, September 07, 2015 2:27 AMQuoted 5 lines · Sharma Bhupesh
Quoted 5 lines
From: pku.leo at gmail.com [mailto:pku.leo at gmail.com]
Sent: Saturday, September 05, 2015 2:33 AM On Fri, Sep 4, 2015 atQuoted 2 lines · Bhupesh Sharma
This patch updates the LS2085a DTSI (DTS Include) file to add support for various peripherals supported by FSL LS2085a SoC, for
e.g.:
Quoted 16 lines
Quoted 2 lines
The title and description here are still using the old LS2085 name.
Ok.
[snip] ..
Quoted 9 lines
Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +8
-0+ amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,primecell";Quoted 5 lines
Quoted 2 lines
Binding of Primecell requires a specific name for the device instead of just a "arm,primecell".
The sp805 driver doesn't have a compatible string like arm, sp805. You can refer to '
Documentation/devicetree/bindings/wdt' for details -there is no entry for sp805 here.
Because no one wrote it yet. Please read
Documentation/devicetree/bindings/arm/primecell.txt. If sp805 has no binding doc, please write one.Quoted 3 lines
Instead it relies on the '
drivers/amba/bus.c' framework to invoke the probe function of the
sp805 wdt driver using the unique PRIMECELL identifiers of the sp805
Quoted 8 lines
Quoted 5 lines
wdt IP.
Whether the kernel chooses to bind with the ID registers or compatible strings is up to the kernel. That is independent of the bindings.
Right. But wouldn't the driver require DTS awareness to handle the compatible string then. Shouldn't the DTS awareness added both in terms of bindings and driver handling?
No. The OS is free to do device enumeration however it sees fit and that could change independent of the DT.
Rob
Quoted 3 lines
Regards,
Bhupesh
PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
Quoted 53 lines
From: Rob Herring [mailto:robherring2 at gmail.com]
Sent: Tuesday, September 08, 2015 2:28 AMQuoted 38 lines · Sharma Bhupesh
Quoted 38 lines
From: Rob Herring [mailto:robherring2 at gmail.com]
Sent: Monday, September 07, 2015 2:27 AM On Sat, Sep 5, 2015 at 3:37Quoted 6 lines · Sharma Bhupesh
Quoted 6 lines
From: pku.leo at gmail.com [mailto:pku.leo at gmail.com]
Sent: Saturday, September 05, 2015 2:33 AM On Fri, Sep 4, 2015 atQuoted 3 lines · Bhupesh Sharma
This patch updates the LS2085a DTSI (DTS Include) file to add support for various peripherals supported by FSL LS2085a SoC, for
e.g.:
Quoted 16 lines
Quoted 2 lines
The title and description here are still using the old LS2085 name.
Ok.
[snip] ..
Quoted 9 lines
Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +8
-0+ amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,primecell";Quoted 6 lines
Quoted 2 lines
Binding of Primecell requires a specific name for the device instead of just a "arm,primecell".
The sp805 driver doesn't have a compatible string like arm, sp805. You can refer to '
Documentation/devicetree/bindings/wdt' for details -there is no entry for sp805 here.
Because no one wrote it yet. Please read
Documentation/devicetree/bindings/arm/primecell.txt. If sp805 has no binding doc, please write one.Quoted 8 lines
Quoted 8 lines
Quoted 4 lines
Instead it relies on the '
drivers/amba/bus.c' framework to invoke the probe function of the
sp805 wdt driver using the unique PRIMECELL identifiers of the sp805wdt IP.
Whether the kernel chooses to bind with the ID registers or compatible strings is up to the kernel. That is independent of the
bindings.
Quoted 2 lines
Quoted 1 line
Quoted 7 lines
Quoted 1 line
Right. But wouldn't the driver require DTS awareness to handle the
compatible string then.
Quoted 1 line
Shouldn't the DTS awareness added both in terms of bindings and driver
handling?
No. The OS is free to do device enumeration however it sees fit and that could change independent of the DT.
Ok. Will address this in v3 of this patchset then.
Regards,
Bhupesh
PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
In reply to Bhupesh SharmaQuoted 98 lines · Bhupesh Sharma
This patch updates the LS2085a DTSI (DTS Include) file to add support for various peripherals supported by FSL LS2085a SoC, for e.g.:
- USB 3.0 Host
- PMU
- CCN-504
- Watchdog
- SATA
- SPI
- PCIe
- etc.Signed-off-by Bhupesh Sharma <[email protected]>Signed-off-by Jaiprakash Singh <[email protected]>Signed-off-by Alison Wang <[email protected]>Signed-off-by Liu Gang <[email protected]>Signed-off-by Minghuan Lian <[email protected]>Signed-off-by Shaohui Xie <[email protected]>Signed-off-by Nikhil Badola <[email protected]>Signed-off-by Yangbo Lu <[email protected]>Signed-off-by Scott Wood <[email protected]>--- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 469 +++++++++++++++++++++++- 1 file changed, 459 insertions(+), 10 deletions(-)arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +8
-5@@ -20,11 +20,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person@@ -71,48 +66,56 @@ device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; }; cpu at 1 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x1>; + clocks = <&clockgen 1 0>; }; cpu at 100 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x100>; + clocks = <&clockgen 1 1>; }; cpu at 101 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x101>; + clocks = <&clockgen 1 1>; }; cpu at 200 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x200>; + clocks = <&clockgen 1 2>; }; cpu at 201 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x201>; + clocks = <&clockgen 1 2>; }; cpu at 300 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x300>; + clocks = <&clockgen 1 3>; }; cpu at 301 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x301>; + clocks = <&clockgen 1 3>; }; };
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 133
Quoted 9 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +5
-0@@ -122,13 +125,44 @@ /* DRAM space - 1, size : 2 GB DRAM */ }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ + }; + gic: interrupt-controller at 6000000 {
This should be under a bus node.
Quoted 12 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +7
-1compatible = "arm,gic-v3"; reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ + <0x0 0x0c0c0000 0 0x2000>, /* GICC */ + <0x0 0x0c0d0000 0 0x1000>, /* GICH */ + <0x0 0x0c0e0000 0 0x20000>; /* GICV */ #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; interrupt-controller;
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 154
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +9
-0interrupts = <1 9 0x4>; + + its: gic-its at 6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; + }; + + clockgen: clocking at 1300000 {
This should be under a bus node.
Quoted 15 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +11
-0+ compatible = "fsl,ls2080a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; }; timer {
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 177
Quoted 5 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +2
-0@@ -139,25 +173,440 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */ }; + amba { + compatible = "arm,amba-bus";
Use simple-bus. "arm,amba-bus" is meaningless.
Quoted 60 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +60
-0+ #address-cells = <2>; + #size-cells = <2>; + ranges; + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster1_core1_watchdog: wdt at c010000 { + compatible = "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster2_core0_watchdog: wdt at c100000 { + compatible = "arm,primecell"; + reg = <0x0 0xc100000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster2_core1_watchdog: wdt at c110000 { + compatible = "arm,primecell"; + reg = <0x0 0xc110000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster3_core0_watchdog: wdt at c200000 { + compatible = "arm,primecell"; + reg = <0x0 0xc200000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster3_core1_watchdog: wdt at c210000 { + compatible = "arm,primecell"; + reg = <0x0 0xc210000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster4_core0_watchdog: wdt at c300000 { + compatible = "arm,primecell"; + reg = <0x0 0xc300000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; +
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 247
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +9
-0+ cluster4_core1_watchdog: wdt at c310000 { + compatible = "arm,primecell"; + reg = <0x0 0xc310000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + }; + serial0: serial at 21c0500 {
This too should be moved under a bus node.
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 248
Quoted 1 line
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +0
-0device_type = "serial";
You should drop this.
Quoted 98 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +80
-4compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0500 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ + clocks = <&clockgen 4 3>; + interrupts = <0 32 0x4>; /* Level high type */ }; serial1: serial at 21c0600 { device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ + clocks = <&clockgen 4 3>; + interrupts = <0 32 0x4>; /* Level high type */ }; fsl_mc: fsl-mc at 80c000000 { compatible = "fsl,qoriq-mc"; + #stream-id-cells = <2>; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + lpi-parent = <&its>; + }; + + smmu: iommu at 5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #global-interrupts = <12>; + interrupts = <0 13 4>, /* global secure fault */ + <0 14 4>, /* combined secure interrupt */ + <0 15 4>, /* global non-secure fault */ + <0 16 4>, /* combined non-secure interrupt */ + /* performance counter interrupts 0-7 */ + <0 211 4>, + <0 212 4>, + <0 213 4>, + <0 214 4>, + <0 215 4>, + <0 216 4>, + <0 217 4>, + <0 218 4>, + /* per context interrupt, 64 interrupts */ + <0 146 4>, + <0 147 4>, + <0 148 4>, + <0 149 4>, + <0 150 4>, + <0 151 4>, + <0 152 4>, + <0 153 4>, + <0 154 4>, + <0 155 4>, + <0 156 4>, + <0 157 4>, + <0 158 4>, + <0 159 4>, + <0 160 4>, + <0 161 4>, + <0 162 4>, + <0 163 4>, + <0 164 4>, + <0 165 4>, + <0 166 4>, + <0 167 4>, + <0 168 4>, + <0 169 4>, + <0 170 4>, + <0 171 4>, + <0 172 4>, + <0 173 4>, + <0 174 4>, + <0 175 4>, + <0 176 4>, + <0 177 4>, + <0 178 4>, + <0 179 4>, + <0 180 4>, + <0 181 4>, + <0 182 4>, + <0 183 4>, + <0 184 4>, + <0 185 4>, + <0 186 4>, + <0 187 4>, + <0 188 4>, + <0 189 4>, + <0 190 4>, + <0 191 4>, + <0 192 4>, + <0 193 4>, + <0 194 4>, + <0 195 4>, + <0 196 4>, + <0 197 4>, + <0 198 4>, + <0 199 4>,
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 352
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ <0 200 4>, + <0 201 4>, + <0 202 4>, + <0 203 4>, + <0 204 4>, + <0 205 4>, + <0 206 4>, + <0 207 4>, + <0 208 4>, + <0 209 4>;
Perhaps more than 1 per line.
Quoted 269 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +258
-1+ mmu-masters = <&fsl_mc 0x300 0>; + }; + + dspi: dspi at 2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; /* Level high type */ + tcfq-mode; + clocks = <&clockgen 4 3>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <0>; + spi-cpol; + spi-cpha; + }; + + esdhc: esdhc at 2140000 { + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + clock-frequency = <0>; /* Updated by bootloader */ + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; + bus-width = <4>; + }; + + gpio0: gpio at 2300000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio at 2310000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio at 2320000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 37 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio at 2330000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 37 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2c0: i2c at 2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c1: i2c at 2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c2: i2c at 2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c3: i2c at 2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + ifc: ifc at 2240000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x2240000 0x0 0x20000>; + interrupts = <0 21 0x4>; /* Level high type */ + little-endian; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0 0 0x5 0x80000000 0x08000000 + 2 0 0x5 0x30000000 0x00010000 + 3 0 0x5 0x20000000 0x00010000>; + }; + + qspi: quadspi at 20c0000 { + compatible = "fsl,vf610-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <0 25 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "qspi_en", "qspi"; + }; + + pcie at 3400000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x10 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 108 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, + <0000 0 0 2 &gic 0 0 0 110 4>, + <0000 0 0 3 &gic 0 0 0 111 4>, + <0000 0 0 4 &gic 0 0 0 112 4>; + }; + + pcie at 3500000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x12 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 113 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, + <0000 0 0 2 &gic 0 0 0 115 4>, + <0000 0 0 3 &gic 0 0 0 116 4>, + <0000 0 0 4 &gic 0 0 0 117 4>; + }; + + pcie at 3600000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x14 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 118 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, + <0000 0 0 2 &gic 0 0 0 120 4>, + <0000 0 0 3 &gic 0 0 0 121 4>, + <0000 0 0 4 &gic 0 0 0 122 4>; + }; + + pcie at 3700000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x16 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 123 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, + <0000 0 0 2 &gic 0 0 0 125 4>, + <0000 0 0 3 &gic 0 0 0 126 4>, + <0000 0 0 4 &gic 0 0 0 127 4>; + }; + + sata0: sata at 3200000 { + compatible = "fsl,ls2080a-ahci", "fsl,ls1021a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>; + }; + + sata1: sata at 3210000 { + compatible = "fsl,ls2080a-ahci", "fsl,ls1021a-ahci"; + reg = <0x0 0x3210000 0x0 0x10000>; + interrupts = <0 136 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>; + }; + + usb0: usb3 at 3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + usb1: usb3 at 3110000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + ccn at 4000000 { + compatible = "arm,ccn-504"; + reg = <0x0 0x04000000 0x0 0x01000000>; + interrupts = <0 12 4>; }; }; --1.7.9.5
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PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
Hi Rob,
Quoted 30 lines · Rob Herring
Quoted 28 lines · Bhupesh Sharma
This patch updates the LS2085a DTSI (DTS Include) file to add support for various peripherals supported by FSL LS2085a SoC, for e.g.:
- USB 3.0 Host
- PMU
- CCN-504
- Watchdog
- SATA
- SPI
- PCIe
- etc.Signed-off-by Bhupesh Sharma <[email protected]>Signed-off-by Jaiprakash Singh <[email protected]>Signed-off-by Alison Wang <[email protected]>Signed-off-by Liu Gang <[email protected]>Signed-off-by Minghuan Lian <[email protected]>Signed-off-by Shaohui Xie <[email protected]>Signed-off-by Nikhil Badola <[email protected]>Signed-off-by Yangbo Lu <[email protected]>Signed-off-by Scott Wood <[email protected]>--- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 469 +++++++++++++++++++++++- 1 file changed, 459 insertions(+), 10 deletions(-)arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +0
-0
[snip..]
Quoted 4 lines
Quoted 2 lines
+
gic: interrupt-controller at 6000000 {This should be under a bus node.
Ok.
Quoted 16 lines
Quoted 16 lines
compatible = "arm,gic-v3"; reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-1- <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ + <0x0 0x0c0c0000 0 0x2000>, /* GICC */ + <0x0 0x0c0d0000 0 0x1000>, /* GICH */ + <0x0 0x0c0e0000 0 0x20000>; /* GICV */ #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; interrupt-controller; interrupts = <1 9 0x4>; + + its: gic-its at 6020000 { + compatible = "arm,gic-v3-its";
Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 154
Quoted 6 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +6
-0+ msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; + }; + + clockgen: clocking at 1300000 {This should be under a bus node.
Ok.
Quoted 18 lines
Quoted 18 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +11
-0+ compatible = "fsl,ls2080a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; }; timer {@@ -139,25 +173,440 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */ };
Quoted 4 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 177
Quoted 2 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +2
-0+ amba { + compatible = "arm,amba-bus";Use simple-bus. "arm,amba-bus" is meaningless.
Not sure I understand your comment here. Without this compatible in place I cannot see the 'drivers/amba/bus.c' amba_match() function getting called which in turn will call the amba_lookup() function,
thus invoking the probe function of the sp805_wdt driver.
Here is the comment on top of struct amba_bustype:
188 /*
189 * Primecells are part of the Advanced Microcontroller Bus Architecture, 190 * so we call the bus "amba". 191 */
Reference: http://lxr.free-electrons.com/source/drivers/amba/bus.c#L188
So, this should be "arm,amba-bus", as used in other DTS as well like ARM versatile
DTS:
90 amba {
91 compatible = "arm,amba-bus"; 92 #address-cells = <1>; 93 #size-cells = <1>; 94 ranges;
Reference: http://lxr.free-electrons.com/source/arch/arm/boot/dts/versatile-ab.dts#L90
Quoted 73 lines
Quoted 60 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +60
-0+ #address-cells = <2>; + #size-cells = <2>; + ranges; + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster1_core1_watchdog: wdt at c010000 { + compatible = "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster2_core0_watchdog: wdt at c100000 { + compatible = "arm,primecell"; + reg = <0x0 0xc100000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster2_core1_watchdog: wdt at c110000 { + compatible = "arm,primecell"; + reg = <0x0 0xc110000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster3_core0_watchdog: wdt at c200000 { + compatible = "arm,primecell"; + reg = <0x0 0xc200000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster3_core1_watchdog: wdt at c210000 { + compatible = "arm,primecell"; + reg = <0x0 0xc210000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster4_core0_watchdog: wdt at c300000 { + compatible = "arm,primecell"; + reg = <0x0 0xc300000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; +arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 247
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +9
-0+ cluster4_core1_watchdog: wdt at c310000 { + compatible = "arm,primecell"; + reg = <0x0 0xc310000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + }; + serial0: serial at 21c0500 {This too should be moved under a bus node.
Quoted 3 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 248
Quoted 1 line
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +0
-0device_type = "serial";You should drop this.
Ok.
Quoted 109 lines
Quoted 98 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +80
-4compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0500 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ + clocks = <&clockgen 4 3>; + interrupts = <0 32 0x4>; /* Level high type */ }; serial1: serial at 21c0600 { device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ + clocks = <&clockgen 4 3>; + interrupts = <0 32 0x4>; /* Level high type */ }; fsl_mc: fsl-mc at 80c000000 { compatible = "fsl,qoriq-mc"; + #stream-id-cells = <2>; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + lpi-parent = <&its>; + }; + + smmu: iommu at 5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #global-interrupts = <12>; + interrupts = <0 13 4>, /* global secure fault */ + <0 14 4>, /* combined secure interrupt */ + <0 15 4>, /* global non-secure fault */ + <0 16 4>, /* combined non-secure interrupt */ + /* performance counter interrupts 0-7 */ + <0 211 4>, + <0 212 4>, + <0 213 4>, + <0 214 4>, + <0 215 4>, + <0 216 4>, + <0 217 4>, + <0 218 4>, + /* per context interrupt, 64 interrupts */ + <0 146 4>, + <0 147 4>, + <0 148 4>, + <0 149 4>, + <0 150 4>, + <0 151 4>, + <0 152 4>, + <0 153 4>, + <0 154 4>, + <0 155 4>, + <0 156 4>, + <0 157 4>, + <0 158 4>, + <0 159 4>, + <0 160 4>, + <0 161 4>, + <0 162 4>, + <0 163 4>, + <0 164 4>, + <0 165 4>, + <0 166 4>, + <0 167 4>, + <0 168 4>, + <0 169 4>, + <0 170 4>, + <0 171 4>, + <0 172 4>, + <0 173 4>, + <0 174 4>, + <0 175 4>, + <0 176 4>, + <0 177 4>, + <0 178 4>, + <0 179 4>, + <0 180 4>, + <0 181 4>, + <0 182 4>, + <0 183 4>, + <0 184 4>, + <0 185 4>, + <0 186 4>, + <0 187 4>, + <0 188 4>, + <0 189 4>, + <0 190 4>, + <0 191 4>, + <0 192 4>, + <0 193 4>, + <0 194 4>, + <0 195 4>, + <0 196 4>, + <0 197 4>, + <0 198 4>, + <0 199 4>,arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 352
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ <0 200 4>, + <0 201 4>, + <0 202 4>, + <0 203 4>, + <0 204 4>, + <0 205 4>, + <0 206 4>, + <0 207 4>, + <0 208 4>, + <0 209 4>;
Quoted 1 line
Perhaps more than 1 per line.
Ok.
Quoted 269 lines
Quoted 269 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +258
-1+ mmu-masters = <&fsl_mc 0x300 0>; + }; + + dspi: dspi at 2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; /* Level high type */ + tcfq-mode; + clocks = <&clockgen 4 3>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <0>; + spi-cpol; + spi-cpha; + }; + + esdhc: esdhc at 2140000 { + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + clock-frequency = <0>; /* Updated by bootloader */ + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; + bus-width = <4>; + }; + + gpio0: gpio at 2300000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio at 2310000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio at 2320000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 37 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio at 2330000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 37 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2c0: i2c at 2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c1: i2c at 2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c2: i2c at 2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c3: i2c at 2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + ifc: ifc at 2240000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x2240000 0x0 0x20000>; + interrupts = <0 21 0x4>; /* Level high type */ + little-endian; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0 0 0x5 0x80000000 0x08000000 + 2 0 0x5 0x30000000 0x00010000 + 3 0 0x5 0x20000000 0x00010000>; + }; + + qspi: quadspi at 20c0000 { + compatible = "fsl,vf610-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <0 25 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "qspi_en", "qspi"; + }; + + pcie at 3400000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x10 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 108 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, + <0000 0 0 2 &gic 0 0 0 110 4>, + <0000 0 0 3 &gic 0 0 0 111 4>, + <0000 0 0 4 &gic 0 0 0 112 4>; + }; + + pcie at 3500000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x12 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 113 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, + <0000 0 0 2 &gic 0 0 0 115 4>, + <0000 0 0 3 &gic 0 0 0 116 4>, + <0000 0 0 4 &gic 0 0 0 117 4>; + }; + + pcie at 3600000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x14 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 118 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, + <0000 0 0 2 &gic 0 0 0 120 4>, + <0000 0 0 3 &gic 0 0 0 121 4>, + <0000 0 0 4 &gic 0 0 0 122 4>; + }; + + pcie at 3700000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x16 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 123 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, + <0000 0 0 2 &gic 0 0 0 125 4>, + <0000 0 0 3 &gic 0 0 0 126 4>, + <0000 0 0 4 &gic 0 0 0 127 4>; + }; + + sata0: sata at 3200000 { + compatible = "fsl,ls2080a-ahci", "fsl,ls1021a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>; + }; + + sata1: sata at 3210000 { + compatible = "fsl,ls2080a-ahci", "fsl,ls1021a-ahci"; + reg = <0x0 0x3210000 0x0 0x10000>; + interrupts = <0 136 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>; + }; + + usb0: usb3 at 3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + usb1: usb3 at 3110000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + ccn at 4000000 { + compatible = "arm,ccn-504"; + reg = <0x0 0x04000000 0x0 0x01000000>; + interrupts = <0 12 4>; }; }; --1.7.9.5
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Rob Herring
maintainerPATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
Quoted 45 lines · Bhupesh SHARMA
Hi Rob,
Quoted 30 lines · Rob Herring
Quoted 28 lines · Bhupesh Sharma
This patch updates the LS2085a DTSI (DTS Include) file to add support for various peripherals supported by FSL LS2085a SoC, for e.g.:
- USB 3.0 Host
- PMU
- CCN-504
- Watchdog
- SATA
- SPI
- PCIe
- etc.Signed-off-by Bhupesh Sharma <[email protected]>Signed-off-by Jaiprakash Singh <[email protected]>Signed-off-by Alison Wang <[email protected]>Signed-off-by Liu Gang <[email protected]>Signed-off-by Minghuan Lian <[email protected]>Signed-off-by Shaohui Xie <[email protected]>Signed-off-by Nikhil Badola <[email protected]>Signed-off-by Yangbo Lu <[email protected]>Signed-off-by Scott Wood <[email protected]>--- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 469 +++++++++++++++++++++++- 1 file changed, 459 insertions(+), 10 deletions(-)arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +0
-0[snip..]
Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 177
Quoted 6 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +2
-0@@ -139,25 +173,440 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */ }; + amba { + compatible = "arm,amba-bus";Use simple-bus. "arm,amba-bus" is meaningless.
Quoted 5 lines
Not sure I understand your comment here. Without this compatible in place I cannot see the '
drivers/amba/bus.c'amba_match()function getting called which in turn will call theamba_lookup()function,
thus invoking the probe function of thesp805_wdtdriver.
I'm not saying the devices are not amba_bustype devices. That has nothing to do with matching them. "arm,primecell" is what matters there. There is nothing visible to s/w about "arm,amba-bus," and it is ambiguous as there are multiple types of AMBA buses (APB, AHB, AXI). So unless you have bus level registers, use simple-bus. If you have doubts, try changing it and see that it still works.
Rob
A message that is not in the archive (sent off-list or not yet received): CALRxmdC9ZzGiw6CVnVTqhH1xvA-P9s8cpYbk8DoVq7CodFS0VA@mail.gmail.com
PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
Hi Rob,
Had a question about your comments on the patch below.
You singled out 3 nodes (gic,uart,clockgen) and said "This should be under a bus node."
What is special about those 3 nodes types? There are a bunch of other memory mapped SoC devices as well in the DTS.
I skimmed the dts files under arch/arm64 and it looks like most have a simple-bus SoC node like this where SoC devices are under:
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;Is that what you are looking for-- for all SoC devices?
Or, should I read in more to your comments that you want gic/uart/clockgen treated differently for some reason? If so, can you explain?
Thanks,
Stuart
Quoted 647 lines
-----Original Message-----
From: Rob Herring <[email protected]>
Date: Fri, Sep 4, 2015 at 4:15 PM
Subject: Re: [PATCH v2 07/10] dts/ls2085a: Update DTSI to add support of various peripherals
To: Bhupesh Sharma <[email protected]>
Cc: Mark Rutland <[email protected]>, Shaohui Xie <[email protected]>, Arnd Bergmann <[email protected]>, Alison Wang <[email protected]>, Marc Zyngier <[email protected]>, Catalin Marinas <[email protected]>, Olof Johansson <[email protected]>, Will Deacon <[email protected]>, Minghuan Lian <[email protected]>, Liu Gang <[email protected]>, Scott Wood <[email protected]>, Jaiprakash Singh <[email protected]>, Nikhil Badola <[email protected]>, bhupesh.linux at gmail.com, linux-clk at vger.kernel.org, "linux-arm-kernel at lists.infradead.org" <[email protected]>, Yangbo Lu <[email protected]>arch/arm64/boot/dts/freescale/fsl-
Quoted 25 lines · Bhupesh Sharma
This patch updates the LS2085a DTSI (DTS Include) file to add support for various peripherals supported by FSL LS2085a SoC, for e.g.:
- USB 3.0 Host
- PMU
- CCN-504
- Watchdog
- SATA
- SPI
- PCIe
- etc.Signed-off-by Bhupesh Sharma <[email protected]>Signed-off-by Jaiprakash Singh <[email protected]>Signed-off-by Alison Wang <[email protected]>Signed-off-by Liu Gang <[email protected]>Signed-off-by Minghuan Lian <[email protected]>Signed-off-by Shaohui Xie <[email protected]>Signed-off-by Nikhil Badola <[email protected]>Signed-off-by Yangbo Lu <[email protected]>Signed-off-by Scott Wood <[email protected]>--- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 469 +++++++++++++++++++++++- 1 file changed, 459 insertions(+), 10 deletions(-)arch/arm64/boot/dts/freescale/fsl- renamed from arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +0
-0
ls2080a.dtsiQuoted 73 lines
index 333d942..5fee0a7 100644
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +8
-5@@ -20,11 +20,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person@@ -71,48 +66,56 @@ device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; }; cpu at 1 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x1>; + clocks = <&clockgen 1 0>; }; cpu at 100 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x100>; + clocks = <&clockgen 1 1>; }; cpu at 101 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x101>; + clocks = <&clockgen 1 1>; }; cpu at 200 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x200>; + clocks = <&clockgen 1 2>; }; cpu at 201 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x201>; + clocks = <&clockgen 1 2>; }; cpu at 300 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x300>; + clocks = <&clockgen 1 3>; }; cpu at 301 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x301>; + clocks = <&clockgen 1 3>; }; };arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 133
Quoted 9 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +5
-0@@ -122,13 +125,44 @@ /* DRAM space - 1, size : 2 GB DRAM */ }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ + }; + gic: interrupt-controller at 6000000 {This should be under a bus node.
Quoted 12 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +7
-1compatible = "arm,gic-v3"; reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ + <0x0 0x0c0c0000 0 0x2000>, /* GICC */ + <0x0 0x0c0d0000 0 0x1000>, /* GICH */ + <0x0 0x0c0e0000 0 0x20000>; /* GICV */ #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; interrupt-controller;arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 154
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +9
-0interrupts = <1 9 0x4>; + + its: gic-its at 6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; + }; + + clockgen: clocking at 1300000 {This should be under a bus node.
Quoted 15 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +11
-0+ compatible = "fsl,ls2080a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; }; timer {arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 177
Quoted 5 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +2
-0@@ -139,25 +173,440 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */ }; + amba { + compatible = "arm,amba-bus";Use simple-bus. "arm,amba-bus" is meaningless.
Quoted 60 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +60
-0+ #address-cells = <2>; + #size-cells = <2>; + ranges; + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster1_core1_watchdog: wdt at c010000 { + compatible = "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster2_core0_watchdog: wdt at c100000 { + compatible = "arm,primecell"; + reg = <0x0 0xc100000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster2_core1_watchdog: wdt at c110000 { + compatible = "arm,primecell"; + reg = <0x0 0xc110000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster3_core0_watchdog: wdt at c200000 { + compatible = "arm,primecell"; + reg = <0x0 0xc200000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster3_core1_watchdog: wdt at c210000 { + compatible = "arm,primecell"; + reg = <0x0 0xc210000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster4_core0_watchdog: wdt at c300000 { + compatible = "arm,primecell"; + reg = <0x0 0xc300000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; +arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 247
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +9
-0+ cluster4_core1_watchdog: wdt at c310000 { + compatible = "arm,primecell"; + reg = <0x0 0xc310000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + }; + serial0: serial at 21c0500 {This too should be moved under a bus node.
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 248
Quoted 1 line
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +0
-0device_type = "serial";You should drop this.
Quoted 98 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +80
-4compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0500 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ + clocks = <&clockgen 4 3>; + interrupts = <0 32 0x4>; /* Level high type */ }; serial1: serial at 21c0600 { device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ + clocks = <&clockgen 4 3>; + interrupts = <0 32 0x4>; /* Level high type */ }; fsl_mc: fsl-mc at 80c000000 { compatible = "fsl,qoriq-mc"; + #stream-id-cells = <2>; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + lpi-parent = <&its>; + }; + + smmu: iommu at 5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #global-interrupts = <12>; + interrupts = <0 13 4>, /* global secure fault */ + <0 14 4>, /* combined secure interrupt */ + <0 15 4>, /* global non-secure fault */ + <0 16 4>, /* combined non-secure interrupt */ + /* performance counter interrupts 0-7 */ + <0 211 4>, + <0 212 4>, + <0 213 4>, + <0 214 4>, + <0 215 4>, + <0 216 4>, + <0 217 4>, + <0 218 4>, + /* per context interrupt, 64 interrupts */ + <0 146 4>, + <0 147 4>, + <0 148 4>, + <0 149 4>, + <0 150 4>, + <0 151 4>, + <0 152 4>, + <0 153 4>, + <0 154 4>, + <0 155 4>, + <0 156 4>, + <0 157 4>, + <0 158 4>, + <0 159 4>, + <0 160 4>, + <0 161 4>, + <0 162 4>, + <0 163 4>, + <0 164 4>, + <0 165 4>, + <0 166 4>, + <0 167 4>, + <0 168 4>, + <0 169 4>, + <0 170 4>, + <0 171 4>, + <0 172 4>, + <0 173 4>, + <0 174 4>, + <0 175 4>, + <0 176 4>, + <0 177 4>, + <0 178 4>, + <0 179 4>, + <0 180 4>, + <0 181 4>, + <0 182 4>, + <0 183 4>, + <0 184 4>, + <0 185 4>, + <0 186 4>, + <0 187 4>, + <0 188 4>, + <0 189 4>, + <0 190 4>, + <0 191 4>, + <0 192 4>, + <0 193 4>, + <0 194 4>, + <0 195 4>, + <0 196 4>, + <0 197 4>, + <0 198 4>, + <0 199 4>,arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 352
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ <0 200 4>, + <0 201 4>, + <0 202 4>, + <0 203 4>, + <0 204 4>, + <0 205 4>, + <0 206 4>, + <0 207 4>, + <0 208 4>, + <0 209 4>;Perhaps more than 1 per line.
Quoted 138 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +138
-0+ mmu-masters = <&fsl_mc 0x300 0>; + }; + + dspi: dspi at 2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; /* Level high type */ + tcfq-mode; + clocks = <&clockgen 4 3>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <0>; + spi-cpol; + spi-cpha; + }; + + esdhc: esdhc at 2140000 { + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + clock-frequency = <0>; /* Updated by bootloader */ + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; + bus-width = <4>; + }; + + gpio0: gpio at 2300000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio at 2310000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio at 2320000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 37 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio at 2330000 { + compatible = "fsl,ls2080a-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 37 0x4>; /* Level high type */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2c0: i2c at 2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c1: i2c at 2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c2: i2c at 2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + i2c3: i2c at 2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 0x4>; /* Level high type */ + clock-names = "i2c"; + clocks = <&clockgen 4 3>; + }; + + ifc: ifc at 2240000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x2240000 0x0 0x20000>; + interrupts = <0 21 0x4>; /* Level high type */ + little-endian; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0 0 0x5 0x80000000 0x08000000 + 2 0 0x5 0x30000000 0x00010000 + 3 0 0x5 0x20000000 0x00010000>; + }; + + qspi: quadspi at 20c0000 { + compatible = "fsl,vf610-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <0 25 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "qspi_en", "qspi"; + }; + + pcie at 3400000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x10 0x00000000 0x0 0x00001000>; /* configuration space */arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ reg-names = "regs", "config"; + interrupts = <0 108 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchablememory */
Quoted 13 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +13
-0+ msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, + <0000 0 0 2 &gic 0 0 0 110 4>, + <0000 0 0 3 &gic 0 0 0 111 4>, + <0000 0 0 4 &gic 0 0 0 112 4>; + }; + + pcie at 3500000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x12 0x00000000 0x0 0x00001000>; /* configuration space */arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ reg-names = "regs", "config"; + interrupts = <0 113 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchablememory */
Quoted 13 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +13
-0+ msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, + <0000 0 0 2 &gic 0 0 0 115 4>, + <0000 0 0 3 &gic 0 0 0 116 4>, + <0000 0 0 4 &gic 0 0 0 117 4>; + }; + + pcie at 3600000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x14 0x00000000 0x0 0x00001000>; /* configuration space */arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ reg-names = "regs", "config"; + interrupts = <0 118 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchablememory */
Quoted 13 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +13
-0+ msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, + <0000 0 0 2 &gic 0 0 0 120 4>, + <0000 0 0 3 &gic 0 0 0 121 4>, + <0000 0 0 4 &gic 0 0 0 122 4>; + }; + + pcie at 3700000 { + compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x16 0x00000000 0x0 0x00001000>; /* configuration space */arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ reg-names = "regs", "config"; + interrupts = <0 123 0x4>; /* Level high type */ + interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchablememory */
Quoted 48 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +41
-1+ msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, + <0000 0 0 2 &gic 0 0 0 125 4>, + <0000 0 0 3 &gic 0 0 0 126 4>, + <0000 0 0 4 &gic 0 0 0 127 4>; + }; + + sata0: sata at 3200000 { + compatible = "fsl,ls2080a-ahci", "fsl,ls1021a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>; + }; + + sata1: sata at 3210000 { + compatible = "fsl,ls2080a-ahci", "fsl,ls1021a-ahci"; + reg = <0x0 0x3210000 0x0 0x10000>; + interrupts = <0 136 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>; + }; + + usb0: usb3 at 3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + usb1: usb3 at 3110000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + ccn at 4000000 { + compatible = "arm,ccn-504"; + reg = <0x0 0x04000000 0x0 0x01000000>; + interrupts = <0 12 4>; }; }; --1.7.9.5
Quoted 4 lines
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PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
Quoted 12 lines · Stuart Yoder
Hi Rob,
Had a question about your comments on the patch below.
You singled out 3 nodes (gic,uart,clockgen) and said "This should be under a bus node."
What is special about those 3 nodes types? There are a bunch of other memory mapped SoC devices as well in the DTS.
I skimmed the dts files under
arch/arm64and it looks like most have a simple-bus SoC node like this where SoC devices are under:
Quoted 7 lines
soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges;Is that what you are looking for-- for all SoC devices?
I think the key is to have the soc node and have all the on-chip devices defined underneath it.
I read the following from the booting-without-of.txt document:
f) the /soc<SOCname> node
This node is used to represent a system-on-a-chip (SoC) and must be present if the processor is a SoC. The top-level soc node contains information that is global to all devices on the SoC. The node name should contain a unit address for the SoC, which is the base address of the memory-mapped register set for the SoC. The name of an SoC node should start with "soc", and the remainder of the name should represent the part number for the soc. For example, the MPC8540's soc node would be called "soc8540".
A lot of device trees didn't follow the soc<SOCname> naming scheme and just used "soc" as the node name. I am not sure if we want to enforce the naming in the future or update the document to make it more relax.
Regards,
Leo
PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
Quoted 41 lines · Li Yang
Quoted 15 lines · Stuart Yoder
Hi Rob,
Had a question about your comments on the patch below.
You singled out 3 nodes (gic,uart,clockgen) and said "This should be under a bus node."
What is special about those 3 nodes types? There are a bunch of other memory
mapped SoC devices as well in the DTS.I skimmed the dts files under
arch/arm64and it looks like most have a simple-bus
SoC node like this where SoC devices are under:Quoted 7 lines
soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges;Is that what you are looking for-- for all SoC devices?
I think the key is to have the soc node and have all the on-chip devices defined underneath it.
I read the following from the booting-without-of.txt document:
f) the /soc<SOCname> node
This node is used to represent a system-on-a-chip (SoC) and must be present if the processor is a SoC. The top-level soc node contains information that is global to all devices on the SoC. The node name should contain a unit address for the SoC, which is the base address of the memory-mapped register set for the SoC. The name of an SoC node should start with "soc", and the remainder of the name should represent the part number for the soc. For example, the MPC8540's soc node would be called "soc8540".
Quoted 3 lines
A lot of device trees didn't follow the soc<SOCname> naming scheme and just used "soc" as the node name. I am not sure if we want to enforce the naming in the future or update the document to make it more relax.
Update the document. Having the SoC name in the node name was a pain, which is why we don't do it anymore. Ideally, this text should be moved into a binding for Freescale PPC/LS SoCs. It really doesn't have the broad applicability that this historical document suggests, and even on our SoCs it doesn't represent the entire SoC. It represents CCSR/IMMR.
-Scott
PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
Quoted 46 lines · Scott Wood
Quoted 41 lines · Li Yang
Quoted 15 lines · Stuart Yoder
Hi Rob,
Had a question about your comments on the patch below.
You singled out 3 nodes (gic,uart,clockgen) and said "This should be under a bus node."
What is special about those 3 nodes types? There are a bunch of other memory
mapped SoC devices as well in the DTS.I skimmed the dts files under
arch/arm64and it looks like most have a simple-bus
SoC node like this where SoC devices are under:Quoted 7 lines
soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges;Is that what you are looking for-- for all SoC devices?
I think the key is to have the soc node and have all the on-chip devices defined underneath it.
I read the following from the booting-without-of.txt document:
f) the /soc<SOCname> node
This node is used to represent a system-on-a-chip (SoC) and must be present if the processor is a SoC. The top-level soc node contains information that is global to all devices on the SoC. The node name should contain a unit address for the SoC, which is the base address of the memory-mapped register set for the SoC. The name of an SoC node should start with "soc", and the remainder of the name should represent the part number for the soc. For example, the MPC8540's soc node would be called "soc8540".
Quoted 3 lines
A lot of device trees didn't follow the soc<SOCname> naming scheme and just used "soc" as the node name. I am not sure if we want to enforce the naming in the future or update the document to make it more relax.
Quoted 5 lines
Update the document. Having the SoC name in the node name was a pain, which is why we don't do it anymore. Ideally, this text should be moved into a binding for Freescale PPC/LS SoCs. It really doesn't have the broad applicability that this historical document suggests, and even on our SoCs it doesn't represent the entire SoC. It represents CCSR/IMMR.
Having the soc node to represent the CCSR space is a Freescale specific thing. But using the soc node to be the parent for all the on-chip devices seems to be a good practice for all device trees. I do think we should maintain a standard for the top level nodes of a device tree.
Regards,
Leo
PATCH v2 7/10 dts/ls2085a: Update DTSI to add support of various peripherals
Quoted 56 lines · Li Yang
Quoted 47 lines · Scott Wood
Quoted 42 lines · Li Yang
On Thu, Oct 1, 2015 at 3:05 PM, Stuart Yoder <[email protected]>
Quoted 15 lines · wrote:
Hi Rob,
Had a question about your comments on the patch below.
You singled out 3 nodes (gic,uart,clockgen) and said "This should be under a bus node."
What is special about those 3 nodes types? There are a bunch of other memory
mapped SoC devices as well in the DTS.I skimmed the dts files under
arch/arm64and it looks like most have a simple-bus
SoC node like this where SoC devices are under:Quoted 7 lines
soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges;Is that what you are looking for-- for all SoC devices?
I think the key is to have the soc node and have all the on-chip devices defined underneath it.
I read the following from the booting-without-of.txt document:
f) the /soc<SOCname> node
This node is used to represent a system-on-a-chip (SoC) and must be present if the processor is a SoC. The top-level soc node contains information that is global to all devices on the SoC. The node name should contain a unit address for the SoC, which is the base address of the memory-mapped register set for the SoC. The name of an SoC node should start with "soc", and the remainder of the name should represent the part number for the soc. For example, the MPC8540's soc node would be called "soc8540".
Quoted 3 lines
A lot of device trees didn't follow the soc<SOCname> naming scheme and just used "soc" as the node name. I am not sure if we want to enforce the naming in the future or update the document to make it more relax.
Quoted 7 lines
Update the document. Having the SoC name in the node name was a pain, which
is why we don't do it anymore. Ideally, this text should be moved into a binding for Freescale PPC/LS SoCs. It really doesn't have the broad applicability that this historical document suggests, and even on our SoCs it
doesn't represent the entire SoC. It represents CCSR/IMMR.
Quoted 5 lines
Having the soc node to represent the CCSR space is a Freescale specific thing. But using the soc node to be the parent for all the on-chip devices seems to be a good practice for all device trees. I do think we should maintain a standard for the top level nodes of a device tree.
But it doesn't represent all on-chip devices. E.g. DPAA portals don't go under it, because they're not part of CCSR. DCSR doesn't go under it, etc. If the definition doesn't even work for our own SoCs, how are we going to force it on everyone else's?
-Scott