vf610: refactor DDRMC code

PATCH New Albert ARIBAUD (3ADEV) 2 participants 6 messages Sep 21, 2015 – Oct 2, 2015

Subsystems (4)

Arm (32-bit) Arm i.MX and Layerscape Arm STM32 I2C

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Albert ARIBAUD (3ADEV)

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2015-09-21 20:43 UTC #0 lore raw

PATCH v2 1/3 vf610: refactor DDRMC code

The VF610 DDRMC driver code contains settings which are board-specific. Move these out to boards so that new boards can define their own without having to modify the driver.

Signed-off-by Albert ARIBAUD (3ADEV) <[email protected]>

---

Changes in v2:
- reverted from all-custom to JEDEC+PHY+custom settings

 arch/arm/imx-common/ddrmc-vf610.c             | 193 ++++++++++----------------
 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h |  40 ++++--
 arch/arm/include/asm/arch-vf610/imx-regs.h    |   6 +-
 board/freescale/vf610twr/vf610twr.c           | 156 ++++++++++++++-------
 board/toradex/colibri_vf/colibri_vf.c         | 144 +++++++++++++------
 5 files changed, 314 insertions(+), 225 deletions(-)

arch/arm/imx-common/ddrmc-vf610.c +76 ~~-117~~

index e462631..daf3c7e 100644
@@ -12,9 +12,9 @@
 #include <asm/arch/iomux-vf610.h>
 #include <asm/arch/ddrmc-vf610.h>
 
-void ddrmc_setup_iomux(void)
+void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
 {
-	static const iomux_v3_cfg_t ddr_pads[] = {
+	static const iomux_v3_cfg_t default_pads[] = {
 		VF610_PAD_DDR_A15__DDR_A_15,
 		VF610_PAD_DDR_A14__DDR_A_14,
 		VF610_PAD_DDR_A13__DDR_A_13,

@@ -65,76 +65,54 @@ void ddrmc_setup_iomux(void)
 		VF610_PAD_DDR_RESETB,
 	};
 
-	imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
-}
+	if ((pads == NULL) || (pads_count == 0)) {
+		pads = default_pads;
+		pads_count = ARRAY_SIZE(default_pads);
+	}
 
-void ddrmc_phy_init(void)
-{
-	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+	imx_iomux_v3_setup_multiple_pads(pads, pads_count);
+}
 
-	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
-	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
-	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
+static struct ddrmc_phy_setting default_phy_settings[] = {
+	{ DDRMC_PHY_DQ_TIMING,  0 },
+	{ DDRMC_PHY_DQ_TIMING, 16 },
+	{ DDRMC_PHY_DQ_TIMING, 32 },
 
-	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
-	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
+	{ DDRMC_PHY_DQS_TIMING,  1 },
+	{ DDRMC_PHY_DQS_TIMING, 17 },
 
-	writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
-	writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
-	writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
+	{ DDRMC_PHY_CTRL,  2 },
+	{ DDRMC_PHY_CTRL, 18 },
+	{ DDRMC_PHY_CTRL, 34 },
 
-	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
-	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
-	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
+	{ DDRMC_PHY_MASTER_CTRL,  3 },
+	{ DDRMC_PHY_MASTER_CTRL, 19 },
+	{ DDRMC_PHY_MASTER_CTRL, 35 },
 
-	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
-	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
-	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
+	{ DDRMC_PHY_SLAVE_CTRL,  4 },
+	{ DDRMC_PHY_SLAVE_CTRL, 20 },
+	{ DDRMC_PHY_SLAVE_CTRL, 36 },
 
 	/* LPDDR2 only parameter */
-	writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
+	{ DDRMC_PHY_OFF, 49 },
 
-	writel(DDRMC_PHY50_DDR3_MODE |
-		   DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]);
+	{ DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
 
 	/* Processor Pad ODT settings */
-	writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
-}
-
-static void ddrmc_ctrl_lvl_init(struct ddrmc_lvl_info *lvl)
-{
-	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
-	u32 cr102 = 0, cr105 = 0, cr106 = 0, cr110 = 0;
+	{ DDRMC_PHY_PROC_PAD_ODT, 52 },
 
-	if (lvl->wrlvl_reg_en) {
-		writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
-		writel(DDRMC_CR98_WRLVL_DL_0(lvl->wrlvl_dl_0), &ddrmr->cr[98]);
-		writel(DDRMC_CR99_WRLVL_DL_1(lvl->wrlvl_dl_1), &ddrmr->cr[99]);
-	}
-
-	if (lvl->rdlvl_reg_en) {
-		cr102 |= DDRMC_CR102_RDLVL_REG_EN;
-		cr105 |= DDRMC_CR105_RDLVL_DL_0(lvl->rdlvl_dl_0);
-		cr110 |= DDRMC_CR110_RDLVL_DL_1(lvl->rdlvl_dl_1);
-	}
-
-	if (lvl->rdlvl_gt_reg_en) {
-		cr102 |= DDRMC_CR102_RDLVL_GT_REGEN;
-		cr106 |= DDRMC_CR106_RDLVL_GTDL_0(lvl->rdlvl_gt_dl_0);
-		cr110 |= DDRMC_CR110_RDLVL_GTDL_1(lvl->rdlvl_gt_dl_1);
-	}
-
-	writel(cr102, &ddrmr->cr[102]);
-	writel(cr105, &ddrmr->cr[105]);
-	writel(cr106, &ddrmr->cr[106]);
-	writel(cr110, &ddrmr->cr[110]);
-}
+	/* end marker */
+	{ 0, -1 }
+};
 
 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
-						  struct ddrmc_lvl_info *lvl,
-						  int col_diff, int row_diff)
+			  struct ddrmc_cr_setting *board_cr_settings,
+			  struct ddrmc_phy_setting *board_phy_settings,
+			  int col_diff, int row_diff)
 {
 	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+	struct ddrmc_cr_setting *cr_setting;
+	struct ddrmc_phy_setting *phy_setting;
 
 	writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
 	writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);

@@ -144,7 +122,9 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 	writel(DDRMC_CR12_WRLAT(timings->wrlat) |
 		   DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
 	writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
-		   DDRMC_CR13_TCCD(timings->tccd), &ddrmr->cr[13]);
+		   DDRMC_CR13_TCCD(timings->tccd) |
+		   DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval),
+		   &ddrmr->cr[13]);
 	writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
 		   DDRMC_CR14_TWTR(timings->twtr) |
 		   DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);

@@ -156,18 +136,19 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 		   DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
 
 	writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
-	writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) |
-		   DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+	writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN |
+		   DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout),
+		   &ddrmr->cr[21]);
 
 	writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
-	writel(DDRMC_CR23_BSTLEN(3) |
+	writel(DDRMC_CR23_BSTLEN(timings->bstlen) |
 		   DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
 	writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
 
 	writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
 	writel(DDRMC_CR26_TREF(timings->tref) |
 		   DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
-	writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
+	writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]);
 	writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
 
 	writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);

@@ -177,7 +158,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 	writel(DDRMC_CR34_CKSRX(timings->cksrx) |
 		   DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
 
-	writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
+	writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]);
 	writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
 		   DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);

@@ -191,13 +172,14 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 	writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
 
 	writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
-	writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
+	writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]);
 
 	writel(DDRMC_CR73_APREBIT(timings->aprebit) |
 		   DDRMC_CR73_COL_DIFF(col_diff) |
 		   DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
 	writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
-		   DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
+		   DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) |
+		   DDRMC_CR74_AGE_CNT(timings->age_cnt),
 		   &ddrmr->cr[74]);
 	writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
 		   DDRMC_CR75_PLEN, &ddrmr->cr[75]);

@@ -205,13 +187,15 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 		   DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
 	writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
 		   DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
-	writel(DDRMC_CR78_Q_FULLNESS(7) |
+	writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
 		   DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
 	writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
 
 	writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
 
-	writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
+	writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) |
+		   DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0),
+		   &ddrmr->cr[87]);
 	writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
 	writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);

@@ -219,58 +203,33 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 	writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
 		   DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
 
-	if (lvl != NULL)
-		ddrmc_ctrl_lvl_init(lvl);
-
-	writel(DDRMC_CR117_AXI0_W_PRI(0) |
-		   DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]);
-	writel(DDRMC_CR118_AXI1_W_PRI(1) |
-		   DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]);
-
-	writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) |
-		   DDRMC_CR120_AXI0_PRI0_RPRI(2), &ddrmr->cr[120]);
-	writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) |
-		   DDRMC_CR121_AXI0_PRI2_RPRI(2), &ddrmr->cr[121]);
-	writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
-		   DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
-	writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
-		   DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
-	writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
-
-	writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
-	writel(DDRMC_CR132_WRLAT_ADJ(5) |
-		   DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]);
-	writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
-	writel(DDRMC_CR138_PHY_WRLV_MXDL(256) |
-		   DDRMC_CR138_PHYDRAM_CK_EN(1), &ddrmr->cr[138]);
-	writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
-		   DDRMC_CR139_PHY_WRLV_DLL(3) |
-		   DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]);
-	writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
-	writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) |
-		   DDRMC_CR143_RDLV_MXDL(128), &ddrmr->cr[143]);
-	writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
-		   DDRMC_CR144_PHY_RDLV_DLL(3) |
-		   DDRMC_CR144_PHY_RDLV_EN(3), &ddrmr->cr[144]);
-	writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
-	writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
-	writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
-	writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
-	writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
-		   DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
-
-	writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
-		   DDRMC_CR154_PAD_ZQ_MODE(1) |
-		   DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
-		   DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
-	writel(DDRMC_CR155_PAD_ODT_BYTE1(2) |
-		   DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]);
-	writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
-	writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
-		   DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
-
-	ddrmc_phy_init();
+	/* execute custom CR setting sequence (may be NULL) */
+	cr_setting = board_cr_settings;
+	if (cr_setting != NULL)
+		while (cr_setting->cr_rnum >= 0) {
+			writel(cr_setting->setting,
+			       &ddrmr->cr[cr_setting->cr_rnum]);
+			cr_setting++;
+		}
+
+	/* perform default PHY settings (may be overriden by custom settings */
+	phy_setting = default_phy_settings;
+	while (phy_setting->phy_rnum >= 0) {
+		writel(phy_setting->setting,
+		       &ddrmr->phy[phy_setting->phy_rnum]);
+		phy_setting++;
+	}
+
+	/* execute custom PHY setting sequence (may be NULL) */
+	phy_setting = board_phy_settings;
+	if (phy_setting != NULL)
+		while (phy_setting->phy_rnum >= 0) {
+			writel(phy_setting->setting,
+			       &ddrmr->phy[phy_setting->phy_rnum]);
+			phy_setting++;
+		}
 
+	/* all inits done, start the DDR controller */
 	writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
 
 	while (!(readl(&ddrmr->cr[80]) && 0x100))

arch/arm/include/asm/arch-vf610/ddrmc-vf610.h +25 ~~-15~~

index 6730cde..9022c46 100644
@@ -11,18 +11,6 @@
 #ifndef __ASM_ARCH_VF610_DDRMC_H
 #define __ASM_ARCH_VF610_DDRMC_H
 
-struct ddrmc_lvl_info {
-	u16 wrlvl_reg_en;
-	u16 wrlvl_dl_0;
-	u16 wrlvl_dl_1;
-	u16 rdlvl_gt_reg_en;
-	u16 rdlvl_gt_dl_0;
-	u16 rdlvl_gt_dl_1;
-	u16 rdlvl_reg_en;
-	u16 rdlvl_dl_0;
-	u16 rdlvl_dl_1;
-};
-
 struct ddr3_jedec_timings {
 	u8 tinit;
 	u32 trst_pwron;

@@ -32,6 +20,7 @@ struct ddr3_jedec_timings {
 	u8 trc;
 	u8 trrd;
 	u8 tccd;
+	u8 tbst_int_interval;
 	u8 tfaw;
 	u8 trp;
 	u8 twtr;

@@ -43,30 +32,51 @@ struct ddr3_jedec_timings {
 	u8 tckesr;
 	u8 tcke;
 	u8 trcd_int;
+	u8 tras_lockout;
 	u8 tdal;
+	u8 bstlen;
 	u16 tdll;
 	u8 trp_ab;
 	u16 tref;
 	u8 trfc;
+	u16 tref_int;
 	u8 tpdex;
 	u8 txpdll;
 	u8 txsnr;
 	u16 txsr;
 	u8 cksrx;
 	u8 cksre;
+	u8 freq_chg_en;
 	u16 zqcl;
 	u16 zqinit;
 	u8 zqcs;
 	u8 ref_per_zq;
+	u8 zqcs_rotate;
 	u8 aprebit;
+	u8 cmd_age_cnt;
+	u8 age_cnt;
+	u8 q_fullness;
+	u8 odt_rd_mapcs0;
+	u8 odt_wr_mapcs0;
 	u8 wlmrd;
 	u8 wldqsen;
 };
 
-void ddrmc_setup_iomux(void);
+struct ddrmc_cr_setting {
+	u32	setting;
+	int	cr_rnum; /* CR register ; -1 for last entry */
+};
+
+struct ddrmc_phy_setting {
+	u32	setting;
+	int	phy_rnum; /* PHY register ; -1 for last entry */
+};
+
+void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count);
 void ddrmc_phy_init(void);
 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
-						  struct ddrmc_lvl_info *lvl,
-						  int col_diff, int row_diff);
+			  struct ddrmc_cr_setting *board_cr_settings,
+			  struct ddrmc_phy_setting *board_phy_settings,
+			  int col_diff, int row_diff);
 
 #endif

arch/arm/include/asm/arch-vf610/imx-regs.h +3 -3

index 4366985..9758323 100644
@@ -148,7 +148,7 @@
 #define DDRMC_CR18_TCKE(v)				((v) & 0x7)
 #define DDRMC_CR20_AP_EN				(1 << 24)
 #define DDRMC_CR21_TRCD_INT(v)				(((v) & 0xff) << 16)
-#define DDRMC_CR21_TRAS_LOCKOUT				(1 << 8)
+#define DDRMC_CR21_TRAS_LOCKOUT(v)			((v) << 8)
 #define DDRMC_CR21_CCMAP_EN				1
 #define DDRMC_CR22_TDAL(v)				(((v) & 0x3f) << 16)
 #define DDRMC_CR23_BSTLEN(v)				(((v) & 0x7) << 24)

@@ -200,8 +200,8 @@
 #define DDRMC_CR78_BUR_ON_FLY_BIT(v)			((v) & 0xf)
 #define DDRMC_CR79_CTLUPD_AREF(v)			(((v) & 0x1) << 24)
 #define DDRMC_CR82_INT_MASK				0x10000000
-#define DDRMC_CR87_ODT_WR_MAPCS0			(1 << 24)
-#define DDRMC_CR87_ODT_RD_MAPCS0			(1 << 16)
+#define DDRMC_CR87_ODT_WR_MAPCS0(v)			((v) << 24)
+#define DDRMC_CR87_ODT_RD_MAPCS0(v)			((v) << 16)
 #define DDRMC_CR88_TODTL_CMD(v)				(((v) & 0x1f) << 16)
 #define DDRMC_CR89_AODT_RWSMCS(v)			((v) & 0xf)
 #define DDRMC_CR91_R2W_SMCSDL(v)			(((v) & 0x7) << 16)

board/freescale/vf610twr/vf610twr.c +105 ~~-51~~

168 lines not on this page · raw message

board/toradex/colibri_vf/colibri_vf.c +105 ~~-39~~

159 lines not on this page · raw message

Signature · 1 line

2.1.4

Albert ARIBAUD (3ADEV)

author

2015-09-21 20:43 UTC #1 lore raw

PATCH v2 2/3 I2C: mxc_i2c: make I2C1 and I2C2 optional

The driver assumed that I2C1 and I2C2 were always enabled, and if they were not, then an asynchronous abort was (silently) raised, to be caught much later on in the Linux kernel.

Fix this by making I2C1 and I2C2 optional just like I2C3 and I2C4 are.

To make the change binary-invariant, declare I2C1 and I2C2 in every include/configs/ file which defines CONFIG_SYS_I2C_MXC.

Also, while updating README about CONFIG_SYS_I2C_MXC_I2C1 and CONFIG_SYS_I2C_MXC_I2C2, add missing descriptions for I2C4 speed (CONFIG_SYS_MXC_I2C4_SPEED) and slave (CONFIG_SYS_MXC_I2C4_SLAVE) config options.

Signed-off-by Albert ARIBAUD (3ADEV) <[email protected]>

---

Changes in v2:
- Make MXC I2C1 and I2C2 optional

 README                                | 8 ++++++--
 drivers/i2c/mxc_i2c.c                 | 6 ++++++
 include/configs/apf27.h               | 2 ++
 include/configs/aristainetos-common.h | 2 ++
 include/configs/cgtqmx6eval.h         | 2 ++
 include/configs/cm_fx6.h              | 2 ++
 include/configs/embestmx6boards.h     | 2 ++
 include/configs/flea3.h               | 2 ++
 include/configs/gw_ventana.h          | 2 ++
 include/configs/imx31_phycore.h       | 2 ++
 include/configs/ls1021aqds.h          | 2 ++
 include/configs/ls1021atwr.h          | 2 ++
 include/configs/ls2085a_common.h      | 2 ++
 include/configs/m53evk.h              | 2 ++
 include/configs/mx25pdk.h             | 2 ++
 include/configs/mx35pdk.h             | 2 ++
 include/configs/mx53ard.h             | 2 ++
 include/configs/mx53evk.h             | 2 ++
 include/configs/mx53loco.h            | 2 ++
 include/configs/mx53smd.h             | 2 ++
 include/configs/mx6qsabreauto.h       | 2 ++
 include/configs/mx6sabresd.h          | 2 ++
 include/configs/mx6slevk.h            | 2 ++
 include/configs/mx6sxsabresd.h        | 2 ++
 include/configs/mx6ul_14x14_evk.h     | 2 ++
 include/configs/mx7dsabresd.h         | 2 +-
 include/configs/nitrogen6x.h          | 2 ++
 include/configs/novena.h              | 2 ++
 include/configs/ot1200.h              | 2 ++
 include/configs/platinum.h            | 2 ++
 include/configs/tbs2910.h             | 2 ++
 include/configs/titanium.h            | 2 ++
 include/configs/tqma6.h               | 2 ++
 include/configs/usbarmory.h           | 2 ++
 include/configs/vf610twr.h            | 2 ++
 include/configs/wandboard.h           | 2 ++
 include/configs/warp.h                | 2 ++
 include/configs/woodburn_common.h     | 2 ++
 38 files changed, 83 insertions(+), 3 deletions(-)

README +6 -2

index a13705a..c22b60b 100644
@@ -2359,16 +2359,20 @@ CBFS (Coreboot Filesystem) support
 
 		- drivers/i2c/i2c_mxc.c
 		  - activate this driver with CONFIG_SYS_I2C_MXC
+		  - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1
+		  - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2
+		  - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
+		  - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
 		  - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
 		  - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
 		  - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
 		  - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
 		  - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
 		  - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
+		  - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED
+		  - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE
 		If those defines are not set, default value is 100000
 		for speed, and 0 for slave.
-		  - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
-		  - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
 
 		- drivers/i2c/rcar_i2c.c:
 		  - activate this driver with CONFIG_SYS_I2C_RCAR

drivers/i2c/mxc_i2c.c +6 -0

index f1056e2..0f977d7 100644
@@ -612,16 +612,22 @@ static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 /*
  * Register mxc i2c adapters
  */
+#ifdef CONFIG_SYS_I2C_MXC_I2C1
 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
 			 mxc_i2c_read, mxc_i2c_write,
 			 mxc_i2c_set_bus_speed,
 			 CONFIG_SYS_MXC_I2C1_SPEED,
 			 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
+#endif
+
+#ifdef CONFIG_SYS_I2C_MXC_I2C2
 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
 			 mxc_i2c_read, mxc_i2c_write,
 			 mxc_i2c_set_bus_speed,
 			 CONFIG_SYS_MXC_I2C2_SPEED,
 			 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
+#endif
+
 #ifdef CONFIG_SYS_I2C_MXC_I2C3
 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
 			 mxc_i2c_read, mxc_i2c_write,

include/configs/apf27.h +2 -0

index 43fbdd3..49fbcac 100644
@@ -317,6 +317,8 @@
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_MXC_I2C1_SPEED	100000	/* 100 kHz */
 #define CONFIG_SYS_MXC_I2C1_SLAVE	0x7F
 #define CONFIG_SYS_MXC_I2C2_SPEED	100000	/* 100 kHz */

include/configs/aristainetos-common.h +2 -0

index 20afdd6..f03297e 100644
@@ -189,6 +189,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_SYS_I2C_SLAVE		0x7f

include/configs/cgtqmx6eval.h +2 -0

index c7d54ee..5b6a4a5 100644
@@ -39,6 +39,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_SPEED		  100000

include/configs/cm_fx6.h +2 -0

index 12734a1..0513204 100644
@@ -198,6 +198,8 @@
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_SYS_MXC_I2C3_SPEED	400000

include/configs/embestmx6boards.h +2 -0

index 58cee96..f55ba9f 100644
@@ -33,6 +33,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000

include/configs/flea3.h +2 -0

index 5b4b011..f646fee 100644
@@ -52,6 +52,8 @@
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_SPD_BUS_NUM		2 /* I2C3 */
 #define CONFIG_SYS_MXC_I2C3_SLAVE	0xfe

include/configs/gw_ventana.h +2 -0

index 231bea7..484d763 100644
@@ -107,6 +107,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_I2C_GSC			0

include/configs/imx31_phycore.h +2 -0

index 86f327c..3bea71b 100644
@@ -38,6 +38,8 @@
 
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_CLK_OFFSET	I2C2_CLK_OFFSET

include/configs/ls1021aqds.h +2 -0

index b44f326..f73900f 100644
@@ -389,6 +389,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 
 /*

include/configs/ls1021atwr.h +2 -0

index 7dcb719..f6bd5fc 100644
@@ -275,6 +275,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 
 /* EEPROM */

include/configs/ls2085a_common.h +2 -0

index 2dbb5f7..55b909c 100644
@@ -97,6 +97,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */

include/configs/m53evk.h +2 -0

index 35058e2..8853d8f 100644
@@ -172,6 +172,8 @@
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_RTC_BUS_NUM		1 /* I2C2 */
 #endif

include/configs/mx25pdk.h +2 -0

index bd7216e..0414086 100644
@@ -115,6 +115,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 
 /* RTC */
 #define CONFIG_RTC_IMXDI

include/configs/mx35pdk.h +2 -0

index c9983f3..6bfdaa6 100644
@@ -42,6 +42,8 @@
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO

include/configs/mx53ard.h +2 -0

index 0479195..b889c25 100644
@@ -48,6 +48,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 
 /* MMC Configs */

include/configs/mx53evk.h +2 -0

index 82c8af8..4f304ed 100644
@@ -41,6 +41,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 
 /* PMIC Configs */

include/configs/mx53loco.h +2 -0

index ad2629d..3a65861 100644
@@ -76,6 +76,8 @@
 /* I2C Configs */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 
 /* PMIC Controller */

include/configs/mx53smd.h +2 -0

index bcdb054..e46f2ee 100644
@@ -38,6 +38,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 
 /* MMC Configs */

include/configs/mx6qsabreauto.h +2 -0

index 11cf538..1c99805 100644
@@ -51,6 +51,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000

include/configs/mx6sabresd.h +2 -0

index 5f635ca..e9e3b27 100644
@@ -44,6 +44,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		  100000

include/configs/mx6slevk.h +2 -0

index 51b297a..ae39503 100644
@@ -35,6 +35,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		  100000

include/configs/mx6sxsabresd.h +2 -0

index 381eaa2..edf7d3f 100644
@@ -127,6 +127,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		  100000

include/configs/mx6ul_14x14_evk.h +2 -0

index 465ddee..d5faae6 100644
@@ -54,6 +54,8 @@
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_SPEED		100000
 
 /* PMIC only for 9X9 EVK */

include/configs/mx7dsabresd.h +1 -1

index ec6e0a6..f39c786 100644
@@ -48,7 +48,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
 #define CONFIG_SYS_I2C_SPEED		100000
 
 #define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */

include/configs/nitrogen6x.h +2 -0

index dd4cb0f..b113771 100644
@@ -43,6 +43,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_I2C_EDID

include/configs/novena.h +2 -0

index 0970fd7..cd426be 100644
@@ -102,6 +102,8 @@
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_MXC

include/configs/ot1200.h +2 -0

index 0d06fce..426ec72 100644
@@ -44,6 +44,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED            100000

include/configs/platinum.h +2 -0

index d651432..bb7e845 100644
@@ -45,6 +45,8 @@
 /* I2C config */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED			100000

include/configs/tbs2910.h +2 -0

index 70b4403..8371fe9 100644
@@ -167,6 +167,8 @@
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_I2C_EDID

include/configs/titanium.h +2 -0

index 1b4ca29..acfa84a 100644
@@ -33,6 +33,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000

include/configs/tqma6.h +2 -0

index f7fade1..295e163 100644
@@ -62,6 +62,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_SYS_I2C_SPEED		100000

include/configs/usbarmory.h +2 -0

index 4a7702c..714e3e2 100644
@@ -67,6 +67,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 
 /* Fuse */
 #define CONFIG_CMD_FUSE

include/configs/vf610twr.h +2 -0

index c5131af..324ba8f 100644
@@ -110,6 +110,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_SPD_BUS_NUM		0
 
 #define CONFIG_BOOTDELAY		3

include/configs/wandboard.h +2 -0

index f4e9cf2..6e8aec2 100644
@@ -37,6 +37,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000

include/configs/warp.h +2 -0

index fa102bb..3e9a5a3 100644
@@ -98,6 +98,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_SPEED		  100000
 
 /* PMIC */

include/configs/woodburn_common.h +2 -0

index 5d9f529..fc46565 100644
@@ -47,6 +47,8 @@
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_SPD_BUS_NUM		0
 #define CONFIG_MXC_SPI

Signature · 1 line

2.1.4

Albert ARIBAUD (3ADEV)

author

2015-09-21 20:43 UTC #2 lore raw

PATCH v2 3/3 vf610: add support for Phytec PCM052

Devices supported are:
- NFC (NAND FLASH)
- MMC
- QSPI (SPI NOR FLASH)
- I2C (only bus 2)
- I2C RTC
- I2C EEPROM
- FEC

Patch-series: 2
- remove useless CONFIG_SYS_SPD_BUS_NUM from config
- remove include of config_cmd_default.h
- remove duplicate CONFIG_CMD_NET

Signed-off-by Albert ARIBAUD (3ADEV) <[email protected]>

---

Changes in v2: None

 arch/arm/Kconfig                 |   5 +
 board/phytec/pcm052/Kconfig      |  15 ++
 board/phytec/pcm052/MAINTAINERS  |   6 +
 board/phytec/pcm052/Makefile     |   7 +
 board/phytec/pcm052/imximage.cfg |  17 ++
 board/phytec/pcm052/pcm052.c     | 515 +++++++++++++++++++++++++++++++++++++++
 configs/pcm052_defconfig         |   6 +
 include/configs/pcm052.h         | 231 ++++++++++++++++++
 8 files changed, 802 insertions(+)
 create mode 100644 board/phytec/pcm052/Kconfig
 create mode 100644 board/phytec/pcm052/MAINTAINERS
 create mode 100644 board/phytec/pcm052/Makefile
 create mode 100644 board/phytec/pcm052/imximage.cfg
 create mode 100644 board/phytec/pcm052/pcm052.c
 create mode 100644 configs/pcm052_defconfig
 create mode 100644 include/configs/pcm052.h

arch/arm/Kconfig +5 -0

index c4371c7..341320c 100644
@@ -538,6 +538,10 @@ config TARGET_COLIBRI_VF
 	bool "Support Colibri VF50/61"
 	select CPU_V7
 
+config TARGET_PCM052
+	bool "Support pcm-052"
+	select CPU_V7
+
 config ARCH_ZYNQ
 	bool "Xilinx Zynq Platform"
 	select CPU_V7

@@ -751,6 +755,7 @@ source "board/maxbcm/Kconfig"
 source "board/mpl/vcma9/Kconfig"
 source "board/olimex/mx23_olinuxino/Kconfig"
 source "board/phytec/pcm051/Kconfig"
+source "board/phytec/pcm052/Kconfig"
 source "board/ppcag/bg0900/Kconfig"
 source "board/samsung/smdk2410/Kconfig"
 source "board/sandisk/sansa_fuze_plus/Kconfig"

board/phytec/pcm052/Kconfig new file +15 -0

new file mode 100644
index 0000000..d67a69a
@@ -0,0 +1,15 @@
+if TARGET_PCM052
+
+config SYS_BOARD
+	default "pcm052"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_SOC
+	default "vf610"
+
+config SYS_CONFIG_NAME
+	default "pcm052"
+
+endif

board/phytec/pcm052/MAINTAINERS new file +6 -0

new file mode 100644
index 0000000..a877436
@@ -0,0 +1,6 @@
+PCM052 BOARD
+M:	Albert ARIBAUD (3ADEV) <[email protected]>
+S:	Maintained
+F:	board/phytec/pcm052/
+F:	include/configs/pcm052.h
+F:	configs/pcm052_defconfig

board/phytec/pcm052/Makefile new file +7 -0

new file mode 100644
index 0000000..144f4e7
@@ -0,0 +1,7 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= pcm052.o

board/phytec/pcm052/imximage.cfg new file +17 -0

new file mode 100644
index 0000000..f5a9747
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2015 3ADEV <http://www.3adev.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION	2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSET	FLASH_OFFSET_STANDARD

board/phytec/pcm052/pcm052.c new file +515 -0

515 lines not on this page · raw message

configs/pcm052_defconfig new file +6 -0

new file mode 100644
index 0000000..e8dc402
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_PCM052=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_NAND_VF610_NFC=y
+CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES=y

include/configs/pcm052.h new file +231 -0

231 lines not on this page · raw message

Signature · 1 line

2.1.4

Stefano Babic

2015-10-02 08:43 UTC #3 lore raw

PATCH v2 3/3 vf610: add support for Phytec PCM052

Quoted 9 lines · On 21/09/2015 22:43, Albert ARIBAUD (3ADEV) wrote:

Devices supported are:
- NFC (NAND FLASH)
- MMC
- QSPI (SPI NOR FLASH)
- I2C (only bus 2)
- I2C RTC
- I2C EEPROM
- FEC

Quoted 7 lines

Patch-series: 2
- remove useless CONFIG_SYS_SPD_BUS_NUM from config
- remove include of config_cmd_default.h
- remove duplicate CONFIG_CMD_NET
Signed-off-by Albert ARIBAUD (3ADEV) <[email protected]>
---

Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2015-10-02 08:43 UTC #4 lore raw

PATCH v2 2/3 I2C: mxc_i2c: make I2C1 and I2C2 optional

In reply to Albert ARIBAUD (3ADEV)

Quoted 10 lines · On 21/09/2015 22:43, Albert ARIBAUD (3ADEV) wrote:

The driver assumed that I2C1 and I2C2 were always enabled, and if they were not, then an asynchronous abort was (silently) raised, to be caught much later on in the Linux kernel.
Fix this by making I2C1 and I2C2 optional just like I2C3 and I2C4 are.
To make the change binary-invariant, declare I2C1 and I2C2 in every include/configs/ file which defines CONFIG_SYS_I2C_MXC.

Quoted 7 lines

Also, while updating README about CONFIG_SYS_I2C_MXC_I2C1 and CONFIG_SYS_I2C_MXC_I2C2, add missing descriptions for I2C4 speed (CONFIG_SYS_MXC_I2C4_SPEED) and slave (CONFIG_SYS_MXC_I2C4_SLAVE) config options.
Signed-off-by Albert ARIBAUD (3ADEV) <[email protected]>
---

Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2015-10-02 08:38 UTC #5 lore raw

PATCH v2 1/3 vf610: refactor DDRMC code

In reply to Albert ARIBAUD (3ADEV)

Quoted 6 lines · On 21/09/2015 22:43, Albert ARIBAUD (3ADEV) wrote:

The VF610 DDRMC driver code contains settings which are board-specific. Move these out to boards so that new boards can define their own without having to modify the driver.
Signed-off-by Albert ARIBAUD (3ADEV) <[email protected]>
---

Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================