ARM: tegra: rename dummy XUSB padctl implementation

similarity index 100%
rename from arch/arm/mach-tegra/xusb-padctl.c
rename to arch/arm/mach-tegra/xusb-padctl-dummy.c

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index 709b02e1b7f7..ed6c1456bc71 100644
@@ -8,16 +8,9 @@
 
 #include <common.h>
 #include <errno.h>
-#include <fdtdec.h>
-#include <malloc.h>
 
 #include "../xusb-padctl-common.h"
 
-#include <asm/io.h>
-
-#include <asm/arch/clock.h>
-#include <asm/arch-tegra/xusb-padctl.h>
-
 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
 
 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c

@@ -302,68 +295,27 @@ static const struct tegra_xusb_phy_ops sata_phy_ops = {
 	.unprepare = phy_unprepare,
 };
 
-struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
-	.phys = {
-		[0] = {
-			.ops = &pcie_phy_ops,
-		},
-		[1] = {
-			.ops = &sata_phy_ops,
-		},
+static struct tegra_xusb_phy tegra124_phys[] = {
+	{
+		.type = TEGRA_XUSB_PADCTL_PCIE,
+		.ops = &pcie_phy_ops,
+		.padctl = &padctl,
+	},
+	{
+		.type = TEGRA_XUSB_PADCTL_SATA,
+		.ops = &sata_phy_ops,
+		.padctl = &padctl,
 	},
 };
 
-int process_nodes(const void *fdt, int nodes[], unsigned int count)
-{
-	unsigned int i;
-
-	for (i = 0; i < count; i++) {
-		enum fdt_compat_id id;
-		int err;
-
-		if (!fdtdec_get_is_enabled(fdt, nodes[i]))
-			continue;
-
-		id = fdtdec_lookup(fdt, nodes[i]);
-		switch (id) {
-		case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
-			break;
-
-		default:
-			error("tegra-xusb-padctl: unsupported compatible: %s",
-			      fdtdec_get_compatible(id));
-			continue;
-		}
-
-		padctl->num_lanes = ARRAY_SIZE(tegra124_lanes);
-		padctl->lanes = tegra124_lanes;
-
-		padctl->num_functions = ARRAY_SIZE(tegra124_functions);
-		padctl->functions = tegra124_functions;
-
-		err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
-		if (err < 0) {
-			error("tegra-xusb-padctl: failed to parse DT: %d",
-			      err);
-			continue;
-		}
-
-		/* deassert XUSB padctl reset */
-		reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
-
-		err = tegra_xusb_padctl_config_apply(padctl, &padctl->config);
-		if (err < 0) {
-			error("tegra-xusb-padctl: failed to apply pinmux: %d",
-			      err);
-			continue;
-		}
-
-		/* only a single instance is supported */
-		break;
-	}
-
-	return 0;
-}
+static const struct tegra_xusb_padctl_soc tegra124_socdata = {
+	.lanes = tegra124_lanes,
+	.num_lanes = ARRAY_SIZE(tegra124_lanes),
+	.functions = tegra124_functions,
+	.num_functions = ARRAY_SIZE(tegra124_functions),
+	.phys = tegra124_phys,
+	.num_phys = ARRAY_SIZE(tegra124_phys),
+};
 
 void tegra_xusb_padctl_init(const void *fdt)
 {

@@ -372,6 +324,6 @@ void tegra_xusb_padctl_init(const void *fdt)
 	count = fdtdec_find_aliases_for_id(fdt, "padctl",
 					   COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
 					   nodes, ARRAY_SIZE(nodes));
-	if (process_nodes(fdt, nodes, count))
+	if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra124_socdata))
 		return;
 }

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index a65b754f6b7d..11ecb99b749d 100644
@@ -33,8 +33,8 @@ struct tegra_xusb_phy_ops {
 };
 
 struct tegra_xusb_phy {
+	unsigned int type;
 	const struct tegra_xusb_phy_ops *ops;
-
 	struct tegra_xusb_padctl *padctl;
 };
 

@@ -58,6 +58,15 @@ struct tegra_xusb_padctl_group {
 	int iddq;
 };
 
+struct tegra_xusb_padctl_soc {
+	const struct tegra_xusb_padctl_lane *lanes;
+	unsigned int num_lanes;
+	const char *const *functions;
+	unsigned int num_functions;
+	struct tegra_xusb_phy *phys;
+	unsigned int num_phys;
+};
+
 struct tegra_xusb_padctl_config {
 	const char *name;
 

@@ -66,20 +75,13 @@ struct tegra_xusb_padctl_config {
 };
 
 struct tegra_xusb_padctl {
+	const struct tegra_xusb_padctl_soc *socdata;
+	struct tegra_xusb_padctl_config config;
 	struct fdt_resource regs;
-
 	unsigned int enable;
 
-	struct tegra_xusb_phy phys[2];
-
-	const struct tegra_xusb_padctl_lane *lanes;
-	unsigned int num_lanes;
-
-	const char *const *functions;
-	unsigned int num_functions;
-
-	struct tegra_xusb_padctl_config config;
 };
+extern struct tegra_xusb_padctl padctl;
 
 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
 			       unsigned long offset)

@@ -93,11 +95,7 @@ static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
 	writel(value, padctl->regs.start + offset);
 }
 
-extern struct tegra_xusb_padctl *padctl;
-
-int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
-			       const void *fdt, int node);
-int tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
-				   struct tegra_xusb_padctl_config *config);
+int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count,
+	const struct tegra_xusb_padctl_soc *socdata);
 
 #endif

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index 503354344067..6022f1614bda 100644
@@ -15,6 +15,76 @@
 
 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
 
+enum tegra210_function {
+	TEGRA210_FUNC_SNPS,
+	TEGRA210_FUNC_XUSB,
+	TEGRA210_FUNC_UART,
+	TEGRA210_FUNC_PCIE_X1,
+	TEGRA210_FUNC_PCIE_X4,
+	TEGRA210_FUNC_USB3,
+	TEGRA210_FUNC_SATA,
+	TEGRA210_FUNC_RSVD,
+};
+
+static const char *const tegra210_functions[] = {
+	"snps",
+	"xusb",
+	"uart",
+	"pcie-x1",
+	"pcie-x4",
+	"usb3",
+	"sata",
+	"rsvd",
+};
+
+static const unsigned int tegra210_otg_functions[] = {
+	TEGRA210_FUNC_SNPS,
+	TEGRA210_FUNC_XUSB,
+	TEGRA210_FUNC_UART,
+	TEGRA210_FUNC_RSVD,
+};
+
+static const unsigned int tegra210_usb_functions[] = {
+	TEGRA210_FUNC_SNPS,
+	TEGRA210_FUNC_XUSB,
+};
+
+static const unsigned int tegra210_pci_functions[] = {
+	TEGRA210_FUNC_PCIE_X1,
+	TEGRA210_FUNC_USB3,
+	TEGRA210_FUNC_SATA,
+	TEGRA210_FUNC_PCIE_X4,
+};
+
+#define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs)	\
+	{								\
+		.name = _name,						\
+		.offset = _offset,					\
+		.shift = _shift,					\
+		.mask = _mask,						\
+		.iddq = _iddq,						\
+		.num_funcs = ARRAY_SIZE(tegra210_##_funcs##_functions),	\
+		.funcs = tegra210_##_funcs##_functions,			\
+	}
+
+static const struct tegra_xusb_padctl_lane tegra210_lanes[] = {
+	TEGRA210_LANE("otg-0",     0x004,  0, 0x3, 0, otg),
+	TEGRA210_LANE("otg-1",     0x004,  2, 0x3, 0, otg),
+	TEGRA210_LANE("otg-2",     0x004,  4, 0x3, 0, otg),
+	TEGRA210_LANE("otg-3",     0x004,  6, 0x3, 0, otg),
+	TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg),
+	TEGRA210_LANE("hsic-0",    0x004, 14, 0x1, 0, usb),
+	TEGRA210_LANE("hsic-1",    0x004, 15, 0x1, 0, usb),
+	TEGRA210_LANE("pcie-0",    0x028, 12, 0x3, 1, pci),
+	TEGRA210_LANE("pcie-1",    0x028, 14, 0x3, 2, pci),
+	TEGRA210_LANE("pcie-2",    0x028, 16, 0x3, 3, pci),
+	TEGRA210_LANE("pcie-3",    0x028, 18, 0x3, 4, pci),
+	TEGRA210_LANE("pcie-4",    0x028, 20, 0x3, 5, pci),
+	TEGRA210_LANE("pcie-5",    0x028, 22, 0x3, 6, pci),
+	TEGRA210_LANE("pcie-6",    0x028, 24, 0x3, 7, pci),
+	TEGRA210_LANE("sata-0",    0x028, 30, 0x3, 8, pci),
+};
+
 #define XUSB_PADCTL_ELPG_PROGRAM 0x024
 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)

@@ -328,10 +398,10 @@ static struct tegra_xusb_phy tegra210_phys[] = {
 };
 
 static const struct tegra_xusb_padctl_soc tegra210_socdata = {
-	.lanes = NULL,
-	.num_lanes = 0,
-	.functions = NULL,
-	.num_functions = 0,
+	.lanes = tegra210_lanes,
+	.num_lanes = ARRAY_SIZE(tegra210_lanes),
+	.functions = tegra210_functions,
+	.num_functions = ARRAY_SIZE(tegra210_functions),
 	.phys = tegra210_phys,
 	.num_phys = ARRAY_SIZE(tegra210_phys),
 };

index 11ecb99b749d..f44790a65004 100644
@@ -45,8 +45,8 @@ struct tegra_xusb_padctl_pin {
 	int iddq;
 };
 
-#define MAX_GROUPS 3
-#define MAX_PINS 6
+#define MAX_GROUPS 5
+#define MAX_PINS 7
 
 struct tegra_xusb_padctl_group {
 	const char *name;

index 6022f1614bda..9ec93e7c4c4c 100644
@@ -279,7 +279,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
 		if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
 			break;
 	}
-
+	if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) {
+		debug("  timeout\n");
+		return -ETIMEDOUT;
+	}
 	debug("  done\n");
 
 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);

@@ -295,7 +298,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
 		if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
 			break;
 	}
-
+	if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) {
+		debug("  timeout\n");
+		return -ETIMEDOUT;
+	}
 	debug("  done\n");
 
 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);

@@ -310,7 +316,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
 		if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
 			break;
 	}
-
+	if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) {
+		debug("  timeout\n");
+		return -ETIMEDOUT;
+	}
 	debug("  done\n");
 
 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);

@@ -326,7 +335,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
 		if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
 			break;
 	}
-
+	if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) {
+		debug("  timeout\n");
+		return -ETIMEDOUT;
+	}
 	debug("  done\n");
 
 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);

@@ -341,7 +353,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
 		if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
 			break;
 	}
-
+	if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) {
+		debug("  timeout\n");
+		return -ETIMEDOUT;
+	}
 	debug("  done\n");
 
 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);