ARM: dts: exynos5422-odroidxu3: use cd-gpio method to detect sd-card
Subsystems (2)
PATCH 1/3 ARM: dts: exynos5422-odroidxu3: use cd-gpio method to detect sd-card
From: Jaehoon Chung <[email protected]>
To detect sd-card use the cd-gpio method.
It can decrease the interrupt for detecting sd-card.
---
Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch
--- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3 -1
@@ -352,8 +352,10 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + cd-gpios = <&gpc2 2 GPIO_ACTIVE_HIGH>; + cd-inverted; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; };
Signature · 1 line
2.1.4
PATCH 2/3 ARM: dts: use vmmc-supply of emmc/sd for exynos5422-odroidxu3
Added support for vmmc/vqmmc-supply for emmc/sd cards. Fixed the min values for regulator ldo13_reg (VDDQ_MMC2). Added ramp-delay for LDO9(VDD33_USB3_0).
Added ramp-delay for LDO13(VDDQ_MMC2).
Added ramp-delay for LDO15(ETH_P3V3).
---
Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch
Note:
Changes need for support of UHS-I highspeed cards. changes for vqmmc-supply for emmc is not supported.
[ 1.831136] vdd_ldo9: ramp_delay not set [ 1.843049] vdd_ldo13: ramp_delay not set [ 1.850975] vdd_ldo15: ramp_delay not set [ 1.862816] vdd_sd: ramp_delay not set --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +7 -1
@@ -157,6 +157,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; + regulator-ramp-delay = <12000>; }; ldo10_reg: LDO10 {
@@ -182,9 +183,10 @@ ldo13_reg: LDO13 { regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>; }; ldo15_reg: LDO15 {
@@ -213,6 +215,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>; }; ldo24_reg: LDO24 {
@@ -338,6 +341,7 @@ samsung,dw-mshc-ddr-timing = <0 2>; samsung,dw-mshc-hs400-timing = <0 2>; samsung,read-strobe-delay = <90>; + vmmc-supply = <&ldo3_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; bus-width = <8>;
@@ -352,6 +356,8 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>; cd-gpios = <&gpc2 2 GPIO_ACTIVE_HIGH>; cd-inverted; pinctrl-names = "default";
Signature · 1 line
2.1.4
Re: [PATCH 2/3] ARM: dts: use vmmc-supply of emmc/sd for exynos5422-odroidxu3
Quoted 2 lines · Anand Moon
Added support for vmmc/vqmmc-supply for emmc/sd cards. Fixed the min values for regulator
ldo13_reg(VDDQ_MMC2).
I can't see the description of a problem which is fixed. If you fix something, then please describe what is wrong.
Quoted 46 lines
Added ramp-delay for
LDO9(VDD33_USB3_0).
Added ramp-delay forLDO13(VDDQ_MMC2).
Added ramp-delay forLDO15(ETH_P3V3).Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchNote:
Changes need for support of UHS-I highspeed cards. changes for vqmmc-supply for emmc is not supported.[ 1.831136] vdd_ldo9: ramp_delay not set [ 1.843049] vdd_ldo13: ramp_delay not set [ 1.850975] vdd_ldo15: ramp_delay not set [ 1.862816] vdd_sd: ramp_delay not set --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3
-1@@ -157,6 +157,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; + regulator-ramp-delay = <12000>; }; ldo10_reg: LDO10 {@@ -182,9 +183,10 @@ ldo13_reg: LDO13 { regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>; }; ldo15_reg: LDO15 {
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 218
Quoted 4 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0@@ -213,6 +215,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>;
Where did you get this value from? It looks wrong... My datasheet does not have 12000 uV/uS.
Quoted 12 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0}; ldo24_reg: LDO24 {@@ -338,6 +341,7 @@ samsung,dw-mshc-ddr-timing = <0 2>; samsung,dw-mshc-hs400-timing = <0 2>; samsung,read-strobe-delay = <90>; + vmmc-supply = <&ldo3_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; bus-width = <8>;
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 360
Quoted 5 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +2
-0@@ -352,6 +356,8 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>;
It looks wrong. LDO13 is used in one place as VQMMC and in other as VMMC. How did you figure out which regulator supplies which power domain?
Best regards,
Krzysztof
Quoted 4 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +0
-0cd-gpios = <&gpc2 2 GPIO_ACTIVE_HIGH>; cd-inverted; pinctrl-names = "default";
Re: [PATCH 2/3] ARM: dts: use vmmc-supply of emmc/sd for exynos5422-odroidxu3
Quoted 51 lines · Krzysztof Kozlowski
Quoted 2 lines · Anand Moon
Added support for vmmc/vqmmc-supply for emmc/sd cards. Fixed the min values for regulator
ldo13_reg(VDDQ_MMC2).I can't see the description of a problem which is fixed. If you fix something, then please describe what is wrong.
Quoted 44 lines
Added ramp-delay for
LDO9(VDD33_USB3_0).
Added ramp-delay forLDO13(VDDQ_MMC2).
Added ramp-delay forLDO15(ETH_P3V3).Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchNote:
Changes need for support of UHS-I highspeed cards. changes for vqmmc-supply for emmc is not supported.[ 1.831136] vdd_ldo9: ramp_delay not set [ 1.843049] vdd_ldo13: ramp_delay not set [ 1.850975] vdd_ldo15: ramp_delay not set [ 1.862816] vdd_sd: ramp_delay not set --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3
-1@@ -157,6 +157,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; + regulator-ramp-delay = <12000>; }; ldo10_reg: LDO10 {@@ -182,9 +183,10 @@ ldo13_reg: LDO13 { regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>; };
Quoted 9 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 218
Quoted 6 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0ldo15_reg: LDO15 {@@ -213,6 +215,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>;Where did you get this value from? It looks wrong... My datasheet does not have 12000 uV/uS.
Anand,
We have actually been here:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/351601.html
That time you used 8000. I asked the same question - how did you figure out the exact value.
Now we have the same question - why 12000?
It is completely fine to make a mistake (I do a lot of them) but please try not to make the same mistake again.
BR,
Krzysztof
Quoted 31 lines
Quoted 13 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0}; ldo24_reg: LDO24 {@@ -338,6 +341,7 @@ samsung,dw-mshc-ddr-timing = <0 2>; samsung,dw-mshc-hs400-timing = <0 2>; samsung,read-strobe-delay = <90>; + vmmc-supply = <&ldo3_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; bus-width = <8>;arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 360
Quoted 5 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +2
-0@@ -352,6 +356,8 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>;It looks wrong. LDO13 is used in one place as VQMMC and in other as VMMC. How did you figure out which regulator supplies which power domain?
Best regards,
KrzysztofQuoted 4 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +0
-0cd-gpios = <&gpc2 2 GPIO_ACTIVE_HIGH>; cd-inverted; pinctrl-names = "default";
Re: [PATCH 2/3] ARM: dts: use vmmc-supply of emmc/sd for exynos5422-odroidxu3
Hi Krzysztof,
Quoted 71 lines · Krzysztof Kozlowski
Quoted 51 lines · Krzysztof Kozlowski
Quoted 2 lines · Anand Moon
Added support for vmmc/vqmmc-supply for emmc/sd cards. Fixed the min values for regulator
ldo13_reg(VDDQ_MMC2).I can't see the description of a problem which is fixed. If you fix something, then please describe what is wrong.
Quoted 44 lines
Added ramp-delay for
LDO9(VDD33_USB3_0).
Added ramp-delay forLDO13(VDDQ_MMC2).
Added ramp-delay forLDO15(ETH_P3V3).Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchNote:
Changes need for support of UHS-I highspeed cards. changes for vqmmc-supply for emmc is not supported.[ 1.831136] vdd_ldo9: ramp_delay not set [ 1.843049] vdd_ldo13: ramp_delay not set [ 1.850975] vdd_ldo15: ramp_delay not set [ 1.862816] vdd_sd: ramp_delay not set --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3
-1@@ -157,6 +157,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; + regulator-ramp-delay = <12000>; }; ldo10_reg: LDO10 {@@ -182,9 +183,10 @@ ldo13_reg: LDO13 { regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>; };Quoted 9 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 218
Quoted 6 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0ldo15_reg: LDO15 {@@ -213,6 +215,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>;Where did you get this value from? It looks wrong... My datasheet does not have 12000 uV/uS.
Anand,
We have actually been here:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/351601.htmlThat time you used 8000. I asked the same question - how did you figure out the exact value.
Quoted 7 lines
Now we have the same question - why 12000?
It is completely fine to make a mistake (I do a lot of them) but please try not to make the same mistake again.
BR,
Krzysztof
I will focus more in the future to clamp down my mistakes to minimal.
Quoted 15 lines
Quoted 15 lines
Quoted 15 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0}; ldo24_reg: LDO24 {@@ -338,6 +341,7 @@ samsung,dw-mshc-ddr-timing = <0 2>; samsung,dw-mshc-hs400-timing = <0 2>; samsung,read-strobe-delay = <90>; + vmmc-supply = <&ldo3_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; bus-width = <8>;@@ -352,6 +356,8 @@ samsung,dw-mshc-ciu-div = <3>;
Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 360
Quoted 4 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +2
-0samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>;It looks wrong. LDO13 is used in one place as VQMMC and in other as VMMC. How did you figure out which regulator supplies which power domain?
I refer Schematics diagram to XU4_MAIN_REV0.1.pdf
Quoted 12 lines
From the
PWR_PMCI_S2MPS11_LDO_CTRLdocument it LDO13 point toVDDQ_MMC2.Quoted 9 lines
Best regards,
KrzysztofQuoted 4 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +0
-0cd-gpios = <&gpc2 2 GPIO_ACTIVE_HIGH>; cd-inverted; pinctrl-names = "default";
-Anand Moon
Re: [PATCH 2/3] ARM: dts: use vmmc-supply of emmc/sd for exynos5422-odroidxu3
W dniu 12.10.2015 o 20:08, Anand Moon pisze:
Quoted 109 lines
Hi Krzysztof,
Quoted 71 lines · Krzysztof Kozlowski
Quoted 51 lines · Krzysztof Kozlowski
Quoted 2 lines · Anand Moon
Added support for vmmc/vqmmc-supply for emmc/sd cards. Fixed the min values for regulator
ldo13_reg(VDDQ_MMC2).I can't see the description of a problem which is fixed. If you fix something, then please describe what is wrong.
Quoted 44 lines
Added ramp-delay for
LDO9(VDD33_USB3_0).
Added ramp-delay forLDO13(VDDQ_MMC2).
Added ramp-delay forLDO15(ETH_P3V3).Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchNote:
Changes need for support of UHS-I highspeed cards. changes for vqmmc-supply for emmc is not supported.[ 1.831136] vdd_ldo9: ramp_delay not set [ 1.843049] vdd_ldo13: ramp_delay not set [ 1.850975] vdd_ldo15: ramp_delay not set [ 1.862816] vdd_sd: ramp_delay not set --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3
-1@@ -157,6 +157,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; + regulator-ramp-delay = <12000>; }; ldo10_reg: LDO10 {@@ -182,9 +183,10 @@ ldo13_reg: LDO13 { regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>; };Quoted 9 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 218
Quoted 6 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0ldo15_reg: LDO15 {@@ -213,6 +215,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>;Where did you get this value from? It looks wrong... My datasheet does not have 12000 uV/uS.
Anand,
We have actually been here:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/351601.htmlThat time you used 8000. I asked the same question - how did you figure out the exact value.
Quoted 7 lines
Now we have the same question - why 12000?
It is completely fine to make a mistake (I do a lot of them) but please try not to make the same mistake again.
BR,
KrzysztofI will focus more in the future to clamp down my mistakes to minimal.
Quoted 15 lines
Quoted 15 lines
Quoted 15 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0}; ldo24_reg: LDO24 {@@ -338,6 +341,7 @@ samsung,dw-mshc-ddr-timing = <0 2>; samsung,dw-mshc-hs400-timing = <0 2>; samsung,read-strobe-delay = <90>; + vmmc-supply = <&ldo3_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; bus-width = <8>;@@ -352,6 +356,8 @@ samsung,dw-mshc-ciu-div = <3>;Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 360
Quoted 4 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +2
-0samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>;It looks wrong. LDO13 is used in one place as VQMMC and in other as VMMC. How did you figure out which regulator supplies which power domain?
Quoted 4 lines
I refer Schematics diagram to XU4_MAIN_REV0.1.pdf
From the
PWR_PMCI_S2MPS11_LDO_CTRLdocument it LDO13 point toVDDQ_MMC2.
Aaa right, by mistake I thought that you put LDO13 here and in the node before, but there is LDO3, not 13. You did this correctly.
But I have two other questions:
1. Maybe these regulators now should not be always-enabled?
2. Why changing minimum voltage of LDO13 to 1.8V? The schematics says 2.8V.
Best regards,
Krzysztof
Re: [PATCH 2/3] ARM: dts: use vmmc-supply of emmc/sd for exynos5422-odroidxu3
Hi Krzysztof,
Quoted 112 lines · Krzysztof Kozlowski
W dniu 12.10.2015 o 20:08, Anand Moon pisze:
Quoted 111 lines
Hi Krzysztof,
Quoted 71 lines · Krzysztof Kozlowski
Quoted 51 lines · Krzysztof Kozlowski
Quoted 2 lines · Anand Moon
Added support for vmmc/vqmmc-supply for emmc/sd cards. Fixed the min values for regulator
ldo13_reg(VDDQ_MMC2).I can't see the description of a problem which is fixed. If you fix something, then please describe what is wrong.
Quoted 44 lines
Added ramp-delay for
LDO9(VDD33_USB3_0).
Added ramp-delay forLDO13(VDDQ_MMC2).
Added ramp-delay forLDO15(ETH_P3V3).Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchNote:
Changes need for support of UHS-I highspeed cards. changes for vqmmc-supply for emmc is not supported.[ 1.831136] vdd_ldo9: ramp_delay not set [ 1.843049] vdd_ldo13: ramp_delay not set [ 1.850975] vdd_ldo15: ramp_delay not set [ 1.862816] vdd_sd: ramp_delay not set --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3
-1@@ -157,6 +157,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; + regulator-ramp-delay = <12000>; }; ldo10_reg: LDO10 {@@ -182,9 +183,10 @@ ldo13_reg: LDO13 { regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>; };Quoted 9 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 218
Quoted 6 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0ldo15_reg: LDO15 {@@ -213,6 +215,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>;Where did you get this value from? It looks wrong... My datasheet does not have 12000 uV/uS.
Anand,
We have actually been here:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/351601.htmlThat time you used 8000. I asked the same question - how did you figure out the exact value.
Quoted 7 lines
Now we have the same question - why 12000?
It is completely fine to make a mistake (I do a lot of them) but please try not to make the same mistake again.
BR,
KrzysztofI will focus more in the future to clamp down my mistakes to minimal.
Quoted 15 lines
Quoted 15 lines
Quoted 15 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0}; ldo24_reg: LDO24 {@@ -338,6 +341,7 @@ samsung,dw-mshc-ddr-timing = <0 2>; samsung,dw-mshc-hs400-timing = <0 2>; samsung,read-strobe-delay = <90>; + vmmc-supply = <&ldo3_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; bus-width = <8>;@@ -352,6 +356,8 @@ samsung,dw-mshc-ciu-div = <3>;Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 360
Quoted 4 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +2
-0samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>;It looks wrong. LDO13 is used in one place as VQMMC and in other as VMMC. How did you figure out which regulator supplies which power domain?
I refer Schematics diagram to XU4_MAIN_REV0.1.pdf
Quoted 8 lines
Quoted 2 lines
From the
PWR_PMCI_S2MPS11_LDO_CTRLdocument it LDO13 point toVDDQ_MMC2.Aaa right, by mistake I thought that you put LDO13 here and in the node before, but there is LDO3, not 13. You did this correctly.
But I have two other questions:
1. Maybe these regulators now should not be always-enabled?
regulator-always-on can be removed: I have tested this.
Quoted 2 lines
2. Why changing minimum voltage of LDO13 to 1.8V? The schematics says 2.8V.
In the schematics diagram to XU4_MAIN_REV0.1.pdf
Quoted 1 line
From the EXYNOS5422 MMC UFS diagram CH2 range is
VDDQ_MMC2(1.8V/2.8V).
-Anand Moon
Quoted 4 lines
Best regards,
Krzysztof
Re: [PATCH 2/3] ARM: dts: use vmmc-supply of emmc/sd for exynos5422-odroidxu3
Quoted 125 lines · Anand Moon
Hi Krzysztof,
Quoted 112 lines · Krzysztof Kozlowski
W dniu 12.10.2015 o 20:08, Anand Moon pisze:
Quoted 111 lines
Hi Krzysztof,
Quoted 71 lines · Krzysztof Kozlowski
Quoted 51 lines · Krzysztof Kozlowski
Quoted 2 lines · Anand Moon
Added support for vmmc/vqmmc-supply for emmc/sd cards. Fixed the min values for regulator
ldo13_reg(VDDQ_MMC2).I can't see the description of a problem which is fixed. If you fix something, then please describe what is wrong.
Quoted 44 lines
Added ramp-delay for
LDO9(VDD33_USB3_0).
Added ramp-delay forLDO13(VDDQ_MMC2).
Added ramp-delay forLDO15(ETH_P3V3).Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchNote:
Changes need for support of UHS-I highspeed cards. changes for vqmmc-supply for emmc is not supported.[ 1.831136] vdd_ldo9: ramp_delay not set [ 1.843049] vdd_ldo13: ramp_delay not set [ 1.850975] vdd_ldo15: ramp_delay not set [ 1.862816] vdd_sd: ramp_delay not set --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3
-1@@ -157,6 +157,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; + regulator-ramp-delay = <12000>; }; ldo10_reg: LDO10 {@@ -182,9 +183,10 @@ ldo13_reg: LDO13 { regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>; };Quoted 9 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 218
Quoted 6 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0ldo15_reg: LDO15 {@@ -213,6 +215,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>;Where did you get this value from? It looks wrong... My datasheet does not have 12000 uV/uS.
Anand,
We have actually been here:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/351601.htmlThat time you used 8000. I asked the same question - how did you figure out the exact value.
Quoted 7 lines
Now we have the same question - why 12000?
It is completely fine to make a mistake (I do a lot of them) but please try not to make the same mistake again.
BR,
KrzysztofI will focus more in the future to clamp down my mistakes to minimal.
Quoted 15 lines
Quoted 15 lines
Quoted 15 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0}; ldo24_reg: LDO24 {@@ -338,6 +341,7 @@ samsung,dw-mshc-ddr-timing = <0 2>; samsung,dw-mshc-hs400-timing = <0 2>; samsung,read-strobe-delay = <90>; + vmmc-supply = <&ldo3_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; bus-width = <8>;@@ -352,6 +356,8 @@ samsung,dw-mshc-ciu-div = <3>;Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 360
Quoted 4 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +2
-0samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>;It looks wrong. LDO13 is used in one place as VQMMC and in other as VMMC. How did you figure out which regulator supplies which power domain?
I refer Schematics diagram to XU4_MAIN_REV0.1.pdf
Quoted 8 lines
Quoted 2 lines
From the
PWR_PMCI_S2MPS11_LDO_CTRLdocument it LDO13 point toVDDQ_MMC2.Aaa right, by mistake I thought that you put LDO13 here and in the node before, but there is LDO3, not 13. You did this correctly.
But I have two other questions:
1. Maybe these regulators now should not be always-enabled?
Quoted 8 lines
regulator-always-on can be removed: I have tested this.
Quoted 2 lines
2. Why changing minimum voltage of LDO13 to 1.8V? The schematics says 2.8V.
In the schematics diagram to XU4_MAIN_REV0.1.pdf
Quoted 1 line
From the EXYNOS5422 MMC UFS diagram CH2 range is
VDDQ_MMC2(1.8V/2.8V).
Okay, so try to setting it to 1.8V (min and max) and see if it works correctly.
On the same diagram few lines below:VDDQ_MMC2: 2.8V 250mA
Best regards,
Krzysztof
Re: [PATCH 2/3] ARM: dts: use vmmc-supply of emmc/sd for exynos5422-odroidxu3
Hi Krzysztof,
Quoted 133 lines · Krzysztof Kozlowski
Quoted 132 lines · Anand Moon
Hi Krzysztof,
Quoted 112 lines · Krzysztof Kozlowski
W dniu 12.10.2015 o 20:08, Anand Moon pisze:
Quoted 111 lines
Hi Krzysztof,
Quoted 71 lines · Krzysztof Kozlowski
Quoted 51 lines · Krzysztof Kozlowski
Quoted 2 lines · Anand Moon
Added support for vmmc/vqmmc-supply for emmc/sd cards. Fixed the min values for regulator
ldo13_reg(VDDQ_MMC2).I can't see the description of a problem which is fixed. If you fix something, then please describe what is wrong.
Quoted 44 lines
Added ramp-delay for
LDO9(VDD33_USB3_0).
Added ramp-delay forLDO13(VDDQ_MMC2).
Added ramp-delay forLDO15(ETH_P3V3).Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchNote:
Changes need for support of UHS-I highspeed cards. changes for vqmmc-supply for emmc is not supported.[ 1.831136] vdd_ldo9: ramp_delay not set [ 1.843049] vdd_ldo13: ramp_delay not set [ 1.850975] vdd_ldo15: ramp_delay not set [ 1.862816] vdd_sd: ramp_delay not set --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3
-1@@ -157,6 +157,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; + regulator-ramp-delay = <12000>; }; ldo10_reg: LDO10 {@@ -182,9 +183,10 @@ ldo13_reg: LDO13 { regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>; };Quoted 9 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 218
Quoted 6 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0ldo15_reg: LDO15 {@@ -213,6 +215,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>;Where did you get this value from? It looks wrong... My datasheet does not have 12000 uV/uS.
Anand,
We have actually been here:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/351601.htmlThat time you used 8000. I asked the same question - how did you figure out the exact value.
Quoted 7 lines
Now we have the same question - why 12000?
It is completely fine to make a mistake (I do a lot of them) but please try not to make the same mistake again.
BR,
KrzysztofI will focus more in the future to clamp down my mistakes to minimal.
Quoted 15 lines
Quoted 15 lines
Quoted 15 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0}; ldo24_reg: LDO24 {@@ -338,6 +341,7 @@ samsung,dw-mshc-ddr-timing = <0 2>; samsung,dw-mshc-hs400-timing = <0 2>; samsung,read-strobe-delay = <90>; + vmmc-supply = <&ldo3_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; bus-width = <8>;@@ -352,6 +356,8 @@ samsung,dw-mshc-ciu-div = <3>;Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 360
Quoted 4 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +2
-0samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>;It looks wrong. LDO13 is used in one place as VQMMC and in other as VMMC. How did you figure out which regulator supplies which power domain?
I refer Schematics diagram to XU4_MAIN_REV0.1.pdf
Quoted 8 lines
Quoted 2 lines
From the
PWR_PMCI_S2MPS11_LDO_CTRLdocument it LDO13 point toVDDQ_MMC2.Aaa right, by mistake I thought that you put LDO13 here and in the node before, but there is LDO3, not 13. You did this correctly.
But I have two other questions:
1. Maybe these regulators now should not be always-enabled?regulator-always-on can be removed: I have tested this.
Quoted 2 lines
2. Why changing minimum voltage of LDO13 to 1.8V? The schematics says 2.8V.
In the schematics diagram to XU4_MAIN_REV0.1.pdf
Quoted 8 lines
Quoted 1 line
Quoted 1 line
From the EXYNOS5422 MMC UFS diagram CH2 range is
VDDQ_MMC2(1.8V/2.8V).Okay, so try to setting it to 1.8V (min and max) and see if it works correctly.
On the same diagram few lines below:
VDDQ_MMC2: 2.8V 250mA
You are correct.
While working on this issue I tent to encounter make bugs.
---------------------------------------------------------------------------------
[ 4.713553] random: nonblocking pool is initialized [ 4.718423] 14530000.hdmi supply hdmi-en not found, using dummy regulator [ 4.726206] exynos-drm exynos-drm: bound 14400000.fimd (ops fimd_component_ops) [ 4.732555] exynos-drm exynos-drm: bound 14450000.mixer (ops mixer_component_ops) [ 4.740180] exynos-drm exynos-drm: bound 14530000.hdmi (ops hdmi_component_ops) [ 4.746936] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 4.753428] [drm] No driver support for vblank timestamp query. [ 4.940794] Console: switching to colour frame buffer device 274x77 [ 4.995344] exynos-drm exynos-drm: fb0: frame buffer device [ 5.024573] [drm] Initialized exynos 1.0.0 20110530 on minor 0 [ 5.031164] exynos-dwc3 usb at 12000000: no suspend clk specified [ 5.054571] usb 2-1: new full-speed USB device number 2 using exynos-ohci [ 5.159527] dwmmc_exynos 12220000.mmc: Busy; trying anyway [ 5.163705] mmc_host mmc1: Timeout sending command (cmd 0x202000
arg 0x0 status 0x0)
---------------------------------------------------------------------------------
This is one bug. related to this changes. It stops booting waiting for the mmc1 card.
-Anand Moon
Quoted 2 lines
Best regards,
Krzysztof
Re: [PATCH 2/3] ARM: dts: use vmmc-supply of emmc/sd for exynos5422-odroidxu3
Quoted 166 lines · Anand Moon
Hi Krzysztof,
Quoted 133 lines · Krzysztof Kozlowski
Quoted 132 lines · Anand Moon
Hi Krzysztof,
Quoted 112 lines · Krzysztof Kozlowski
W dniu 12.10.2015 o 20:08, Anand Moon pisze:
Quoted 111 lines
Hi Krzysztof,
Quoted 71 lines · Krzysztof Kozlowski
Quoted 51 lines · Krzysztof Kozlowski
Quoted 2 lines · Anand Moon
Added support for vmmc/vqmmc-supply for emmc/sd cards. Fixed the min values for regulator
ldo13_reg(VDDQ_MMC2).I can't see the description of a problem which is fixed. If you fix something, then please describe what is wrong.
Quoted 44 lines
Added ramp-delay for
LDO9(VDD33_USB3_0).
Added ramp-delay forLDO13(VDDQ_MMC2).
Added ramp-delay forLDO15(ETH_P3V3).Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchNote:
Changes need for support of UHS-I highspeed cards. changes for vqmmc-supply for emmc is not supported.[ 1.831136] vdd_ldo9: ramp_delay not set [ 1.843049] vdd_ldo13: ramp_delay not set [ 1.850975] vdd_ldo15: ramp_delay not set [ 1.862816] vdd_sd: ramp_delay not set --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3
-1@@ -157,6 +157,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; + regulator-ramp-delay = <12000>; }; ldo10_reg: LDO10 {@@ -182,9 +183,10 @@ ldo13_reg: LDO13 { regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>; };Quoted 9 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 218
Quoted 6 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0ldo15_reg: LDO15 {@@ -213,6 +215,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>;Where did you get this value from? It looks wrong... My datasheet does not have 12000 uV/uS.
Anand,
We have actually been here:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/351601.htmlThat time you used 8000. I asked the same question - how did you figure out the exact value.
Quoted 7 lines
Now we have the same question - why 12000?
It is completely fine to make a mistake (I do a lot of them) but please try not to make the same mistake again.
BR,
KrzysztofI will focus more in the future to clamp down my mistakes to minimal.
Quoted 15 lines
Quoted 15 lines
Quoted 15 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0}; ldo24_reg: LDO24 {@@ -338,6 +341,7 @@ samsung,dw-mshc-ddr-timing = <0 2>; samsung,dw-mshc-hs400-timing = <0 2>; samsung,read-strobe-delay = <90>; + vmmc-supply = <&ldo3_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; bus-width = <8>;@@ -352,6 +356,8 @@ samsung,dw-mshc-ciu-div = <3>;Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 360
Quoted 4 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +2
-0samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>;It looks wrong. LDO13 is used in one place as VQMMC and in other as VMMC. How did you figure out which regulator supplies which power domain?
I refer Schematics diagram to XU4_MAIN_REV0.1.pdf
Quoted 8 lines
Quoted 2 lines
From the
PWR_PMCI_S2MPS11_LDO_CTRLdocument it LDO13 point toVDDQ_MMC2.Aaa right, by mistake I thought that you put LDO13 here and in the node before, but there is LDO3, not 13. You did this correctly.
But I have two other questions:
1. Maybe these regulators now should not be always-enabled?regulator-always-on can be removed: I have tested this.
Quoted 2 lines
2. Why changing minimum voltage of LDO13 to 1.8V? The schematics says 2.8V.
In the schematics diagram to XU4_MAIN_REV0.1.pdf
Quoted 8 lines
Quoted 1 line
Quoted 1 line
From the EXYNOS5422 MMC UFS diagram CH2 range is
VDDQ_MMC2(1.8V/2.8V).Okay, so try to setting it to 1.8V (min and max) and see if it works correctly.
On the same diagram few lines below:
VDDQ_MMC2: 2.8V 250mAYou are correct.
While working on this issue I tent to encounter make bugs.
---------------------------------------------------------------------------------[ 4.713553] random: nonblocking pool is initialized [ 4.718423] 14530000.hdmi supply hdmi-en not found, using dummy regulator [ 4.726206] exynos-drm exynos-drm: bound 14400000.fimd (ops fimd_component_ops) [ 4.732555] exynos-drm exynos-drm: bound 14450000.mixer (ops mixer_component_ops) [ 4.740180] exynos-drm exynos-drm: bound 14530000.hdmi (ops hdmi_component_ops) [ 4.746936] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 4.753428] [drm] No driver support for vblank timestamp query. [ 4.940794] Console: switching to colour frame buffer device 274x77 [ 4.995344] exynos-drm exynos-drm: fb0: frame buffer device [ 5.024573] [drm] Initialized exynos 1.0.0 20110530 on minor 0 [ 5.031164] exynos-dwc3 usb at 12000000: no suspend clk specified [ 5.054571] usb 2-1: new full-speed USB device number 2 using exynos-ohci [ 5.159527] dwmmc_exynos 12220000.mmc: Busy; trying anyway [ 5.163705] mmc_host mmc1: Timeout sending command (cmd 0x202000
Quoted 4 lines
arg
0x0status0x0)
---------------------------------------------------------------------------------
This is one bug. related to this changes. It stops booting waiting for the mmc1 card.
It seems that it failed to switch voltage.
Best Regards,
Jaehoon Chung
Quoted 6 lines
-Anand Moon
Quoted 2 lines
Best regards,
Krzysztof
Re: [PATCH 2/3] ARM: dts: use vmmc-supply of emmc/sd for exynos5422-odroidxu3
Hi Jaehoon Chung,
Quoted 172 lines · Jaehoon Chung
Quoted 166 lines · Anand Moon
Hi Krzysztof,
Quoted 133 lines · Krzysztof Kozlowski
Quoted 132 lines · Anand Moon
Hi Krzysztof,
Quoted 112 lines · Krzysztof Kozlowski
W dniu 12.10.2015 o 20:08, Anand Moon pisze:
Quoted 111 lines
Hi Krzysztof,
Quoted 71 lines · Krzysztof Kozlowski
Quoted 51 lines · Krzysztof Kozlowski
Quoted 2 lines · Anand Moon
Added support for vmmc/vqmmc-supply for emmc/sd cards. Fixed the min values for regulator
ldo13_reg(VDDQ_MMC2).I can't see the description of a problem which is fixed. If you fix something, then please describe what is wrong.
Quoted 44 lines
Added ramp-delay for
LDO9(VDD33_USB3_0).
Added ramp-delay forLDO13(VDDQ_MMC2).
Added ramp-delay forLDO15(ETH_P3V3).Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchNote:
Changes need for support of UHS-I highspeed cards. changes for vqmmc-supply for emmc is not supported.[ 1.831136] vdd_ldo9: ramp_delay not set [ 1.843049] vdd_ldo13: ramp_delay not set [ 1.850975] vdd_ldo15: ramp_delay not set [ 1.862816] vdd_sd: ramp_delay not set --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3
-1@@ -157,6 +157,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; + regulator-ramp-delay = <12000>; }; ldo10_reg: LDO10 {@@ -182,9 +183,10 @@ ldo13_reg: LDO13 { regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>; };Quoted 9 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 218
Quoted 6 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0ldo15_reg: LDO15 {@@ -213,6 +215,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-ramp-delay = <12000>;Where did you get this value from? It looks wrong... My datasheet does not have 12000 uV/uS.
Anand,
We have actually been here:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/351601.htmlThat time you used 8000. I asked the same question - how did you figure out the exact value.
Quoted 7 lines
Now we have the same question - why 12000?
It is completely fine to make a mistake (I do a lot of them) but please try not to make the same mistake again.
BR,
KrzysztofI will focus more in the future to clamp down my mistakes to minimal.
Quoted 15 lines
Quoted 15 lines
Quoted 15 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +1
-0}; ldo24_reg: LDO24 {@@ -338,6 +341,7 @@ samsung,dw-mshc-ddr-timing = <0 2>; samsung,dw-mshc-hs400-timing = <0 2>; samsung,read-strobe-delay = <90>; + vmmc-supply = <&ldo3_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; bus-width = <8>;@@ -352,6 +356,8 @@ samsung,dw-mshc-ciu-div = <3>;Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 360
Quoted 4 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +2
-0samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>;It looks wrong. LDO13 is used in one place as VQMMC and in other as VMMC. How did you figure out which regulator supplies which power domain?
I refer Schematics diagram to XU4_MAIN_REV0.1.pdf
Quoted 8 lines
Quoted 2 lines
From the
PWR_PMCI_S2MPS11_LDO_CTRLdocument it LDO13 point toVDDQ_MMC2.Aaa right, by mistake I thought that you put LDO13 here and in the node before, but there is LDO3, not 13. You did this correctly.
But I have two other questions:
1. Maybe these regulators now should not be always-enabled?regulator-always-on can be removed: I have tested this.
Quoted 2 lines
2. Why changing minimum voltage of LDO13 to 1.8V? The schematics says 2.8V.
In the schematics diagram to XU4_MAIN_REV0.1.pdf
Quoted 8 lines
Quoted 1 line
Quoted 1 line
From the EXYNOS5422 MMC UFS diagram CH2 range is
VDDQ_MMC2(1.8V/2.8V).Okay, so try to setting it to 1.8V (min and max) and see if it works correctly.
On the same diagram few lines below:
VDDQ_MMC2: 2.8V 250mAYou are correct.
While working on this issue I tent to encounter make bugs.
---------------------------------------------------------------------------------[ 4.713553] random: nonblocking pool is initialized [ 4.718423] 14530000.hdmi supply hdmi-en not found, using dummy regulator [ 4.726206] exynos-drm exynos-drm: bound 14400000.fimd (ops fimd_component_ops) [ 4.732555] exynos-drm exynos-drm: bound 14450000.mixer (ops mixer_component_ops) [ 4.740180] exynos-drm exynos-drm: bound 14530000.hdmi (ops hdmi_component_ops) [ 4.746936] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 4.753428] [drm] No driver support for vblank timestamp query. [ 4.940794] Console: switching to colour frame buffer device 274x77 [ 4.995344] exynos-drm exynos-drm: fb0: frame buffer device [ 5.024573] [drm] Initialized exynos 1.0.0 20110530 on minor 0 [ 5.031164] exynos-dwc3 usb at 12000000: no suspend clk specified [ 5.054571] usb 2-1: new full-speed USB device number 2 using exynos-ohci [ 5.159527] dwmmc_exynos 12220000.mmc: Busy; trying anyway [ 5.163705] mmc_host mmc1: Timeout sending command (cmd 0x202000Quoted 4 lines
arg
0x0status0x0)
---------------------------------------------------------------------------------
This is one bug. related to this changes. It stops booting waiting for the mmc1 card.
Quoted 5 lines
It seems that it failed to switch voltage.
Best Regards,
Jaehoon Chung
You are correct. This happens when the min/max value for ldo13_reg is 2.8V.
-Anand Moon
Quoted 7 lines
Quoted 6 lines
-Anand Moon
Quoted 2 lines
Best regards,
Krzysztof
PATCH 3/3 ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
In reply to Anand MoonAdded support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
---
Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch
Changes Fixed the UHS-I bus speed detedtion on cold boot.
[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2 --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +4 -0
@@ -364,6 +364,10 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; }; &pinctrl_0 {
Signature · 1 line
2.1.4
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
How do you know that these modes are really supported? I don't know. Can you convince me?
Quoted 7 lines
Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchChanges Fixed the UHS-I bus speed detedtion on cold boot.
I don't get what is exactly fixed here. What was the error? What is the outcome of this fix? The log below is before or after?
Best regards,
Krzysztof
Quoted 26 lines
[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2--- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +4
-0@@ -364,6 +364,10 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; }; &pinctrl_0 {
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Hi Krzysztof,
Quoted 8 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
Looks like I missed it, I will add this in the next patch,
Quoted 43 lines
How do you know that these modes are really supported? I don't know. Can you convince me?
Quoted 7 lines
Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchChanges Fixed the UHS-I bus speed detedtion on cold boot.
I don't get what is exactly fixed here. What was the error? What is the outcome of this fix? The log below is before or after?
Best regards,
KrzysztofQuoted 24 lines
[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2--- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +4
-0@@ -364,6 +364,10 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; };
Quoted 3 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 373
Quoted 2 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +0
-0&pinctrl_0 {
Changes were made to support Sandisk Ultra UHS-I class 10 card support. OdroidXU3/XU4 board would not boot up using this card.
Depending on the capability of the UHS-I card, the speed of the card is selected.
I have just added the enhance capability feature to support them.
On warm boot: i.e reboot of the board.
[ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.657555] mmc1: new high speed SDHC card at address aaaa [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.669206] mmcblk0: p1 p2
On cold boot:: ie: power on the board.
[ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.650293] IRQ56 no longer affine to CPU7 [ 4.650581] CPU7: shutdown [ 4.658293] mmcblk0: p1 p2
Note: Their is need to reset the PMIC S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers
to support this feature consistently on every reboot.
-Anand Moon
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Quoted 84 lines · Anand Moon
Hi Krzysztof,
Quoted 8 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
Looks like I missed it, I will add this in the next patch,
Quoted 43 lines
How do you know that these modes are really supported? I don't know. Can you convince me?
Quoted 7 lines
Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchChanges Fixed the UHS-I bus speed detedtion on cold boot.
I don't get what is exactly fixed here. What was the error? What is the outcome of this fix? The log below is before or after?
Best regards,
KrzysztofQuoted 24 lines
[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2--- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +4
-0@@ -364,6 +364,10 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; };Quoted 3 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 373
Quoted 2 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +0
-0&pinctrl_0 {Changes were made to support Sandisk Ultra UHS-I class 10 card support. OdroidXU3/XU4 board would not boot up using this card.
Depending on the capability of the UHS-I card, the speed of the card is selected.
I have just added the enhance capability feature to support them.On warm boot: i.e reboot of the board.
[ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.657555] mmc1: new high speed SDHC card at address aaaa [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.669206] mmcblk0: p1 p2On cold boot:: ie: power on the board.
[ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.650293] IRQ56 no longer affine to CPU7 [ 4.650581] CPU7: shutdown [ 4.658293] mmcblk0: p1 p2
Quoted 3 lines
Note: Their is need to reset the PMIC S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers
to support this feature consistently on every reboot.
I don't understand...why needs to reset?
I know it needs to switch the voltage, doesn't it?
Best Regards,
Jaehoon Chung
Quoted 3 lines
-Anand Moon
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Hi Jaehoon Chung
Quoted 85 lines · Jaehoon Chung
Quoted 84 lines · Anand Moon
Hi Krzysztof,
Quoted 8 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
Looks like I missed it, I will add this in the next patch,
Quoted 43 lines
How do you know that these modes are really supported? I don't know. Can you convince me?
Quoted 7 lines
Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchChanges Fixed the UHS-I bus speed detedtion on cold boot.
I don't get what is exactly fixed here. What was the error? What is the outcome of this fix? The log below is before or after?
Best regards,
KrzysztofQuoted 24 lines
[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2--- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +4
-0@@ -364,6 +364,10 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; };Quoted 3 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 373
Quoted 2 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +0
-0&pinctrl_0 {Changes were made to support Sandisk Ultra UHS-I class 10 card support. OdroidXU3/XU4 board would not boot up using this card.
Depending on the capability of the UHS-I card, the speed of the card is selected.
I have just added the enhance capability feature to support them.On warm boot: i.e reboot of the board.
[ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.657555] mmc1: new high speed SDHC card at address aaaa [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.669206] mmcblk0: p1 p2On cold boot:: ie: power on the board.
[ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.650293] IRQ56 no longer affine to CPU7 [ 4.650581] CPU7: shutdown [ 4.658293] mmcblk0: p1 p2
Quoted 7 lines
Quoted 3 lines
Note: Their is need to reset the PMIC S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers
to support this feature consistently on every reboot.I don't understand...why needs to reset?
I know it needs to switch the voltage, doesn't it?
I was referring to this code.
https://github.com/hardkernel/linux/blob/odroidxu3-3.10.y/drivers/regulator/s2mps11.c#L451
I am not sure if this need to fixed in u-boot of hardkernel or shutdown function.
-Anand Moon
Quoted 7 lines
Best Regards,
Jaehoon ChungQuoted 3 lines
-Anand Moon
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
In reply to Anand MoonW dniu 12.10.2015 o 19:46, Anand Moon pisze:
Quoted 5 lines
Hi Krzysztof,
Quoted 1 line · Krzysztof Kozlowski
On 12.10.2015 00:46, Anand Moon wrote:
Quoted 11 lines
Quoted 7 lines
Quoted 1 line
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
Looks like I missed it, I will add this in the next patch,
Quoted 3 lines
How do you know that these modes are really supported? I don't know. Can you convince me?
That part was not answered...
Quoted 44 lines
Quoted 40 lines
Quoted 9 lines
Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchChanges Fixed the UHS-I bus speed detedtion on cold boot.
I don't get what is exactly fixed here. What was the error? What is the outcome of this fix? The log below is before or after?
Best regards,
KrzysztofQuoted 24 lines
[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2--- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +4
-0@@ -364,6 +364,10 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; };Quoted 3 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 373
Quoted 2 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +0
-0&pinctrl_0 {
Quoted 6 lines
Changes were made to support Sandisk Ultra UHS-I class 10 card support. OdroidXU3/XU4 board would not boot up using this card.
Depending on the capability of the UHS-I card, the speed of the card is selected.
I have just added the enhance capability feature to support them.
So without these capabilities mentioned microSD card cannot be used? So I have a UHS-I card, that one exactly:
http://www.samsung.com/us/support/owners/product/MB-MP32D/APC
It works:
[ 2.628365] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 2.693296] mmc1: new high speed SDHC card at address 0001 [ 2.703867] mmcblk0: mmc1:0001 00000 29.8 GiB [ 2.708406] mmcblk0: p1 p2
This is just HS mode.
In the same time isn't UHS-I backward compatible? Your report seems surprising.
Best regards,
Krzysztof
Quoted 29 lines
On warm boot: i.e reboot of the board.
[ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.657555] mmc1: new high speed SDHC card at address aaaa [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.669206] mmcblk0: p1 p2On cold boot:: ie: power on the board.
[ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.650293] IRQ56 no longer affine to CPU7 [ 4.650581] CPU7: shutdown [ 4.658293] mmcblk0: p1 p2Note: Their is need to reset the PMIC S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers
to support this feature consistently on every reboot.-Anand Moon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo at vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Quoted 12 lines · Krzysztof Kozlowski
W dniu 12.10.2015 o 19:46, Anand Moon pisze:
Quoted 11 lines
Hi Krzysztof,
Quoted 7 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
Quoted 7 lines
Quoted 5 lines
Quoted 1 line
You mentioned DDR50 but I don't see respective property below.
Looks like I missed it, I will add this in the next patch,
Quoted 3 lines
How do you know that these modes are really supported? I don't know. Can you convince me?
That part was not answered...
In my experiment, it needs two requirements.
One is that Host controller supported UHS-I mode or others, other is SD-card. In Anand's commit message, there is no information for this.
And 50MB/s or 104MB/s is not real performance. (Just theoretical values) It seems that can get those performances.
Quoted 63 lines
Quoted 45 lines
Quoted 41 lines
Quoted 10 lines
Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchChanges Fixed the UHS-I bus speed detedtion on cold boot.
I don't get what is exactly fixed here. What was the error? What is the outcome of this fix? The log below is before or after?
Best regards,
KrzysztofQuoted 24 lines
[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2--- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +4
-0@@ -364,6 +364,10 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; };Quoted 3 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 373
Quoted 2 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +0
-0&pinctrl_0 {Quoted 6 lines
Changes were made to support Sandisk Ultra UHS-I class 10 card support. OdroidXU3/XU4 board would not boot up using this card.
Depending on the capability of the UHS-I card, the speed of the card is selected.
I have just added the enhance capability feature to support them.So without these capabilities mentioned microSD card cannot be used? So I have a UHS-I card, that one exactly:
http://www.samsung.com/us/support/owners/product/MB-MP32D/APCIt works:
[ 2.628365] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 2.693296] mmc1: new high speed SDHC card at address 0001 [ 2.703867] mmcblk0: mmc1:0001 00000 29.8 GiB [ 2.708406] mmcblk0: p1 p2
Quoted 4 lines
This is just HS mode.
In the same time isn't UHS-I backward compatible? Your report seems surprising.
Right. it's not issue. just working as lower mode than its capability.
Best Regards,
Jaehoon Chung
Quoted 35 lines
Best regards,
KrzysztofQuoted 29 lines
On warm boot: i.e reboot of the board.
[ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.657555] mmc1: new high speed SDHC card at address aaaa [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.669206] mmcblk0: p1 p2On cold boot:: ie: power on the board.
[ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.650293] IRQ56 no longer affine to CPU7 [ 4.650581] CPU7: shutdown [ 4.658293] mmcblk0: p1 p2Note: Their is need to reset the PMIC S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers
to support this feature consistently on every reboot.-Anand Moon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo at vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
W dniu 12.10.2015 o 22:04, Jaehoon Chung pisze:
Quoted 19 lines · Krzysztof Kozlowski
Quoted 18 lines
W dniu 12.10.2015 o 19:46, Anand Moon pisze:
Quoted 16 lines
Hi Krzysztof,
Quoted 8 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
Looks like I missed it, I will add this in the next patch,
Quoted 3 lines
How do you know that these modes are really supported? I don't know. Can you convince me?
Quoted 8 lines
Quoted 1 line
That part was not answered...
In my experiment, it needs two requirements.
One is that Host controller supported UHS-I mode or others, other is SD-card. In Anand's commit message, there is no information for this.And 50MB/s or 104MB/s is not real performance. (Just theoretical values) It seems that can get those performances.
Right. But do you know if the host actually supports these?
Quoted 64 lines
Quoted 64 lines
Quoted 46 lines
Quoted 42 lines
Quoted 11 lines
Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchChanges Fixed the UHS-I bus speed detedtion on cold boot.
I don't get what is exactly fixed here. What was the error? What is the outcome of this fix? The log below is before or after?
Best regards,
KrzysztofQuoted 24 lines
[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2--- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +4
-0@@ -364,6 +364,10 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; };Quoted 3 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 373
Quoted 2 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +0
-0&pinctrl_0 {Quoted 6 lines
Changes were made to support Sandisk Ultra UHS-I class 10 card support. OdroidXU3/XU4 board would not boot up using this card.
Depending on the capability of the UHS-I card, the speed of the card is selected.
I have just added the enhance capability feature to support them.So without these capabilities mentioned microSD card cannot be used? So I have a UHS-I card, that one exactly:
http://www.samsung.com/us/support/owners/product/MB-MP32D/APCIt works:
[ 2.628365] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 2.693296] mmc1: new high speed SDHC card at address 0001 [ 2.703867] mmcblk0: mmc1:0001 00000 29.8 GiB [ 2.708406] mmcblk0: p1 p2
Quoted 6 lines
Quoted 4 lines
This is just HS mode.
In the same time isn't UHS-I backward compatible? Your report seems surprising.
Right. it's not issue. just working as lower mode than its capability.
Anand's report mentions "board would not boot up" which seems quite drastic. :)
Thanks Jaehoon for help in reviewing this patch.
Dear Anand,
Could you describe in more details observable issues, what is fixed or what feature is added?
Best regards,
Krzysztof
Quoted 40 lines
Best Regards,
Jaehoon ChungQuoted 35 lines
Best regards,
KrzysztofQuoted 29 lines
On warm boot: i.e reboot of the board.
[ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.657555] mmc1: new high speed SDHC card at address aaaa [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.669206] mmcblk0: p1 p2On cold boot:: ie: power on the board.
[ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.650293] IRQ56 no longer affine to CPU7 [ 4.650581] CPU7: shutdown [ 4.658293] mmcblk0: p1 p2Note: Their is need to reset the PMIC S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers
to support this feature consistently on every reboot.-Anand Moon
--
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Quoted 22 lines · Krzysztof Kozlowski
W dniu 12.10.2015 o 22:04, Jaehoon Chung pisze:
Quoted 21 lines · Krzysztof Kozlowski
Quoted 19 lines
W dniu 12.10.2015 o 19:46, Anand Moon pisze:
Quoted 5 lines
Hi Krzysztof,
Quoted 1 line · Krzysztof Kozlowski
On 12.10.2015 00:46, Anand Moon wrote:
Quoted 11 lines
Quoted 7 lines
Quoted 1 line
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
Looks like I missed it, I will add this in the next patch,
Quoted 3 lines
How do you know that these modes are really supported? I don't know. Can you convince me?
That part was not answered...
Quoted 8 lines
Quoted 6 lines
In my experiment, it needs two requirements.
One is that Host controller supported UHS-I mode or others, other is SD-card. In Anand's commit message, there is no information for this.And 50MB/s or 104MB/s is not real performance. (Just theoretical values) It seems that can get those performances.
Right. But do you know if the host actually supports these?
Actually, it needs to check the User Manual for SoC.
If i can't check the User manual, i can't also know whether it supports or not. Especially, there is no register that can be known which SD specification version at dw-mmc controller.
Well, if i miss something, let me know. I will also check more.
Best Regards,
Jaehoon Chung
Quoted 128 lines
Quoted 65 lines
Quoted 65 lines
Quoted 47 lines
Quoted 43 lines
Quoted 6 lines
Quoted 6 lines
Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchChanges Fixed the UHS-I bus speed detedtion on cold boot.
I don't get what is exactly fixed here. What was the error? What is the outcome of this fix? The log below is before or after?
Best regards,
KrzysztofQuoted 24 lines
[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2--- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +4
-0@@ -364,6 +364,10 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; };Quoted 3 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 373
Quoted 2 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +0
-0&pinctrl_0 {Quoted 6 lines
Changes were made to support Sandisk Ultra UHS-I class 10 card support. OdroidXU3/XU4 board would not boot up using this card.
Depending on the capability of the UHS-I card, the speed of the card is selected.
I have just added the enhance capability feature to support them.So without these capabilities mentioned microSD card cannot be used? So I have a UHS-I card, that one exactly:
http://www.samsung.com/us/support/owners/product/MB-MP32D/APCIt works:
[ 2.628365] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 2.693296] mmc1: new high speed SDHC card at address 0001 [ 2.703867] mmcblk0: mmc1:0001 00000 29.8 GiB [ 2.708406] mmcblk0: p1 p2Quoted 6 lines
Quoted 4 lines
This is just HS mode.
In the same time isn't UHS-I backward compatible? Your report seems surprising.
Right. it's not issue. just working as lower mode than its capability.
Anand's report mentions "board would not boot up" which seems quite drastic. :)
Thanks Jaehoon for help in reviewing this patch.
Dear Anand,
Could you describe in more details observable issues, what is fixed or what feature is added?
Best regards,
KrzysztofQuoted 40 lines
Best Regards,
Jaehoon ChungQuoted 35 lines
Best regards,
KrzysztofQuoted 29 lines
On warm boot: i.e reboot of the board.
[ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.657555] mmc1: new high speed SDHC card at address aaaa [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.669206] mmcblk0: p1 p2On cold boot:: ie: power on the board.
[ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.650293] IRQ56 no longer affine to CPU7 [ 4.650581] CPU7: shutdown [ 4.658293] mmcblk0: p1 p2Note: Their is need to reset the PMIC S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers
to support this feature consistently on every reboot.-Anand Moon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo at vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
In reply to Krzysztof KozlowskiHi Krzysztof,
Quoted 11 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
How do you know that these modes are really supported? I don't know. Can you convince me?
Setting this DDR50 capability give me this error. That's the reason to drop this capability.
Sep 24 09:37:04 odroidxu4 kernel: [ 4.138418] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) Sep 24 09:37:04 odroidxu4 kernel: [ 4.138546] mmc1: new ultra high speed DDR50 SDHC card at address aaaa Sep 24 09:37:04 odroidxu4 kernel: [ 4.141585] mmcblk0: mmc1:aaaa SL32G 29.7 GiB Sep 24 09:37:04 odroidxu4 kernel: [ 4.146477] mmcblk0: error -110 sending status command, retrying Sep 24 09:37:04 odroidxu4 kernel: [ 4.146577] mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0x900 Sep 24 09:37:04 odroidxu4 kernel: [ 4.146581] mmcblk0: error -84
transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0
Quoted 38 lines
Quoted 7 lines
Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branchChanges Fixed the UHS-I bus speed detedtion on cold boot.
I don't get what is exactly fixed here. What was the error? What is the outcome of this fix? The log below is before or after?
Best regards,
KrzysztofQuoted 24 lines
[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2--- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +4
-0@@ -364,6 +364,10 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; };
Quoted 3 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 373
Quoted 2 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +0
-0&pinctrl_0 {
-Anand Moon
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Quoted 11 lines · Anand Moon
Hi Krzysztof,
Quoted 7 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
Quoted 7 lines
Quoted 4 lines
You mentioned DDR50 but I don't see respective property below.
How do you know that these modes are really supported? I don't know. Can you convince me?
Setting this DDR50 capability give me this error. That's the reason to drop this capability.
But you mentioned it in commit message! "Added support for UHS-I ... (DDR50)"
In the same time dropping DDR50 is not an sufficient proof that "SDR50 and SDR104 are really supported".
Best regards,
Krzysztof
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Hi Krzysztof,
Quoted 17 lines · Krzysztof Kozlowski
Quoted 16 lines · Anand Moon
Hi Krzysztof,
Quoted 11 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
How do you know that these modes are really supported? I don't know. Can you convince me?
Quoted 9 lines
Quoted 2 lines
Setting this DDR50 capability give me this error. That's the reason to drop this capability.
But you mentioned it in commit message! "Added support for UHS-I ... (DDR50)"
In the same time dropping DDR50 is not an sufficient proof that "SDR50 and SDR104 are really supported".
These changes are related to the microSD card capabilities. So SDR50 have better frequency over DDR50. On the same Sandisk card.
When the card select the capability for DDR50
---------------------------------------------------
[ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.009179] mmcblk0: error -110 sending status command, retrying [ 4.009271] mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0x900 [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63) [ 4.067770] Console: switching to colour frame buffer device 274x77 [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.099692] mmc1: tried to reset card [ 4.101332] mmcblk0: p1 p2
When the card select the capability for SDR50
---------------------------------------------------------------------------------
[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2
Which will relate to better read/write speed.
-Anand Moon
Quoted 3 lines
Best regards,
Krzysztof
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Quoted 56 lines · Anand Moon
Hi Krzysztof,
Quoted 17 lines · Krzysztof Kozlowski
Quoted 16 lines · Anand Moon
Hi Krzysztof,
Quoted 11 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
How do you know that these modes are really supported? I don't know. Can you convince me?
Quoted 9 lines
Quoted 2 lines
Setting this DDR50 capability give me this error. That's the reason to drop this capability.
But you mentioned it in commit message! "Added support for UHS-I ... (DDR50)"
In the same time dropping DDR50 is not an sufficient proof that "SDR50 and SDR104 are really supported".
These changes are related to the microSD card capabilities. So SDR50 have better frequency over DDR50. On the same Sandisk card.
When the card select the capability for DDR50
---------------------------------------------------[ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.009179] mmcblk0: error -110 sending status command, retrying [ 4.009271] mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0x900 [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63) [ 4.067770] Console: switching to colour frame buffer device 274x77 [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.099692] mmc1: tried to reset card [ 4.101332] mmcblk0: p1 p2When the card select the capability for SDR50
---------------------------------------------------------------------------------
Quoted 7 lines
[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2Which will relate to better read/write speed.
Which is not an answer to my question. To none of my previous questions.
Best regards,
Krzysztof
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Hi Krzysztof,
Quoted 63 lines · Krzysztof Kozlowski
Quoted 62 lines · Anand Moon
Hi Krzysztof,
Quoted 17 lines · Krzysztof Kozlowski
Quoted 16 lines · Anand Moon
Hi Krzysztof,
Quoted 11 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
How do you know that these modes are really supported? I don't know. Can you convince me?
Quoted 9 lines
Quoted 2 lines
Setting this DDR50 capability give me this error. That's the reason to drop this capability.
But you mentioned it in commit message! "Added support for UHS-I ... (DDR50)"
In the same time dropping DDR50 is not an sufficient proof that "SDR50 and SDR104 are really supported".
These changes are related to the microSD card capabilities. So SDR50 have better frequency over DDR50. On the same Sandisk card.
When the card select the capability for DDR50
---------------------------------------------------[ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.009179] mmcblk0: error -110 sending status command, retrying [ 4.009271] mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0x900 [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63) [ 4.067770] Console: switching to colour frame buffer device 274x77 [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.099692] mmc1: tried to reset card [ 4.101332] mmcblk0: p1 p2When the card select the capability for SDR50
---------------------------------------------------------------------------------[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2
Quoted 3 lines
Quoted 1 line
Which will relate to better read/write speed.
Which is not an answer to my question. To none of my previous questions.
OK, you are correct.Just ignore these changes.
-Anand Moon
Quoted 3 lines
Best regards,
Krzysztof
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
In reply to Krzysztof KozlowskiHi Krzysztof,
Quoted 64 lines · Krzysztof Kozlowski
Quoted 62 lines · Anand Moon
Hi Krzysztof,
Quoted 17 lines · Krzysztof Kozlowski
Quoted 16 lines · Anand Moon
Hi Krzysztof,
Quoted 11 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
How do you know that these modes are really supported? I don't know. Can you convince me?
Quoted 9 lines
Quoted 2 lines
Setting this DDR50 capability give me this error. That's the reason to drop this capability.
But you mentioned it in commit message! "Added support for UHS-I ... (DDR50)"
In the same time dropping DDR50 is not an sufficient proof that "SDR50 and SDR104 are really supported".
These changes are related to the microSD card capabilities. So SDR50 have better frequency over DDR50. On the same Sandisk card.
When the card select the capability for DDR50
---------------------------------------------------[ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.009179] mmcblk0: error -110 sending status command, retrying [ 4.009271] mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0x900 [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63) [ 4.067770] Console: switching to colour frame buffer device 274x77 [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.099692] mmc1: tried to reset card [ 4.101332] mmcblk0: p1 p2When the card select the capability for SDR50
---------------------------------------------------------------------------------[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2
Quoted 4 lines
Quoted 1 line
Which will relate to better read/write speed.
Which is not an answer to my question. To none of my previous questions.
Basically UHS-I capability (sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50, sd-uhs-sdr104) help tune speed supported for mmc
I have tired to compare the speed on high speed UHS-I vs ultra high speed UHS-I using izone utility.
[ 2.572469] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 2.572609] mmc1: new high speed SDHC card at address aaaa
Command line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k
-r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls
Output is in kBytes/sec
Time Resolution = 0.000001 seconds.
Processor cache size set to 32 kBytes.
Processor cache line size set to 64 bytes.
File stride size set to 17 * record size.
random
random bkwd record stride
kB reclen write rewrite read reread read
write read rewrite read fwrite frewrite fread
freread
10240 4 1631 0 6556 0 5538 982
10240 64 8828 0 18897 0 17994 303
10240 128 6269 0 20670 0 20128 1096
---------------------------------------------------------------------------------------------------------
[ 2.613761] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot
req 100000000Hz, actual 100000000HZ div = 0)
[ 2.623573] mmc1: new ultra high speed SDR50 SDHC card at address aaaaCommand line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k
-r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls
Output is in kBytes/sec
Time Resolution = 0.000001 seconds.
Processor cache size set to 32 kBytes.
Processor cache line size set to 64 bytes.
File stride size set to 17 * record size.
random
random bkwd record stride
kB reclen write rewrite read reread read
write read rewrite read fwrite frewrite fread
freread
10240 4 1809 0 7507 0 5233 859
10240 64 11622 0 31250 0 28072 516
10240 128 4320 0 34417 0 32509 1148My observation is that their slight increase in read/write operation.
Hope I have tried to answer you query. If I am wrong please let me know.
-Anand Moon
Quoted 3 lines
Best regards,
Krzysztof
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Quoted 115 lines · Anand Moon
Hi Krzysztof,
Quoted 64 lines · Krzysztof Kozlowski
Quoted 62 lines · Anand Moon
Hi Krzysztof,
Quoted 17 lines · Krzysztof Kozlowski
Quoted 16 lines · Anand Moon
Hi Krzysztof,
Quoted 11 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
How do you know that these modes are really supported? I don't know. Can you convince me?
Quoted 9 lines
Quoted 2 lines
Setting this DDR50 capability give me this error. That's the reason to drop this capability.
But you mentioned it in commit message! "Added support for UHS-I ... (DDR50)"
In the same time dropping DDR50 is not an sufficient proof that "SDR50 and SDR104 are really supported".
These changes are related to the microSD card capabilities. So SDR50 have better frequency over DDR50. On the same Sandisk card.
When the card select the capability for DDR50
---------------------------------------------------[ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.009179] mmcblk0: error -110 sending status command, retrying [ 4.009271] mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0x900 [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63) [ 4.067770] Console: switching to colour frame buffer device 274x77 [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.099692] mmc1: tried to reset card [ 4.101332] mmcblk0: p1 p2When the card select the capability for SDR50
---------------------------------------------------------------------------------[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2Quoted 4 lines
Quoted 1 line
Which will relate to better read/write speed.
Which is not an answer to my question. To none of my previous questions.
Basically UHS-I capability (sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50, sd-uhs-sdr104) help tune speed supported for mmc
I have tired to compare the speed on high speed UHS-I vs ultra high speed UHS-I using izone utility.
[ 2.572469] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 2.572609] mmc1: new high speed SDHC card at address aaaaCommand line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k-r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls
Output is in kBytes/sec
Time Resolution = 0.000001 seconds.
Processor cache size set to 32 kBytes.
Processor cache line size set to 64 bytes.
File stride size set to 17 * record size.
random
random bkwd record stride
kB reclen write rewrite read reread read
write read rewrite read fwrite frewrite fread
freread10240 4 1631 0 6556 0 5538 982 10240 64 8828 0 18897 0 17994 303 10240 128 6269 0 20670 0 20128 1096 --------------------------------------------------------------------------------------------------------- [ 2.613761] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.623573] mmc1: new ultra high speed SDR50 SDHC card at address aaaaCommand line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k-r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls
Output is in kBytes/sec
Time Resolution = 0.000001 seconds.
Processor cache size set to 32 kBytes.
Processor cache line size set to 64 bytes.
File stride size set to 17 * record size.
random
random bkwd record stride
kB reclen write rewrite read reread read
write read rewrite read fwrite frewrite fread
freread
Quoted 7 lines
10240 4 1809 0 7507 0 5233 859 10240 64 11622 0 31250 0 28072 516 10240 128 4320 0 34417 0 32509 1148My observation is that their slight increase in read/write operation.
Hope I have tried to answer you query. If I am wrong please let me know.
Nope, that did not answer my query. You gave some performance benchmarks but my question was not about the speed of anything. The question is (once again):
How do you know that these modes are really supported?
You are marking the *host* as supporting these modes. Please provide information that host supports them *really*, not by experimenting "oh, it seems to work now, maybe it will work always".
Usually vendors, if their products implement some kind of specification/protocol, they mark the products as "compatible with XYZ" etc.
Best regards,
Krzysztof
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
+Doug
Hello,
AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 and SDR104 modes.
[1]: http://www.spinics.net/lists/linux-mmc/msg28186.html
What I remember is, one need to set "broken-cd" property also in order to make it work because of the vqmmc and vmmc connection on board. I didn't find the link right now, but you can search on the web, there was a long discussion about handling this.
Have not checked it recently, so not sure if this got broken somehow.
Regards,
Alim
Quoted 142 lines · Krzysztof Kozlowski
Quoted 115 lines · Anand Moon
Hi Krzysztof,
Quoted 64 lines · Krzysztof Kozlowski
Quoted 62 lines · Anand Moon
Hi Krzysztof,
Quoted 17 lines · Krzysztof Kozlowski
Quoted 16 lines · Anand Moon
Hi Krzysztof,
Quoted 11 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
How do you know that these modes are really supported? I don't know. Can you convince me?
Quoted 9 lines
Quoted 2 lines
Setting this DDR50 capability give me this error. That's the reason to drop this capability.
But you mentioned it in commit message! "Added support for UHS-I ... (DDR50)"
In the same time dropping DDR50 is not an sufficient proof that "SDR50 and SDR104 are really supported".
These changes are related to the microSD card capabilities. So SDR50 have better frequency over DDR50. On the same Sandisk card.
When the card select the capability for DDR50
---------------------------------------------------[ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.009179] mmcblk0: error -110 sending status command, retrying [ 4.009271] mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0x900 [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63) [ 4.067770] Console: switching to colour frame buffer device 274x77 [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.099692] mmc1: tried to reset card [ 4.101332] mmcblk0: p1 p2When the card select the capability for SDR50
---------------------------------------------------------------------------------[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2Quoted 4 lines
Quoted 1 line
Which will relate to better read/write speed.
Which is not an answer to my question. To none of my previous questions.
Basically UHS-I capability (sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50, sd-uhs-sdr104) help tune speed supported for mmc
I have tired to compare the speed on high speed UHS-I vs ultra high speed UHS-I using izone utility.
[ 2.572469] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 2.572609] mmc1: new high speed SDHC card at address aaaaCommand line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k-r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls
Output is in kBytes/sec
Time Resolution = 0.000001 seconds.
Processor cache size set to 32 kBytes.
Processor cache line size set to 64 bytes.
File stride size set to 17 * record size.
random
random bkwd record stride
kB reclen write rewrite read reread read
write read rewrite read fwrite frewrite fread
freread10240 4 1631 0 6556 0 5538 982 10240 64 8828 0 18897 0 17994 303 10240 128 6269 0 20670 0 20128 1096 --------------------------------------------------------------------------------------------------------- [ 2.613761] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.623573] mmc1: new ultra high speed SDR50 SDHC card at address aaaaCommand line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k-r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls
Output is in kBytes/sec
Time Resolution = 0.000001 seconds.
Processor cache size set to 32 kBytes.
Processor cache line size set to 64 bytes.
File stride size set to 17 * record size.
random
random bkwd record stride
kB reclen write rewrite read reread read
write read rewrite read fwrite frewrite fread
frereadQuoted 7 lines
10240 4 1809 0 7507 0 5233 859 10240 64 11622 0 31250 0 28072 516 10240 128 4320 0 34417 0 32509 1148My observation is that their slight increase in read/write operation.
Hope I have tried to answer you query. If I am wrong please let me know.
Nope, that did not answer my query. You gave some performance benchmarks but my question was not about the speed of anything. The question is (once again):
How do you know that these modes are really supported?You are marking the *host* as supporting these modes. Please provide information that host supports them *really*, not by experimenting "oh, it seems to work now, maybe it will work always".
Usually vendors, if their products implement some kind of specification/protocol, they mark the products as "compatible with XYZ" etc.
Best regards,
Krzysztof
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Signature · 2 lines
Regards, Alim
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Quoted 5 lines · Alim Akhtar
+Doug
Hello,
AFAIR,dw_mmchost controller does support UHS-I [1], specially SDR50 and SDR104 modes.
Quoted 8 lines
[1]: http://www.spinics.net/lists/linux-mmc/msg28186.html
What I remember is, one need to set "broken-cd" property also in order to make it work because of the vqmmc and vmmc connection on board. I didn't find the link right now, but you can search on the web, there was a long discussion about handling this.
Have not checked it recently, so not sure if this got broken somehow.
Please, don't top post.
I am not a SD/MMC specialist (I do not feel enough confident in its internals) but the datasheet for 5422 does not mention UHS. However it mentions "High Speed DDR Mode with 200 MHz clock rate (HS400)". This does not look like UHS...
https://www.sdcard.org/developers/overview/bus_speed/
This of course is not a definite proof that 5422 does not support UHS. I am just saying that I couldn't find any information that *it does*.
Best regards,
Krzysztof
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Quoted 15 lines · Krzysztof Kozlowski
Quoted 5 lines · Alim Akhtar
+Doug
Hello,
AFAIR,dw_mmchost controller does support UHS-I [1], specially SDR50 and SDR104 modes.Quoted 8 lines
[1]: http://www.spinics.net/lists/linux-mmc/msg28186.html
What I remember is, one need to set "broken-cd" property also in order to make it work because of the vqmmc and vmmc connection on board. I didn't find the link right now, but you can search on the web, there was a long discussion about handling this.
Have not checked it recently, so not sure if this got broken somehow.
Quoted 6 lines
Please, don't top post.
I am not a SD/MMC specialist (I do not feel enough confident in its internals) but the datasheet for 5422 does not mention UHS. However it mentions "High Speed DDR Mode with 200 MHz clock rate (HS400)". This does not look like UHS...
You're right. It's not UHS mode. it mentions eMMC's HS400 mode. UHS and HS400 are difference mode.
eMMC mode are supported
Quoted 3 lines
https://www.sdcard.org/developers/overview/bus_speed/
This of course is not a definite proof that 5422 does not support UHS. I am just saying that I couldn't find any information that *it does*.
Well, I think you want to know whether it supported or not. Then you can find the information at User manual.
In mobile storage part of User manual, it described the overview. Mobile storage host supports these specification:
- Secure Digital memory (SD memory version 3.0)
- Secure Digital I/O SDIO (SDIO version 3.0)
- etc...
SD3.0 is supported UHS-I mode.
If user manual of exynos5422 is mentioned this specification, it should be supported UHS-I mode.
If my understanding is wrong, let me know, plz.
Best Regards,
Jaehoon Chung
Quoted 5 lines
Best regards,
Krzysztof
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Quoted 40 lines · Jaehoon Chung
Quoted 15 lines · Krzysztof Kozlowski
Quoted 5 lines · Alim Akhtar
+Doug
Hello,
AFAIR,dw_mmchost controller does support UHS-I [1], specially SDR50 and SDR104 modes.Quoted 8 lines
[1]: http://www.spinics.net/lists/linux-mmc/msg28186.html
What I remember is, one need to set "broken-cd" property also in order to make it work because of the vqmmc and vmmc connection on board. I didn't find the link right now, but you can search on the web, there was a long discussion about handling this.
Have not checked it recently, so not sure if this got broken somehow.Quoted 6 lines
Please, don't top post.
I am not a SD/MMC specialist (I do not feel enough confident in its internals) but the datasheet for 5422 does not mention UHS. However it mentions "High Speed DDR Mode with 200 MHz clock rate (HS400)". This does not look like UHS...
You're right. It's not UHS mode. it mentions eMMC's HS400 mode. UHS and HS400 are difference mode.
eMMC mode are supported
Quoted 3 lines
https://www.sdcard.org/developers/overview/bus_speed/
This of course is not a definite proof that 5422 does not support UHS. I am just saying that I couldn't find any information that *it does*.Well, I think you want to know whether it supported or not. Then you can find the information at User manual.
In mobile storage part of User manual, it described the overview. Mobile storage host supports these specification:
- Secure Digital memory (SD memory version 3.0)
- Secure Digital I/O SDIO (SDIO version 3.0)
- etc...
Quoted 2 lines
SD3.0 is supported UHS-I mode.
If user manual of exynos5422 is mentioned this specification, it should be supported UHS-I mode.
Thanks! Indeed datasheet mentions that supported SD and SDIO is version 3.0 (not 3.01... which seems irrelevant because 3.0 introduced UHS-I, right?).
Best regards,
Krzysztof
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Quoted 41 lines · Krzysztof Kozlowski
Quoted 40 lines · Jaehoon Chung
Quoted 15 lines · Krzysztof Kozlowski
Quoted 5 lines · Alim Akhtar
+Doug
Hello,
AFAIR,dw_mmchost controller does support UHS-I [1], specially SDR50 and SDR104 modes.Quoted 8 lines
[1]: http://www.spinics.net/lists/linux-mmc/msg28186.html
What I remember is, one need to set "broken-cd" property also in order to make it work because of the vqmmc and vmmc connection on board. I didn't find the link right now, but you can search on the web, there was a long discussion about handling this.
Have not checked it recently, so not sure if this got broken somehow.Quoted 6 lines
Please, don't top post.
I am not a SD/MMC specialist (I do not feel enough confident in its internals) but the datasheet for 5422 does not mention UHS. However it mentions "High Speed DDR Mode with 200 MHz clock rate (HS400)". This does not look like UHS...
You're right. It's not UHS mode. it mentions eMMC's HS400 mode. UHS and HS400 are difference mode.
eMMC mode are supported
Quoted 3 lines
https://www.sdcard.org/developers/overview/bus_speed/
This of course is not a definite proof that 5422 does not support UHS. I am just saying that I couldn't find any information that *it does*.Well, I think you want to know whether it supported or not. Then you can find the information at User manual.
In mobile storage part of User manual, it described the overview. Mobile storage host supports these specification:
- Secure Digital memory (SD memory version 3.0)
- Secure Digital I/O SDIO (SDIO version 3.0)
- etc...
Quoted 7 lines
Quoted 2 lines
SD3.0 is supported UHS-I mode.
If user manual of exynos5422 is mentioned this specification, it should be supported UHS-I mode.Thanks! Indeed datasheet mentions that supported SD and SDIO is version 3.0 (not 3.01... which seems irrelevant because 3.0 introduced UHS-I, right?).
Yes, your understanding is right. SD3.0 does includes UHS-I.
Quoted 2 lines
Best regards,
Krzysztof
Signature · 2 lines
Regards, Alim
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
In reply to Krzysztof KozlowskiQuoted 8 lines · Krzysztof Kozlowski
Quoted 7 lines · Alim Akhtar
+Doug
Hello,
AFAIR,dw_mmchost controller does support UHS-I [1], specially SDR50 and SDR104 modes.
Quoted 9 lines
Quoted 6 lines
What I remember is, one need to set "broken-cd" property also in order to make it work because of the vqmmc and vmmc connection on board. I didn't find the link right now, but you can search on the web, there was a long discussion about handling this.
Have not checked it recently, so not sure if this got broken somehow.Please, don't top post.
I am sorry, but I didn't get this, what is the guide line here???
Quoted 11 lines
I am not a SD/MMC specialist (I do not feel enough confident in its internals) but the datasheet for 5422 does not mention UHS. However it mentions "High Speed DDR Mode with 200 MHz clock rate (HS400)". This does not look like UHS...
https://www.sdcard.org/developers/overview/bus_speed/
This of course is not a definite proof that 5422 does not support UHS. I am just saying that I couldn't find any information that *it does*.Best regards,
Krzysztof
Signature · 2 lines
Regards, Alim
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Quoted 17 lines · Alim Akhtar
Quoted 15 lines · Krzysztof Kozlowski
Quoted 13 lines · Alim Akhtar
+Doug
Hello,
AFAIR,dw_mmchost controller does support UHS-I [1], specially SDR50 and SDR104 modes.[1]: http://www.spinics.net/lists/linux-mmc/msg28186.html
What I remember is, one need to set "broken-cd" property also in order to make it work because of the vqmmc and vmmc connection on board. I didn't find the link right now, but you can search on the web, there was a long discussion about handling this.
Have not checked it recently, so not sure if this got broken somehow.
Quoted 3 lines
Quoted 2 lines
Please, don't top post.
I am sorry, but I didn't get this, what is the guide line here???
I mean reply inline, under the other person's quote, not above it.
And some old, really old joke:
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?
:)
Best regards,
Krzysztof
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Quoted 24 lines · Krzysztof Kozlowski
Quoted 17 lines · Alim Akhtar
Quoted 15 lines · Krzysztof Kozlowski
Quoted 13 lines · Alim Akhtar
+Doug
Hello,
AFAIR,dw_mmchost controller does support UHS-I [1], specially SDR50 and SDR104 modes.[1]: http://www.spinics.net/lists/linux-mmc/msg28186.html
What I remember is, one need to set "broken-cd" property also in order to make it work because of the vqmmc and vmmc connection on board. I didn't find the link right now, but you can search on the web, there was a long discussion about handling this.
Have not checked it recently, so not sure if this got broken somehow.Quoted 3 lines
Quoted 2 lines
Please, don't top post.
I am sorry, but I didn't get this, what is the guide line here???
I mean reply inline, under the other person's quote, not above it.
Quoted 8 lines
And some old, really old joke:
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?:)
I see..got it..thanks for clarification.
Quoted 3 lines
Best regards,
Krzysztof
Signature · 2 lines
Regards, Alim
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
In reply to Alim AkhtarHi,
Quoted 5 lines · Alim Akhtar
+Doug
Hello,
AFAIR,dw_mmchost controller does support UHS-I [1], specially SDR50 and SDR104 modes.
Quoted 7 lines
[1]: http://www.spinics.net/lists/linux-mmc/msg28186.html
What I remember is, one need to set "broken-cd" property also in order to make it work because of the vqmmc and vmmc connection on board. I didn't find the link right now, but you can search on the web, there was a long discussion about handling this.
Have not checked it recently, so not sure if this got broken somehow.
Right. It _shouldn't_ be possible to add "vmmc/vqmmc" supplies to your DTS (which you do in patch 2/3) and also to use the "gpc2-2" pin for card detect (even if you configure it as a GPIO). Once you add "vmmc/vqmmc" then Linux ought to be turning these regulators off when no card is plugged in. Presumably the "vqmmc" regulator is hooked up to the "VDDQ_MMC2". If you look in the user manual for 5422 you can see that "GPC2[2]/SD_2_CDn" has power domain "VDDQ_MMC2". Thus you really shouldn't be using that pin when vqmmc is off. I think at some point someone claimed that it still worked for them, but nobody could ever explain why. Full discussion at
<https://patchwork.kernel.org/patch/4763881/>
---
In case it matters, comments on stuff from earlier in the thread:
* As people pointed out, exynos5422 certainly supports all these modes (including DDR50) in the SoC.
* Just because the SoC supports these modes doesn't mean that the boards do, which is why the SoC .dtsi doesn't include them. Thus, this patch is "right" in that it changes a board-specific file.
* As Krzysztof points out this board doesn't "add" support but rather "enables" support. The distinction is subtle.
* You might be able to get DDR50 working, but probably better to just start with SDR modes. Previously I never attempted to get DDR50 cards working, so possibly the software needs extra work?
-Doug
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Hi Doug/ Krzysztof ,
Quoted 39 lines · Doug Anderson
Hi,
Quoted 5 lines · Alim Akhtar
+Doug
Hello,
AFAIR,dw_mmchost controller does support UHS-I [1], specially SDR50 and SDR104 modes.Quoted 7 lines
[1]: http://www.spinics.net/lists/linux-mmc/msg28186.html
What I remember is, one need to set "broken-cd" property also in order to make it work because of the vqmmc and vmmc connection on board. I didn't find the link right now, but you can search on the web, there was a long discussion about handling this.
Have not checked it recently, so not sure if this got broken somehow.Right. It _shouldn't_ be possible to add "vmmc/vqmmc" supplies to your DTS (which you do in patch 2/3) and also to use the "gpc2-2" pin for card detect (even if you configure it as a GPIO). Once you add "vmmc/vqmmc" then Linux ought to be turning these regulators off when no card is plugged in. Presumably the "vqmmc" regulator is hooked up to the "
VDDQ_MMC2". If you look in the user manual for 5422 you can see that "GPC2[2]/SD_2_CDn" has power domain "VDDQ_MMC2". Thus you really shouldn't be using that pin when vqmmc is off. I think at some point someone claimed that it still worked for them, but nobody could ever explain why. Full discussion at
<https://patchwork.kernel.org/patch/4763881/>---
In case it matters, comments on stuff from earlier in the thread:
* As people pointed out, exynos5422 certainly supports all these modes (including DDR50) in the SoC.
* Just because the SoC supports these modes doesn't mean that the boards do, which is why the SoC .dtsi doesn't include them. Thus, this patch is "right" in that it changes a board-specific file.
Quoted 7 lines
* As Krzysztof points out this board doesn't "add" support but rather "enables" support. The distinction is subtle.
* You might be able to get DDR50 working, but probably better to just start with SDR modes. Previously I never attempted to get DDR50 cards working, so possibly the software needs extra work?
Thanks for clarifying all the background details on the mmc changes.
Here is what I would conclude from the previous mail chain's.
1 Drop the cd-gpios changes. pinctrl-0 changes.
2 Fix the regulator changes for vmmc/vqmmc with disable of regulator-always-on;
3 Drop this UHS-I changes as if now.
Is this ok with you.
-Anand Moon
Quoted 2 lines
-Doug
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
W dniu 19.10.2015 o 19:11, Anand Moon pisze:
Quoted 8 lines
Hi Doug/ Krzysztof ,
Thanks for clarifying all the background details on the mmc changes.
Here is what I would conclude from the previous mail chain's.
1 Drop the cd-gpios changes. pinctrl-0 changes.
OK
Quoted 2 lines
2 Fix the regulator changes for vmmc/vqmmc with disable of regulator-always-on;
Just fix all the comments for patch 2.
Quoted 4 lines
3 Drop this UHS-I changes as if now.
Is this ok with you.
It's okay.
Best regards,
Krzysztof
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
In reply to Anand MoonHi,
Quoted 1 line · Anand Moon
1 Drop the cd-gpios changes. pinctrl-0 changes.
Right.
Quoted 1 line
2 Fix the regulator changes for vmmc/vqmmc with disable of regulator-always-on;
I'm not totally sure I understand. You should need to keep vmmc and vqmmc always on because otherwise you can't do card detection (unless you poll for card detect).
Quoted 1 line
3 Drop this UHS-I changes as if now.
Sounds right.
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
In reply to Krzysztof Kozlowskihi Krzysztof,
Quoted 129 lines · Krzysztof Kozlowski
Quoted 115 lines · Anand Moon
Hi Krzysztof,
Quoted 64 lines · Krzysztof Kozlowski
Quoted 62 lines · Anand Moon
Hi Krzysztof,
Quoted 17 lines · Krzysztof Kozlowski
Quoted 16 lines · Anand Moon
Hi Krzysztof,
Quoted 11 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
How do you know that these modes are really supported? I don't know. Can you convince me?
Quoted 9 lines
Quoted 2 lines
Setting this DDR50 capability give me this error. That's the reason to drop this capability.
But you mentioned it in commit message! "Added support for UHS-I ... (DDR50)"
In the same time dropping DDR50 is not an sufficient proof that "SDR50 and SDR104 are really supported".
These changes are related to the microSD card capabilities. So SDR50 have better frequency over DDR50. On the same Sandisk card.
When the card select the capability for DDR50
---------------------------------------------------[ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.009179] mmcblk0: error -110 sending status command, retrying [ 4.009271] mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0x900 [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63) [ 4.067770] Console: switching to colour frame buffer device 274x77 [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.099692] mmc1: tried to reset card [ 4.101332] mmcblk0: p1 p2When the card select the capability for SDR50
---------------------------------------------------------------------------------[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2Quoted 4 lines
Quoted 1 line
Which will relate to better read/write speed.
Which is not an answer to my question. To none of my previous questions.
Basically UHS-I capability (sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50, sd-uhs-sdr104) help tune speed supported for mmc
I have tired to compare the speed on high speed UHS-I vs ultra high speed UHS-I using izone utility.
[ 2.572469] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 2.572609] mmc1: new high speed SDHC card at address aaaaCommand line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k-r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls
Output is in kBytes/sec
Time Resolution = 0.000001 seconds.
Processor cache size set to 32 kBytes.
Processor cache line size set to 64 bytes.
File stride size set to 17 * record size.
random
random bkwd record stride
kB reclen write rewrite read reread read
write read rewrite read fwrite frewrite fread
freread10240 4 1631 0 6556 0 5538 982 10240 64 8828 0 18897 0 17994 303 10240 128 6269 0 20670 0 20128 1096 --------------------------------------------------------------------------------------------------------- [ 2.613761] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.623573] mmc1: new ultra high speed SDR50 SDHC card at address aaaaCommand line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k-r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls
Output is in kBytes/sec
Time Resolution = 0.000001 seconds.
Processor cache size set to 32 kBytes.
Processor cache line size set to 64 bytes.
File stride size set to 17 * record size.
random
random bkwd record stride
kB reclen write rewrite read reread read
write read rewrite read fwrite frewrite fread
frereadQuoted 7 lines
10240 4 1809 0 7507 0 5233 859 10240 64 11622 0 31250 0 28072 516 10240 128 4320 0 34417 0 32509 1148My observation is that their slight increase in read/write operation.
Hope I have tried to answer you query. If I am wrong please let me know.
Nope, that did not answer my query. You gave some performance benchmarks but my question was not about the speed of anything. The question is (once again):
How do you know that these modes are really supported?
Quoted 6 lines
You are marking the *host* as supporting these modes. Please provide information that host supports them *really*, not by experimenting "oh, it seems to work now, maybe it will work always".
Usually vendors, if their products implement some kind of specification/protocol, they mark the products as "compatible with XYZ" etc.
I found this link from hardkernel website which specify the interface support
http://www.hardkernel.com/main/products/prdt_info.php?g_code=G141578491347
Manufacturer Part Number : Sandisk SDSDQAD-016G
Interface : UHS-1 SDR50
I don't know much internal specification of the Odroid XU3/XU4 Boards.
I am not sure if it will support host will sd-uhs-sdr104, but it will be compatible for sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50.
-Anand Moon
Quoted 3 lines
Best regards,
Krzysztof
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
Quoted 144 lines · Anand Moon
hi Krzysztof,
Quoted 129 lines · Krzysztof Kozlowski
Quoted 115 lines · Anand Moon
Hi Krzysztof,
Quoted 64 lines · Krzysztof Kozlowski
Quoted 62 lines · Anand Moon
Hi Krzysztof,
Quoted 17 lines · Krzysztof Kozlowski
Quoted 16 lines · Anand Moon
Hi Krzysztof,
Quoted 11 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
How do you know that these modes are really supported? I don't know. Can you convince me?
Quoted 9 lines
Quoted 2 lines
Setting this DDR50 capability give me this error. That's the reason to drop this capability.
But you mentioned it in commit message! "Added support for UHS-I ... (DDR50)"
In the same time dropping DDR50 is not an sufficient proof that "SDR50 and SDR104 are really supported".
These changes are related to the microSD card capabilities. So SDR50 have better frequency over DDR50. On the same Sandisk card.
When the card select the capability for DDR50
---------------------------------------------------[ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.009179] mmcblk0: error -110 sending status command, retrying [ 4.009271] mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0x900 [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63) [ 4.067770] Console: switching to colour frame buffer device 274x77 [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.099692] mmc1: tried to reset card [ 4.101332] mmcblk0: p1 p2When the card select the capability for SDR50
---------------------------------------------------------------------------------[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2Quoted 4 lines
Quoted 1 line
Which will relate to better read/write speed.
Which is not an answer to my question. To none of my previous questions.
Basically UHS-I capability (sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50, sd-uhs-sdr104) help tune speed supported for mmc
I have tired to compare the speed on high speed UHS-I vs ultra high speed UHS-I using izone utility.
[ 2.572469] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 2.572609] mmc1: new high speed SDHC card at address aaaaCommand line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k-r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls
Output is in kBytes/sec
Time Resolution = 0.000001 seconds.
Processor cache size set to 32 kBytes.
Processor cache line size set to 64 bytes.
File stride size set to 17 * record size.
random
random bkwd record stride
kB reclen write rewrite read reread read
write read rewrite read fwrite frewrite fread
freread10240 4 1631 0 6556 0 5538 982 10240 64 8828 0 18897 0 17994 303 10240 128 6269 0 20670 0 20128 1096 --------------------------------------------------------------------------------------------------------- [ 2.613761] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.623573] mmc1: new ultra high speed SDR50 SDHC card at address aaaaCommand line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k-r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls
Output is in kBytes/sec
Time Resolution = 0.000001 seconds.
Processor cache size set to 32 kBytes.
Processor cache line size set to 64 bytes.
File stride size set to 17 * record size.
random
random bkwd record stride
kB reclen write rewrite read reread read
write read rewrite read fwrite frewrite fread
frereadQuoted 7 lines
10240 4 1809 0 7507 0 5233 859 10240 64 11622 0 31250 0 28072 516 10240 128 4320 0 34417 0 32509 1148My observation is that their slight increase in read/write operation.
Hope I have tried to answer you query. If I am wrong please let me know.
Nope, that did not answer my query. You gave some performance benchmarks but my question was not about the speed of anything. The question is (once again):
How do you know that these modes are really supported?Quoted 6 lines
You are marking the *host* as supporting these modes. Please provide information that host supports them *really*, not by experimenting "oh, it seems to work now, maybe it will work always".
Usually vendors, if their products implement some kind of specification/protocol, they mark the products as "compatible with XYZ" etc.
I found this link from hardkernel website which specify the interface support
http://www.hardkernel.com/main/products/prdt_info.php?g_code=G141578491347
Quoted 7 lines
Manufacturer Part Number : Sandisk SDSDQAD-016G
Interface : UHS-1 SDR50I don't know much internal specification of the Odroid XU3/XU4 Boards.
I am not sure if it will support host will sd-uhs-sdr104, but it will be compatible for sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50.
I can't find how this proofs anything.
You can sell an UHS-II card labelled "for ODROID-XU3 and XU4" and it will work fine on Odroid-XU3. Does it mean that Odroid-XU3 supports UHS-II?
That UHS-II card will work even on 10-year camera! Of course not in UHS mode... Does it mean that this 10-year old camera supports UHS-II? Of course not because it will work in some HS mode (or even pre-HS).
You can label any SD card as "for Odroid XU3" because any card will work...
Best regards,
Krzysztof
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
In reply to Anand MoonHi, Anand.
Quoted 63 lines · Anand Moon
hi Krzysztof,
Quoted 59 lines · Krzysztof Kozlowski
Quoted 58 lines · Anand Moon
Hi Krzysztof,
Quoted 54 lines · Krzysztof Kozlowski
Quoted 52 lines · Anand Moon
Hi Krzysztof,
Quoted 17 lines · Krzysztof Kozlowski
Quoted 16 lines · Anand Moon
Hi Krzysztof,
Quoted 11 lines · Krzysztof Kozlowski
Quoted 1 line · Anand Moon
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported").
You mentioned DDR50 but I don't see respective property below.
How do you know that these modes are really supported? I don't know. Can you convince me?
Quoted 9 lines
Quoted 2 lines
Setting this DDR50 capability give me this error. That's the reason to drop this capability.
But you mentioned it in commit message! "Added support for UHS-I ... (DDR50)"
In the same time dropping DDR50 is not an sufficient proof that "SDR50 and SDR104 are really supported".
These changes are related to the microSD card capabilities. So SDR50 have better frequency over DDR50. On the same Sandisk card.
When the card select the capability for DDR50
---------------------------------------------------[ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.009179] mmcblk0: error -110 sending status command, retrying [ 4.009271] mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0x900 [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63) [ 4.067770] Console: switching to colour frame buffer device 274x77 [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.099692] mmc1: tried to reset card [ 4.101332] mmcblk0: p1 p2
I found this issue that produced on your board. I will send the patch and test DDR50 on your board.
Best Regards,
Jaehoon Chung
Quoted 95 lines
Quoted 70 lines
Quoted 57 lines
Quoted 10 lines
Quoted 10 lines
When the card select the capability for SDR50
---------------------------------------------------------------------------------[ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2Quoted 4 lines
Quoted 1 line
Which will relate to better read/write speed.
Which is not an answer to my question. To none of my previous questions.
Basically UHS-I capability (sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50, sd-uhs-sdr104) help tune speed supported for mmc
I have tired to compare the speed on high speed UHS-I vs ultra high speed UHS-I using izone utility.
[ 2.572469] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 2.572609] mmc1: new high speed SDHC card at address aaaaCommand line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k-r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls
Output is in kBytes/sec
Time Resolution = 0.000001 seconds.
Processor cache size set to 32 kBytes.
Processor cache line size set to 64 bytes.
File stride size set to 17 * record size.
random
random bkwd record stride
kB reclen write rewrite read reread read
write read rewrite read fwrite frewrite fread
freread10240 4 1631 0 6556 0 5538 982 10240 64 8828 0 18897 0 17994 303 10240 128 6269 0 20670 0 20128 1096 --------------------------------------------------------------------------------------------------------- [ 2.613761] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.623573] mmc1: new ultra high speed SDR50 SDHC card at address aaaaCommand line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k-r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls
Output is in kBytes/sec
Time Resolution = 0.000001 seconds.
Processor cache size set to 32 kBytes.
Processor cache line size set to 64 bytes.
File stride size set to 17 * record size.
random
random bkwd record stride
kB reclen write rewrite read reread read
write read rewrite read fwrite frewrite fread
frereadQuoted 7 lines
10240 4 1809 0 7507 0 5233 859 10240 64 11622 0 31250 0 28072 516 10240 128 4320 0 34417 0 32509 1148My observation is that their slight increase in read/write operation.
Hope I have tried to answer you query. If I am wrong please let me know.
Nope, that did not answer my query. You gave some performance benchmarks but my question was not about the speed of anything. The question is (once again):
How do you know that these modes are really supported?Quoted 6 lines
You are marking the *host* as supporting these modes. Please provide information that host supports them *really*, not by experimenting "oh, it seems to work now, maybe it will work always".
Usually vendors, if their products implement some kind of specification/protocol, they mark the products as "compatible with XYZ" etc.
I found this link from hardkernel website which specify the interface support
http://www.hardkernel.com/main/products/prdt_info.php?g_code=G141578491347
Manufacturer Part Number : Sandisk SDSDQAD-016G
Interface : UHS-1 SDR50I don't know much internal specification of the Odroid XU3/XU4 Boards.
I am not sure if it will support host will sd-uhs-sdr104, but it will be compatible for sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50.
-Anand Moon
Quoted 3 lines
Best regards,
Krzysztof
Quoted 19 lines · Anand Moon
From: Jaehoon Chung <[email protected]>
To detect sd-card use the cd-gpio method.
It can decrease the interrupt for detecting sd-card.Signed-off-by Jaehoon Chung <[email protected]>Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branch--- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +0
-0
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 358
Quoted 8 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3
-1@@ -352,8 +352,10 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + cd-gpios = <&gpc2 2 GPIO_ACTIVE_HIGH>; + cd-inverted; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
Anand,
You essentially reverted here af6ad88acbd6 ("ARM: dts: Mux XMMCnDATA[0] pad correctly for Exynos5420 boards"). Why? There is no explanation in the commit message about this.
Best regards,
Krzysztof
Hi,
Quoted 15 lines · Krzysztof Kozlowski
Quoted 14 lines · Anand Moon
From: Jaehoon Chung <[email protected]>
To detect sd-card use the cd-gpio method.
It can decrease the interrupt for detecting sd-card.Signed-off-by Jaehoon Chung <[email protected]>Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branch--- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
Quoted 13 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 358
Quoted 13 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3
-1@@ -352,8 +352,10 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + cd-gpios = <&gpc2 2 GPIO_ACTIVE_HIGH>; + cd-inverted; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
Don't do change this.
Quoted 6 lines
Anand,
You essentially reverted here
af6ad88acbd6("ARM: dts: Mux XMMCnDATA[0] pad correctly for Exynos5420 boards"). Why? There is no explanation in the commit message about this.
I don't remember to send the patch relevant to this. Hmm... Well, Is this patch really signed-off by me?
Best Regards,
Jaehoon Chung
Quoted 5 lines
Best regards,
Krzysztof
PATCH 1/3 ARM: dts: exynos5422-odroidxu3: use cd-gpio method to detect sd-card
Hi All,
On Monday, October 12, 2015 10:14 AM, Jaehoon Chung <[email protected]> wrote:
Hi,
Quoted 15 lines · Krzysztof Kozlowski
Quoted 14 lines · Anand Moon
From: Jaehoon Chung <[email protected]>
To detect sd-card use the cd-gpio method.
It can decrease the interrupt for detecting sd-card.Signed-off-by Jaehoon Chung <[email protected]>Signed-off-by Anand Moon <[email protected]>---
Changes based ongit://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.gitv4.4-next/dt-samsung branch--- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
Quoted 13 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 358
Quoted 13 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3
-1@@ -352,8 +352,10 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + cd-gpios = <&gpc2 2 GPIO_ACTIVE_HIGH>; + cd-inverted; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
Don't do change this.
Quoted 6 lines
Anand,
You essentially reverted here
af6ad88acbd6("ARM: dts: Mux XMMCnDATA[0] pad correctly for Exynos5420 boards"). Why? There is no explanation in the commit message about this.
I don't remember to send the patch relevant to this. Hmm... Well, Is this patch really signed-off by me?
Best Regards,
Jaehoon Chung
Quoted 6 lines
Best regards,
Krzysztof
Some how I don't receive these mail on my email id.
I have picked up these changes from tizen repository for OdroidXU3. I have tested with this changes to detect UHS-I micro cd cards. That's the reason for this email.
If it's wrong then I will drop it.
-Anand Moon
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Quoted 21 lines · Anand Moon
Quoted 6 lines
Anand,
You essentially reverted here
af6ad88acbd6("ARM: dts: Mux XMMCnDATA[0] pad correctly for Exynos5420 boards"). Why? There is no explanation in the commit message about this.I don't remember to send the patch relevant to this. Hmm... Well, Is this patch really signed-off by me?
Best Regards,
Jaehoon Chung
Quoted 6 lines
Best regards,
Krzysztof
Quoted 5 lines
Some how I don't receive these mail on my email id.
I have picked up these changes from tizen repository for OdroidXU3. I have tested with this changes to detect UHS-I micro cd cards. That's the reason for this email.
... and you applied it blindly without looking at actual existing contents and at previous commits.
That is not how patches from different repositories should be cherry picked.
Best regards,
Krzysztof
Dear, Anand.
Quoted 22 lines · Krzysztof Kozlowski
Quoted 21 lines · Anand Moon
Quoted 6 lines
Anand,
You essentially reverted here
af6ad88acbd6("ARM: dts: Mux XMMCnDATA[0] pad correctly for Exynos5420 boards"). Why? There is no explanation in the commit message about this.I don't remember to send the patch relevant to this. Hmm... Well, Is this patch really signed-off by me?
Best Regards,
Jaehoon Chung
Quoted 6 lines
Best regards,
Krzysztof
Quoted 5 lines
Quoted 5 lines
Some how I don't receive these mail on my email id.
I have picked up these changes from tizen repository for OdroidXU3. I have tested with this changes to detect UHS-I micro cd cards. That's the reason for this email.
It seems to make manually, right?
I have checked the tizen repository.
The below is
arch/arm/boot/dts/exynos5422-odroidxu3.dts +3 -1
@@ -335,7 +335,9 @@ samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + cd-gpios = <&gpc2 2 0>; + cd-inverted; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; };
Yours
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3 -1
@@ -352,8 +352,10 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + cd-gpios = <&gpc2 2 GPIO_ACTIVE_HIGH>; + cd-inverted; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
Did you know what differ? :)
Best Regards,
Jaehoon Chung
Quoted 10 lines
... and you applied it blindly without looking at actual existing contents and at previous commits.
That is not how patches from different repositories should be cherry picked.
Best regards,
Krzysztof
Hi Jaehoon Chung,
Quoted 59 lines · Jaehoon Chung
Dear, Anand.
Quoted 22 lines · Krzysztof Kozlowski
Quoted 21 lines · Anand Moon
Quoted 6 lines
Anand,
You essentially reverted here
af6ad88acbd6("ARM: dts: Mux XMMCnDATA[0] pad correctly for Exynos5420 boards"). Why? There is no explanation in the commit message about this.I don't remember to send the patch relevant to this. Hmm... Well, Is this patch really signed-off by me?
Best Regards,
Jaehoon Chung
Quoted 6 lines
Best regards,
KrzysztofQuoted 5 lines
Quoted 5 lines
Some how I don't receive these mail on my email id.
I have picked up these changes from tizen repository for OdroidXU3. I have tested with this changes to detect UHS-I micro cd cards. That's the reason for this email.
It seems to make manually, right?
I have checked the tizen repository.The below is
arch/arm/boot/dts/exynos5422-odroidxu3.dts +3
-1@@ -335,7 +335,9 @@ samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + cd-gpios = <&gpc2 2 0>; + cd-inverted; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; };Yours
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +0
-0@@ -352,8 +352,10 @@ samsung,dw-mshc-ciu-div = <3>;
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi line 361
Quoted 10 lines
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3
-1samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + cd-gpios = <&gpc2 2 GPIO_ACTIVE_HIGH>; + cd-inverted; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; Did you know what differ? :)
My mistake, I will drop the changes. Sorry for the whole mess.
-Anand Moon
Quoted 14 lines
Best Regards,
Jaehoon ChungQuoted 10 lines
... and you applied it blindly without looking at actual existing contents and at previous commits.
That is not how patches from different repositories should be cherry picked.
Best regards,
Krzysztof
Hi Jaehoon,
Quoted 69 lines · Jaehoon Chung
Dear, Anand.
Quoted 22 lines · Krzysztof Kozlowski
Quoted 21 lines · Anand Moon
Quoted 6 lines
Anand,
You essentially reverted here
af6ad88acbd6("ARM: dts: Mux XMMCnDATA[0] pad correctly for Exynos5420 boards"). Why? There is no explanation in the commit message about this.I don't remember to send the patch relevant to this. Hmm... Well, Is this patch really signed-off by me?
Best Regards,
Jaehoon Chung
Quoted 6 lines
Best regards,
KrzysztofQuoted 5 lines
Quoted 5 lines
Some how I don't receive these mail on my email id.
I have picked up these changes from tizen repository for OdroidXU3. I have tested with this changes to detect UHS-I micro cd cards. That's the reason for this email.
It seems to make manually, right?
I have checked the tizen repository.The below is
arch/arm/boot/dts/exynos5422-odroidxu3.dts +3
-1@@ -335,7 +335,9 @@ samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + cd-gpios = <&gpc2 2 0>; + cd-inverted; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; };Yours
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +3
-1@@ -352,8 +352,10 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + cd-gpios = <&gpc2 2 GPIO_ACTIVE_HIGH>; + cd-inverted; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; Did you know what differ? :)
Quoted 14 lines
Best Regards,
Jaehoon ChungQuoted 10 lines
... and you applied it blindly without looking at actual existing contents and at previous commits.
That is not how patches from different repositories should be cherry picked.
Best regards,
Krzysztof
Looks like my changes have introduce another bug so please ignore this changes.
-Anand Moon
Hi Krzysztof,
Quoted 24 lines · Krzysztof Kozlowski
Quoted 23 lines · Anand Moon
Quoted 6 lines
Anand,
You essentially reverted here
af6ad88acbd6("ARM: dts: Mux XMMCnDATA[0] pad correctly for Exynos5420 boards"). Why? There is no explanation in the commit message about this.I don't remember to send the patch relevant to this. Hmm... Well, Is this patch really signed-off by me?
Best Regards,
Jaehoon Chung
Quoted 6 lines
Best regards,
KrzysztofSome how I don't receive these mail on my email id.
Quoted 8 lines
Quoted 3 lines
I have picked up these changes from tizen repository for OdroidXU3. I have tested with this changes to detect UHS-I micro cd cards. That's the reason for this email.
... and you applied it blindly without looking at actual existing contents and at previous commits.
That is not how patches from different repositories should be cherry picked.
Sorry But I did not change it right way. By looking at the diff. If the changes are wrong I will drop that changes.
I have to dig in my logs to find out why I have changes this setting. Here is the log below, I will check If I am able to reproduce this bug in the current kernel.
Sorry for the mess I have created.
---------------------------------------------------------------------------------------
Oct 6 08:23:21 odroidxu4 kernel: [ 6.559940]
======================================================
Oct 6 08:23:21 odroidxu4 kernel: [ 6.559943] [ INFO: possible
circular locking dependency detected ]
Oct 6 08:23:21 odroidxu4 kernel: [ 6.559947] 4.2.0-xu4hkdn #7 Not tainted
Oct 6 08:23:21 odroidxu4 kernel: [ 6.559950]
-------------------------------------------------------
Oct 6 08:23:21 odroidxu4 kernel: [ 6.559954] swapper/0/1 is trying
to acquire lock:
Oct 6 08:23:21 odroidxu4 kernel: [ 6.559972]
(&map->mutex){+.+...}, at: [<c04a9414>] regmap_lock_mutex+0x1c/0x20
Oct 6 08:23:21 odroidxu4 kernel: [ 6.559975]
Oct 6 08:23:21 odroidxu4 kernel: [ 6.559975] but task is already
holding lock:
Oct 6 08:23:21 odroidxu4 kernel: [ 6.559987]
(prepare_lock){+.+.+.}, at: [<c05b468c>] clk_prepare_lock+0x20/0x108
Oct 6 08:23:21 odroidxu4 kernel: [ 6.559990]
Oct 6 08:23:21 odroidxu4 kernel: [ 6.559990] which lock already
depends on the new lock.
Oct 6 08:23:21 odroidxu4 kernel: [ 6.559990]
Oct 6 08:23:21 odroidxu4 kernel: [ 6.559993]
Oct 6 08:23:21 odroidxu4 kernel: [ 6.559993] the existing
dependency chain (in reverse order) is:
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560004]
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560004] -> #1 (prepare_lock){+.+.+.}:
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560019] [<c06b90d0>]
mutex_lock_nested+0x84/0x4e4
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560026] [<c05b46cc>]
clk_prepare_lock+0x60/0x108
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560033] [<c05b84a8>]
clk_unprepare+0x28/0x38
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560044] [<c0542ba8>]
exynos5_i2c_xfer+0x2dc/0x3a4
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560051] [<c053e1b4>]
__i2c_transfer+0x160/0xc60
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560057] [<c053ed28>]
i2c_transfer+0x74/0xa0
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560065] [<c04b2be4>]
regmap_i2c_read+0x58/0x74
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560072] [<c04ac38c>]
_regmap_raw_read+0x130/0x654
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560078] [<c04ac8e4>]
_regmap_bus_read+0x34/0x6c
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560083] [<c04ab350>]
_regmap_read+0x7c/0x350
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560090] [<c04ab674>]
regmap_read+0x50/0x70
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560100] [<c04043a0>]
regulator_is_enabled_regmap+0x30/0xa4
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560107] [<c03ff73c>]
_regulator_is_enabled.part.10+0x2c/0x38
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560113] [<c04000c4>]
_regulator_do_set_voltage+0x720/0x9d0
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560119] [<c0400438>]
regulator_set_voltage+0xc4/0x150
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560129] [<c0589d6c>]
dw_mci_switch_voltage+0x98/0xbc
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560136] [<c0570dc0>]
mmc_power_up.part.16+0x6c/0x108
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560143] [<c0571e44>]
mmc_start_host+0x54/0x78
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560149] [<c0573194>]
mmc_add_host+0x6c/0x90
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560156] [<c058ae84>]
dw_mci_probe+0x660/0xc98
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560162] [<c058c978>]
dw_mci_pltfm_register+0x9c/0xa8
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560168] [<c058d014>]
dw_mci_exynos_probe+0x30/0x38
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560176] [<c048de40>]
platform_drv_probe+0x54/0xb4
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560183] [<c048b9d8>]
driver_probe_device+0x184/0x2c0
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560189] [<c048bbb8>]
__driver_attach+0xa4/0xa8
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560195] [<c0489b90>]
bus_for_each_dev+0x78/0xac
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560202] [<c048b498>]
driver_attach+0x2c/0x30
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560208] [<c048b0a4>]
bus_add_driver+0x1b0/0x228
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560214] [<c048ce6c>]
driver_register+0x88/0x108
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560221] [<c048dd6c>]
__platform_driver_register+0x64/0x6c
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560229] [<c0995abc>]
dw_mci_exynos_pltfm_driver_init+0x1c/0x20
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560237] [<c0009820>]
do_one_initcall+0x9c/0x1e8
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560245] [<c095efa8>]
kernel_init_freeable+0x250/0x2f4
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560252] [<c06b3774>]
kernel_init+0x1c/0xf8
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560259] [<c000fe58>]
ret_from_fork+0x14/0x3c
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560269]
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560269] -> #0 (&map->mutex){+.+...}:
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560277] [<c008ac00>]
lock_acquire+0x128/0x378
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560284] [<c06b90d0>]
mutex_lock_nested+0x84/0x4e4
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560290] [<c04a9414>]
regmap_lock_mutex+0x1c/0x20
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560296] [<c04ab664>]
regmap_read+0x40/0x70
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560304] [<c05bd62c>]
s2mps11_clk_is_prepared+0x30/0x4c
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560310] [<c05b4bc8>]
clk_unprepare_unused_subtree+0x84/0x564
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560316] [<c05b7940>]
clk_disable_unused+0xb8/0x148
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560322] [<c0009820>]
do_one_initcall+0x9c/0x1e8
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560328] [<c095efa8>]
kernel_init_freeable+0x250/0x2f4
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560334] [<c06b3774>]
kernel_init+0x1c/0xf8
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560340] [<c000fe58>]
ret_from_fork+0x14/0x3c
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560343]
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560343] other info that might
help us debug this:
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560343]
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560346] Possible unsafe
locking scenario:
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560346]
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560349] CPU0
CPU1
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560351] ----
----
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560358] lock(prepare_lock);
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560365]
lock(&map->mutex);
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560371]
lock(prepare_lock);
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560378] lock(&map->mutex);
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560380]
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560380] *** DEADLOCK ***
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560380]
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560384] 1 lock held by swapper/0/1:
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560397] #0:
(prepare_lock){+.+.+.}, at: [<c05b468c>] clk_prepare_lock+0x20/0x108
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560400]
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560400] stack backtrace:
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560405] CPU: 2 PID: 1 Comm:
swapper/0 Not tainted 4.2.0-xu4hkdn #7
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560408] Hardware name:
SAMSUNG EXYNOS (Flattened Device Tree)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560418] [<c00189bc>]
(unwind_backtrace) from [<c0014608>] (show_stack+0x20/0x24)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560424] [<c0014608>]
(show_stack) from [<c06b64f8>] (dump_stack+0x8c/0xcc)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560430] [<c06b64f8>]
(dump_stack) from [<c0083c34>] (print_circular_bug+0x218/0x340)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560436] [<c0083c34>]
(print_circular_bug) from [<c0089d14>] (__lock_acquire+0x1c40/0x227c)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560441] [<c0089d14>]
(__lock_acquire) from [<c008ac00>] (lock_acquire+0x128/0x378)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560447] [<c008ac00>]
(lock_acquire) from [<c06b90d0>] (mutex_lock_nested+0x84/0x4e4)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560453] [<c06b90d0>]
(mutex_lock_nested) from [<c04a9414>] (regmap_lock_mutex+0x1c/0x20)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560458] [<c04a9414>]
(regmap_lock_mutex) from [<c04ab664>] (regmap_read+0x40/0x70)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560464] [<c04ab664>]
(regmap_read) from [<c05bd62c>] (s2mps11_clk_is_prepared+0x30/0x4c)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560471] [<c05bd62c>]
(s2mps11_clk_is_prepared) from [<c05b4bc8>]
(clk_unprepare_unused_subtree+0x84/0x564)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560477] [<c05b4bc8>]
(clk_unprepare_unused_subtree) from [<c05b7940>]
(clk_disable_unused+0xb8/0x148)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560482] [<c05b7940>]
(clk_disable_unused) from [<c0009820>] (do_one_initcall+0x9c/0x1e8)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560487] [<c0009820>]
(do_one_initcall) from [<c095efa8>] (kernel_init_freeable+0x250/0x2f4)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560493] [<c095efa8>]
(kernel_init_freeable) from [<c06b3774>] (kernel_init+0x1c/0xf8)
Oct 6 08:23:21 odroidxu4 kernel: [ 6.560498] [<c06b3774>](kernel_init) from [<c000fe58>] (ret_from_fork+0x14/0x3c)
-Anand Moon
Quoted 4 lines
Best regards,
Krzysztof