ARM: sunxi: Introduce CHIP support
Subsystems (5)
v2 cover ARM: sunxi: Introduce CHIP support
Hi,
Here is a serie introducing the support for the Allwinner R8 and the Nextthing's CHIP.
The only missing parts for now are the display on the composite output and the NAND support that will come in due time.
Everything else should work just fine, including the USB gadget and host support.
Let me know what you think,
Maxime
Changes from v1:
- Rebased on top of current sunxi next branch
- Added regulators voltage
- Synced the DTS with what has been accepted in the kernel
- Added CONFIG_MMC rework
Maxime Ripard (7):
fastboot: Implement OEM format only when we have MMC support
mmc: Add generic Kconfig option
sunxi: board: Only try to use the MMC related functions if enabled
sunxi: Use Kconfig CONFIG_MMC
sun5i: Sync the DTSI with the kernel
axp209: Sync the DTSI with the kernel
sunxi: Add CHIP support
arch/arm/cpu/armv7/sunxi/board.c | 6 +- arch/arm/dts/Makefile | 3 +- arch/arm/dts/axp209.dtsi | 5 + arch/arm/dts/sun5i-a10s.dtsi | 47 +++++++-- arch/arm/dts/sun5i-a13.dtsi | 28 ++++- arch/arm/dts/sun5i-r8-chip.dts | 214 +++++++++++++++++++++++++++++++++++++++ arch/arm/dts/sun5i-r8.dtsi | 59 +++++++++++ arch/arm/dts/sun5i.dtsi | 22 ++++ board/sunxi/Kconfig | 4 + configs/CHIP_defconfig | 14 +++ drivers/mmc/Kconfig | 6 ++ drivers/usb/gadget/f_fastboot.c | 2 +- include/configs/sunxi-common.h | 8 +- 13 files changed, 402 insertions(+), 16 deletions(-) create mode 100644 arch/arm/dts/sun5i-r8-chip.dts create mode 100644 arch/arm/dts/sun5i-r8.dtsi create mode 100644 configs/CHIP_defconfig
Signature · 1 line
2.5.3
PATCH v2 1/7 fastboot: Implement OEM format only when we have MMC support
The current fastboot support assumes that CONFIG_FASTBOOT_FLASH implies that we have an MMC in our system, which might not be the case if we have some other storage device.
Change the configuration option protecting that call to FASTBOOT_FLASH_MMC_DEV, that makes much more sense.
Signed-off-by Maxime Ripard <[email protected]>
Reviewed-by Tom Rini <[email protected]>
--- drivers/usb/gadget/f_fastboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/usb/gadget/f_fastboot.c +1 -1
@@ -554,7 +554,7 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req) static void cb_oem(struct usb_ep *ep, struct usb_request *req) { char *cmd = req->buf; -#ifdef CONFIG_FASTBOOT_FLASH +#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV if (strncmp("format", cmd + 4, 6) == 0) { char cmdbuf[32]; sprintf(cmdbuf, "gpt write mmc %x $partitions",
Signature · 1 line
2.5.3
PATCH v2 2/7 mmc: Add generic Kconfig option
In reply to Maxime RipardAdd a generic Kconfig option for the CONFIG_MMC option that was used before in the configuration headers.
Since all the architectures need to be converted to that first, depend on an non-existent config option that will be extended with architectures that use that option.
Signed-off-by Maxime Ripard <[email protected]>
--- drivers/mmc/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+)
drivers/mmc/Kconfig +6 -0
@@ -1,5 +1,11 @@ menu "MMC Host controller Support" +config MMC + bool "Enable MMC support" + depends on UNUSED + help + TODO: Move all architectures to use this option + config DM_MMC bool "Enable MMC controllers using Driver Model" depends on DM
Signature · 1 line
2.5.3
PATCH v2 3/7 sunxi: board: Only try to use the MMC related functions if enabled
In reply to Maxime RipardSo far, even if CONFIG_MMC was not enabled the board code was trying to use the MMC-related functions, resulting in linker errors.
Protect those calls by an ifdef.
Signed-off-by Maxime Ripard <[email protected]>
--- arch/arm/cpu/armv7/sunxi/board.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/sunxi/board.c +5 -1
@@ -136,7 +136,7 @@ DECLARE_GLOBAL_DATA_PTR;*/ u32 spl_boot_device (void ) { -struct mmc *mmc0, *mmc1; +__maybe_unused struct mmc *mmc0, *mmc1;/* * When booting from the SD card or NAND memory, the "eGON.BT0" * signature is expected to be found in memory at the address 0x0004
@@ -157,15 +157,18 @@ u32 spl_boot_device(void)return BOOT_DEVICE_BOARD ;/* The BROM will try to boot from mmc0 first, so try that first. */ +#ifdef CONFIG_MMC mmc_initialize (gd->bd); mmc0 =find_mmc_device (0 );if (sunxi_mmc_has_egon_boot_signature (mmc0))return BOOT_DEVICE_MMC1 ; +#endif /* Fallback to booting NAND if enabled. */ if (IS_ENABLED (CONFIG_SPL_NAND_SUPPORT ))return BOOT_DEVICE_NAND ; +#ifdef CONFIG_MMC if (CONFIG_MMC_SUNXI_SLOT_EXTRA ==2 ) { mmc1 =find_mmc_device (1 );if (sunxi_mmc_has_egon_boot_signature (mmc1)) {
@@ -179,6 +182,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_MMC2; } } +#endif panic ("Could not determine boot source\n" );return -1 ;/* Never reached */
Signature · 1 line
2.5.3
PATCH v2 4/7 sunxi: Use Kconfig CONFIG_MMC
In reply to Maxime RipardNot all sunxi boards have an MMC embedded. Switching to the Kconfig option will allow to enable or disable the support in each boards' defconfig.
Signed-off-by Maxime Ripard <[email protected]>
--- board/sunxi/Kconfig | 4 ++++ drivers/mmc/Kconfig | 2 +- include/configs/sunxi-common.h | 8 +++++--- 3 files changed, 10 insertions(+), 4 deletions(-)
board/sunxi/Kconfig +4 -0
@@ -227,6 +227,10 @@ config OLD_SUNXI_KERNEL_COMPAT Set this to enable various workarounds for old kernels, this results in sub-optimal settings for newer kernels, only enable if needed. +config MMC + depends on !UART0_PORT_F + default y if ARCH_SUNXI + config MMC0_CD_PIN string "Card detect pin for mmc0" default ""
drivers/mmc/Kconfig +1 -1
@@ -2,7 +2,7 @@ menu "MMC Host controller Support" config MMC bool "Enable MMC support" - depends on UNUSED + depends on ARCH_SUNXI help TODO: Move all architectures to use this option
include/configs/sunxi-common.h +5 -3
@@ -140,8 +140,7 @@#endif /* mmc config */ -#if !defined(CONFIG_UART0_PORT_F ) -#define CONFIG_MMC +#if defined(CONFIG_MMC )#define CONFIG_GENERIC_MMC #define CONFIG_CMD_MMC #define CONFIG_MMC_SUNXI
@@ -197,7 +196,7 @@#define CONFIG_SPL_LIBDISK_SUPPORT -#if !defined(CONFIG_UART0_PORT_F ) +#if defined(CONFIG_MMC )#define CONFIG_SPL_MMC_SUPPORT #endif
@@ -354,9 +353,12 @@ extern int soft_i2c_gpio_scl;#define CONFIG_FASTBOOT_BUF_SIZE 0x2000000#define CONFIG_FASTBOOT_FLASH + +#ifdef CONFIG_MMC #define CONFIG_FASTBOOT_FLASH_MMC_DEV 0#define CONFIG_EFI_PARTITION #endif +#endif #ifdef CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_CMD_USB_MASS_STORAGE
Signature · 1 line
2.5.3
PATCH v2 5/7 sun5i: Sync the DTSI with the kernel
In reply to Maxime RipardAdd the latest kernel changes to the sun5i family DTSI.
Signed-off-by Maxime Ripard <[email protected]>
--- arch/arm/dts/sun5i-a10s.dtsi | 47 ++++++++++++++++++++++++++++------- arch/arm/dts/sun5i-a13.dtsi | 28 ++++++++++++++++++++- arch/arm/dts/sun5i-r8.dtsi | 59 ++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/sun5i.dtsi | 22 +++++++++++++++++ 4 files changed, 146 insertions(+), 10 deletions(-) create mode 100644 arch/arm/dts/sun5i-r8.dtsi
arch/arm/dts/sun5i-a10s.dtsi +38 -9
@@ -77,6 +77,15 @@ clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; status = "disabled"; }; + + framebuffer at 2 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-tve0"; + clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, + <&ahb_gates 44>; + status = "disabled"; + }; }; clocks {
@@ -85,6 +94,17 @@ compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <5>, <6>, + <7>, <8>, <9>, + <10>, <13>, + <14>, <17>, <18>, + <20>, <21>, <22>, + <26>, <28>, <32>, + <34>, <36>, <40>, + <43>, <44>, + <46>, <51>, + <52>; clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
@@ -103,6 +123,9 @@ compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; + clock-indices = <0>, <3>, + <5>, <6>, + <10>; clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio", "apb0_ir", "apb0_keypad";
@@ -113,9 +136,14 @@ compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; + clock-indices = <0>, <1>, + <2>, <16>, + <17>, <18>, + <19>; clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_uart0", "apb1_uart1", - "apb1_uart2", "apb1_uart3"; + "apb1_i2c2", "apb1_uart0", + "apb1_uart1", "apb1_uart2", + "apb1_uart3"; }; };
@@ -137,6 +165,14 @@ #size-cells = <0>; }; + pwm: pwm at 01c20e00 { + compatible = "allwinner,sun5i-a10s-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + uart0: serial at 01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>;
@@ -176,13 +212,6 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - uart3_pins_a: uart3 at 0 { - allwinner,pins = "PG9", "PG10"; - allwinner,function = "uart3"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - emac_pins_a: emac0 at 0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6",
arch/arm/dts/sun5i-a13.dtsi +27 -1
@@ -104,6 +104,16 @@ compatible = "allwinner,sun5i-a13-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <5>, <6>, + <7>, <8>, <9>, + <10>, <13>, + <14>, <20>, + <21>, <22>, + <28>, <32>, <36>, + <40>, <44>, + <46>, <51>, + <52>; clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
@@ -121,6 +131,8 @@ compatible = "allwinner,sun5i-a13-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; + clock-indices = <0>, <5>, + <6>; clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; };
@@ -130,8 +142,22 @@ compatible = "allwinner,sun5i-a13-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; + clock-indices = <0>, <1>, + <2>, <17>, + <19>; clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_uart1", "apb1_uart3"; + "apb1_i2c2", "apb1_uart1", + "apb1_uart3"; + }; + }; + + soc at 01c00000 { + pwm: pwm at 01c20e00 { + compatible = "allwinner,sun5i-a13-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; }; }; };
arch/arm/dts/sun5i-r8.dtsi new file +59 -0
59 lines not on this page · raw message
arch/arm/dts/sun5i.dtsi +22 -0
@@ -178,6 +178,7 @@ compatible = "allwinner,sun4i-a10-axi-gates-clk"; reg = <0x01c2005c 0x4>; clocks = <&axi>; + clock-indices = <0>; clock-output-names = "axi_dram"; };
@@ -528,6 +529,27 @@ allwinner,drive = <SUN4I_PINCTRL_30_MA>; allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; + + uart3_pins_a: uart3 at 0 { + allwinner,pins = "PG9", "PG10"; + allwinner,function = "uart3"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart3_pins_cts_rts_a: uart3-cts-rts at 0 { + allwinner,pins = "PG11", "PG12"; + allwinner,function = "uart3"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + pwm0_pins: pwm0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; timer at 01c20c00 {
Signature · 1 line
2.5.3
PATCH v2 6/7 axp209: Sync the DTSI with the kernel
In reply to Maxime RipardLinux had a number of changes to the AXP209 DTSI. Sync ours.
Signed-off-by Maxime Ripard <[email protected]>
--- arch/arm/dts/axp209.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm/dts/axp209.dtsi +5 -0
@@ -89,4 +89,9 @@ regulator-name = "ldo5"; }; }; + + usb_power_supply: usb_power_supply { + compatible = "x-powers,axp202-usb-power-supply"; + status = "disabled"; + }; };
Signature · 1 line
2.5.3
PATCH v2 7/7 sunxi: Add CHIP support
In reply to Maxime RipardThe C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack and two connectors to plug additional boards on top of it.
The DT is identical to the DT submitted to the upstream kernel.
Signed-off-by Maxime Ripard <[email protected]>
Reviewed-by Tom Rini <[email protected]>
--- arch/arm/dts/Makefile | 3 +- arch/arm/dts/sun5i-r8-chip.dts | 214 +++++++++++++++++++++++++++++++++++++++++ configs/CHIP_defconfig | 14 +++ 3 files changed, 230 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/sun5i-r8-chip.dts create mode 100644 configs/CHIP_defconfig
arch/arm/dts/Makefile +2 -1
@@ -113,7 +113,8 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb \ sun5i-a13-q8-tablet.dtb \ - sun5i-a13-utoo-p66.dtb + sun5i-a13-utoo-p66.dtb \ + sun5i-r8-chip.dtb dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31-app4-evb1.dtb \ sun6i-a31-colombus.dtb \
arch/arm/dts/sun5i-r8-chip.dts new file +214 -0
214 lines not on this page · raw message
configs/CHIP_defconfig new file +14 -0
@@ -0,0 +1,14 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y +# CONFIG_MMC is not set +CONFIG_USB0_VBUS_PIN="PB10" +CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" +# CONFIG_CMD_IMLS is not set +CONFIG_AXP_DCDC2_VOLT=1300 +CONFIG_AXP_ALDO3_VOLT=3300 +CONFIG_AXP_ALDO4_VOLT=3300 +CONFIG_USB_MUSB_GADGET=y
Signature · 1 line
2.5.3
PATCH v2 7/7 sunxi: Add CHIP support
Hi,
Quoted 256 lines · Maxime Ripard
The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack and two connectors to plug additional boards on top of it.
The DT is identical to the DT submitted to the upstream kernel.
Signed-off-by Maxime Ripard <[email protected]>Reviewed-by Tom Rini <[email protected]>--- arch/arm/dts/Makefile | 3 +- arch/arm/dts/sun5i-r8-chip.dts | 214 +++++++++++++++++++++++++++++++++++++++++ configs/CHIP_defconfig | 14 +++ 3 files changed, 230 insertions(+), 1 deletion(-)create mode 100644
arch/arm/dts/sun5i-r8-chip.dtscreate mode 100644 configs/CHIP_defconfigarch/arm/dts/Makefile +2
-1@@ -113,7 +113,8 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb \ sun5i-a13-q8-tablet.dtb \ - sun5i-a13-utoo-p66.dtb + sun5i-a13-utoo-p66.dtb \ + sun5i-r8-chip.dtb dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31-app4-evb1.dtb \ sun6i-a31-colombus.dtb \arch/arm/dts/sun5i-r8-chip.dts new file +214
-0@@ -0,0 +1,214 @@ +/* + * Copyright 2015 Free Electrons + * Copyright 2015 NextThing Co + * + * Maxime Ripard <[email protected]> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-r8.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "NextThing C.H.I.P."; + compatible = "nextthing,chip", "allwinner,sun5i-r8"; + + aliases { + i2c0 = &i2c0; + i2c2 = &i2c2; + serial0 = &uart1; + serial1 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic at 34 { + reg = <0x34>; + + /* + * The interrupt is routed through the "External Fast + * Interrupt Request" pin (ball G13 of the module) + * directly to the main interrupt controller, without + * any other controller interfering. + */ + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + + xio: gpio at 38 { + compatible = "nxp,pcf8574a"; + reg = <0x38>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&pio>; + interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + chip_vbus_pin: chip_vbus_pin at 0 { + allwinner,pins = "PB10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + chip_id_det_pin: chip_id_det_pin at 0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +®_dcdc2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "cpuvdd"; + regulator-always-on; +}; + +®_dcdc3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "corevdd"; + regulator-always-on; +}; + +®_ldo1 { + regulator-name = "rtcvdd"; +}; + +®_ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; + regulator-always-on; +}; + +®_ldo5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_usb0_vbus { + pinctrl-0 = <&chip_vbus_pin>; + vin-supply = <®_vcc5v0>; + gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_a>, + <&uart3_pins_cts_rts_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&chip_id_det_pin>; + status = "okay"; + + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_vcc5v0>; +};configs/CHIP_defconfig new file +0
-0
configs/CHIP_defconfig line 9
Quoted 9 lines
configs/CHIP_defconfig new file +9
-0@@ -0,0 +1,14 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y +# CONFIG_MMC is not set +CONFIG_USB0_VBUS_PIN="PB10" +CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER"
I've dropped AXP209_POWER from these, in u-boot-sunxi/next this has been turned into a Kconfig bool which is enabled by default on sun7i.
Other then that I've merged the entire series into u-boot-sunxi/next (will push as soon as my build-all-boards test has completed).
Regards,
Hans