ASoC: adau1701: Add 44.1 KHz to supported sample rates
Subsystems (3)
PATCH 1/1 ASoC: adau1701: Add 44.1 KHz to supported sample rates
From: Pascal Huerst <[email protected]>
According to the datasheet, this device does also support 44.1 KHz as sample rate. This adds the necessary changes to support this.
See Datasheet: Rev. B / page 39 / SR[1:0]
--- sound/soc/codecs/adau1701.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
sound/soc/codecs/adau1701.c +3 -2
@@ -459,6 +459,7 @@ static int adau1701_hw_params(struct snd_pcm_substream *substream,case 96000 : val =ADAU1701_DSPCTRL_SR_96 ;break ; +case 44100 :case 48000 : val =ADAU1701_DSPCTRL_SR_48 ;break ;
@@ -623,8 +624,8 @@ static int adau1701_startup(struct snd_pcm_substream *substream,return sigmadsp_restrict_params (adau1701->sigmadsp, substream); } -#define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \ - SNDRV_PCM_RATE_192000) +#define ADAU1701_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)#define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ SNDRV_PCM_FMTBIT_S24_LE)
Signature · 1 line
2.4.3
Lars-Peter Clausen
maintainerQuoted 8 lines · On 10/15/2015 01:16 PM, [email protected] wrote:
From: Pascal Huerst <[email protected]>
According to the datasheet, this device does also support 44.1 KHz as sample rate. This adds the necessary changes to support this.
See Datasheet: Rev. B / page 39 / SR[1:0]
Signed-off-by Pascal Huerst <[email protected]>
Hm, right. The sample rates that part can run at depend on the external clock rate. It can run at ext_clk / 256, ext_clk / 128 or ext_clk / 64. Maybe we should just implement it like that.
Do you have support for switching the external clock at runtime on your platform?
Quoted 28 lines
--- sound/soc/codecs/adau1701.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)sound/soc/codecs/adau1701.c +3
-2@@ -459,6 +459,7 @@ static int adau1701_hw_params(struct snd_pcm_substream *substream,case 96000 : val =ADAU1701_DSPCTRL_SR_96 ;break ; +case 44100 :case 48000 : val =ADAU1701_DSPCTRL_SR_48 ;break ;@@ -623,8 +624,8 @@ static int adau1701_startup(struct snd_pcm_substream *substream,return sigmadsp_restrict_params (adau1701->sigmadsp, substream); } -#define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \ - SNDRV_PCM_RATE_192000) +#define ADAU1701_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)#define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ SNDRV_PCM_FMTBIT_S24_LE)
Quoted 8 lines · Lars-Peter Clausen
Quoted 7 lines · On 10/15/2015 01:16 PM, [email protected] wrote:
From: Pascal Huerst <[email protected]>
According to the datasheet, this device does also support 44.1 KHz as sample rate. This adds the necessary changes to support this.
See Datasheet: Rev. B / page 39 / SR[1:0]
Quoted 8 lines
Quoted 1 line
Signed-off-by Pascal Huerst <[email protected]>Hm, right. The sample rates that part can run at depend on the external clock rate. It can run at
ext_clk/ 256,ext_clk/ 128 orext_clk/ 64. Maybe we should just implement it like that.Do you have support for switching the external clock at runtime on your platform?
Yes, I can switch th eclock at runtime.
Quoted 29 lines
Quoted 28 lines
--- sound/soc/codecs/adau1701.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)sound/soc/codecs/adau1701.c +3
-2@@ -459,6 +459,7 @@ static int adau1701_hw_params(struct snd_pcm_substream *substream,case 96000 : val =ADAU1701_DSPCTRL_SR_96 ;break ; +case 44100 :case 48000 : val =ADAU1701_DSPCTRL_SR_48 ;break ;@@ -623,8 +624,8 @@ static int adau1701_startup(struct snd_pcm_substream *substream,return sigmadsp_restrict_params (adau1701->sigmadsp, substream); } -#define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \ - SNDRV_PCM_RATE_192000) +#define ADAU1701_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)#define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ SNDRV_PCM_FMTBIT_S24_LE)
Lars-Peter Clausen
maintainerQuoted 11 lines · Pascal Huerst
Quoted 10 lines · Lars-Peter Clausen
Quoted 8 lines · On 10/15/2015 01:16 PM, [email protected] wrote:
From: Pascal Huerst <[email protected]>
According to the datasheet, this device does also support 44.1 KHz as sample rate. This adds the necessary changes to support this.
See Datasheet: Rev. B / page 39 / SR[1:0]
Signed-off-by Pascal Huerst <[email protected]>
Quoted 8 lines
Quoted 6 lines
Hm, right. The sample rates that part can run at depend on the external clock rate. It can run at
ext_clk/ 256,ext_clk/ 128 orext_clk/ 64. Maybe we should just implement it like that.Do you have support for switching the external clock at runtime on your platform?
Yes, I can switch th eclock at runtime.
How do you do it? From the board driver?
- Lars
Quoted 16 lines · Lars-Peter Clausen
Quoted 15 lines · Pascal Huerst
Quoted 14 lines · Lars-Peter Clausen
Quoted 8 lines · On 10/15/2015 01:16 PM, [email protected] wrote:
From: Pascal Huerst <[email protected]>
According to the datasheet, this device does also support 44.1 KHz as sample rate. This adds the necessary changes to support this.
See Datasheet: Rev. B / page 39 / SR[1:0]
Signed-off-by Pascal Huerst <[email protected]>Hm, right. The sample rates that part can run at depend on the external clock rate. It can run at
ext_clk/ 256,ext_clk/ 128 orext_clk/ 64. Maybe we should just implement it like that.
Quoted 6 lines
Quoted 4 lines
Quoted 2 lines
Do you have support for switching the external clock at runtime on your platform?
Yes, I can switch th eclock at runtime.
How do you do it? From the board driver?
Yes, in the board driver, within the .hw_params callback.
Quoted 6 lines
- Lars
_______________________________________________
Alsa-devel mailing list
[email protected]
http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
Quoted 6 lines · Lars-Peter Clausen
Quoted 5 lines · On 10/15/2015 01:16 PM, [email protected] wrote:
From: Pascal Huerst <[email protected]>
According to the datasheet, this device does also support 44.1 KHz as sample rate. This adds the necessary changes to support this.
Quoted 7 lines
Quoted 3 lines
See Datasheet: Rev. B / page 39 / SR[1:0]
Signed-off-by Pascal Huerst <[email protected]>Hm, right. The sample rates that part can run at depend on the external clock rate. It can run at
ext_clk/ 256,ext_clk/ 128 orext_clk/ 64. Maybe we should just implement it like that.
Don't you think, that it is just consistent to add 44100, just as the other sample rates that are supported?
Quoted 32 lines
Do you have support for switching the external clock at runtime on your platform?
Quoted 28 lines
--- sound/soc/codecs/adau1701.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)sound/soc/codecs/adau1701.c +3
-2@@ -459,6 +459,7 @@ static int adau1701_hw_params(struct snd_pcm_substream *substream,case 96000 : val =ADAU1701_DSPCTRL_SR_96 ;break ; +case 44100 :case 48000 : val =ADAU1701_DSPCTRL_SR_48 ;break ;@@ -623,8 +624,8 @@ static int adau1701_startup(struct snd_pcm_substream *substream,return sigmadsp_restrict_params (adau1701->sigmadsp, substream); } -#define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \ - SNDRV_PCM_RATE_192000) +#define ADAU1701_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)#define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ SNDRV_PCM_FMTBIT_S24_LE)