spi: Tegra: add device tree binding doc for SPI/QSPI
PATCH v2 1/1 spi: Tegra: add device tree binding doc for SPI/QSPI
This patch adds the device tree binding doc for the Tegra SPI/QSPI controllers on Tegra114 and Tegra210.
---
Changes in v2:
- based it more on kernel's nvidia,tegra114-spi.txt binding
- changes based on prelim review by swarren at nvidia.com
doc/device-tree-bindings/spi/spi-tegra.txt | 60 ++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 doc/device-tree-bindings/spi/spi-tegra.txt
doc/device-tree-bindings/spi/spi-tegra.txt new file +60 -0
@@ -0,0 +1,60 @@ +NVIDIA Tegra SPI/QSPI controller. + +Required properties: +- compatible : should be one of the following: + "nvidia,tegra114-spi" (for Tegra114) + "nvidia,tegra210-qspi" (for Tegra210) +- reg: Should contain SPI registers location and length. +- interrupts: Should contain SPI interrupts. +- clock-names : Must include the following entries: + - spi +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- resets : Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names : Must include the following entries: + - spi + +Optional properties: +- dmas : Must contain an entry for each entry in clock-names. + See ../dma/dma.txt for details. +- dma-names : Must include the following entries: + - rx + - tx + +Recommended properties: +- spi-max-frequency: Definition as per spi-bus.txt + +Example: + +spi at 7000d600 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d600 0x200>; + interrupts = <0 82 0x04>; + spi-max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 44>; + clock-names = "spi"; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + status = "disabled"; +}; + +spi at 70410000 { + compatible = "nvidia,tegra210-qspi"; + reg = <0x0 0x70410000 0x0 0x1000>; + interrupts = <0 10 0x04>; + spi-max-frequency = <24000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 211>; + clock-names = "spi"; + resets = <&tegra_car 211>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + status = "disabled"; +};
Signature · 1 line
1.8.2.1.610.g562af5b
PATCH v2 1/1 spi: Tegra: add device tree binding doc for SPI/QSPI
doc/device-tree-bindings/spi/spi-tegra.txt
Quoted 4 lines · Tom Warren
This patch adds the device tree binding doc for the Tegra SPI/QSPI controllers on Tegra114 and Tegra210.
doc/device-tree-bindings/spi/spi-tegra.txt +0
-0
Since this is a patch to the Linux kernel, it should use the path and file names from the Linux kernel, so that should be:
Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt
(or perhaps an earlier SoC number if this HW block first appeared before Tegra210)
Quoted 1 line
+NVIDIA Tegra SPI/QSPI controller.
There's already a binding document for the regular SPI controller. The plain SPI entries should be removed from this file, leaving it covering the QSPI controller only.
Can you confirm that there physically is a separate QSPI controller in HW and that it has different registers to the regular SPI controller? Or, is QSPI simply a new mode of operation for the existing HW?
doc/device-tree-bindings/spi/spi-tegra.txt line 8
Quoted 6 lines
doc/device-tree-bindings/spi/spi-tegra.txt +6
-0+Required properties: +- compatible : should be one of the following: + "nvidia,tegra114-spi" (for Tegra114) + "nvidia,tegra210-qspi" (for Tegra210) +- reg: Should contain SPI registers location and length. +- interrupts: Should contain SPI interrupts.
Are there multiple interrupts or just one? I imagine just one, in which case just "interrupt" at the end of that description.
PATCH v2 1/1 spi: Tegra: add device tree binding doc for SPI/QSPI
Stephen,
Quoted 16 lines
-----Original Message-----
From: Stephen Warren [mailto:swarren at wwwdotorg.org]
Sent: Monday, October 26, 2015 9:33 AM
To: Tom Warren <[email protected]>; u-boot at lists.denx.de
Cc: Stephen Warren <[email protected]>; tomcwarren3959 at gmail.com; jteki at openedev.com; robh+dt at kernel.org; pawel.moll at arm.com; mark.rutland at arm.com; ijc+devicetree at hellion.org.uk;
galak at codeaurora.org; Thierry Reding <[email protected]>; linux- tegra at vger.kernel.org; Alex Courbot <[email protected]>; linux-arm- kernel at lists.infradead.org
Subject: Re: [PATCH v2] spi: Tegra: add device tree binding doc for SPI/QSPIQuoted 2 lines · Tom Warren
This patch adds the device tree binding doc for the Tegra SPI/QSPI controllers on Tegra114 and Tegra210.
Quoted 7 lines
doc/device-tree-bindings/spi/spi-tegra.txt
Quoted 2 lines
doc/device-tree-bindings/spi/spi-tegra.txt +0
-0Since this is a patch to the Linux kernel, it should use the path and file names from the Linux kernel, so that should be:
Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt
I thought I was adding a binding doc to U-Boot, so the QSPI driver for T210 can go in. I wasn't aware that I had to submit a changelist against the kernel's binding first. I'll redo the file path.
Quoted 3 lines
(or perhaps an earlier SoC number if this HW block first appeared before Tegra210)
AFAICT, QSPI first appeared in Tegra210/X1.
Quoted 6 lines
Quoted 2 lines
+NVIDIA Tegra SPI/QSPI controller.
There's already a binding document for the regular SPI controller. The plain SPI entries should be removed from this file, leaving it covering the QSPI controller only.
There is no spi binding for Tegra114 in U-Boot at present, hence my duplication. I'll remove the SPI entries from this file, and perhaps copy over the kernel's tegra114 spi binding for U-Boot at a later date.
Quoted 4 lines
Can you confirm that there physically is a separate QSPI controller in HW and that it has different registers to the regular SPI controller? Or, is QSPI simply a new mode of operation for the existing HW?
QSPI is its own controller, separate from the traditional 4 Tegra SPI controllers. It has its own address space, and some differences in bits in some registers, and adds misc and timing registers that don't exist in the SPI controller. It supports Master mode only (no slave mode), and adds Dual (x2) and Quad mode (x4) transfer options. It's basically a superset of the Tegra SPI controller.
Quoted 10 lines
doc/device-tree-bindings/spi/spi-tegra.txt line 8
Quoted 7 lines
doc/device-tree-bindings/spi/spi-tegra.txt +6
-0+Required properties: +- compatible : should be one of the following: + "nvidia,tegra114-spi" (for Tegra114) + "nvidia,tegra210-qspi" (for Tegra210) +- reg: Should contain SPI registers location and length. +- interrupts: Should contain SPI interrupts.Are there multiple interrupts or just one? I imagine just one, in which case just "interrupt" at the end of that description.
Only 1 interrupt for QSPI. Note that this was copied verbatim from the kernel's current nvidia,tegra114-spi.txt binding, so if it's wrong, it's wrong there, too.
Tom
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