Tegra: DT: add device tree binding doc for QSPI
Subsystems (3)
PATCH v3 1/1 Tegra: DT: add device tree binding doc for QSPI
This patch adds the device tree binding doc for the Tegra QSPI controller on Tegra210.
---
Changes in v2:
- based it more on kernel's nvidia,tegra114-spi.txt binding
- changes based on prelim review by swarren at nvidia.com Changes in v3:
- renamed to 'nvidia,tegra210-qspi.txt' to match kernel bindings
- more changes based on review from swarren at nvidia.com
Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt | 42 ++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt
Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt new file +42 -0
@@ -0,0 +1,42 @@ +NVIDIA Tegra QSPI controller. + +Required properties: +- compatible : for Tegra210, must contain "nvidia,tegra210-qspi". +- reg: Should contain QSPI registers location and length. +- interrupts: Should contain QSPI interrupt. +- clock-names : Must include the following entries: + - qspi +- resets : Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names : Must include the following entries: + - qspi +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. + +Optional properties: +- dmas : Must contain an entry for each entry in clock-names. + See ../dma/dma.txt for details. +- dma-names : Must include the following entries: + - rx + - tx + +Recommended properties: +- spi-max-frequency: Definition as per spi-bus.txt + +Example: + +spi at 70410000 { + compatible = "nvidia,tegra210-qspi"; + reg = <0x0 0x70410000 0x0 0x1000>; + interrupts = <0 10 0x04>; + spi-max-frequency = <24000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 211>; + clock-names = "qspi"; + resets = <&tegra_car 211>; + reset-names = "qspi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + status = "disabled"; +};
Signature · 1 line
1.8.2.1.610.g562af5b
PATCH v3 1/1 Tegra: DT: add device tree binding doc for QSPI
Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt line 14
Quoted 13 lines · Tom Warren
This patch adds the device tree binding doc for the Tegra QSPI controller on Tegra210.
Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt +8
-0+- clock-names : Must include the following entries: + - qspi +- resets : Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names : Must include the following entries: + - qspi +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details.
Let's keep clocks and clock-names next to each-other in the doc. I don't know why they aren't in the eixsting Tegra SPI doc.
With this issue fixed, this patch looks good to me.
Note: I don't see the devicetree mailing list in the CC list. You should probably replace the U-Boot mailing list with it.
Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt line 21
Quoted 6 lines
Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt +6
-0+Optional properties: +- dmas : Must contain an entry for each entry in clock-names. + See ../dma/dma.txt for details. +- dma-names : Must include the following entries: + - rx + - tx
Eventually, we should have a property that describes the SPI bus width (x1, x2, x4 I assume). However, we can assume that unless otherwise specified, the width is x1, and add a property to specify the width later as/when we need it if you want.
PATCH v3 1/1 Tegra: DT: add device tree binding doc for QSPI
Stephen,
Quoted 29 lines
-----Original Message-----
From: Stephen Warren [mailto:swarren at wwwdotorg.org]
Sent: Monday, October 26, 2015 2:04 PM
To: Tom Warren <[email protected]>
Cc: u-boot at lists.denx.de; Stephen Warren <[email protected]>; tomcwarren3959 at gmail.com; jteki at openedev.com; robh+dt at kernel.org; pawel.moll at arm.com; mark.rutland at arm.com; ijc+devicetree at hellion.org.uk; galak at codeaurora.org; Thierry Reding <[email protected]>; linux- tegra at vger.kernel.org; Alex Courbot <[email protected]>; linux-arm- kernel at lists.infradead.org
Subject: Re: [PATCH v3] Tegra: DT: add device tree binding doc for QSPIQuoted 8 lines · Tom Warren
This patch adds the device tree binding doc for the Tegra QSPI controller on Tegra210.
diff --git
a/Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txtb/Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt+- clock-names : Must include the following entries:
Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt line 14
Quoted 7 lines
Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt new file +7
-0+ - qspi +- resets : Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names : Must include the following entries: + - qspi +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details.
Quoted 2 lines
Let's keep clocks and clock-names next to each-other in the doc. I don't know why they aren't in the eixsting Tegra SPI doc.
OK. I assume 'clock-names', then 'clocks' since 'clocks' references clock-names.
Quoted 5 lines
With this issue fixed, this patch looks good to me.
Note: I don't see the devicetree mailing list in the CC list. You should probably replace the U-Boot mailing list with it.
I thought I had it, but may have dropped it. What exactly is the URL of the devicetree mailing list? devicetree-discuss at lists.ozlabs.org? or devicetree at vger.kernel.org?
Quoted 8 lines
Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt line 21
Quoted 7 lines
Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt new file +6
-0+Optional properties: +- dmas : Must contain an entry for each entry in clock-names. + See ../dma/dma.txt for details. +- dma-names : Must include the following entries: + - rx + - tx
Quoted 4 lines
Eventually, we should have a property that describes the SPI bus width (x1, x2, x4 I assume). However, we can assume that unless otherwise specified, the width is x1, and add a property to specify the width later as/when we need it if you want.
Tom
--
nvpublic
PATCH v3 1/1 Tegra: DT: add device tree binding doc for QSPI
Quoted 18 lines · Tom Warren
Stephen Warren wrote at Monday, October 26, 2015 2:04 PM:
Quoted 17 lines · Tom Warren
Quoted 15 lines
This patch adds the device tree binding doc for the Tegra QSPI controller on Tegra210.
diff --git
a/Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txtb/Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt+- clock-names : Must include the following entries:
Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt new file +7
-0+ - qspi +- resets : Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names : Must include the following entries: + - qspi +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details.
Quoted 4 lines
Quoted 2 lines
Let's keep clocks and clock-names next to each-other in the doc. I don't know why they aren't in the eixsting Tegra SPI doc.
OK. I assume 'clock-names', then 'clocks' since 'clocks' references clock-names.
That sounds correct.
Quoted 6 lines
Quoted 4 lines
With this issue fixed, this patch looks good to me.
Note: I don't see the devicetree mailing list in the CC list. You should probably replace the U-Boot mailing list with it.
I thought I had it, but may have dropped it. What exactly is the URL of the devicetree mailing list? devicetree-discuss at lists.ozlabs.org? or devicetree at vger.kernel.org?
devicetree at vger.kernel.org
(See the "OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" in "MAINTAINERS", or the output of ./scripts/get_maintainers.pl)