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imx: cpu: move common chip revision id's

PATCH New Adrian Alonso 2 participants 11 messages Oct 12, 2015 – Oct 30, 2015

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Arm (32-bit) Arm i.MX and Layerscape
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Adrian Alonso

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#0 lore raw

PATCH v3 1/10 imx: cpu: move common chip revision id's

Move common chip revision id's to main cpu header file mx25 generic include cpu header for chip revision

Signed-off-by Adrian Alonso <[email protected]>

---
Chages for V2: Resend
Chages for V3: Resend

 arch/arm/cpu/arm926ejs/mx25/generic.c     |  1 +
 arch/arm/include/asm/arch-imx/cpu.h       | 12 ++++++++++++
 arch/arm/include/asm/arch-mx25/imx-regs.h |  4 ----
 arch/arm/include/asm/arch-mx5/imx-regs.h  | 11 -----------
 arch/arm/include/asm/arch-mx6/imx-regs.h  |  4 ----
 5 files changed, 13 insertions(+), 19 deletions(-)
arch/arm/cpu/arm926ejs/mx25/generic.c +1 -0
index 8912098..0b1a8f4 100644
@@ -13,6 +13,7 @@
 #include <div64.h>
 #include <netdev.h>
 #include <asm/io.h>
+#include <asm/arch-imx/cpu.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
arch/arm/include/asm/arch-imx/cpu.h +12 -0
index 7e681e9..8a75902 100644
@@ -27,6 +27,18 @@
 #define MXC_SOC_MX6		0x60
 #define MXC_SOC_MX7		0x70
 
+#define CHIP_REV_1_0            0x10
+#define CHIP_REV_1_1            0x11
+#define CHIP_REV_1_2            0x12
+#define CHIP_REV_1_5            0x15
+#define CHIP_REV_2_0            0x20
+#define CHIP_REV_2_5            0x25
+#define CHIP_REV_3_0            0x30
+
+#define BOARD_REV_1_0           0x0
+#define BOARD_REV_2_0           0x1
+#define BOARD_VER_OFFSET        0x8
+
 #define CS0_128					0
 #define CS0_64M_CS1_64M				1
 #define CS0_64M_CS1_32M_CS2_32M			2
arch/arm/include/asm/arch-mx25/imx-regs.h +0 -4
index 78c4e9b..1b00ed7 100644
@@ -526,8 +526,4 @@ struct cspi_regs {
 	IMX_CSPI2_BASE, \
 	IMX_CSPI3_BASE
 
-#define CHIP_REV_1_0		0x10
-#define CHIP_REV_1_1		0x11
-#define CHIP_REV_1_2		0x12
-
 #endif				/* _IMX_REGS_H */
arch/arm/include/asm/arch-mx5/imx-regs.h +0 -11
index 5f0e1e6..e73cc07 100644
@@ -291,17 +291,6 @@
 #define DP_MFD_216	(4 - 1)
 #define DP_MFN_216	3
 
-#define CHIP_REV_1_0            0x10
-#define CHIP_REV_1_1            0x11
-#define CHIP_REV_2_0            0x20
-#define CHIP_REV_2_5		0x25
-#define CHIP_REV_3_0            0x30
-
-#define BOARD_REV_1_0           0x0
-#define BOARD_REV_2_0           0x1
-
-#define BOARD_VER_OFFSET	0x8
-
 #define IMX_IIM_BASE            (IIM_BASE_ADDR)
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
arch/arm/include/asm/arch-mx6/imx-regs.h +0 -4
index 74512ac..6249b33 100644
@@ -325,10 +325,6 @@
 #define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ?	\
 			 MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR)
 
-#define CHIP_REV_1_0                 0x10
-#define CHIP_REV_1_2                 0x12
-#define CHIP_REV_1_5                 0x15
-#define CHIP_REV_2_0                 0x20
 #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define IRAM_SIZE                    0x00040000
 #else
Signature · 1 line
2.1.4
author
#1 lore raw

PATCH v3 2/10 imx: hab: rework secure boot support for imx6

Rework secure boot support for imx6, move existing hab support for imx6 into imx-common for SoC reuse.

Signed-off-by Adrian Alonso <[email protected]>

---
Changes for V2: Split patch
- Move existing hab mx6 into common location
- Update include hab header location
Changes for V3:
- Fix commit log message, to reflect mx6 change sets.

 arch/arm/cpu/armv7/mx6/Makefile                     | 1 -
 arch/arm/imx-common/Makefile                        | 1 +
 arch/arm/{cpu/armv7/mx6 => imx-common}/hab.c        | 2 +-
 arch/arm/include/asm/{arch-mx6 => imx-common}/hab.h | 0
 4 files changed, 2 insertions(+), 2 deletions(-)
 rename arch/arm/{cpu/armv7/mx6 => imx-common}/hab.c (99%)
 rename arch/arm/include/asm/{arch-mx6 => imx-common}/hab.h (100%)
arch/arm/cpu/armv7/mx6/Makefile +0 -1
index bf6effc..8af191d 100644
@@ -9,5 +9,4 @@
 
 obj-y	:= soc.o clock.o
 obj-$(CONFIG_SPL_BUILD)	     += ddr.o
-obj-$(CONFIG_SECURE_BOOT)    += hab.o
 obj-$(CONFIG_MP)             += mp.o
arch/arm/imx-common/Makefile +1 -0
index 1698d06..4abffee 100644
@@ -27,6 +27,7 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
 obj-y 	+= cache.o init.o
 obj-$(CONFIG_CMD_SATA) += sata.o
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
+obj-$(CONFIG_SECURE_BOOT)    += hab.o
 endif
 ifeq ($(SOC),$(filter $(SOC),vf610))
 obj-y += ddrmc-vf610.o
arch/arm/imx-common/hab.c renamed from arch/arm/cpu/armv7/mx6/hab.c +1 -1
similarity index 99%
rename from arch/arm/cpu/armv7/mx6/hab.c
rename to arch/arm/imx-common/hab.c
index 27cabe4..9ee0f12 100644
@@ -7,9 +7,9 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/system.h>
-#include <asm/arch/hab.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/imx-common/hab.h>
 
 /* -------- start of HAB API updates ------------*/
arch/arm/include/asm/imx-common/hab.h renamed from arch/arm/include/asm/arch-mx6/hab.h +0 -0
similarity index 100%
rename from arch/arm/include/asm/arch-mx6/hab.h
rename to arch/arm/include/asm/imx-common/hab.h
Signature · 1 line
2.1.4
author
#2 lore raw

PATCH v3 3/10 imx: hab: use unified rom section for mx6sx and mx6ul

In reply to Adrian Alonso

Add CONFIG_ROM_UNIFIED_SECTIONS for mx6sx and mx6ul target platforms to resolve corresponding HAB_RVT_BASE base address, the RVT table contains pointers to the HAB API functions in ROM code.

Signed-off-by Adrian Alonso <[email protected]>

---
Changes for V2: New patch in series
Changes for V3:
- Add ROM_UNIFIED_SECTIONS in Kconfig and select it for mx6sx and mx6ul SoC targets
- Improve commit log description

 arch/arm/cpu/armv7/mx6/Kconfig        | 2 ++
 arch/arm/imx-common/Kconfig           | 3 +++
 arch/arm/include/asm/imx-common/hab.h | 2 +-
 3 files changed, 6 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/mx6/Kconfig +2 -0
index 0b02e9e..273e209 100644
@@ -23,10 +23,12 @@ config MX6SL
 	bool
 
 config MX6SX
+	select ROM_UNIFIED_SECTIONS
 	bool
 
 config MX6UL
 	select SYS_L2CACHE_OFF
+	select ROM_UNIFIED_SECTIONS
 	bool
 
 choice
arch/arm/imx-common/Kconfig +3 -0
index 37b3752..2296239 100644
@@ -1,2 +1,5 @@
 config IMX_CONFIG
 	string
+
+config ROM_UNIFIED_SECTIONS
+	bool
arch/arm/include/asm/imx-common/hab.h +1 -1
index d0eaa67..af77d45 100644
@@ -113,7 +113,7 @@ typedef void hapi_clock_init_t(void);
 #define HAB_ENG_RTL		0x77   /* RTL simulation engine */
 #define HAB_ENG_SW		0xff   /* Software engine */
 
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_ROM_UNIFIED_SECTIONS
 #define HAB_RVT_BASE			0x00000100
 #else
 #define HAB_RVT_BASE			0x00000094
Signature · 1 line
2.1.4
author
#3 lore raw

PATCH v3 4/10 imx: hab: rework unified rom section for mx7

In reply to Adrian Alonso

Rework unified section macro select via Kconfig option instead of macro definition in mx7_common header file.

Signed-off-by Adrian Alonso <[email protected]>

---
Changes for V3: New patch in series

 arch/arm/cpu/armv7/mx7/Kconfig | 2 ++
 include/configs/mx7_common.h   | 1 -
 2 files changed, 2 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/mx7/Kconfig +2 -0
index ea19e5c..97d6238 100644
@@ -2,9 +2,11 @@ if ARCH_MX7
 
 config MX7
 	bool
+	select ROM_UNIFIED_SECTIONS
 	default y
 
 config MX7D
+	select ROM_UNIFIED_SECTIONS
 	bool
 
 choice
include/configs/mx7_common.h +0 -1
index ea2be49..bf43d09 100644
@@ -32,7 +32,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_ROM_UNIFIED_SECTIONS
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
Signature · 1 line
2.1.4
author
#4 lore raw

PATCH v3 5/10 imx: hab: add secure boot fuse details

In reply to Adrian Alonso

Add secure boot fuse helper struct to abstract the way to find out secure boot settings per SoC iMX family

Signed-off-by Adrian Alonso <[email protected]>

---
Changes for V3: New patch in series

 arch/arm/include/asm/imx-common/hab.h | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/arm/include/asm/imx-common/hab.h +9 -0
index af77d45..dab6789 100644
@@ -85,6 +85,15 @@ enum hab_context {
 	HAB_CTX_MAX
 };
 
+struct imx_sec_config_fuse_t {
+	int bank;
+	int word;
+};
+
+#if defined(CONFIG_SECURE_BOOT)
+extern struct imx_sec_config_fuse_t const imx_sec_config_fuse;
+#endif
+
 /*Function prototype description*/
 typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
 		uint8_t* , size_t*);
Signature · 1 line
2.1.4
author
#5 lore raw

PATCH v3 6/10 arm: imx: add secure boot fuse details for imx6 SoC

In reply to Adrian Alonso

Add secure boot fuse details (location) bank = 0, word = 6; for imx6 SoC platforms.

Signed-off-by Adrian Alonso <[email protected]>

---
Changes for V3: New patch in series

 arch/arm/cpu/armv7/mx6/soc.c | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm/cpu/armv7/mx6/soc.c +8 -0
index 282302b..d545021 100644
@@ -15,6 +15,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/dma.h>
+#include <asm/imx-common/hab.h>
 #include <stdbool.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>

@@ -48,6 +49,13 @@ U_BOOT_DEVICE(imx6_thermal) = {
 };
 #endif
 
+#if defined(CONFIG_SECURE_BOOT)
+struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+	.bank = 0,
+	.word = 6,
+};
+#endif
+
 u32 get_nr_cpus(void)
 {
 	struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
Signature · 1 line
2.1.4
author
#6 lore raw

PATCH v3 7/10 arm: imx: add secure boot fuse details for imx7 SoC

In reply to Adrian Alonso

Add secure boot fuse details (location) bank = 1, word = 3; for imx7 SoC platforms.

Signed-off-by Adrian Alonso <[email protected]>

---
Changes for V3: New patch in series

 arch/arm/cpu/armv7/mx7/soc.c | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm/cpu/armv7/mx7/soc.c +8 -0
index 2ed05ea..a6224af 100644
@@ -11,6 +11,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/dma.h>
+#include <asm/imx-common/hab.h>
 #include <asm/arch/crm_regs.h>
 #include <dm.h>
 #include <imx_thermal.h>

@@ -28,6 +29,13 @@ U_BOOT_DEVICE(imx7_thermal) = {
 };
 #endif
 
+#if defined(CONFIG_SECURE_BOOT)
+struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+	.bank = 1,
+	.word = 3,
+};
+#endif
+
 /*
  * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
  * defines a 2-bit SPEED_GRADING
Signature · 1 line
2.1.4
author
#7 lore raw

PATCH v3 8/10 imx: hab: use read_fuse for secure boot settings

In reply to Adrian Alonso

Use read_fuse api fuction call to read secure boot fuse settings (enabled/disabled).

Signed-off-by Adrian Alonso <[email protected]>

---
Changes for V3: New patch in series

 arch/arm/imx-common/hab.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)
arch/arm/imx-common/hab.c +12 -5
index 9ee0f12..ee2da01 100644
@@ -5,6 +5,8 @@
  */
 
 #include <common.h>
+#include <config.h>
+#include <fuse.h>
 #include <asm/io.h>
 #include <asm/system.h>
 #include <asm/arch/clock.h>

@@ -260,11 +262,16 @@ uint8_t hab_engines[16] = {
 
 bool is_hab_enabled(void)
 {
-	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-	struct fuse_bank *bank = &ocotp->bank[0];
-	struct fuse_bank0_regs *fuse =
-		(struct fuse_bank0_regs *)bank->fuse_regs;
-	uint32_t reg = readl(&fuse->cfg5);
+	struct imx_sec_config_fuse_t *fuse =
+		(struct imx_sec_config_fuse_t*)&imx_sec_config_fuse;
+	uint32_t reg;
+	int ret;
+
+	ret = fuse_read(fuse->bank, fuse->word, &reg);
+	if (ret) {
+		puts("\nSecure boot fuse read error\n");
+		return ret;
+	}
 
 	return (reg & 0x2) == 0x2;
 }
Signature · 1 line
2.1.4
author
#8 lore raw

PATCH v3 9/10 imx: hab: add mx7 secure boot support

In reply to Adrian Alonso

Add mx7 secure boot support, add helper macro IS_HAB_ENABLED_BIT to get the corresponding bit mask per SoC (mx7 or mx6) to identify if securue boot feature is enabled/disabled.

On authenticate_image only check for mmu enabled on mx6 SoC to force pu_irom_mmu_enabled so ROM code can perform mmu cache flush mx7 SoC ROM code does not have this issue as ROM enables cache support based on fuse settings.

Signed-off-by Adrian Alonso <[email protected]>

---
Changes for V2:
- Split from original patch to track mx7 change set
hab: rework support for imx6/imx7
Changes for V3:
- Add helper macro to identify if secure boot is enabled per SoC family (mx6/mx7)
- Improve commit log description

 arch/arm/imx-common/hab.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
arch/arm/imx-common/hab.c +4 -2
index ee2da01..56b3c22 100644
@@ -81,6 +81,8 @@
 #define MX6DQ_PU_IROM_MMU_EN_VAR	0x009024a8
 #define MX6DLS_PU_IROM_MMU_EN_VAR	0x00901dd0
 #define MX6SL_PU_IROM_MMU_EN_VAR	0x00900a18
+#define IS_HAB_ENABLED_BIT \
+	(is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)
 
 /*
  * +------------+  0x0 (DDR_UIMAGE_START) -

@@ -273,7 +275,7 @@ bool is_hab_enabled(void)
 		return ret;
 	}
 
-	return (reg & 0x2) == 0x2;
+	return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
 }
 
 static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)

@@ -421,7 +423,7 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
 			 * crash.
 			 */
 			/* Check MMU enabled */
-			if (get_cr() & CR_M) {
+			if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
 				if (is_cpu_type(MXC_CPU_MX6Q) ||
 				    is_cpu_type(MXC_CPU_MX6D)) {
 					/*
Signature · 1 line
2.1.4
author
#9 lore raw

PATCH v3 10/10 mx7dsabresd: add secure boot support

In reply to Adrian Alonso

Add secure boot support for mx7dsabresd target board

Signed-off-by Adrian Alonso <[email protected]>

---
Changes for V2: Resend
Changes for V3: Resend

 board/freescale/mx7dsabresd/imximage.cfg | 7 +++++++
 include/configs/mx7dsabresd.h            | 4 ++++
 2 files changed, 11 insertions(+)
board/freescale/mx7dsabresd/imximage.cfg +7 -0
index 91b70ee..76574ff 100644
@@ -23,6 +23,13 @@ IMAGE_VERSION 2
 BOOT_FROM	sd
 
 /*
+ * Secure boot support
+ */
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
  * Device Configuration Data (DCD)
  *
  * Each entry must have the format:
include/configs/mx7dsabresd.h +4 -0
index f16f9c1..eb45d50 100644
@@ -14,6 +14,10 @@
 #define CONFIG_DBG_MONITOR
 #define PHYS_SDRAM_SIZE			SZ_1G
 
+/* Uncomment to enable secure boot support */
+/* #define CONFIG_SECURE_BOOT */
+#define CONFIG_CSF_SIZE			0x4000
+
 /* Network */
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
Signature · 1 line
2.1.4
#10 lore raw

PATCH v3 1/10 imx: cpu: move common chip revision id's

In reply to Adrian Alonso
Quoted 5 lines · Adrian Alonso

Move common chip revision id's to main cpu header file mx25 generic include cpu header for chip revision

Signed-off-by Adrian Alonso <[email protected]>

---

Whole series applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines
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