crypto/fsl: SEC driver cleanup for 64 bit and endianness
PATCH v5 3/3 crypto/fsl: SEC driver cleanup for 64 bit and endianness
The SEC driver code has been cleaned up to work for 64 bit physical addresses and systems where endianess of SEC block is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings will be depend on endianness of SEC block as 32 bit low and high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in descriptor will vary depending on endianness of SEC.
---
Changes in v5:
Removed compile time warnings
drivers/crypto/fsl/desc_constr.h | 26 ++++++++++++ drivers/crypto/fsl/fsl_hash.c | 8 ++-- drivers/crypto/fsl/jr.c | 86 ++++++++++++++++++++++++++++++++++------ drivers/crypto/fsl/jr.h | 7 ++-- include/fsl_sec.h | 6 +-- 5 files changed, 109 insertions(+), 24 deletions(-)
drivers/crypto/fsl/desc_constr.h +26 -0
@@ -36,6 +36,23 @@ LDST_SRCDST_WORD_DECOCTRL | \ (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT)) +#ifdef CONFIG_PHYS_64BIT +union ptr_addr_t { +u64 m_whole; +struct { +#ifdef CONFIG_SYS_FSL_SEC_LE +u32 low; +u32 high; +#elif defined(CONFIG_SYS_FSL_SEC_BE ) +u32 high; +u32 low; +#else +#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined +#endif + } m_halfs; +}; +#endif +static inline int desc_len (u32 *desc) {return *desc &HDR_DESCLEN_MASK ;
@@ -65,7 +82,16 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr) {dma_addr_t *offset = (dma_addr_t *)desc_end (desc); +#ifdef CONFIG_PHYS_64BIT +/* The Position of low and high part of 64 bit address +* will depend on the endianness of CAAM Block */ +union ptr_addr_t ptr_addr; + ptr_addr.m_halfs.high = (u32)(ptr >>32 ); + ptr_addr.m_halfs.low = (u32 )ptr; + *offset = ptr_addr.m_whole; +#else *offset = ptr; +#endif (*desc) +=CAAM_PTR_SZ /CAAM_CMD_SZ ; }
drivers/crypto/fsl/fsl_hash.c +4 -4
@@ -84,7 +84,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf, enum caam_hash_algos caam_algo) {uint32_t final =0 ; -dma_addr_t addr =virt_to_phys ((void *)buf); +phys_addr_t addr =virt_to_phys ((void *)buf);struct sha_ctx *ctx = hash_ctx;if (ctx->sg_num >=MAX_SG_32 ) {
@@ -93,11 +93,11 @@ static int caam_hash_update(void *hash_ctx, const void *buf, }#ifdef CONFIG_PHYS_64BIT - ctx->sg_tbl[ctx->sg_num].addr_hi = addr >>32 ; +sec_out32 (&ctx->sg_tbl[ctx->sg_num].addr_hi, (uint32_t )(addr >>32 ));#else - ctx->sg_tbl[ctx->sg_num].addr_hi =0x0 ; +sec_out32 (&ctx->sg_tbl[ctx->sg_num].addr_hi,0x0 );#endif - ctx->sg_tbl[ctx->sg_num].addr_lo = addr; +sec_out32 (&ctx->sg_tbl[ctx->sg_num].addr_lo, (uint32_t )addr);sec_out32 (&ctx->sg_tbl[ctx->sg_num].len_flag, (size &SG_ENTRY_LENGTH_MASK ));
drivers/crypto/fsl/jr.c +74 -12
143 lines not on this page · raw message
drivers/crypto/fsl/jr.h +3 -4
@@ -37,14 +37,13 @@#define JQ_ENQ_ERR -3struct op_ring { -dma_addr_t desc; +phys_addr_t desc;uint32_t status; } __packed;struct jr_info { -void (*callback)(dma_addr_t desc,uint32_t status,void *arg); -dma_addr_t desc_phys_addr; -uint32_t desc_addr; +void (*callback)(uint32_t status,void *arg); +phys_addr_t desc_phys_addr;uint32_t desc_len;uint32_t op_done;void *arg;
include/fsl_sec.h +2 -4
@@ -194,11 +194,9 @@ struct jr_regs {struct sg_entry {#if defined(CONFIG_SYS_FSL_SEC_LE ) && !defined(CONFIG_MX6 )uint32_t addr_lo;/* Memory Address - lo */ -uint16_t addr_hi;/* Memory Address of start of buffer - hi */ -uint16_t reserved_zero; +uint32_t addr_hi;/* Memory Address of start of buffer - hi */ #else -uint16_t reserved_zero; -uint16_t addr_hi;/* Memory Address of start of buffer - hi */ +uint32_t addr_hi;/* Memory Address of start of buffer - hi */ uint32_t addr_lo;/* Memory Address - lo */ #endif
Signature · 1 line
1.8.1.4
PATCH v5 3/3 crypto/fsl: SEC driver cleanup for 64 bit and endianness
Quoted 12 lines · Aneesh Bansal
The SEC driver code has been cleaned up to work for 64 bit physical addresses and systems where endianess of SEC block is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings will be depend on endianness of SEC block as 32 bit low and high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in descriptor will vary depending on endianness of SEC.
Quoted 4 lines
Signed-off-by Aneesh Bansal <[email protected]>---
Changes in v5:
Removed compile time warnings
Applied to u-boot-fsl-qoriq. Awaiting upstream. Thanks.
York