add LS1043A platform support

index 486e828..7632041 100644
@@ -806,7 +806,7 @@ static init_fnc_t init_sequence_f[] = {
 #if defined(CONFIG_BOARD_POSTCLK_INIT)
 	board_postclk_init,
 #endif
-#ifdef CONFIG_FSL_CLK
+#ifdef CONFIG_SYS_FSL_CLK
 	get_clocks,
 #endif
 #ifdef CONFIG_M68K

index a006dce..54dcf3b 100644
@@ -17,7 +17,6 @@
 #define CONFIG_BSC9132
 #endif
 
-#define CONFIG_FSL_CLK
 #define CONFIG_MISC_INIT_R
 
 #ifdef CONFIG_SDCARD

index cfa5931..551b72d 100644
@@ -10,7 +10,6 @@
 #define __CONFIG_H
 
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
 
 /*
  * High Level Configuration Options

index 990fc04..7d1262d 100644
@@ -9,7 +9,6 @@
 #define __CONFIG_H
 
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
 
 /*
  * High Level Configuration Options

index fcc531b..ab68e63 100644
@@ -16,7 +16,6 @@
 #define CONFIG_MPC837x		1 /* MPC837x CPU specific */
 #define CONFIG_MPC837XERDB	1
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
 
 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
 

index af8eb8c..29c27fa 100644
@@ -12,7 +12,6 @@
 #define __CONFIG_H
 
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
 #include "../board/freescale/common/ics307_clk.h"
 
 #ifdef CONFIG_36BIT

index 9f784e0..6f614b0 100644
@@ -12,7 +12,6 @@
 
 #define CONFIG_DISPLAY_BOARDINFO
 
-#define CONFIG_FSL_CLK
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */

index 9e40730..81b0855 100644
@@ -15,7 +15,6 @@
 #define CONFIG_PHYS_64BIT
 #endif
 #define	CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
 
 #define CONFIG_P1010
 #define CONFIG_E500			/* BOOKE e500 family */

index c571fac..a9d825b 100644
@@ -12,7 +12,6 @@
 #include "../board/freescale/common/ics307_clk.h"
 
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
 
 #ifdef CONFIG_36BIT
 #define CONFIG_PHYS_64BIT

index 0cd9904..2c4c8b5 100644
@@ -15,7 +15,6 @@
 #define CONFIG_PHYS_64BIT
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_PPC_P2041
-#define CONFIG_FSL_CLK
 
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE

index 4f22657..52942ed 100644
@@ -20,7 +20,6 @@
 #define CONFIG_MP			/* support multiple processors */
 #define CONFIG_PHYS_64BIT
 #define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_FSL_CLK
 
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP		1

index d412d0b..39fa5e2 100644
@@ -20,7 +20,6 @@
 #define CONFIG_MP			/* support multiple processors */
 #define CONFIG_PHYS_64BIT
 #define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_FSL_CLK
 
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP		1

index 18df237..d8b86e6 100644
@@ -29,7 +29,6 @@
 #define CONFIG_T1040QDS
 #define CONFIG_PHYS_64BIT
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
 
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE

index 2091015..da2ccb8 100644
@@ -13,7 +13,6 @@
 #define CONFIG_T104xRDB
 #define CONFIG_PHYS_64BIT
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
 
 #define CONFIG_E500			/* BOOKE e500 family */
 #include <asm/config_mpc85xx.h>

index d35b9d2..a81f1e6 100644
@@ -13,7 +13,6 @@
 
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
-#define CONFIG_FSL_CLK
 #define CONFIG_MMC
 #define CONFIG_USB_EHCI
 #if defined(CONFIG_PPC_T2080)

index c632b8e..8b76234 100644
@@ -14,7 +14,6 @@
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_T2080RDB
 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
-#define CONFIG_FSL_CLK
 #define CONFIG_MMC
 #define CONFIG_USB_EHCI
 #define CONFIG_FSL_SATA_V2

index dd8dd73..4edb3cb 100644
@@ -12,7 +12,6 @@
 
 #define CONFIG_T4240QDS
 #define CONFIG_PHYS_64BIT
-#define CONFIG_FSL_CLK
 
 #define CONFIG_FSL_SATA_V2
 #define CONFIG_PCIE4

index 2c5f800..2e875d2 100644
@@ -13,7 +13,6 @@
 #define CONFIG_T4240RDB
 #define CONFIG_PHYS_64BIT
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
 
 #define CONFIG_FSL_SATA_V2
 #define CONFIG_PCIE4

index 0b609af..8611473 100644
@@ -15,7 +15,6 @@
 #define __CONFIG_H
 
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
 
 #define CONFIG_FSL_ELBC
 #define CONFIG_PCI

index 9fa8f81..7658e61 100644
@@ -18,7 +18,7 @@
 #define CONFIG_SYS_THUMB_BUILD
 #define CONFIG_USE_ARCH_MEMCPY
 #define CONFIG_USE_ARCH_MEMSET
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_ARCH_MISC_INIT
 #define CONFIG_DISPLAY_CPUINFO

index 77c2edc..600bb83 100644
@@ -44,7 +44,6 @@
 #define CONFIG_P1022
 #define CONFIG_CONTROLCENTERD
 #define CONFIG_MP			/* support multiple processors */
-#define CONFIG_FSL_CLK
 
 
 #define CONFIG_SYS_NO_FLASH

index 3c9a529..9210216 100644
@@ -11,7 +11,6 @@
 #define __CONFIG_H
 
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
 
 #include "../board/freescale/common/ics307_clk.h"
 

index e2b9deb..3cb279a 100644
@@ -23,7 +23,6 @@
 #define CONFIG_IDENT_STRING	" hrcon 0.01"
 
 
-#define CONFIG_FSL_CLK
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_LAST_STAGE_INIT

index b8477e8..03cd414 100644
@@ -11,7 +11,7 @@
 
 #define CONFIG_ARMV7_PSCI
 
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

index 784331f..1527164 100644
@@ -11,7 +11,7 @@
 
 #define CONFIG_ARMV7_PSCI
 
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

index 4cfcf98..406d0e6 100644
@@ -16,7 +16,7 @@ unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
 #endif
 
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 #define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
 #define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)

index 583fed5..4395cff 100644
@@ -18,7 +18,7 @@
 unsigned long get_board_sys_clk(void);
 #endif
 
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 #define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQ		133333333
 #define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)

index 152e295..fbaa600 100644
@@ -17,7 +17,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_REVISION_TAG
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_FIT
 

index 0ee8e0d..f113302 100644
@@ -14,7 +14,7 @@
 #define CONFIG_MX25
 #define CONFIG_SYS_TEXT_BASE		0x81200000
 #define CONFIG_MXC_GPIO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_SYS_TIMER_RATE		32768
 #define CONFIG_SYS_TIMER_COUNTER	\

index 41f518e..1b2f952 100644
@@ -19,7 +19,7 @@
 #define CONFIG_MX35
 
 #define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 
 /* Set TEXT at the beginning of the NOR flash */
 #define CONFIG_SYS_TEXT_BASE	0xA0000000

index 35c9346..32cd58e 100644
@@ -18,7 +18,7 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 #define CONFIG_SYS_TEXT_BASE	0x97800000
 
 #include <asm/arch/imx-regs.h>

index be37ce5..fdb4134 100644
@@ -23,7 +23,7 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)

index 81af248..37430f0 100644
@@ -23,7 +23,7 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_OF_LIBFDT
 

index 53fb4f7..54d3e3e 100644
@@ -22,7 +22,7 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)

index f5fcd83..d915b88 100644
@@ -23,7 +23,7 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)

index ba13178..29bfbde 100644
@@ -45,7 +45,7 @@
 
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 
 /* ATAGs */
 #define CONFIG_CMDLINE_TAG

index 04468b9..1b6edee 100644
@@ -21,6 +21,7 @@
 #define CONFIG_MXC_GPT_HCLK
 #define CONFIG_SYSCOUNTER_TIMER
 #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
+#define CONFIG_SYS_FSL_CLK
 
 /* Enable iomux-lpsr support */
 #define CONFIG_IOMUX_LPSR

index 03eb185..433c409 100644
@@ -11,7 +11,6 @@
 #define __CONFIG_H
 
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
 
 #ifdef CONFIG_36BIT
 #define CONFIG_PHYS_64BIT

index 46f5f0f..d83daa0 100644
@@ -11,7 +11,6 @@
 #define __CONFIG_H
 
 #define	CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
 #if defined(CONFIG_TWR_P1025)
 #define CONFIG_BOARDNAME "TWR-P1025"
 #define CONFIG_P1025

index 6735055..6f66662 100644
@@ -14,7 +14,7 @@
 #define CONFIG_MX53
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_OF_LIBFDT
 #define CONFIG_MXC_GPIO

index abd1e98..a3ea2e0 100644
@@ -15,7 +15,7 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_MACH_TYPE		4146
 

index e6f3e28..2acebf1 100644
@@ -16,7 +16,7 @@
  /* High Level Configuration Options */
 #define CONFIG_MX35
 #define CONFIG_MX35_HCLK_FREQ	24000000
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_SYS_CACHELINE_SIZE	32

index b53f699..a921fb6 100644
@@ -7,22 +7,6 @@
 #ifndef __FSL_NS_ACCESS_H_
 #define __FSL_NS_ACCESS_H_
 
-enum csu_cslx_access {
-	CSU_NS_SUP_R = 0x08,
-	CSU_NS_SUP_W = 0x80,
-	CSU_NS_SUP_RW = 0x88,
-	CSU_NS_USER_R = 0x04,
-	CSU_NS_USER_W = 0x40,
-	CSU_NS_USER_RW = 0x44,
-	CSU_S_SUP_R = 0x02,
-	CSU_S_SUP_W = 0x20,
-	CSU_S_SUP_RW = 0x22,
-	CSU_S_USER_R = 0x01,
-	CSU_S_USER_W = 0x10,
-	CSU_S_USER_RW = 0x11,
-	CSU_ALL_RW = 0xff,
-};
-
 enum csu_cslx_ind {
 	CSU_CSLX_PCIE2_IO = 0,
 	CSU_CSLX_PCIE1_IO,

@@ -108,11 +92,88 @@ enum csu_cslx_ind {
 	CSU_CSLX_MAX,
 };
 
-struct csu_ns_dev {
-	unsigned long ind;
-	uint32_t val;
+static struct csu_ns_dev ns_dev[] = {
+	{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+	{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+	{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+	{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+	{ CSU_CSLX_OCRAM, CSU_ALL_RW },
+	{ CSU_CSLX_GIC, CSU_ALL_RW },
+	{ CSU_CSLX_PCIE1, CSU_ALL_RW },
+	{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
+	{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+	{ CSU_CSLX_PCIE2, CSU_ALL_RW },
+	{ CSU_CSLX_SATA, CSU_ALL_RW },
+	{ CSU_CSLX_USB3, CSU_ALL_RW },
+	{ CSU_CSLX_SERDES, CSU_ALL_RW },
+	{ CSU_CSLX_QDMA, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART2, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART1, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART4, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART3, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART6, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART5, CSU_ALL_RW },
+	{ CSU_CSLX_DSPI2, CSU_ALL_RW },
+	{ CSU_CSLX_DSPI1, CSU_ALL_RW },
+	{ CSU_CSLX_QSPI, CSU_ALL_RW },
+	{ CSU_CSLX_ESDHC, CSU_ALL_RW },
+	{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
+	{ CSU_CSLX_IFC, CSU_ALL_RW },
+	{ CSU_CSLX_I2C1, CSU_ALL_RW },
+	{ CSU_CSLX_USB2, CSU_ALL_RW },
+	{ CSU_CSLX_I2C3, CSU_ALL_RW },
+	{ CSU_CSLX_I2C2, CSU_ALL_RW },
+	{ CSU_CSLX_DUART2, CSU_ALL_RW },
+	{ CSU_CSLX_DUART1, CSU_ALL_RW },
+	{ CSU_CSLX_WDT2, CSU_ALL_RW },
+	{ CSU_CSLX_WDT1, CSU_ALL_RW },
+	{ CSU_CSLX_EDMA, CSU_ALL_RW },
+	{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+	{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+	{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+	{ CSU_CSLX_DDR, CSU_ALL_RW },
+	{ CSU_CSLX_QUICC, CSU_ALL_RW },
+	{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+	{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+	{ CSU_CSLX_SFP, CSU_ALL_RW },
+	{ CSU_CSLX_TMU, CSU_ALL_RW },
+	{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+	{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
+	{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
+	{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
+	{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
+	{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO2, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO1, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO4, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO3, CSU_ALL_RW },
+	{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+	{ CSU_CSLX_CSU, CSU_ALL_RW },
+	{ CSU_CSLX_ASRC, CSU_ALL_RW },
+	{ CSU_CSLX_SPDIF, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+	{ CSU_CSLX_SAI2, CSU_ALL_RW },
+	{ CSU_CSLX_SAI1, CSU_ALL_RW },
+	{ CSU_CSLX_SAI4, CSU_ALL_RW },
+	{ CSU_CSLX_SAI3, CSU_ALL_RW },
+	{ CSU_CSLX_FTM2, CSU_ALL_RW },
+	{ CSU_CSLX_FTM1, CSU_ALL_RW },
+	{ CSU_CSLX_FTM4, CSU_ALL_RW },
+	{ CSU_CSLX_FTM3, CSU_ALL_RW },
+	{ CSU_CSLX_FTM6, CSU_ALL_RW },
+	{ CSU_CSLX_FTM5, CSU_ALL_RW },
+	{ CSU_CSLX_FTM8, CSU_ALL_RW },
+	{ CSU_CSLX_FTM7, CSU_ALL_RW },
+	{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+	{ CSU_CSLX_EPU, CSU_ALL_RW },
+	{ CSU_CSLX_GDI, CSU_ALL_RW },
+	{ CSU_CSLX_DDI, CSU_ALL_RW },
+	{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
+	{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+	{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
 };
 
-void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
-
 #endif

index d7de982..d8d16c5 100644
@@ -6,9 +6,10 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <fsl_csu.h>
 #include <asm/arch/ns_access.h>
 
-void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
 {
 	u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
 	u32 *reg;

@@ -28,3 +29,8 @@ void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
 		out_be32(reg, val);
 	}
 }
+
+void enable_layerscape_ns_access(void)
+{
+	enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+}

137 lines not on this page · raw message

138 lines not on this page · raw message

index 03cd414..62636fd 100644
@@ -563,7 +563,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ARMV7_NONSEC
 #define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
-#define CONFIG_LS102XA_NS_ACCESS
+#define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
 #define CONFIG_TIMER_CLK_FREQ		12500000
 

index 1527164..c757193 100644
@@ -415,7 +415,7 @@
 #define CONFIG_ARMV7_NONSEC
 #define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
-#define CONFIG_LS102XA_NS_ACCESS
+#define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
 #define CONFIG_TIMER_CLK_FREQ		12500000
 

new file mode 100644
index 0000000..f4d97fb
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __FSL_CSU_H__
+#define __FSL_CSU_H__
+
+enum csu_cslx_access {
+	CSU_NS_SUP_R = 0x08,
+	CSU_NS_SUP_W = 0x80,
+	CSU_NS_SUP_RW = 0x88,
+	CSU_NS_USER_R = 0x04,
+	CSU_NS_USER_W = 0x40,
+	CSU_NS_USER_RW = 0x44,
+	CSU_S_SUP_R = 0x02,
+	CSU_S_SUP_W = 0x20,
+	CSU_S_SUP_RW = 0x22,
+	CSU_S_USER_R = 0x01,
+	CSU_S_USER_W = 0x10,
+	CSU_S_USER_RW = 0x11,
+	CSU_ALL_RW = 0xff,
+};
+
+struct csu_ns_dev {
+	unsigned long ind;
+	uint32_t val;
+};
+
+void enable_layerscape_ns_access(void);
+
+#endif

index 6702f5a..368d554 100644
@@ -109,7 +109,7 @@ static int tgec_is_fibre(struct eth_device *dev)
 static u16 muram_readw(u16 *addr)
 {
 	u32 base = (u32)addr & ~0x3;
-	u32 val32 = *(u32 *)base;
+	u32 val32 = in_be32((u32 *)base);
 	int byte_pos;
 	u16 ret;
 

@@ -125,7 +125,7 @@ static u16 muram_readw(u16 *addr)
 static void muram_writew(u16 *addr, u16 val)
 {
 	u32 base = (u32)addr & ~0x3;
-	u32 org32 = *(u32 *)base;
+	u32 org32 = in_be32((u32 *)base);
 	u32 val32;
 	int byte_pos;
 

@@ -135,7 +135,7 @@ static void muram_writew(u16 *addr, u16 val)
 	else
 		val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
 
-	*(u32 *)base = val32;
+	out_be32((u32 *)base, val32);
 }
 
 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)

@@ -213,10 +213,10 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
 	pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
 
 	/* enable global mode- snooping data buffers and BDs */
-	pram->mode = PRAM_MODE_GLOBAL;
+	out_be32(&pram->mode, PRAM_MODE_GLOBAL);
 
 	/* init the Rx queue descriptor pionter */
-	pram->rxqd_ptr = pram_page_offset + 0x20;
+	out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
 
 	/* set the max receive buffer length, power of 2 */
 	muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);

@@ -243,10 +243,11 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
 	/* init Rx BDs ring */
 	rxbd = (struct fm_port_bd *)rx_bd_ring_base;
 	for (i = 0; i < RX_BD_RING_SIZE; i++) {
-		rxbd->status = RxBD_EMPTY;
-		rxbd->len = 0;
-		rxbd->buf_ptr_hi = 0;
-		rxbd->buf_ptr_lo = (u32)rx_buf_pool + i * MAX_RXBUF_LEN;
+		muram_writew(&rxbd->status, RxBD_EMPTY);
+		muram_writew(&rxbd->len, 0);
+		muram_writew(&rxbd->buf_ptr_hi, 0);
+		out_be32(&rxbd->buf_ptr_lo, (u32)rx_buf_pool +
+				i * MAX_RXBUF_LEN);
 		rxbd++;
 	}
 

@@ -254,7 +255,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
 	rxqd = &pram->rxqd;
 	muram_writew(&rxqd->gen, 0);
 	muram_writew(&rxqd->bd_ring_base_hi, 0);
-	rxqd->bd_ring_base_lo = (u32)rx_bd_ring_base;
+	out_be32(&rxqd->bd_ring_base_lo, (u32)rx_bd_ring_base);
 	muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
 			* RX_BD_RING_SIZE);
 	muram_writew(&rxqd->offset_in, 0);

@@ -285,10 +286,10 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
 	pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
 
 	/* enable global mode- snooping data buffers and BDs */
-	pram->mode = PRAM_MODE_GLOBAL;
+	out_be32(&pram->mode, PRAM_MODE_GLOBAL);
 
 	/* init the Tx queue descriptor pionter */
-	pram->txqd_ptr = pram_page_offset + 0x40;
+	out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
 
 	/* alloc Tx buffer descriptors from main memory */
 	tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)

@@ -304,16 +305,17 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
 	/* init Tx BDs ring */
 	txbd = (struct fm_port_bd *)tx_bd_ring_base;
 	for (i = 0; i < TX_BD_RING_SIZE; i++) {
-		txbd->status = TxBD_LAST;
-		txbd->len = 0;
-		txbd->buf_ptr_hi = 0;
-		txbd->buf_ptr_lo = 0;
+		muram_writew(&txbd->status, TxBD_LAST);
+		muram_writew(&txbd->len, 0);
+		muram_writew(&txbd->buf_ptr_hi, 0);
+		out_be32(&txbd->buf_ptr_lo, 0);
+		txbd++;
 	}
 
 	/* set the Tx queue decriptor */
 	txqd = &pram->txqd;
 	muram_writew(&txqd->bd_ring_base_hi, 0);
-	txqd->bd_ring_base_lo = (u32)tx_bd_ring_base;
+	out_be32(&txqd->bd_ring_base_lo, (u32)tx_bd_ring_base);
 	muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
 			* TX_BD_RING_SIZE);
 	muram_writew(&txqd->offset_in, 0);

@@ -368,7 +370,7 @@ static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
 
 	pram = fm_eth->tx_pram;
 	/* graceful stop transmission of frames */
-	pram->mode |= PRAM_MODE_GRACEFUL_STOP;
+	setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
 	sync();
 }
 

@@ -378,7 +380,7 @@ static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
 
 	pram = fm_eth->tx_pram;
 	/* re-enable transmission of frames */
-	pram->mode &= ~PRAM_MODE_GRACEFUL_STOP;
+	clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
 	sync();
 }
 

@@ -469,19 +471,20 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len)
 	txbd = fm_eth->cur_txbd;
 
 	/* find one empty TxBD */
-	for (i = 0; txbd->status & TxBD_READY; i++) {
+	for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
 		udelay(100);
 		if (i > 0x1000) {
-			printf("%s: Tx buffer not ready\n", dev->name);
+			printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
+			       dev->name, muram_readw(&txbd->status));
 			return 0;
 		}
 	}
 	/* setup TxBD */
-	txbd->buf_ptr_hi = 0;
-	txbd->buf_ptr_lo = (u32)buf;
-	txbd->len = len;
+	muram_writew(&txbd->buf_ptr_hi, 0);
+	out_be32(&txbd->buf_ptr_lo, (u32)buf);
+	muram_writew(&txbd->len, len);
 	sync();
-	txbd->status = TxBD_READY | TxBD_LAST;
+	muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
 	sync();
 
 	/* update TxQD, let RISC to send the packet */

@@ -493,10 +496,11 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len)
 	sync();
 
 	/* wait for buffer to be transmitted */
-	for (i = 0; txbd->status & TxBD_READY; i++) {
+	for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
 		udelay(100);
 		if (i > 0x10000) {
-			printf("%s: Tx error\n", dev->name);
+			printf("%s: Tx error, txbd->status = 0x%x\n",
+			       dev->name, muram_readw(&txbd->status));
 			return 0;
 		}
 	}

@@ -525,12 +529,12 @@ static int fm_eth_recv(struct eth_device *dev)
 	fm_eth = (struct fm_eth *)dev->priv;
 	pram = fm_eth->rx_pram;
 	rxbd = fm_eth->cur_rxbd;
-	status = rxbd->status;
+	status = muram_readw(&rxbd->status);
 
 	while (!(status & RxBD_EMPTY)) {
 		if (!(status & RxBD_ERROR)) {
-			data = (u8 *)rxbd->buf_ptr_lo;
-			len = rxbd->len;
+			data = (u8 *)in_be32(&rxbd->buf_ptr_lo);
+			len = muram_readw(&rxbd->len);
 			net_process_received_packet(data, len);
 		} else {
 			printf("%s: Rx error\n", dev->name);

@@ -538,8 +542,8 @@ static int fm_eth_recv(struct eth_device *dev)
 		}
 
 		/* clear the RxBDs */
-		rxbd->status = RxBD_EMPTY;
-		rxbd->len = 0;
+		muram_writew(&rxbd->status, RxBD_EMPTY);
+		muram_writew(&rxbd->len, 0);
 		sync();
 
 		/* advance RxBD */

@@ -548,7 +552,7 @@ static int fm_eth_recv(struct eth_device *dev)
 		if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
 			rxbd = rxbd_base;
 		/* read next status */
-		status = rxbd->status;
+		status = muram_readw(&rxbd->status);
 
 		/* update RxQD */
 		offset_out = muram_readw(&pram->rxqd.offset_out);

index 400e9dd..eb0eb3d 100644
@@ -80,11 +80,11 @@ static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
 	out_be32(&imem->iadd, IRAM_IADD_AIE);
 	/* write microcode to IRAM */
 	for (i = 0; i < size / 4; i++)
-		out_be32(&imem->idata, ucode[i]);
+		out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
 
 	/* verify if the writing is over */
 	out_be32(&imem->iadd, 0);
-	while ((in_be32(&imem->idata) != ucode[0]) && --timeout)
+	while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
 		;
 	if (!timeout)
 		printf("Fman%u: microcode upload timeout\n", fm_idx + 1);

@@ -177,14 +177,15 @@ static int fman_upload_firmware(int fm_idx,
 		const struct qe_microcode *ucode = &firmware->microcode[i];
 
 		/* Upload a microcode if it's present */
-		if (ucode->code_offset) {
+		if (be32_to_cpu(ucode->code_offset)) {
 			u32 ucode_size;
 			u32 *code;
 			printf("Fman%u: Uploading microcode version %u.%u.%u\n",
 			       fm_idx + 1, ucode->major, ucode->minor,
 			       ucode->revision);
-			code = (void *)firmware + ucode->code_offset;
-			ucode_size = sizeof(u32) * ucode->count;
+			code = (void *)firmware +
+			       be32_to_cpu(ucode->code_offset);
+			ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
 			fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
 		}
 	}

index 368d554..8ecfd06 100644
@@ -108,12 +108,12 @@ static int tgec_is_fibre(struct eth_device *dev)
 
 static u16 muram_readw(u16 *addr)
 {
-	u32 base = (u32)addr & ~0x3;
-	u32 val32 = in_be32((u32 *)base);
+	ulong base = (ulong)addr & ~0x3UL;
+	u32 val32 = in_be32((void *)base);
 	int byte_pos;
 	u16 ret;
 
-	byte_pos = (u32)addr & 0x3;
+	byte_pos = (ulong)addr & 0x3UL;
 	if (byte_pos)
 		ret = (u16)(val32 & 0x0000ffff);
 	else

@@ -124,18 +124,18 @@ static u16 muram_readw(u16 *addr)
 
 static void muram_writew(u16 *addr, u16 val)
 {
-	u32 base = (u32)addr & ~0x3;
-	u32 org32 = in_be32((u32 *)base);
+	ulong base = (ulong)addr & ~0x3UL;
+	u32 org32 = in_be32((void *)base);
 	u32 val32;
 	int byte_pos;
 
-	byte_pos = (u32)addr & 0x3;
+	byte_pos = (ulong)addr & 0x3UL;
 	if (byte_pos)
 		val32 = (org32 & 0xffff0000) | val;
 	else
 		val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
 
-	out_be32((u32 *)base, val32);
+	out_be32((void *)base, val32);
 }
 
 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)

@@ -199,6 +199,8 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
 	u32 pram_page_offset;
 	void *rx_bd_ring_base;
 	void *rx_buf_pool;
+	u32 bd_ring_base_lo, bd_ring_base_hi;
+	u32 buf_lo, buf_hi;
 	struct fm_port_bd *rxbd;
 	struct fm_port_qd *rxqd;
 	struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;

@@ -207,10 +209,15 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
 	/* alloc global parameter ram at MURAM */
 	pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
 		FM_PRAM_SIZE, FM_PRAM_ALIGN);
+	if (!pram) {
+		printf("%s: No muram for Rx global parameter\n", __func__);
+		return 0;
+	}
+
 	fm_eth->rx_pram = pram;
 
 	/* parameter page offset to MURAM */
-	pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
+	pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
 
 	/* enable global mode- snooping data buffers and BDs */
 	out_be32(&pram->mode, PRAM_MODE_GLOBAL);

@@ -234,6 +241,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
 	if (!rx_buf_pool)
 		return 0;
 	memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
+	debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
 
 	/* save them to fm_eth */
 	fm_eth->rx_bd_ring = rx_bd_ring_base;

@@ -245,17 +253,22 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
 	for (i = 0; i < RX_BD_RING_SIZE; i++) {
 		muram_writew(&rxbd->status, RxBD_EMPTY);
 		muram_writew(&rxbd->len, 0);
-		muram_writew(&rxbd->buf_ptr_hi, 0);
-		out_be32(&rxbd->buf_ptr_lo, (u32)rx_buf_pool +
-				i * MAX_RXBUF_LEN);
+		buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
+					i * MAX_RXBUF_LEN));
+		buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
+					i * MAX_RXBUF_LEN));
+		muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
+		out_be32(&rxbd->buf_ptr_lo, buf_lo);
 		rxbd++;
 	}
 
 	/* set the Rx queue descriptor */
 	rxqd = &pram->rxqd;
 	muram_writew(&rxqd->gen, 0);
-	muram_writew(&rxqd->bd_ring_base_hi, 0);
-	out_be32(&rxqd->bd_ring_base_lo, (u32)rx_bd_ring_base);
+	bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
+	bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
+	muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
+	out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
 	muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
 			* RX_BD_RING_SIZE);
 	muram_writew(&rxqd->offset_in, 0);

@@ -272,6 +285,7 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
 	struct fm_port_global_pram *pram;
 	u32 pram_page_offset;
 	void *tx_bd_ring_base;
+	u32 bd_ring_base_lo, bd_ring_base_hi;
 	struct fm_port_bd *txbd;
 	struct fm_port_qd *txqd;
 	struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;

@@ -280,10 +294,14 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
 	/* alloc global parameter ram at MURAM */
 	pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
 		FM_PRAM_SIZE, FM_PRAM_ALIGN);
+	if (!pram) {
+		printf("%s: No muram for Tx global parameter\n", __func__);
+		return 0;
+	}
 	fm_eth->tx_pram = pram;
 
 	/* parameter page offset to MURAM */
-	pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
+	pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
 
 	/* enable global mode- snooping data buffers and BDs */
 	out_be32(&pram->mode, PRAM_MODE_GLOBAL);

@@ -314,8 +332,10 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
 
 	/* set the Tx queue decriptor */
 	txqd = &pram->txqd;
-	muram_writew(&txqd->bd_ring_base_hi, 0);
-	out_be32(&txqd->bd_ring_base_lo, (u32)tx_bd_ring_base);
+	bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
+	bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
+	muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
+	out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
 	muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
 			* TX_BD_RING_SIZE);
 	muram_writew(&txqd->offset_in, 0);

@@ -480,8 +500,8 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len)
 		}
 	}
 	/* setup TxBD */
-	muram_writew(&txbd->buf_ptr_hi, 0);
-	out_be32(&txbd->buf_ptr_lo, (u32)buf);
+	muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
+	out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
 	muram_writew(&txbd->len, len);
 	sync();
 	muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);

@@ -522,6 +542,7 @@ static int fm_eth_recv(struct eth_device *dev)
 	struct fm_port_global_pram *pram;
 	struct fm_port_bd *rxbd, *rxbd_base;
 	u16 status, len;
+	u32 buf_lo, buf_hi;
 	u8 *data;
 	u16 offset_out;
 	int ret = 1;

@@ -533,7 +554,9 @@ static int fm_eth_recv(struct eth_device *dev)
 
 	while (!(status & RxBD_EMPTY)) {
 		if (!(status & RxBD_ERROR)) {
-			data = (u8 *)in_be32(&rxbd->buf_ptr_lo);
+			buf_hi = muram_readw(&rxbd->buf_ptr_hi);
+			buf_lo = in_be32(&rxbd->buf_ptr_lo);
+			data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
 			len = muram_readw(&rxbd->len);
 			net_process_received_packet(data, len);
 		} else {

index eb0eb3d..df5db72 100644
@@ -22,21 +22,22 @@
 
 struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
 
-u32 fm_muram_base(int fm_idx)
+void *fm_muram_base(int fm_idx)
 {
 	return muram[fm_idx].base;
 }
 
-u32 fm_muram_alloc(int fm_idx, u32 size, u32 align)
+void *fm_muram_alloc(int fm_idx, size_t size, ulong align)
 {
-	u32 ret;
-	u32 align_mask, off;
-	u32 save;
+	void *ret;
+	ulong align_mask;
+	size_t off;
+	void *save;
 
 	align_mask = align - 1;
 	save = muram[fm_idx].alloc;
 
-	off = save & align_mask;
+	off = (ulong)save & align_mask;
 	if (off != 0)
 		muram[fm_idx].alloc += (align - off);
 	off = size & align_mask;

@@ -45,6 +46,7 @@ u32 fm_muram_alloc(int fm_idx, u32 size, u32 align)
 	if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
 		muram[fm_idx].alloc = save;
 		printf("%s: run out of ram.\n", __func__);
+		return NULL;
 	}
 
 	ret = muram[fm_idx].alloc;

@@ -56,7 +58,7 @@ u32 fm_muram_alloc(int fm_idx, u32 size, u32 align)
 
 static void fm_init_muram(int fm_idx, void *reg)
 {
-	u32 base = (u32)reg;
+	void *base = reg;
 
 	muram[fm_idx].base = base;
 	muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;

@@ -256,7 +258,9 @@ static void fm_init_fpm(struct fm_fpm *fpm)
 static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
 {
 	int blk, i, port_id;
-	u32 val, offset, base;
+	u32 val;
+	size_t offset;
+	void *base;
 
 	/* alloc free buffer pool in MURAM */
 	base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);

index a9691c6..73c525e 100644
@@ -26,10 +26,10 @@
 #define MIIM_TIMEOUT    0xFFFF
 
 struct fm_muram {
-	u32 base;
-	u32 top;
-	u32 size;
-	u32 alloc;
+	void *base;
+	void *top;
+	size_t size;
+	void *alloc;
 };
 #define FM_MURAM_RES_SIZE	0x01000
 

@@ -95,8 +95,8 @@ struct fm_port_global_pram {
 #endif
 #define FM_FREE_POOL_ALIGN	256
 
-u32 fm_muram_alloc(int fm_idx, u32 size, u32 align);
-u32 fm_muram_base(int fm_idx);
+void *fm_muram_alloc(int fm_idx, size_t size, ulong align);
+void *fm_muram_base(int fm_idx);
 int fm_init_common(int index, struct ccsr_fman *reg);
 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info);
 phy_interface_t fman_port_enet_if(enum fm_port port);

index 8ecfd06..728718e 100644
@@ -211,7 +211,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
 		FM_PRAM_SIZE, FM_PRAM_ALIGN);
 	if (!pram) {
 		printf("%s: No muram for Rx global parameter\n", __func__);
-		return 0;
+		return -ENOMEM;
 	}
 
 	fm_eth->rx_pram = pram;

@@ -232,14 +232,16 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
 	rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
 			* RX_BD_RING_SIZE);
 	if (!rx_bd_ring_base)
-		return 0;
+		return -ENOMEM;
+
 	memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
 			* RX_BD_RING_SIZE);
 
 	/* alloc Rx buffer from main memory */
 	rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
 	if (!rx_buf_pool)
-		return 0;
+		return -ENOMEM;
+
 	memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
 	debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
 

@@ -277,7 +279,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
 	/* set IM parameter ram pointer to Rx Frame Queue ID */
 	out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
 
-	return 1;
+	return 0;
 }
 
 static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)

@@ -296,7 +298,7 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
 		FM_PRAM_SIZE, FM_PRAM_ALIGN);
 	if (!pram) {
 		printf("%s: No muram for Tx global parameter\n", __func__);
-		return 0;
+		return -ENOMEM;
 	}
 	fm_eth->tx_pram = pram;
 

@@ -313,7 +315,8 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
 	tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
 			* TX_BD_RING_SIZE);
 	if (!tx_bd_ring_base)
-		return 0;
+		return -ENOMEM;
+
 	memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
 			* TX_BD_RING_SIZE);
 	/* save it to fm_eth */

@@ -344,29 +347,35 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
 	/* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
 	out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
 
-	return 1;
+	return 0;
 }
 
 static int fm_eth_init(struct fm_eth *fm_eth)
 {
+	int ret;
 
-	if (!fm_eth_rx_port_parameter_init(fm_eth))
-		return 0;
+	ret = fm_eth_rx_port_parameter_init(fm_eth);
+	if (ret)
+		return ret;
 
-	if (!fm_eth_tx_port_parameter_init(fm_eth))
-		return 0;
+	ret = fm_eth_tx_port_parameter_init(fm_eth);
+	if (ret)
+		return ret;
 
-	return 1;
+	return 0;
 }
 
 static int fm_eth_startup(struct fm_eth *fm_eth)
 {
 	struct fsl_enet_mac *mac;
+	int ret;
+
 	mac = fm_eth->mac;
 
 	/* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
-	if (!fm_eth_init(fm_eth))
-		return 0;
+	ret = fm_eth_init(fm_eth);
+	if (ret)
+		return ret;
 	/* setup the MAC controller */
 	mac->init_mac(mac);
 

@@ -381,7 +390,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth)
 	/* init bmi tx port, IM mode and disable */
 	bmi_tx_port_init(fm_eth->tx_port);
 
-	return 1;
+	return 0;
 }
 
 static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)

@@ -628,7 +637,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
 	/* alloc mac controller */
 	mac = malloc(sizeof(struct fsl_enet_mac));
 	if (!mac)
-		return 0;
+		return -ENOMEM;
 	memset(mac, 0, sizeof(struct fsl_enet_mac));
 
 	/* save the mac to fm_eth struct */

@@ -643,7 +652,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
 		init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
 #endif
 
-	return 1;
+	return 0;
 }
 
 static int init_phy(struct eth_device *dev)

@@ -696,17 +705,18 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
 	struct eth_device *dev;
 	struct fm_eth *fm_eth;
 	int i, num = info->num;
+	int ret;
 
 	/* alloc eth device */
 	dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 	if (!dev)
-		return 0;
+		return -ENOMEM;
 	memset(dev, 0, sizeof(struct eth_device));
 
 	/* alloc the FMan ethernet private struct */
 	fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
 	if (!fm_eth)
-		return 0;
+		return -ENOMEM;
 	memset(fm_eth, 0, sizeof(struct fm_eth));
 
 	/* save off some things we need from the info struct */

@@ -721,8 +731,9 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
 	fm_eth->max_rx_len = MAX_RXBUF_LEN;
 
 	/* init global mac structure */
-	if (!fm_eth_init_mac(fm_eth, reg))
-		return 0;
+	ret = fm_eth_init_mac(fm_eth, reg);
+	if (ret)
+		return ret;
 
 	/* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
 	if (fm_eth->type == FM_ETH_1G_E)

@@ -743,8 +754,9 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
 	fm_eth->enet_if = info->enet_if;
 
 	/* startup the FM im */
-	if (!fm_eth_startup(fm_eth))
-		return 0;
+	ret = fm_eth_startup(fm_eth);
+	if (ret)
+		return ret;
 
 	init_phy(dev);
 

@@ -753,5 +765,5 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
 		dev->enetaddr[i] = 0;
 	eth_register(dev);
 
-	return 1;
+	return 0;
 }

index 728718e..2111a11 100644
@@ -95,6 +95,7 @@ static void dtsec_init_phy(struct eth_device *dev)
 		dtsec_configure_serdes(fm_eth);
 }
 
+#ifdef CONFIG_PHYLIB
 static int tgec_is_fibre(struct eth_device *dev)
 {
 	struct fm_eth *fm = dev->priv;

@@ -105,6 +106,7 @@ static int tgec_is_fibre(struct eth_device *dev)
 	return hwconfig_arg_cmp(phyopt, "xfi");
 }
 #endif
+#endif
 
 static u16 muram_readw(u16 *addr)
 {

@@ -483,8 +485,10 @@ static void fm_eth_halt(struct eth_device *dev)
 	/* disable bmi Rx port */
 	bmi_rx_port_disable(fm_eth->rx_port);
 
+#ifdef CONFIG_PHYLIB
 	if (fm_eth->phydev)
 		phy_shutdown(fm_eth->phydev);
+#endif
 }
 
 static int fm_eth_send(struct eth_device *dev, void *buf, int len)

@@ -658,13 +662,15 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
 static int init_phy(struct eth_device *dev)
 {
 	struct fm_eth *fm_eth = dev->priv;
+#ifdef CONFIG_PHYLIB
 	struct phy_device *phydev = NULL;
 	u32 supported;
+#endif
 
-#ifdef CONFIG_PHYLIB
 	if (fm_eth->type == FM_ETH_1G_E)
 		dtsec_init_phy(dev);
 
+#ifdef CONFIG_PHYLIB
 	if (fm_eth->bus) {
 		phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
 					fm_eth->enet_if);

index 0c9d85e..101b8db 100644
@@ -19,7 +19,7 @@
 #include <fsl_sec.h>
 #include <fsl_sfp.h>
 #include <asm/fsl_lbc.h>
-#include <asm/fsl_fman.h>
+#include <fsl_fman.h>
 #include <fsl_immap.h>
 
 typedef struct ccsr_local {

index 501d4b3..df90476 100644
@@ -26,7 +26,7 @@
 #include <fsl_mdio.h>
 #include <malloc.h>
 #include <fdt_support.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"

index 396103f..172a55b 100644
@@ -55,7 +55,7 @@
 #include <fsl_mdio.h>
 #include <malloc.h>
 #include <fdt_support.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"

index 5cbec7f..c68dc2c 100644
@@ -24,7 +24,7 @@
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 #define EMI_NONE	0xffffffff
 #define EMI_MASK	0xf0000000

index ad1bffd..62b1635 100644
@@ -55,7 +55,7 @@
 #include <fsl_mdio.h>
 #include <malloc.h>
 #include <fdt_support.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"

index 56f561a..074b713 100644
@@ -26,7 +26,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

index 532eeac..95fe85b 100644
@@ -19,7 +19,7 @@
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <malloc.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 #include "cpld.h"
 #include "../common/fman.h"

index 441d6a3..99c23f7 100644
@@ -21,7 +21,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
 #include "../common/qixis.h"
 #include "../common/fman.h"

index 856ec6e..02b283d 100644
@@ -21,7 +21,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
 #include "../common/fman.h"
 

index 8c82934..8bf34fa 100644
@@ -17,7 +17,7 @@
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <malloc.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <vsc9953.h>
 
 #include "../common/fman.h"

index 71d0457..52cd112 100644
@@ -11,7 +11,7 @@
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <malloc.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <vsc9953.h>
 
 #include "../common/fman.h"

index b82e9e7..1c0ce24 100644
@@ -21,7 +21,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
 #include <hwconfig.h>
 #include "../common/qixis.h"

index cbbc625..ea51195 100644
@@ -21,7 +21,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
 
 int board_eth_init(bd_t *bis)

index 9b416b1..2dfdcbb 100644
@@ -21,7 +21,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
 #include <hwconfig.h>
 #include "../common/qixis.h"

index 879bd1a..e563a61 100644
@@ -23,7 +23,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
 #include <hwconfig.h>
 

index 8d3dc0e..b339a84 100644
@@ -7,7 +7,7 @@
 #include <common.h>
 #include <asm/types.h>
 #include <asm/io.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <fsl_mdio.h>
 #include <phy.h>
 

index 2111a11..ec0a3cb 100644
@@ -13,8 +13,8 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
-#include <asm/fsl_tgec.h>
+#include <fsl_dtsec.h>
+#include <fsl_tgec.h>
 #include <fsl_memac.h>
 
 #include "fm.h"

index 73c525e..fa9bc9f 100644
@@ -10,7 +10,7 @@
 #include <common.h>
 #include <phy.h>
 #include <fm_eth.h>
-#include <asm/fsl_fman.h>
+#include <fsl_fman.h>
 
 /* Port ID */
 #define OH_PORT_ID_BASE		0x01

index 5017123..8d4622f 100644
@@ -12,7 +12,7 @@
 #include <phy.h>
 #include <asm/types.h>
 #include <asm/io.h>
-#include <asm/fsl_tgec.h>
+#include <fsl_tgec.h>
 
 #include "fm.h"
 

index 095f00c..24cb17b 100644
@@ -9,7 +9,7 @@
 #include <miiphy.h>
 #include <phy.h>
 #include <asm/io.h>
-#include <asm/fsl_tgec.h>
+#include <fsl_tgec.h>
 #include <fm_eth.h>
 
 /*

similarity index 100%
rename from arch/powerpc/include/asm/fsl_dtsec.h
rename to include/fsl_dtsec.h

similarity index 100%
rename from arch/powerpc/include/asm/fsl_fman.h
rename to include/fsl_fman.h

similarity index 100%
rename from arch/powerpc/include/asm/fsl_tgec.h
rename to include/fsl_tgec.h

index ec0a3cb..eb8e936 100644
@@ -41,28 +41,35 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
 	bus.priv = priv->mac->phyregs;
 	bool sgmii_2500 = (priv->enet_if ==
 			PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
+	int i = 0;
 
+qsgmii_loop:
 	/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
 	value = PHY_SGMII_IF_MODE_SGMII;
 	if (!sgmii_2500)
 		value |= PHY_SGMII_IF_MODE_AN;
 
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
 
 	/* Dev ability according to SGMII specification */
 	value = PHY_SGMII_DEV_ABILITY_SGMII;
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
 
 	/* Adjust link timer for SGMII  -
 	1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x3);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
 
 	/* Restart AN */
 	value = PHY_SGMII_CR_DEF_VAL;
 	if (!sgmii_2500)
 		value |= PHY_SGMII_CR_RESET_AN;
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
+
+	if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
+		i++;
+		goto qsgmii_loop;
+	}
 #else
 	struct dtsec *regs = priv->mac->base;
 	struct tsec_mii_mng *phyregs = priv->mac->phyregs;

@@ -91,6 +98,7 @@ static void dtsec_init_phy(struct eth_device *dev)
 #endif
 
 	if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
+	    fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
 	    fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
 		dtsec_configure_serdes(fm_eth);
 }

index 3e1b9f4..d43f801 100644
@@ -45,8 +45,10 @@ enum fm_eth_type {
 #ifdef CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#if (CONFIG_SYS_NUM_FMAN == 2)
 #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
 #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
+#endif
 #else
 #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)

@@ -89,6 +91,7 @@ enum fm_eth_type {
 				 offsetof(struct ccsr_fman, memac[n-1]),\
 }
 #else
+#if (CONFIG_SYS_NUM_FMAN == 2)
 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
 {									\
 	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR)	\

@@ -101,6 +104,20 @@ enum fm_eth_type {
 	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
 				offsetof(struct ccsr_fman, memac[n-1+8]),\
 }
+#else
+#define FM_TGEC_INFO_INITIALIZER(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_10G_E,					\
+	.port		= FM##idx##_10GEC##n,				\
+	.rx_port_id	= RX_PORT_10G_BASE + n - 1,			\
+	.tx_port_id	= TX_PORT_10G_BASE + n - 1,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				offsetof(struct ccsr_fman, memac[n-1+8]),\
+}
+#endif
 #endif
 
 #if (CONFIG_SYS_NUM_FM1_10GEC >= 3)

440 lines not on this page · raw message

similarity index 71%
rename from arch/arm/cpu/armv8/fsl-lsch3/cpu.h
rename to arch/arm/cpu/armv8/fsl-layerscape/cpu.h
index 2e3312b..8072f3c 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014, Freescale Semiconductor
+ * Copyright 2014-2015, Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

similarity index 94%
rename from arch/arm/cpu/armv8/fsl-lsch3/fdt.c
rename to arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 567c419..aa88d34 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -7,11 +7,16 @@
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
-#include <asm/arch-fsl-lsch3/fdt.h>
+#include <phy.h>
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch/fdt.h>
+#endif
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
-#include "mp.h"
+#ifdef CONFIG_MP
+#include <asm/arch/mp.h>
+#endif
 
 #ifdef CONFIG_MP
 void ft_fixup_cpu(void *blob)

@@ -150,6 +155,7 @@ void append_mmu_masters(void *blob, const char *smmu_path,
  *      for all DPAA2 devices.
  *
  */
+#ifdef CONFIG_FSL_LSCH3
 static void fdt_fixup_smmu(void *blob)
 {
 	int nodeoffset;

@@ -165,6 +171,7 @@ static void fdt_fixup_smmu(void *blob)
 	fdt_fixup_smmu_pcie(blob);
 #endif
 }
+#endif
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {

@@ -181,9 +188,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	ft_pci_setup(blob, bd);
 #endif
 
-#if defined(CONFIG_FSL_ESDHC)
+#ifdef CONFIG_FSL_ESDHC
 	fdt_fixup_esdhc(blob, bd);
 #endif
 
+#ifdef CONFIG_FSL_LSCH3
 	fdt_fixup_smmu(blob);
+#endif
 }

similarity index 95%
rename from arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
rename to arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index ae08343..2ab8da6 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -8,7 +8,7 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/fsl_serdes.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <asm/arch/soc.h>
 #include <fsl-mc/ldpaa_wriop.h>
 
 #ifdef CONFIG_SYS_FSL_SRDS_1

@@ -35,7 +35,7 @@ int is_serdes_configured(enum srds_prtcl device)
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-	u32 cfg = in_le32(&gur->rcwsr[28]);
+	u32 cfg = gur_in32(&gur->rcwsr[28]);
 	int i;
 
 	switch (sd) {

@@ -76,7 +76,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 
 	memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
 
-	cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask;
+	cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
 	cfg >>= sd_prctl_shift;
 	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 

similarity index 93%
rename from arch/arm/cpu/armv8/fsl-lsch3/speed.c
rename to arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index d9f137c..4054c3c 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014, Freescale Semiconductor, Inc.
+ * Copyright 2014-2015, Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *

@@ -11,8 +11,8 @@
 #include <fsl_ifc.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/soc.h>
 #include "cpu.h"
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -83,15 +83,15 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_ddrbus2 = sysclk;
 #endif
 
-	sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
+	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
 	/* Platform clock is half of platform PLL */
 	sys_info->freq_systembus /= 2;
-	sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
+	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
-	sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
+	sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
 

@@ -118,7 +118,7 @@ void get_sys_info(struct sys_info *sys_info)
 	}
 
 #if defined(CONFIG_FSL_IFC)
-	ccr = in_le32(&ifc_regs.gregs->ifc_ccr);
+	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
 	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 
 	sys_info->freq_localbus = sys_info->freq_systembus / ccr;

similarity index 97%
rename from arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
rename to arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c
index 0b79a50..ea3114c 100644
@@ -1,12 +1,11 @@
 /*
- * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/arch/fsl_serdes.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
 
 struct serdes_config {
 	u8 protocol;

similarity index 92%
rename from arch/arm/cpu/armv8/fsl-lsch3/mp.c
rename to arch/arm/cpu/armv8/fsl-layerscape/mp.c
index da7853a..1b13d32 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -7,9 +7,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/system.h>
-#include <asm/io.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
-#include "mp.h"
+#include <asm/arch/mp.h>
+#include <asm/arch/soc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -23,7 +22,7 @@ phys_addr_t determine_mp_bootpg(void)
 	return (phys_addr_t)&secondary_boot_code;
 }
 
-int fsl_lsch3_wake_seconday_cores(void)
+int fsl_layerscape_wake_seconday_cores(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);

@@ -48,9 +47,10 @@ int fsl_lsch3_wake_seconday_cores(void)
 			   (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
 
 	printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
-	out_le32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
-	out_le32(&gur->bootlocptrl, (u32)gd->relocaddr);
-	out_le32(&gur->scratchrw[6], 1);
+
+	gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
+	gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
+	gur_out32(&gur->scratchrw[6], 1);
 	asm volatile("dsb st" : : : "memory");
 	rst->brrl = cores;
 	asm volatile("dsb st" : : : "memory");

similarity index 73%
rename from arch/arm/cpu/armv8/fsl-lsch3/soc.c
rename to arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 2538001..73e48a7 100644
@@ -1,19 +1,18 @@
 /*
- * Copyright 2015 Freescale Semiconductor
+ * Copyright 2014-2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
 #include <fsl_ifc.h>
-#include <nand.h>
-#include <spl.h>
-#include <asm/arch-fsl-lsch3/soc.h>
+#include <asm/arch/soc.h>
 #include <asm/io.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_LS2085A
 static void erratum_a008751(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751

@@ -77,31 +76,11 @@ void fsl_lsch3_early_init_f(void)
 	init_early_memctl_regs();	/* tighten IFC timing */
 	erratum_a009203();
 }
+#endif
 
-#ifdef CONFIG_SPL_BUILD
-void board_init_f(ulong dummy)
-{
-	/* Clear global data */
-	memset((void *)gd, 0, sizeof(gd_t));
-
-	arch_cpu_init();
-	board_early_init_f();
-	timer_init();
-	env_init();
-	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
-
-	serial_init();
-	console_init_f();
-	dram_init();
-
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	board_init_r(NULL, 0);
-}
-
-u32 spl_boot_device(void)
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
 {
-	return BOOT_DEVICE_NAND;
+	return 0;
 }
 #endif

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deleted file mode 100644
index 15af5b9..0000000
@@ -1,7 +0,0 @@
-/*
- * Copyright 2014, Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-void get_sys_info(struct sys_info *sys_info);

similarity index 56%
rename from arch/arm/include/asm/arch-fsl-lsch3/clock.h
rename to arch/arm/include/asm/arch-fsl-layerscape/clock.h
index 62bc53c..6935913 100644
@@ -1,12 +1,12 @@
 /*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
  */
 
-#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_
-#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_
+#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
+#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
 
 #include <common.h>
 

@@ -21,4 +21,4 @@ enum mxc_clock {
 
 unsigned int mxc_get_clock(enum mxc_clock clk);
 
-#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */
+#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */

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similarity index 71%
rename from arch/arm/include/asm/arch-fsl-lsch3/fdt.h
rename to arch/arm/include/asm/arch-fsl-layerscape/fdt.h
index 21d20fb..4da73ab 100644
@@ -4,7 +4,11 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
+
 void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt);
 void append_mmu_masters(void *blob, const char *smmu_path,
 			const char *master_name, u32 *stream_ids, int count);
 void fdt_fixup_smmu_pcie(void *blob);
+#endif	/* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */

similarity index 88%
rename from arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
rename to arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index 2810f3f..730c2b2 100644
@@ -4,13 +4,12 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __FSL_SERDES_H
-#define __FSL_SERDES_H
+#ifndef __FSL_SERDES_H__
+#define __FSL_SERDES_H__
 
 #include <config.h>
 
-#define	SRDS_MAX_LANES	8
-
+#if defined(CONFIG_LS2085A)
 enum srds_prtcl {
 	NONE = 0,
 	PCIE1,

@@ -56,12 +55,12 @@ enum srds {
 	FSL_SRDS_1  = 0,
 	FSL_SRDS_2  = 1,
 };
+#endif
 
 int is_serdes_configured(enum srds_prtcl device);
 void fsl_serdes_init(void);
-
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
 int is_serdes_prtcl_valid(int serdes, u32 prtcl);
 
-#endif /* __FSL_SERDES_H */
+#endif /* __FSL_SERDES_H__ */

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similarity index 100%
rename from arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h
rename to arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h

new file mode 100644
index 0000000..d54eacd
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
+#include <asm/arch-armv8/mmu.h>
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */

similarity index 82%
rename from arch/arm/cpu/armv8/fsl-lsch3/mp.h
rename to arch/arm/include/asm/arch-fsl-layerscape/mp.h
index c985d6a..e46e076 100644
@@ -1,11 +1,11 @@
 /*
- * Copyright 2014, Freescale Semiconductor
+ * Copyright 2014-2015, Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef _FSL_CH3_MP_H
-#define _FSL_CH3_MP_H
+#ifndef _FSL_LAYERSCAPE_MP_H
+#define _FSL_LAYERSCAPE_MP_H
 
 /*
 * Each spin table element is defined as

@@ -29,10 +29,10 @@ extern u64 __spin_table[];
 extern u64 __real_cntfrq;
 extern u64 *secondary_boot_code;
 extern size_t __secondary_boot_code_size;
-int fsl_lsch3_wake_seconday_cores(void);
+int fsl_layerscape_wake_seconday_cores(void);
 void *get_spin_tbl_addr(void);
 phys_addr_t determine_mp_bootpg(void);
 void secondary_boot_func(void);
 int is_core_online(u64 cpu_id);
 #endif
-#endif /* _FSL_CH3_MP_H */
+#endif /* _FSL_LAYERSCAPE_MP_H */

similarity index 50%
rename from arch/arm/include/asm/arch-fsl-lsch3/soc.h
rename to arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 9a29272..f131f57 100644
@@ -4,6 +4,25 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define gur_in32(a)       in_le32(a)
+#define gur_out32(a, v)   out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
+#define gur_in32(a)       in_be32(a)
+#define gur_out32(a, v)   out_be32(a, v)
+#endif
+
+#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define scfg_in32(a)       in_le32(a)
+#define scfg_out32(a, v)   out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
+#define scfg_in32(a)       in_be32(a)
+#define scfg_out32(a, v)   out_be32(a, v)
+#endif
+
 struct cpu_type {
 	char name[15];
 	u32 soc_ver;

@@ -25,4 +44,4 @@ struct cpu_type {
 
 void fsl_lsch3_early_init_f(void);
 void cpu_name(char *name);
-
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */

new file mode 100644
index 0000000..de795f6
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2014-2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FSL_LAYERSCAPE_SPEED_H
+#define _FSL_LAYERSCAPE_SPEED_H
+void get_sys_info(struct sys_info *sys_info);
+#endif /* _FSL_LAYERSCAPE_SPEED_H */

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deleted file mode 100644
index f23a78c..0000000
@@ -1,9 +0,0 @@
-/*
- * Copyright 2014, Freescale Semiconductor
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARMV8_FSL_LSCH3_GPIO_H_
-#define _ASM_ARMV8_FSL_LSCH3_GPIO_H_
-#endif	/* _ASM_ARMV8_FSL_LSCH3_GPIO_H_ */

deleted file mode 100644
index 8f00535..0000000
@@ -1,13 +0,0 @@
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- */
-
-#ifndef __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
-#define __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
-
-#define I2C_QUIRK_REG	/* enable 8-bit driver */
-
-#endif /* __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ */

index 22fff02..435fc45 100644
@@ -15,14 +15,11 @@
 #define CONFIG_STATIC_RELA
 #endif
 
-#ifdef CONFIG_FSL_LSCH3
-#include <asm/arch-fsl-lsch3/config.h>
-#endif
-
 #if defined(CONFIG_LS102XA) || \
 	defined(CONFIG_CPU_PXA27X) || \
 	defined(CONFIG_CPU_MONAHANS) || \
-	defined(CONFIG_CPU_PXA25X)
+	defined(CONFIG_CPU_PXA25X) || \
+	defined(CONFIG_FSL_LAYERSCAPE)
 #include <asm/arch/config.h>
 #endif
 

index 73c4410..27481e2 100644
@@ -15,7 +15,7 @@
 #include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
 #include <environment.h>
-#include <asm/arch-fsl-lsch3/soc.h>
+#include <asm/arch/soc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

index 007b433..b8a2bf4 100644
@@ -8,7 +8,6 @@
 #include <netdev.h>
 #include <asm/io.h>
 #include <asm/arch/fsl_serdes.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
 #include <hwconfig.h>
 #include <fsl_mdio.h>
 #include <malloc.h>

index 2315bdb..b02d6e8 100644
@@ -17,7 +17,7 @@
 #include <environment.h>
 #include <i2c.h>
 #include <rtc.h>
-#include <asm/arch-fsl-lsch3/soc.h>
+#include <asm/arch/soc.h>
 #include <hwconfig.h>
 
 #include "../common/qixis.h"

index 0a1163a..d578757 100644
@@ -16,7 +16,6 @@
 #include <asm/io.h>
 #include <exports.h>
 #include <asm/arch/fsl_serdes.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
 #include <fsl-mc/ldpaa_wriop.h>
 
 DECLARE_GLOBAL_DATA_PTR;

index 5e7997c..18953b8 100644
@@ -17,7 +17,7 @@
 #include <fsl-mc/fsl_mc.h>
 #include <environment.h>
 #include <i2c.h>
-#include <asm/arch-fsl-lsch3/soc.h>
+#include <asm/arch/soc.h>
 
 #include "../common/qixis.h"
 #include "ls2085ardb_qixis.h"

index 0f977d7..fa4c82f 100644
@@ -523,8 +523,8 @@ static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
 #endif
 
 static struct mxc_i2c_bus mxc_i2c_buses[] = {
-#if defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LSCH3) || \
-		defined(CONFIG_VF610)
+#if defined(CONFIG_LS102XA) || defined(CONFIG_VF610) || \
+	defined(CONFIG_FSL_LAYERSCAPE)
 	{ 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
 	{ 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
 	{ 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },

index a592891..98d9fbe 100644
@@ -8,7 +8,6 @@
 #include <errno.h>
 #include <asm/io.h>
 #include <asm/system.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
 
 #include <fsl-mc/fsl_mc.h>
 #include <fsl_debug_server.h>

index 6b7960a..93ed4f1 100644
@@ -7,9 +7,7 @@
 #include <phy.h>
 #include <fsl-mc/ldpaa_wriop.h>
 #include <asm/io.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
 #include <asm/arch/fsl_serdes.h>
-#include <fsl-mc/ldpaa_wriop.h>
 
 u32 dpmac_to_devdisr[] = {
 	[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,

index 2f24a6a..4cee038 100644
@@ -11,7 +11,9 @@
 #include <asm/io.h>
 #include <errno.h>
 #include <malloc.h>
-#include <asm/arch-fsl-lsch3/fdt.h>
+#ifdef CONFIG_FSL_LAYERSCAPE
+#include <asm/arch/fdt.h>
+#endif
 
 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
 #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE

index ecb1f06..142936b 100644
@@ -76,6 +76,9 @@ typedef volatile unsigned char	vu_char;
 #ifdef CONFIG_SOC_DA8XX
 #include <asm/arch/hardware.h>
 #endif
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch/immap_lsch3.h>
+#endif
 
 #include <part.h>
 #include <flash.h>

index 9c8a864..9755cae 100644
@@ -9,8 +9,10 @@
 
 
 #define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LAYERSCAPE
 #define CONFIG_FSL_LSCH3
 #define CONFIG_LS2085A
+#define CONFIG_MP
 #define CONFIG_GICV3
 #define CONFIG_FSL_TZPC_BP147
 

@@ -18,12 +20,15 @@
 #define CONFIG_ARM_ERRATA_828024
 #define CONFIG_ARM_ERRATA_826974
 
-#include <asm/arch-fsl-lsch3/ls2085a_stream_id.h>
-#include <asm/arch-fsl-lsch3/config.h>
+#include <asm/arch/ls2085a_stream_id.h>
+#include <asm/arch/config.h>
 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
 #define	CONFIG_SYS_HAS_SERDES
 #endif
 
+/* Link Definitions */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+
 /* We need architecture specific misc initializations */
 #define CONFIG_ARCH_MISC_INIT
 

@@ -61,6 +66,7 @@
 
 #define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
 
+#define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

index be7442d..fe9d982 100644
@@ -180,6 +180,8 @@ static inline void early_mmu_setup(void)
 	set_pgtable_table(level1_table0,
 			  CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1,
 			  level2_table1);
+#elif defined(CONFIG_FSL_LSCH2)
+	set_pgtable_table(level1_table0, 1, level2_table1);
 #endif
 	/* Find the table and fill in the block entries */
 	for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) {

@@ -215,6 +217,9 @@ static inline void early_mmu_setup(void)
  *
  * For LSCH3:
  * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB.
+ * For LSCH2:
+ * Level 2 table 1 contains 512 entries for each 2MB from 1GB to 2GB.
+ * Level 2 table 2 contains 512 entries for each 2MB from 20GB to 21GB.
  */
 static inline void final_mmu_setup(void)
 {

@@ -225,6 +230,9 @@ static inline void final_mmu_setup(void)
 	u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
 #ifdef CONFIG_FSL_LSCH3
 	u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+#elif defined(CONFIG_FSL_LSCH2)
+	u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+	u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000);
 #endif
 	struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
 

@@ -239,6 +247,11 @@ static inline void final_mmu_setup(void)
 	set_pgtable_table(level1_table0,
 			  CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
 			  level2_table1);
+#elif defined(CONFIG_FSL_LSCH2)
+	set_pgtable_table(level1_table0, 1, level2_table1);
+	set_pgtable_table(level1_table0,
+			  CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
+			  level2_table2);
 #endif
 
 	/* Find the table and fill in the block entries */

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index 73e48a7..637853d 100644
@@ -76,6 +76,23 @@ void fsl_lsch3_early_init_f(void)
 	init_early_memctl_regs();	/* tighten IFC timing */
 	erratum_a009203();
 }
+
+#elif defined(CONFIG_LS1043A)
+void fsl_lsch2_early_init_f(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+#ifdef CONFIG_FSL_IFC
+	init_early_memctl_regs();	/* tighten IFC timing */
+#endif
+
+	/*
+	 * Enable snoop requests and DVM message requests for
+	 * Slave insterface S4 (A53 core cluster)
+	 */
+	out_le32(&cci->slave[4].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+}
 #endif
 
 #ifdef CONFIG_BOARD_LATE_INIT

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index f131f57..5ed456e 100644
@@ -33,6 +33,7 @@ struct cpu_type {
 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
 
 #define SVR_WO_E		0xFFFFFE
+#define SVR_LS1043		0x879204
 #define SVR_LS2045		0x870120
 #define SVR_LS2080		0x870110
 #define SVR_LS2085		0x870100

@@ -42,6 +43,11 @@ struct cpu_type {
 #define SVR_SOC_VER(svr)	(((svr) >> 8) & SVR_WO_E)
 #define IS_E_PROCESSOR(svr)	(!((svr >> 8) & 0x1))
 
+#ifdef CONFIG_FSL_LSCH3
 void fsl_lsch3_early_init_f(void);
+#elif defined(CONFIG_FSL_LSCH2)
+void fsl_lsch2_early_init_f(void);
+#endif
+
 void cpu_name(char *name);
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */

index 587ee39..d8d9af4 100644
@@ -65,6 +65,7 @@
 /*
  * Section
  */
+#define PMD_SECT_NS		(1 << 5)
 #define PMD_SECT_NON_SHARE	(0 << 8)
 #define PMD_SECT_OUTER_SHARE	(2 << 8)
 #define PMD_SECT_INNER_SHARE	(3 << 8)

index 142936b..09a131d 100644
@@ -79,6 +79,9 @@ typedef volatile unsigned char	vu_char;
 #ifdef CONFIG_FSL_LSCH3
 #include <asm/arch/immap_lsch3.h>
 #endif
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch/immap_lsch2.h>
+#endif
 
 #include <part.h>
 #include <flash.h>

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