mpc85xx: Add support for the Varisys Cyrus board

PATCH Superseded Andy Fleming 2 participants 3 messages Nov 3, 2015 – Nov 4, 2015 PowerPC

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Andy Fleming

author

2015-11-03 23:30 UTC #0 lore raw

PATCH v2 1/1 mpc85xx: Add support for the Varisys Cyrus board

This board runs a P5020 or P5040 chip, and utilizes an EEPROM with similar formatting to the Freescale P5020DS.

Large amounts of this code were developed by
Adrian Cox <adrian@humboldt dot co dot uk>

Signed-off-by Andy Fleming <[email protected]>

---
v2:
* Cleaned up sys_eeprom.c
* Removed CONFIG_CMD_ELF, CONFIG_SYS_GENERIC_BOARD

 arch/powerpc/cpu/mpc85xx/Kconfig     |   4 +
 board/varisys/common/Makefile        |  23 ++
 board/varisys/common/eeprom.h        |   6 +
 board/varisys/common/sys_eeprom.c    | 500 +++++++++++++++++++++++++++++
 board/varisys/cyrus/Kconfig          |  13 +
 board/varisys/cyrus/Makefile         |   8 +
 board/varisys/cyrus/README           |  21 ++
 board/varisys/cyrus/cyrus.c          | 116 +++++++
 board/varisys/cyrus/cyrus.h          |  11 +
 board/varisys/cyrus/ddr.c            | 188 +++++++++++
 board/varisys/cyrus/eth.c            | 100 ++++++
 board/varisys/cyrus/law.c            |  27 ++
 board/varisys/cyrus/pbi.cfg          |  35 +++
 board/varisys/cyrus/pci.c            |  23 ++
 board/varisys/cyrus/rcw_p5020_v2.cfg |  11 +
 board/varisys/cyrus/rcw_p5040.cfg    |  11 +
 board/varisys/cyrus/tlb.c            | 106 +++++++
 configs/Cyrus_P5020_defconfig        |   9 +
 configs/Cyrus_P5040_defconfig        |   9 +
 include/configs/cyrus.h              | 588 +++++++++++++++++++++++++++++++++++
 20 files changed, 1809 insertions(+)
 create mode 100644 board/varisys/common/Makefile
 create mode 100644 board/varisys/common/eeprom.h
 create mode 100644 board/varisys/common/sys_eeprom.c
 create mode 100644 board/varisys/cyrus/Kconfig
 create mode 100644 board/varisys/cyrus/Makefile
 create mode 100644 board/varisys/cyrus/README
 create mode 100644 board/varisys/cyrus/cyrus.c
 create mode 100644 board/varisys/cyrus/cyrus.h
 create mode 100644 board/varisys/cyrus/ddr.c
 create mode 100644 board/varisys/cyrus/eth.c
 create mode 100644 board/varisys/cyrus/law.c
 create mode 100644 board/varisys/cyrus/pbi.cfg
 create mode 100644 board/varisys/cyrus/pci.c
 create mode 100644 board/varisys/cyrus/rcw_p5020_v2.cfg
 create mode 100644 board/varisys/cyrus/rcw_p5040.cfg
 create mode 100644 board/varisys/cyrus/tlb.c
 create mode 100644 configs/Cyrus_P5020_defconfig
 create mode 100644 configs/Cyrus_P5040_defconfig
 create mode 100644 include/configs/cyrus.h

arch/powerpc/cpu/mpc85xx/Kconfig +4 -0

index ae0823a..0b89157 100644
@@ -149,6 +149,9 @@ config TARGET_XPEDITE550X
 config TARGET_UCP1020
 	bool "Support uCP1020"
 
+config TARGET_CYRUS
+	bool "Support Varisys Cyrus"
+
 endchoice
 
 source "board/freescale/b4860qds/Kconfig"

@@ -185,6 +188,7 @@ source "board/gdsys/p1022/Kconfig"
 source "board/keymile/kmp204x/Kconfig"
 source "board/sbc8548/Kconfig"
 source "board/socrates/Kconfig"
+source "board/varisys/cyrus/Kconfig"
 source "board/xes/xpedite520x/Kconfig"
 source "board/xes/xpedite537x/Kconfig"
 source "board/xes/xpedite550x/Kconfig"

board/varisys/common/Makefile new file +23 -0

new file mode 100644
index 0000000..1e6dcbb
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_ID_EEPROM)	+= sys_eeprom.o
+endif
+endif

board/varisys/common/eeprom.h new file +6 -0

new file mode 100644
index 0000000..004816a
@@ -0,0 +1,6 @@
+/* EEPROM init functions for Cyrus */
+
+
+void init_eeprom(int bus_num, int addr, int addr_len);
+void mac_read_from_fixed_id(void);
+int mac_read_from_eeprom_common(void);

board/varisys/common/sys_eeprom.c new file +500 -0

500 lines not on this page · raw message

board/varisys/cyrus/Kconfig new file +13 -0

new file mode 100644
index 0000000..bed6f4f
@@ -0,0 +1,13 @@
+if TARGET_CYRUS
+
+config SYS_BOARD
+	default "cyrus"
+
+config SYS_VENDOR
+	default "varisys"
+
+config SYS_CONFIG_NAME
+	default "cyrus"
+
+endif
+

board/varisys/cyrus/Makefile new file +8 -0

new file mode 100644
index 0000000..303fc42
@@ -0,0 +1,8 @@
+#
+
+obj-y	+= $(BOARD).o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+obj-y	+= eth.o
+obj-$(CONFIG_PCI) += pci.o

board/varisys/cyrus/README new file +21 -0

new file mode 100644
index 0000000..3f675ab
@@ -0,0 +1,21 @@
+Rebuilding u-boot for Cyrus
+
+The Cyrus defconfigs are Cyrus_P5020_defconfig and Cyrus_P5040_defconfig.
+
+They currently disable size optimization in order to avoid a relocation
+bug in some versions of GCC. As the output size is a constant, the size
+optimization is not currently important.
+
+Cyrus boots off a microSD card in a slot on the motherboard. This requires
+that the u-boot is built for the Pre-Boot Loader on the P5020/P5040.
+In order to reflash u-boot, you must download u-boot.pbl, then write it
+onto the card. To do that from u-boot:
+
+> tftp 1000000 u-boot.pbl
+> mmc write 1000000 8 672
+
+If you want to do this via a card reader in linux:
+
+> dd if=u-boot.pbl of=/dev/sdX bs=512 oseek=8
+
+

board/varisys/cyrus/cyrus.c new file +116 -0

116 lines not on this page · raw message

board/varisys/cyrus/cyrus.h new file +11 -0

new file mode 100644
index 0000000..8cd52ba
@@ -0,0 +1,11 @@
+/*
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CYRUS_H
+#define __CYRUS_H
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif

board/varisys/cyrus/ddr.c new file +188 -0

188 lines not on this page · raw message

board/varisys/cyrus/eth.c new file +100 -0

100 lines not on this page · raw message

board/varisys/cyrus/law.c new file +27 -0

new file mode 100644
index 0000000..91e1d85
@@ -0,0 +1,27 @@
+/*
+ * Author: Adrian Cox
+ * Based on corenet_ds law files.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_LBC0_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_LBC1_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

board/varisys/cyrus/pbi.cfg new file +35 -0

new file mode 100644
index 0000000..9b330dd
@@ -0,0 +1,35 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# Refer docs/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+# SPDX-License-Identifier:    GPL-2.0+
+#
+
+#PBI commands
+#Initialize CPC1 as 1MB SRAM
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+09010100 00000000
+09010104 fff0000b
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff00000
+09000d08 81000013
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000

board/varisys/cyrus/pci.c new file +23 -0

new file mode 100644
index 0000000..4780e8c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}

board/varisys/cyrus/rcw_p5020_v2.cfg new file +11 -0

new file mode 100644
index 0000000..9188080
@@ -0,0 +1,11 @@
+#
+# Default RCW for Cyrus P5020
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+0c540000 00000000 1e1e0000 00000000
+44808c00 ff002000 68000000 45000000
+00000000 00000000 00000000 0003000f
+a0000000 00000000 00000000 00000000

board/varisys/cyrus/rcw_p5040.cfg new file +11 -0

new file mode 100644
index 0000000..5284481
@@ -0,0 +1,11 @@
+#
+# Default RCW for Cyrus P5040
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+90e00000 00000000 acac9800 00440000
+44808c00 ff29a000 68000000 61000000
+00000000 00000000 00000000 0003000f
+a0000000 00000000 00000000 00000000

board/varisys/cyrus/tlb.c new file +106 -0

106 lines not on this page · raw message

configs/Cyrus_P5020_defconfig new file +9 -0

new file mode 100644
index 0000000..d9bee34
@@ -0,0 +1,9 @@
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_CYRUS=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/Cyrus_P5040_defconfig new file +9 -0

new file mode 100644
index 0000000..c66238a
@@ -0,0 +1,9 @@
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_CYRUS=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

include/configs/cyrus.h new file +588 -0

588 lines not on this page · raw message

Signature · 1 line

1.9.1

York Sun

2015-11-04 18:39 UTC #1 lore raw

PATCH v2 1/1 mpc85xx: Add support for the Varisys Cyrus board

Quoted 11 lines · Andy Fleming

This board runs a P5020 or P5040 chip, and utilizes an EEPROM with similar formatting to the Freescale P5020DS.
Large amounts of this code were developed by
Adrian Cox <adrian@humboldt dot co dot uk>
Signed-off-by Andy Fleming <[email protected]>
---
v2:
* Cleaned up sys_eeprom.c
* Removed CONFIG_CMD_ELF, CONFIG_SYS_GENERIC_BOARD

Why do you want to remove CONFIG_SYS_GENERIC_BOARD? We are dropping non-generic board.

Quoted 33 lines

 arch/powerpc/cpu/mpc85xx/Kconfig     |   4 +
 board/varisys/common/Makefile        |  23 ++
 board/varisys/common/eeprom.h        |   6 +
 board/varisys/common/sys_eeprom.c    | 500 +++++++++++++++++++++++++++++
 board/varisys/cyrus/Kconfig          |  13 +
 board/varisys/cyrus/Makefile         |   8 +
 board/varisys/cyrus/README           |  21 ++
 board/varisys/cyrus/cyrus.c          | 116 +++++++
 board/varisys/cyrus/cyrus.h          |  11 +
 board/varisys/cyrus/ddr.c            | 188 +++++++++++
 board/varisys/cyrus/eth.c            | 100 ++++++
 board/varisys/cyrus/law.c            |  27 ++
 board/varisys/cyrus/pbi.cfg          |  35 +++
 board/varisys/cyrus/pci.c            |  23 ++
 board/varisys/cyrus/rcw_p5020_v2.cfg |  11 +
 board/varisys/cyrus/rcw_p5040.cfg    |  11 +
 board/varisys/cyrus/tlb.c            | 106 +++++++
 configs/Cyrus_P5020_defconfig        |   9 +
 configs/Cyrus_P5040_defconfig        |   9 +
 include/configs/cyrus.h              | 588 +++++++++++++++++++++++++++++++++++
 20 files changed, 1809 insertions(+)
 create mode 100644 board/varisys/common/Makefile
 create mode 100644 board/varisys/common/eeprom.h
 create mode 100644 board/varisys/common/sys_eeprom.c
 create mode 100644 board/varisys/cyrus/Kconfig
 create mode 100644 board/varisys/cyrus/Makefile
 create mode 100644 board/varisys/cyrus/README
 create mode 100644 board/varisys/cyrus/cyrus.c
 create mode 100644 board/varisys/cyrus/cyrus.h
 create mode 100644 board/varisys/cyrus/ddr.c
 create mode 100644 board/varisys/cyrus/eth.c
 create mode 100644 board/varisys/cyrus/law.c

Quoted 8 lines

 create mode 100644 board/varisys/cyrus/pbi.cfg
 create mode 100644 board/varisys/cyrus/pci.c
 create mode 100644 board/varisys/cyrus/rcw_p5020_v2.cfg
 create mode 100644 board/varisys/cyrus/rcw_p5040.cfg
 create mode 100644 board/varisys/cyrus/tlb.c
 create mode 100644 configs/Cyrus_P5020_defconfig
 create mode 100644 configs/Cyrus_P5040_defconfig
 create mode 100644 include/configs/cyrus.h

Please add MAINTAINERS file.

<snip>

Quoted 30 lines

board/varisys/common/sys_eeprom.c new file +24 -0

new file mode 100644
index 0000000..086fad2
@@ -0,0 +1,500 @@
+/*
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun at freescale.com)
+ * Haiying Wang (haiying.wang at freescale.com)
+ * Timur Tabi (timur at freescale.com)
+ *
+ * This defines the API for storing board information in the
+ * eeprom. It has been adapted from an earlier version of the
+ * Freescale code for doing the same thing. Therefore it is
+ * nearly identical to the Freescale code, but is intended for
+ * use with Varisys-produced boards.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#include "eeprom.h"
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID_MAC
+#define MAX_NUM_PORTS	CONFIG_SYS_I2C_EEPROM_NXID_MAC

board/varisys/common/sys_eeprom.c line 34

Quoted 10 lines

board/varisys/common/sys_eeprom.c new file +10 -0

+#else
+#define MAX_NUM_PORTS	8
+#endif
+#define NXID_VERSION	0
+
+/**
+ * static eeprom: EEPROM layout for NXID formats
+ *
+ * See Freescale application note AN3638 for details.
+ */

This comment and file header still implies this file follows Freescale EEPROM spec. I think additional comment is needed to state the difference.

There are several blank lines added to the end of files.

York

Andy Fleming

author

2015-11-04 19:05 UTC #2 lore raw

PATCH v2 1/1 mpc85xx: Add support for the Varisys Cyrus board

Quoted 9 lines · York Sun

Quoted 6 lines · Andy Fleming
This board runs a P5020 or P5040 chip, and utilizes an EEPROM with similar formatting to the Freescale P5020DS.
Large amounts of this code were developed by
Adrian Cox <adrian@humboldt dot co dot uk>

Quoted 8 lines

Quoted 5 lines
Signed-off-by Andy Fleming <[email protected]>
---
v2:
* Cleaned up sys_eeprom.c
* Removed CONFIG_CMD_ELF, CONFIG_SYS_GENERIC_BOARD
Why do you want to remove CONFIG_SYS_GENERIC_BOARD? We are dropping non-generic board.

Sorry, my comment was misleading. I didn't disable CONFIG_SYS_GENERIC_BOARD. I removed it from the config file because this patch made it the default:

commit 09f3ca3dd53b671b009ddc4e1dad669c280094f0

Author: Masahiro Yamada <[email protected]>
Date:   Tue Oct 20 21:09:06 2015 +0900

arm, powerpc: select SYS_GENERIC_BOARD

Otherwise, u-boot doesn't build. Same thing is true for CONFIG_CMD_ELF. Didn't disable it, just deleted the redundant config.

Quoted 43 lines

Quoted 34 lines


 arch/powerpc/cpu/mpc85xx/Kconfig     |   4 +
 board/varisys/common/Makefile        |  23 ++
 board/varisys/common/eeprom.h        |   6 +
 board/varisys/common/sys_eeprom.c    | 500 +++++++++++++++++++++++++++++
 board/varisys/cyrus/Kconfig          |  13 +
 board/varisys/cyrus/Makefile         |   8 +
 board/varisys/cyrus/README           |  21 ++
 board/varisys/cyrus/cyrus.c          | 116 +++++++
 board/varisys/cyrus/cyrus.h          |  11 +
 board/varisys/cyrus/ddr.c            | 188 +++++++++++
 board/varisys/cyrus/eth.c            | 100 ++++++
 board/varisys/cyrus/law.c            |  27 ++
 board/varisys/cyrus/pbi.cfg          |  35 +++
 board/varisys/cyrus/pci.c            |  23 ++
 board/varisys/cyrus/rcw_p5020_v2.cfg |  11 +
 board/varisys/cyrus/rcw_p5040.cfg    |  11 +
 board/varisys/cyrus/tlb.c            | 106 +++++++
 configs/Cyrus_P5020_defconfig        |   9 +
 configs/Cyrus_P5040_defconfig        |   9 +
 include/configs/cyrus.h              | 588 +++++++++++++++++++++++++++++++++++
 20 files changed, 1809 insertions(+)
 create mode 100644 board/varisys/common/Makefile
 create mode 100644 board/varisys/common/eeprom.h
 create mode 100644 board/varisys/common/sys_eeprom.c
 create mode 100644 board/varisys/cyrus/Kconfig
 create mode 100644 board/varisys/cyrus/Makefile
 create mode 100644 board/varisys/cyrus/README
 create mode 100644 board/varisys/cyrus/cyrus.c
 create mode 100644 board/varisys/cyrus/cyrus.h
 create mode 100644 board/varisys/cyrus/ddr.c
 create mode 100644 board/varisys/cyrus/eth.c
 create mode 100644 board/varisys/cyrus/law.c

Quoted 8 lines

 create mode 100644 board/varisys/cyrus/pbi.cfg
 create mode 100644 board/varisys/cyrus/pci.c
 create mode 100644 board/varisys/cyrus/rcw_p5020_v2.cfg
 create mode 100644 board/varisys/cyrus/rcw_p5040.cfg
 create mode 100644 board/varisys/cyrus/tlb.c
 create mode 100644 configs/Cyrus_P5020_defconfig
 create mode 100644 configs/Cyrus_P5040_defconfig
 create mode 100644 include/configs/cyrus.h

Quoted 1 line

Please add MAINTAINERS file.

Will do.

Quoted 47 lines

<snip>

Quoted 30 lines

board/varisys/common/sys_eeprom.c new file +24 -0

new file mode 100644
index 0000000..086fad2
@@ -0,0 +1,500 @@
+/*
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun at freescale.com)
+ * Haiying Wang (haiying.wang at freescale.com)
+ * Timur Tabi (timur at freescale.com)
+ *
+ * This defines the API for storing board information in the
+ * eeprom. It has been adapted from an earlier version of the
+ * Freescale code for doing the same thing. Therefore it is
+ * nearly identical to the Freescale code, but is intended for
+ * use with Varisys-produced boards.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#include "eeprom.h"
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID_MAC
+#define MAX_NUM_PORTS        CONFIG_SYS_I2C_EEPROM_NXID_MAC

board/varisys/common/sys_eeprom.c line 34

Quoted 10 lines

board/varisys/common/sys_eeprom.c new file +10 -0

+#else
+#define MAX_NUM_PORTS        8
+#endif
+#define NXID_VERSION 0
+
+/**
+ * static eeprom: EEPROM layout for NXID formats
+ *
+ * See Freescale application note AN3638 for details.
+ */

This comment and file header still implies this file follows Freescale EEPROM spec. I think additional comment is needed to state the difference.

Quoted 1 line

There are several blank lines added to the end of files.

I'll fix these and send a new version today.

Andy