dm: timer: x86: 64-bit counter support and tsc timer dm conversion
Subsystems (2)
cover dm: timer: x86: 64-bit counter support and tsc timer dm conversion
This series enhances timer uclass driver to support 64-bit counter value, and convert tsc timer to driver model to be used by all x86 boards.
As a result of dm conversion, the TSC_CALIBRATION_BYPASS Kconfig option is no longer needed, and the TSC frequency can be specified in the board device tree.
Bin Meng (10):
dm: timer: Fix several nits
dm: timer: Implement pre_probe()
timer: altera: Remove the codes to get clock frequency
dm: timer: Support 64-bit counter
x86: Reomve MIN_PORT80_KCLOCKS_DELAY
x86: tsc: Use notrace from <linux/compiler.h>
x86: tsc: Add driver model timer support
x86: Convert to use driver model timer
x86: tsc: Remove legacy timer codes
x86: tsc: Move tsc_timer.c to drivers/timer
arch/x86/Kconfig | 20 ------
arch/x86/cpu/baytrail/valleyview.c | 3 -
arch/x86/cpu/coreboot/timestamp.c | 22 ------
arch/x86/cpu/cpu.c | 18 -----
arch/x86/cpu/efi/efi.c | 4 --
arch/x86/cpu/ivybridge/cpu.c | 1 -
arch/x86/cpu/qemu/Kconfig | 1 -
arch/x86/cpu/qemu/qemu.c | 3 -
arch/x86/cpu/quark/Kconfig | 5 --
arch/x86/cpu/quark/quark.c | 3 -
arch/x86/cpu/queensbay/tnc.c | 3 -
arch/x86/dts/bayleybay.dts | 1 +
arch/x86/dts/broadwell_som-6896.dts | 1 +
arch/x86/dts/chromebook_link.dts | 1 +
arch/x86/dts/chromebox_panther.dts | 1 +
arch/x86/dts/crownbay.dts | 1 +
arch/x86/dts/efi.dts | 5 ++
arch/x86/dts/galileo.dts | 5 ++
arch/x86/dts/minnowmax.dts | 1 +
arch/x86/dts/qemu-x86_i440fx.dts | 5 ++
arch/x86/dts/qemu-x86_q35.dts | 5 ++
arch/x86/dts/tsc_timer.dtsi | 7 ++
arch/x86/include/asm/global_data.h | 3 -
arch/x86/lib/Makefile | 1 -
configs/bayleybay_defconfig | 1 +
configs/chromebook_link_defconfig | 2 +-
configs/chromebox_panther_defconfig | 2 +-
configs/coreboot-x86_defconfig | 3 +-
configs/crownbay_defconfig | 1 +
configs/efi-x86_defconfig | 2 +-
configs/galileo_defconfig | 1 +
configs/minnowmax_defconfig | 1 +
configs/qemu-x86_defconfig | 1 +
drivers/timer/Kconfig | 17 +++--
drivers/timer/Makefile | 1 +
drivers/timer/altera_timer.c | 8 +--
drivers/timer/timer-uclass.c | 43 ++++++++++--
{arch/x86/lib => drivers/timer}/tsc_timer.c | 104 ++++++++++++++++------------
include/configs/x86-common.h | 2 -
include/timer.h | 17 +++--
lib/time.c | 9 ++-
41 files changed, 168 insertions(+), 167 deletions(-)
create mode 100644 arch/x86/dts/tsc_timer.dtsi
rename {arch/x86/lib => drivers/timer}/tsc_timer.c (87%)Signature · 1 line
1.8.2.1
PATCH 1/10 dm: timer: Fix several nits
This changes 'Timer' to 'timer' at several places.
Signed-off-by Bin Meng <[email protected]>
---
drivers/timer/Kconfig | 10 +++++----- drivers/timer/timer-uclass.c | 4 ++-- include/timer.h | 11 ++++++----- 3 files changed, 13 insertions(+), 12 deletions(-)
drivers/timer/Kconfig +5 -5
@@ -1,19 +1,19 @@ menu "Timer Support" config TIMER - bool "Enable Driver Model for Timer drivers" + bool "Enable driver model for timer drivers" depends on DM help - Enable driver model for Timer access. It uses the same API as - lib/time.c. But now implemented by the uclass. The first timer + Enable driver model for timer access. It uses the same API as + lib/time.c, but now implemented by the uclass. The first timer will be used. The timer is usually a 32 bits free-running up counter. There may be no real tick, and no timer interrupt. config ALTERA_TIMER - bool "Altera Timer support" + bool "Altera timer support" depends on TIMER help - Select this to enable an timer for Altera devices. Please find + Select this to enable a timer for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. endmenu
drivers/timer/timer-uclass.c +2 -2
@@ -10,10 +10,10 @@#include <timer.h> /* -* Implement a Timer uclass to work with lib/time.c. The timer is usually +* Implement a timer uclass to work with lib/time.c. The timer is usually * a 32 bits free-running up counter. The get_rate() method is used to get * the input clock frequency of the timer. The get_count() method is used -* get the current 32 bits count value. If the hardware is counting down, +* to get the current 32 bits count value. If the hardware is counting down, * the value should be inversed inside the method. There may be no real * tick, and no timer interrupt. */
include/timer.h +6 -5
@@ -10,30 +10,31 @@/* * Get the current timer count * -* @dev: The Timer device +* @dev: The timer device * @count: pointer that returns the current timer count * @return: 0 if OK, -ve on error */ int timer_get_count (struct udevice *dev,unsigned long *count); +/* * Get the timer input clock frequency * -* @dev: The Timer device +* @dev: The timer device * @return: the timer input clock frequency */ unsigned long timer_get_rate (struct udevice *dev);/* -* struct timer_ops - Driver model Timer operations +* struct timer_ops - Driver model timer operations * -* The uclass interface is implemented by all Timer devices which use +* The uclass interface is implemented by all timer devices which use * driver model. */ struct timer_ops {/* * Get the current timer count * -* @dev: The Timer device +* @dev: The timer device * @count: pointer that returns the current timer count * @return: 0 if OK, -ve on error */
Signature · 1 line
1.8.2.1
PATCH 1/10 dm: timer: Fix several nits
Hi Bin,
Quoted 88 lines · Bin Meng
This changes 'Timer' to 'timer' at several places.
Signed-off-by Bin Meng <[email protected]>---
drivers/timer/Kconfig | 10 +++++----- drivers/timer/timer-uclass.c | 4 ++-- include/timer.h | 11 ++++++----- 3 files changed, 13 insertions(+), 12 deletions(-)drivers/timer/Kconfig +5
-5@@ -1,19 +1,19 @@ menu "Timer Support" config TIMER - bool "Enable Driver Model for Timer drivers" + bool "Enable driver model for timer drivers" depends on DM help - Enable driver model for Timer access. It uses the same API as - lib/time.c. But now implemented by the uclass. The first timer + Enable driver model for timer access. It uses the same API as + lib/time.c, but now implemented by the uclass. The first timer will be used. The timer is usually a 32 bits free-running up counter. There may be no real tick, and no timer interrupt. config ALTERA_TIMER - bool "Altera Timer support" + bool "Altera timer support" depends on TIMER help - Select this to enable an timer for Altera devices. Please find + Select this to enable a timer for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. endmenudrivers/timer/timer-uclass.c +2
-2@@ -10,10 +10,10 @@#include <timer.h> /* -* Implement a Timer uclass to work with lib/time.c. The timer is usually +* Implement a timer uclass to work with lib/time.c. The timer is usually * a 32 bits free-running up counter. The get_rate() method is used to get * the input clock frequency of the timer. The get_count() method is used -* get the current 32 bits count value. If the hardware is counting down, +* to get the current 32 bits count value. If the hardware is counting down, * the value should be inversed inside the method. There may be no real * tick, and no timer interrupt. */ include/timer.h +5
-4@@ -10,30 +10,31 @@/* * Get the current timer count * -* @dev: The Timer device +* @dev: The timer device * @count: pointer that returns the current timer count * @return: 0 if OK, -ve on error */ int timer_get_count (struct udevice *dev,unsigned long *count); +/* * Get the timer input clock frequency * -* @dev: The Timer device +* @dev: The timer device * @return: the timer input clock frequency */ unsigned long timer_get_rate (struct udevice *dev);/* -* struct timer_ops - Driver model Timer operations +* struct timer_ops - Driver model timer operations * -* The uclass interface is implemented by all Timer devices which use +* The uclass interface is implemented by all timer devices which use * driver model.
include/timer.h line 40
Quoted 10 lines
include/timer.h +1
-1*/ struct timer_ops {/* * Get the current timer count * -* @dev: The Timer device +* @dev: The timer device * @count: pointer that returns the current timer count * @return: 0 if OK, -ve on error */
Thanks. Might need rebase after nios2 timer cleaned up and sandbox timer added. Otherwise,
PATCH 1/10 dm: timer: Fix several nits
Quoted 15 lines · Thomas Chou
Hi Bin,
Quoted 11 lines · Bin Meng
This changes 'Timer' to 'timer' at several places.
Signed-off-by Bin Meng <[email protected]>---
drivers/timer/Kconfig | 10 +++++----- drivers/timer/timer-uclass.c | 4 ++-- include/timer.h | 11 ++++++----- 3 files changed, 13 insertions(+), 12 deletions(-)
Reviewed-by Simon Glass <[email protected]>
PATCH 2/10 dm: timer: Implement pre_probe()
In reply to Bin MengEvery timer device needs to have a valid clock frequency and it can be specified in the device tree. Use pre_probe() to get this in the timer uclass driver.
Signed-off-by Bin Meng <[email protected]>
---
drivers/timer/timer-uclass.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
drivers/timer/timer-uclass.c +13 -0
@@ -9,6 +9,8 @@#include <errno.h> #include <timer.h> +DECLARE_GLOBAL_DATA_PTR ; +/* * Implement a timer uclass to work with lib/time.c. The timer is usually * a 32 bits free-running up counter. The get_rate() method is used to get
@@ -35,8 +37,19 @@ unsigned long timer_get_rate(struct udevice *dev)return uc_priv->clock_rate; } +static int timer_pre_probe (struct udevice *dev) +{ +struct timer_dev_priv *uc_priv =dev_get_uclass_priv (dev); + + uc_priv->clock_rate =fdtdec_get_int (gd->fdt_blob, dev->of_offset, +"clock-frequency" ,0 ); + +return 0 ; +} +UCLASS_DRIVER (timer) = { .id =UCLASS_TIMER , .name ="timer" , + .pre_probe = timer_pre_probe, .per_device_auto_alloc_size =sizeof (struct timer_dev_priv ), };
Signature · 1 line
1.8.2.1
PATCH 2/10 dm: timer: Implement pre_probe()
Hi Bin,
Quoted 34 lines · Bin Meng
Every timer device needs to have a valid clock frequency and it can be specified in the device tree. Use
pre_probe()to get this in the timer uclass driver.Signed-off-by Bin Meng <[email protected]>---
drivers/timer/timer-uclass.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)drivers/timer/timer-uclass.c +8
-0@@ -9,6 +9,8 @@#include <errno.h> #include <timer.h> +DECLARE_GLOBAL_DATA_PTR ; +/* * Implement a timer uclass to work with lib/time.c. The timer is usually * a 32 bits free-running up counter. The get_rate() method is used to get @@ -35,8 +37,19 @@ unsigned long timer_get_rate(struct udevice *dev)return uc_priv->clock_rate; } +static int timer_pre_probe (struct udevice *dev) +{ +struct timer_dev_priv *uc_priv =dev_get_uclass_priv (dev); + + uc_priv->clock_rate =fdtdec_get_int (gd->fdt_blob, dev->of_offset, +"clock-frequency" ,0 );
drivers/timer/timer-uclass.c unsigned long timer_get_rate(struct udevice *dev) · line 55
Quoted 10 lines
drivers/timer/timer-uclass.c +5
-0+ +return 0 ; +} +UCLASS_DRIVER (timer) = { .id =UCLASS_TIMER , .name ="timer" , + .pre_probe = timer_pre_probe, .per_device_auto_alloc_size =sizeof (struct timer_dev_priv ), };
Acked-by Thomas Chou <[email protected]>
PATCH 2/10 dm: timer: Implement pre_probe()
Quoted 14 lines · Thomas Chou
Hi Bin,
Quoted 10 lines · Bin Meng
Every timer device needs to have a valid clock frequency and it can be specified in the device tree. Use
pre_probe()to get this in the timer uclass driver.Signed-off-by Bin Meng <[email protected]>---
drivers/timer/timer-uclass.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
Acked-by Simon Glass <[email protected]>
PATCH 3/10 timer: altera: Remove the codes to get clock frequency
In reply to Bin MengSince we have timer uclass to get clock frequency for us, remove the custom version in the altera timer driver.
Signed-off-by Bin Meng <[email protected]>
---
drivers/timer/altera_timer.c | 6 ------ 1 file changed, 6 deletions(-)
drivers/timer/altera_timer.c +0 -6
@@ -27,7 +27,6 @@ struct altera_timer_regs {struct altera_timer_platdata {struct altera_timer_regs *regs; -unsigned long clock_rate; };/* control register */
@@ -54,12 +53,9 @@ static int altera_timer_get_count(struct udevice *dev, unsigned long *count)static int altera_timer_probe (struct udevice *dev) { -struct timer_dev_priv *uc_priv =dev_get_uclass_priv (dev);struct altera_timer_platdata *plat = dev->platdata;struct altera_timer_regs *const regs = plat->regs; - uc_priv->clock_rate = plat->clock_rate; -writel (0 , ®s->status);writel (0 , ®s->control);writel (ALTERA_TIMER_STOP , ®s->control);
@@ -77,8 +73,6 @@ static int altera_timer_ofdata_to_platdata(struct udevice *dev) plat->regs =ioremap (dev_get_addr (dev),sizeof (struct altera_timer_regs )); - plat->clock_rate =fdtdec_get_int (gd->fdt_blob, dev->of_offset, -"clock-frequency" ,0 );return 0 ; }
Signature · 1 line
1.8.2.1
PATCH 3/10 timer: altera: Remove the codes to get clock frequency
Hi Bin,
Quoted 36 lines · Bin Meng
Since we have timer uclass to get clock frequency for us, remove the custom version in the altera timer driver.
Signed-off-by Bin Meng <[email protected]>---
drivers/timer/altera_timer.c | 6 ------ 1 file changed, 6 deletions(-)drivers/timer/altera_timer.c +0
-4@@ -27,7 +27,6 @@ struct altera_timer_regs {struct altera_timer_platdata {struct altera_timer_regs *regs; -unsigned long clock_rate; };/* control register */ @@ -54,12 +53,9 @@ static int altera_timer_get_count(struct udevice *dev, unsigned long *count)static int altera_timer_probe (struct udevice *dev) { -struct timer_dev_priv *uc_priv =dev_get_uclass_priv (dev);struct altera_timer_platdata *plat = dev->platdata;struct altera_timer_regs *const regs = plat->regs; - uc_priv->clock_rate = plat->clock_rate; -writel (0 , ®s->status);writel (0 , ®s->control);writel (ALTERA_TIMER_STOP , ®s->control);
drivers/timer/altera_timer.c static int altera_timer_ofdata_to_platdata(struct udevice *dev) · line 78
Quoted 8 lines
drivers/timer/altera_timer.c +0
-2@@ -77,8 +73,6 @@ static int altera_timer_ofdata_to_platdata(struct udevice *dev) plat->regs =ioremap (dev_get_addr (dev),sizeof (struct altera_timer_regs )); - plat->clock_rate =fdtdec_get_int (gd->fdt_blob, dev->of_offset, -"clock-frequency" ,0 );return 0 ; }
Acked-by Thomas Chou <[email protected]>
PATCH 3/10 timer: altera: Remove the codes to get clock frequency
Quoted 13 lines · Thomas Chou
Hi Bin,
Quoted 9 lines · Bin Meng
Since we have timer uclass to get clock frequency for us, remove the custom version in the altera timer driver.
Signed-off-by Bin Meng <[email protected]>---
drivers/timer/altera_timer.c | 6 ------ 1 file changed, 6 deletions(-)
Acked-by Simon Glass <[email protected]>
PATCH 4/10 dm: timer: Support 64-bit counter
In reply to Bin MengThere are timers with a 64-bit counter value but current timer uclass driver assumes a 32-bit one. Introduce a device tree property "counter-64bit", and modify timer_get_count() in the timer uclass driver to handle the 32-bit/64-bit conversion automatically.
Signed-off-by Bin Meng <[email protected]>
---
drivers/timer/altera_timer.c | 2 +- drivers/timer/timer-uclass.c | 28 ++++++++++++++++++++++++---- include/timer.h | 6 ++++-- lib/time.c | 9 ++++++--- 4 files changed, 35 insertions(+), 10 deletions(-)
drivers/timer/altera_timer.c +1 -1
@@ -34,7 +34,7 @@ struct altera_timer_platdata {#define ALTERA_TIMER_START (1 << 2)/* Start timer */ #define ALTERA_TIMER_STOP (1 << 3)/* Stop timer */ -static int altera_timer_get_count (struct udevice *dev,unsigned long *count) +static int altera_timer_get_count (struct udevice *dev,u64 *count) {struct altera_timer_platdata *plat = dev->platdata;struct altera_timer_regs *const regs = plat->regs;
drivers/timer/timer-uclass.c +24 -4
@@ -13,21 +13,39 @@ DECLARE_GLOBAL_DATA_PTR;/* * Implement a timer uclass to work with lib/time.c. The timer is usually -* a 32 bits free-running up counter. The get_rate() method is used to get +* a 32/64 bits free-running up counter. The get_rate() method is used to get * the input clock frequency of the timer. The get_count() method is used -* to get the current 32 bits count value. If the hardware is counting down, +* to get the current 32/64 bits count value. If the hardware is counting down, * the value should be inversed inside the method. There may be no real * tick, and no timer interrupt. */ -int timer_get_count (struct udevice *dev,unsigned long *count) +int timer_get_count (struct udevice *dev,u64 *count) {const struct timer_ops *ops =device_get_ops (dev); +struct timer_dev_priv *uc_priv =dev_get_uclass_priv (dev); +u32 now; +int ret;if (!ops->get_count)return -ENOSYS ; -return ops->get_count (dev, count); +if (uc_priv->counter_64) { +return ops->get_count (dev, count); + }else { + ret = ops->get_count (dev, count); +if (ret) +return ret; + + now = *count; +/* increment tbh if tbl has rolled over */ +if (now < gd->timebase_l) + gd->timebase_h++; + gd->timebase_l = now; + *count = ((u64 )gd->timebase_h <<32 ) | gd->timebase_l; + +return 0 ; + } }unsigned long timer_get_rate (struct udevice *dev)
@@ -43,6 +61,8 @@ static int timer_pre_probe(struct udevice *dev) uc_priv->clock_rate =fdtdec_get_int (gd->fdt_blob, dev->of_offset,"clock-frequency" ,0 ); + uc_priv->counter_64 =fdtdec_get_bool (gd->fdt_blob, dev->of_offset, +"counter-64bit" );return 0 ; }
include/timer.h +4 -2
@@ -14,7 +14,7 @@* @count: pointer that returns the current timer count * @return: 0 if OK, -ve on error */ -int timer_get_count (struct udevice *dev,unsigned long *count); +int timer_get_count (struct udevice *dev,u64 *count);/* * Get the timer input clock frequency
@@ -38,16 +38,18 @@ struct timer_ops {* @count: pointer that returns the current timer count * @return: 0 if OK, -ve on error */ - int (*get_count)(struct udevice *dev, unsigned long *count); + int (*get_count)(struct udevice *dev, u64 *count); };/* * struct timer_dev_priv - information about a device used by the uclass * * @clock_rate: the timer input clock frequency +* @counter_64: the timer counter is a 64-bit value or not */ struct timer_dev_priv {unsigned long clock_rate; +bool counter_64; };#endif /* _TIMER_H_ */
lib/time.c +6 -3
@@ -69,9 +69,9 @@ ulong notrace get_tbclk(void)return timer_get_rate (gd->timer); } -unsigned long notrace timer_read_counter (void ) +uint64_t notrace get_ticks(void) { -unsigned long count; +u64 count;int ret; ret =dm_timer_init ();
@@ -84,7 +84,8 @@ unsigned long notrace timer_read_counter(void)return count; } -#endif /* CONFIG_TIMER */ + +#else /* !CONFIG_TIMER */ uint64_t __weak notrace get_ticks(void) {
@@ -97,6 +98,8 @@ uint64_t __weak notrace get_ticks(void)return ((uint64_t )gd->timebase_h <<32 ) | gd->timebase_l; } +#endif /* CONFIG_TIMER */ +/* Returns time in milliseconds */ static uint64_t notrace tick_to_time(uint64_t tick) {
Signature · 1 line
1.8.2.1
PATCH 4/10 dm: timer: Support 64-bit counter
Hi Bin,
Quoted 8 lines · Bin Meng
There are timers with a 64-bit counter value but current timer uclass driver assumes a 32-bit one. Introduce a device tree property "counter-64bit", and modify
timer_get_count()in the timer uclass driver to handle the 32-bit/64-bit conversion automatically.Signed-off-by Bin Meng <[email protected]>---
Thanks a lot. I tested patches [1-4] on nios2 boards with "ut time" and "sleep". It works fine.
I would suggest that we do not need the additional "counter-64bit" property by requiring the timer always return 64 bits count. We can provide an inline func to do the 32/64 conversion for all 32 bits timers.
Best regards,
Thomas
PATCH 4/10 dm: timer: Support 64-bit counter
Hi Thomas,
Quoted 14 lines · Thomas Chou
Hi Bin,
Quoted 9 lines · Bin Meng
There are timers with a 64-bit counter value but current timer uclass driver assumes a 32-bit one. Introduce a device tree property "counter-64bit", and modify
timer_get_count()in the timer uclass driver to handle the 32-bit/64-bit conversion automatically.Signed-off-by Bin Meng <[email protected]>---
Quoted 7 lines
Thanks a lot. I tested patches [1-4] on nios2 boards with "ut time" and "sleep". It works fine.
I would suggest that we do not need the additional "counter-64bit" property by requiring the timer always return 64 bits count. We can provide an inline func to do the 32/64 conversion for all 32 bits timers.
Do you mean we move the following codes:
+ /* increment tbh if tbl has rolled over */
+ if (now < gd->timebase_l)
+ gd->timebase_h++;
+ gd->timebase_l = now;
+ *count = ((u64)gd->timebase_h << 32) | gd->timebase_l;
to an inline function, to have 32-bit timer driver to call this inline function in their get_count() op?
This looks duplicate to me.
Regards,
Bin
PATCH 4/10 dm: timer: Support 64-bit counter
Hi Bin,
Quoted 33 lines · Bin Meng
Hi Thomas,
Quoted 14 lines · Thomas Chou
Hi Bin,
Quoted 9 lines · Bin Meng
There are timers with a 64-bit counter value but current timer uclass driver assumes a 32-bit one. Introduce a device tree property "counter-64bit", and modify
timer_get_count()in the timer uclass driver to handle the 32-bit/64-bit conversion automatically.Signed-off-by Bin Meng <[email protected]>---
Quoted 7 lines
Thanks a lot. I tested patches [1-4] on nios2 boards with "ut time" and "sleep". It works fine.
I would suggest that we do not need the additional "counter-64bit" property by requiring the timer always return 64 bits count. We can provide an inline func to do the 32/64 conversion for all 32 bits timers.
Do you mean we move the following codes:
drivers/timer/timer-uclass.c +5
-0+/* increment tbh if tbl has rolled over */ +if (now < gd->timebase_l) + gd->timebase_h++; + gd->timebase_l = now; + *count = ((u64 )gd->timebase_h <<32 ) | gd->timebase_l;
Quoted 4 lines
to an inline function, to have 32-bit timer driver to call this inline function in their
get_count()op?This looks duplicate to me.
Yes. If we want to support 64 bits count, it should be the driver's responsibility to return 64 bits count. It would be more natural than adding a property to tell the uclass to to the conversion. The "duplicate" you mentioned could be an alternative to the "counter-64bit" addition. I believe 64 bits hardware counter will become more popular in the future.
Best regards,
Thomas
PATCH 4/10 dm: timer: Support 64-bit counter
Hi Thomas,
Quoted 46 lines · Thomas Chou
Hi Bin,
Quoted 42 lines · Bin Meng
Hi Thomas,
Quoted 17 lines · Thomas Chou
Hi Bin,
Quoted 10 lines · Bin Meng
There are timers with a 64-bit counter value but current timer uclass driver assumes a 32-bit one. Introduce a device tree property "counter-64bit", and modify
timer_get_count()in the timer uclass driver to handle the 32-bit/64-bit conversion automatically.Signed-off-by Bin Meng <[email protected]>---
Quoted 9 lines
Thanks a lot. I tested patches [1-4] on nios2 boards with "ut time" and "sleep". It works fine.
I would suggest that we do not need the additional "counter-64bit" property
by requiring the timer always return 64 bits count. We can provide an inline
func to do the 32/64 conversion for all 32 bits timers.Do you mean we move the following codes:
drivers/timer/timer-uclass.c +5
-0+/* increment tbh if tbl has rolled over */ +if (now < gd->timebase_l) + gd->timebase_h++; + gd->timebase_l = now; + *count = ((u64 )gd->timebase_h <<32 ) | gd->timebase_l;to an inline function, to have 32-bit timer driver to call this inline function in their
get_count()op?
Quoted 9 lines
Quoted 1 line
This looks duplicate to me.
Yes. If we want to support 64 bits count, it should be the driver's responsibility to return 64 bits count. It would be more natural than adding a property to tell the uclass to to the conversion. The "duplicate" you mentioned could be an alternative to the "counter-64bit" addition. I believe 64 bits hardware counter will become more popular in the future.
OK, will do in v2 and rebase on top of sandbox timer patches.
Regards,
Bin
PATCH 5/10 x86: Reomve MIN_PORT80_KCLOCKS_DELAY
In reply to Bin MengThis is not referenced anywhere. Remove it, as well as tsc_base_kclocks and tsc_prev in the global data.
Signed-off-by Bin Meng <[email protected]>
---
arch/x86/cpu/cpu.c | 18 ------------------ arch/x86/include/asm/global_data.h | 2 -- 2 files changed, 20 deletions(-)
arch/x86/cpu/cpu.c +0 -18
@@ -641,24 +641,6 @@ int cpu_jump_to_64bit(ulong setup_base, ulong target)void show_boot_progress (int val) { -#if MIN_PORT80_KCLOCKS_DELAY -/* -* Scale the time counter reading to avoid using 64 bit arithmetics. -* Can't use get_timer() here becuase it could be not yet -* initialized or even implemented. -*/ -if (!gd->arch.tsc_prev) { - gd->arch.tsc_base_kclocks =rdtsc () /1000 ; - gd->arch.tsc_prev =0 ; - }else { -uint32_t now; - -do { - now =rdtsc () /1000 - gd->arch.tsc_base_kclocks; - }while (now < (gd->arch.tsc_prev +MIN_PORT80_KCLOCKS_DELAY )); - gd->arch.tsc_prev = now; - } -#endif outb (val,POST_PORT ); }
arch/x86/include/asm/global_data.h +0 -2
@@ -54,8 +54,6 @@ struct arch_global_data {uint8_t x86_mask;uint32_t x86_device;uint64_t tsc_base;/* Initial value returned by rdtsc() */ -uint32_t tsc_base_kclocks;/* Initial tsc as a kclocks value */ -uint32_t tsc_prev;/* For show_boot_progress() */ uint32_t tsc_mhz;/* TSC frequency in MHz */ void *new_fdt;/* Relocated FDT */ uint32_t bist;/* Built-in self test value */
Signature · 1 line
1.8.2.1
PATCH 5/10 x86: Reomve MIN_PORT80_KCLOCKS_DELAY
Quoted 9 lines · Bin Meng
This is not referenced anywhere. Remove it, as well as
tsc_base_kclocksandtsc_previn the global data.Signed-off-by Bin Meng <[email protected]>---
arch/x86/cpu/cpu.c | 18 ------------------ arch/x86/include/asm/global_data.h | 2 -- 2 files changed, 20 deletions(-)
Acked-by Simon Glass <[email protected]>
PATCH 6/10 x86: tsc: Use notrace from <linux/compiler.h>
In reply to Bin MengReplace __attribute__((no_instrument_function)) with notrace from <linux/compiler.h>.
Signed-off-by Bin Meng <[email protected]>
---
arch/x86/lib/tsc_timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
arch/x86/lib/tsc_timer.c +3 -3
@@ -288,7 +288,7 @@ void timer_set_base(u64 base)* restart. This yields a free running counter guaranteed to take almost 6 * years to wrap around even at 100GHz clock rate. */ -u64 __attribute__((no_instrument_function))get_ticks (void ) +u64 notrace get_ticks(void) {u64 now_tick =rdtsc ();
@@ -299,7 +299,7 @@ u64 __attribute__((no_instrument_function)) get_ticks(void) }/* Get the speed of the TSC timer in MHz */ -unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void) +unsigned notrace long get_tbclk_mhz (void ) {unsigned long fast_calibrate;
@@ -337,7 +337,7 @@ ulong get_timer(ulong base)return get_ms_timer () - base; } -ulong __attribute__((no_instrument_function))timer_get_us (void ) +ulong notrace timer_get_us(void) {return get_ticks () /get_tbclk_mhz (); }
Signature · 1 line
1.8.2.1
PATCH 6/10 x86: tsc: Use notrace from <linux/compiler.h>
Quoted 8 lines · Bin Meng
Replace __attribute__((no_instrument_function)) with notrace from <
linux/compiler.h>.Signed-off-by Bin Meng <[email protected]>---
arch/x86/lib/tsc_timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
Acked-by Simon Glass <[email protected]>
PATCH 7/10 x86: tsc: Add driver model timer support
In reply to Bin MengThis adds driver model timer support to x86 tsc timer driver.
Signed-off-by Bin Meng <[email protected]>
---
arch/x86/lib/tsc_timer.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+)
arch/x86/lib/tsc_timer.c +65 -0
@@ -8,7 +8,9 @@*/ #include <common.h> +#include <dm.h> #include <malloc.h> +#include <timer.h> #include <asm/io.h> #include <asm/i8254.h> #include <asm/ibmpc.h>
@@ -278,6 +280,7 @@ success:return delta /1000 ; } +#ifndef CONFIG_TIMER void timer_set_base (u64 base) { gd->arch.tsc_base = base;
@@ -297,10 +300,14 @@ u64 notrace get_ticks(void)panic ("No tick base available" ); return now_tick - gd->arch.tsc_base; } +#endif /* CONFIG_TIMER */ /* Get the speed of the TSC timer in MHz */ unsigned notrace long get_tbclk_mhz (void ) { +#ifdef CONFIG_TIMER +return get_tbclk () /1000000 ; +#else unsigned long fast_calibrate;if (gd->arch.tsc_mhz)
@@ -320,12 +327,15 @@ unsigned notrace long get_tbclk_mhz(void) gd->arch.tsc_mhz = fast_calibrate;return fast_calibrate; +#endif } +#ifndef CONFIG_TIMER unsigned long get_tbclk (void ) {return get_tbclk_mhz () *1000 *1000 ; } +#endif static ulong get_ms_timer (void ) {
@@ -375,3 +385,58 @@ int timer_init(void)return 0 ; } + +#ifdef CONFIG_TIMER +static int tsc_timer_get_count (struct udevice *dev,u64 *count) +{ +u64 now_tick =rdtsc (); + + *count = now_tick - gd->arch.tsc_base; + +return 0 ; +} + +static int tsc_timer_probe (struct udevice *dev) +{ +struct timer_dev_priv *uc_priv =dev_get_uclass_priv (dev); + + gd->arch.tsc_base =rdtsc (); + +/* +* If there is no clock frequency specified in the device tree, +* calibrate it by ourselves. +*/ +if (!uc_priv->clock_rate) { +unsigned long fast_calibrate; + + fast_calibrate =try_msr_calibrate_tsc (); +if (!fast_calibrate) { + fast_calibrate =quick_pit_calibrate (); +if (!fast_calibrate) +panic ("TSC frequency is ZERO" ); + } + + uc_priv->clock_rate = fast_calibrate *1000 *1000 ; + } + +return 0 ; +} + +static const struct timer_ops tsc_timer_ops = { + .get_count = tsc_timer_get_count, +}; + +static const struct udevice_id tsc_timer_ids[] = { + { .compatible ="x86,tsc-timer" , }, + { } +}; + +U_BOOT_DRIVER (tsc_timer) = { + .name ="tsc_timer" , + .id =UCLASS_TIMER , + .of_match = tsc_timer_ids, + .probe = tsc_timer_probe, + .ops = &tsc_timer_ops, + .flags =DM_FLAG_PRE_RELOC , +}; +#endif /* CONFIG_TIMER */
Signature · 1 line
1.8.2.1
PATCH 7/10 x86: tsc: Add driver model timer support
Quoted 7 lines · Bin Meng
This adds driver model timer support to x86 tsc timer driver.
Signed-off-by Bin Meng <[email protected]>---
arch/x86/lib/tsc_timer.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+)
Acked-by Simon Glass <[email protected]>
PATCH 8/10 x86: Convert to use driver model timer
In reply to Bin MengConvert all x86 boards to use driver model tsc timer.
Signed-off-by Bin Meng <[email protected]>
---
arch/x86/cpu/baytrail/valleyview.c | 3 --- arch/x86/cpu/coreboot/timestamp.c | 22 ---------------------- arch/x86/cpu/efi/efi.c | 4 ---- arch/x86/cpu/ivybridge/cpu.c | 1 - arch/x86/cpu/qemu/qemu.c | 3 --- arch/x86/cpu/quark/quark.c | 3 --- arch/x86/cpu/queensbay/tnc.c | 3 --- arch/x86/dts/bayleybay.dts | 1 + arch/x86/dts/broadwell_som-6896.dts | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/chromebox_panther.dts | 1 + arch/x86/dts/crownbay.dts | 1 + arch/x86/dts/efi.dts | 5 +++++ arch/x86/dts/galileo.dts | 5 +++++ arch/x86/dts/minnowmax.dts | 1 + arch/x86/dts/qemu-x86_i440fx.dts | 5 +++++ arch/x86/dts/qemu-x86_q35.dts | 5 +++++ arch/x86/dts/tsc_timer.dtsi | 7 +++++++ configs/bayleybay_defconfig | 1 + configs/chromebook_link_defconfig | 2 +- configs/chromebox_panther_defconfig | 2 +- configs/coreboot-x86_defconfig | 2 +- configs/crownbay_defconfig | 1 + configs/efi-x86_defconfig | 1 + configs/galileo_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/qemu-x86_defconfig | 1 + 27 files changed, 42 insertions(+), 42 deletions(-) create mode 100644 arch/x86/dts/tsc_timer.dtsi
arch/x86/cpu/baytrail/valleyview.c +0 -3
@@ -28,9 +28,6 @@ int arch_cpu_init(void)int ret;post_code (POST_CPU_INIT ); -#ifdef CONFIG_SYS_X86_TSC_TIMER -timer_set_base (rdtsc ()); -#endif ret =x86_cpu_init_f ();if (ret)
arch/x86/cpu/coreboot/timestamp.c +0 -22
@@ -27,28 +27,6 @@ static struct timestamp_table *ts_table __attribute__((section(".data")));void timestamp_init (void ) { -#ifdef CONFIG_SYS_X86_TSC_TIMER -uint64_t base_time; -#endif - - ts_table = lib_sysinfo.tstamp_table; -#ifdef CONFIG_SYS_X86_TSC_TIMER -/* -* If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value -* of base_time in coreboot's timestamp table as our timer base, -* otherwise TSC counter value will be used. -* -* Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS, -* the value of base_time in the timestamp table is still zero, so -* we must exclude this case too (this is currently seen on booting -* coreboot in qemu) -*/ -if (ts_table && ts_table->base_time) - base_time = ts_table->base_time; -else - base_time =rdtsc (); -timer_set_base (base_time); -#endif timestamp_add_now (TS_U_BOOT_INITTED ); }
arch/x86/cpu/efi/efi.c +0 -4
@@ -10,10 +10,6 @@int arch_cpu_init (void ) { -#ifdef CONFIG_SYS_X86_TSC_TIMER -timer_set_base (rdtsc ()); -#endif -return 0 ; }
arch/x86/cpu/ivybridge/cpu.c +0 -1
@@ -118,7 +118,6 @@ static void set_spi_speed(void)int arch_cpu_init (void ) {post_code (POST_CPU_INIT ); -timer_set_base (rdtsc ());return x86_cpu_init_f (); }
arch/x86/cpu/qemu/qemu.c +0 -3
@@ -14,9 +14,6 @@ int arch_cpu_init(void)int ret;post_code (POST_CPU_INIT ); -#ifdef CONFIG_SYS_X86_TSC_TIMER -timer_set_base (rdtsc ()); -#endif ret =x86_cpu_init_f ();if (ret)
arch/x86/cpu/quark/quark.c +0 -3
@@ -233,9 +233,6 @@ int arch_cpu_init(void)int ret;post_code (POST_CPU_INIT ); -#ifdef CONFIG_SYS_X86_TSC_TIMER -timer_set_base (rdtsc ()); -#endif ret =x86_cpu_init_f ();if (ret)
arch/x86/cpu/queensbay/tnc.c +0 -3
@@ -52,9 +52,6 @@ int arch_cpu_init(void)int ret;post_code (POST_CPU_INIT ); -#ifdef CONFIG_SYS_X86_TSC_TIMER -timer_set_base (rdtsc ()); -#endif ret =x86_cpu_init_f ();if (ret)
arch/x86/dts/bayleybay.dts +1 -0
@@ -12,6 +12,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "Intel Bayley Bay";
arch/x86/dts/broadwell_som-6896.dts +1 -0
@@ -3,6 +3,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "Advantech SOM-6896";
arch/x86/dts/chromebook_link.dts +1 -0
@@ -3,6 +3,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "Google Link";
arch/x86/dts/chromebox_panther.dts +1 -0
@@ -3,6 +3,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "Google Panther";
arch/x86/dts/crownbay.dts +1 -0
@@ -11,6 +11,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "Intel Crown Bay";
arch/x86/dts/efi.dts +5 -0
@@ -7,6 +7,7 @@ /dts-v1/; /include/ "skeleton.dtsi" +/include/ "tsc_timer.dtsi" / { model = "EFI";
@@ -16,6 +17,10 @@ stdout-path = &serial; }; + tsc-timer { + clock-frequency = <100000000>; + }; + serial: serial { compatible = "efi,uart"; };
arch/x86/dts/galileo.dts +5 -0
@@ -11,6 +11,7 @@ /include/ "skeleton.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "Intel Galileo";
@@ -28,6 +29,10 @@ stdout-path = &pciuart0; }; + tsc-timer { + clock-frequency = <400000000>; + }; + mrc { compatible = "intel,quark-mrc"; flags = <MRC_FLAG_SCRAMBLE_EN>;
arch/x86/dts/minnowmax.dts +1 -0
@@ -12,6 +12,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "Intel Minnowboard Max";
arch/x86/dts/qemu-x86_i440fx.dts +5 -0
@@ -11,6 +11,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "QEMU x86 (I440FX)";
@@ -43,6 +44,10 @@ }; }; + tsc-timer { + clock-frequency = <100000000>; + }; + pci { compatible = "pci-x86"; #address-cells = <3>;
arch/x86/dts/qemu-x86_q35.dts +5 -0
@@ -21,6 +21,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "QEMU x86 (Q35)";
@@ -54,6 +55,10 @@ }; }; + tsc-timer { + clock-frequency = <100000000>; + }; + pci { compatible = "pci-x86"; #address-cells = <3>;
arch/x86/dts/tsc_timer.dtsi new file +7 -0
@@ -0,0 +1,7 @@ +/ { + tsc-timer { + compatible = "x86,tsc-timer"; + u-boot,dm-pre-reloc; + counter-64bit; + }; +};
configs/bayleybay_defconfig +1 -0
@@ -24,6 +24,7 @@ CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y +CONFIG_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO_VESA=y
configs/chromebook_link_defconfig +1 -1
@@ -26,7 +26,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_DEBUG_UART_BOARD_INIT=y -CONFIG_DM_TPM=y +CONFIG_TIMER=y CONFIG_TPM_TIS_LPC=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
configs/chromebox_panther_defconfig +1 -1
@@ -21,7 +21,7 @@ CONFIG_CROS_EC_LPC=y CONFIG_SPI_FLASH=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y -CONFIG_DM_TPM=y +CONFIG_TIMER=y CONFIG_TPM_TIS_LPC=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
configs/coreboot-x86_defconfig +1 -1
@@ -17,7 +17,7 @@ CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y -CONFIG_DM_TPM=y +CONFIG_TIMER=y CONFIG_TPM_TIS_LPC=y CONFIG_USB=y CONFIG_DM_USB=y
configs/crownbay_defconfig +1 -0
@@ -23,6 +23,7 @@ CONFIG_E1000=y CONFIG_PCH_GBE=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y +CONFIG_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO_VESA=y
configs/efi-x86_defconfig +1 -0
@@ -13,4 +13,5 @@ CONFIG_DEBUG_EFI_CONSOLE=y CONFIG_DEBUG_UART_BASE=0 CONFIG_DEBUG_UART_CLOCK=0 # CONFIG_X86_SERIAL is not set +CONFIG_TIMER=y CONFIG_EFI=y
configs/galileo_defconfig +1 -0
@@ -18,6 +18,7 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y +CONFIG_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y
configs/minnowmax_defconfig +1 -0
@@ -25,6 +25,7 @@ CONFIG_DM_RTC=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO_VESA=y
configs/qemu-x86_defconfig +1 -0
@@ -18,6 +18,7 @@ CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_DM_RTC=y +CONFIG_TIMER=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_111=y
Signature · 1 line
1.8.2.1
PATCH 8/10 x86: Convert to use driver model timer
Hi Bin,
Quoted 69 lines · Bin Meng
Convert all x86 boards to use driver model tsc timer.
Signed-off-by Bin Meng <[email protected]>---
arch/x86/cpu/baytrail/valleyview.c | 3 --- arch/x86/cpu/coreboot/timestamp.c | 22 ---------------------- arch/x86/cpu/efi/efi.c | 4 ---- arch/x86/cpu/ivybridge/cpu.c | 1 - arch/x86/cpu/qemu/qemu.c | 3 --- arch/x86/cpu/quark/quark.c | 3 --- arch/x86/cpu/queensbay/tnc.c | 3 --- arch/x86/dts/bayleybay.dts | 1 + arch/x86/dts/broadwell_som-6896.dts | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/chromebox_panther.dts | 1 + arch/x86/dts/crownbay.dts | 1 + arch/x86/dts/efi.dts | 5 +++++ arch/x86/dts/galileo.dts | 5 +++++ arch/x86/dts/minnowmax.dts | 1 + arch/x86/dts/qemu-x86_i440fx.dts | 5 +++++ arch/x86/dts/qemu-x86_q35.dts | 5 +++++ arch/x86/dts/tsc_timer.dtsi | 7 +++++++ configs/bayleybay_defconfig | 1 + configs/chromebook_link_defconfig | 2 +- configs/chromebox_panther_defconfig | 2 +- configs/coreboot-x86_defconfig | 2 +- configs/crownbay_defconfig | 1 + configs/efi-x86_defconfig | 1 + configs/galileo_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/qemu-x86_defconfig | 1 + 27 files changed, 42 insertions(+), 42 deletions(-) create mode 100644 arch/x86/dts/tsc_timer.dtsiarch/x86/cpu/baytrail/valleyview.c +0
-3@@ -28,9 +28,6 @@ int arch_cpu_init(void)int ret;post_code (POST_CPU_INIT ); -#ifdef CONFIG_SYS_X86_TSC_TIMER -timer_set_base (rdtsc ()); -#endif ret =x86_cpu_init_f ();if (ret)arch/x86/cpu/coreboot/timestamp.c +0
-12@@ -27,28 +27,6 @@ static struct timestamp_table *ts_table __attribute__((section(".data")));void timestamp_init (void ) { -#ifdef CONFIG_SYS_X86_TSC_TIMER -uint64_t base_time; -#endif - - ts_table = lib_sysinfo.tstamp_table; -#ifdef CONFIG_SYS_X86_TSC_TIMER -/* -* If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value -* of base_time in coreboot's timestamp table as our timer base, -* otherwise TSC counter value will be used. -* -* Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
arch/x86/cpu/coreboot/timestamp.c static struct timestamp_table *ts_table __attribute__((section(".data"))); · line 51
Quoted 10 lines
arch/x86/cpu/coreboot/timestamp.c +0
-10-* the value of base_time in the timestamp table is still zero, so -* we must exclude this case too (this is currently seen on booting -* coreboot in qemu) -*/ -if (ts_table && ts_table->base_time) - base_time = ts_table->base_time; -else - base_time =rdtsc (); -timer_set_base (base_time); -#endif
Where does this code end up now? It seems to be deleted.
Regards,
Simon
PATCH 8/10 x86: Convert to use driver model timer
Hi Simon,
Quoted 76 lines · Simon Glass
Hi Bin,
Quoted 73 lines · Bin Meng
Convert all x86 boards to use driver model tsc timer.
Signed-off-by Bin Meng <[email protected]>---
arch/x86/cpu/baytrail/valleyview.c | 3 --- arch/x86/cpu/coreboot/timestamp.c | 22 ---------------------- arch/x86/cpu/efi/efi.c | 4 ---- arch/x86/cpu/ivybridge/cpu.c | 1 - arch/x86/cpu/qemu/qemu.c | 3 --- arch/x86/cpu/quark/quark.c | 3 --- arch/x86/cpu/queensbay/tnc.c | 3 --- arch/x86/dts/bayleybay.dts | 1 + arch/x86/dts/broadwell_som-6896.dts | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/chromebox_panther.dts | 1 + arch/x86/dts/crownbay.dts | 1 + arch/x86/dts/efi.dts | 5 +++++ arch/x86/dts/galileo.dts | 5 +++++ arch/x86/dts/minnowmax.dts | 1 + arch/x86/dts/qemu-x86_i440fx.dts | 5 +++++ arch/x86/dts/qemu-x86_q35.dts | 5 +++++ arch/x86/dts/tsc_timer.dtsi | 7 +++++++ configs/bayleybay_defconfig | 1 + configs/chromebook_link_defconfig | 2 +- configs/chromebox_panther_defconfig | 2 +- configs/coreboot-x86_defconfig | 2 +- configs/crownbay_defconfig | 1 + configs/efi-x86_defconfig | 1 + configs/galileo_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/qemu-x86_defconfig | 1 + 27 files changed, 42 insertions(+), 42 deletions(-) create mode 100644 arch/x86/dts/tsc_timer.dtsiarch/x86/cpu/baytrail/valleyview.c +0
-3@@ -28,9 +28,6 @@ int arch_cpu_init(void)int ret;post_code (POST_CPU_INIT ); -#ifdef CONFIG_SYS_X86_TSC_TIMER -timer_set_base (rdtsc ()); -#endif ret =x86_cpu_init_f ();if (ret)arch/x86/cpu/coreboot/timestamp.c +0
-16@@ -27,28 +27,6 @@ static struct timestamp_table *ts_table __attribute__((section(".data")));void timestamp_init (void ) { -#ifdef CONFIG_SYS_X86_TSC_TIMER -uint64_t base_time; -#endif - - ts_table = lib_sysinfo.tstamp_table; -#ifdef CONFIG_SYS_X86_TSC_TIMER -/* -* If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value -* of base_time in coreboot's timestamp table as our timer base, -* otherwise TSC counter value will be used. -* -* Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS, -* the value of base_time in the timestamp table is still zero, so -* we must exclude this case too (this is currently seen on booting -* coreboot in qemu) -*/
Quoted 9 lines
arch/x86/cpu/coreboot/timestamp.c static struct timestamp_table *ts_table __attribute__((section(".data"))); · line 51
Quoted 6 lines
arch/x86/cpu/coreboot/timestamp.c +0
-6-if (ts_table && ts_table->base_time) - base_time = ts_table->base_time; -else - base_time =rdtsc (); -timer_set_base (base_time); -#endif Where does this code end up now? It seems to be deleted.
The TSC base was saved when TSC timer driver is probed. Please see tsc_timer.c::tsc_timer_probe().
Regards,
Bin
PATCH 8/10 x86: Convert to use driver model timer
Quoted 89 lines · Bin Meng
Hi Simon,
Quoted 76 lines · Simon Glass
Hi Bin,
Quoted 73 lines · Bin Meng
Convert all x86 boards to use driver model tsc timer.
Signed-off-by Bin Meng <[email protected]>---
arch/x86/cpu/baytrail/valleyview.c | 3 --- arch/x86/cpu/coreboot/timestamp.c | 22 ---------------------- arch/x86/cpu/efi/efi.c | 4 ---- arch/x86/cpu/ivybridge/cpu.c | 1 - arch/x86/cpu/qemu/qemu.c | 3 --- arch/x86/cpu/quark/quark.c | 3 --- arch/x86/cpu/queensbay/tnc.c | 3 --- arch/x86/dts/bayleybay.dts | 1 + arch/x86/dts/broadwell_som-6896.dts | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/chromebox_panther.dts | 1 + arch/x86/dts/crownbay.dts | 1 + arch/x86/dts/efi.dts | 5 +++++ arch/x86/dts/galileo.dts | 5 +++++ arch/x86/dts/minnowmax.dts | 1 + arch/x86/dts/qemu-x86_i440fx.dts | 5 +++++ arch/x86/dts/qemu-x86_q35.dts | 5 +++++ arch/x86/dts/tsc_timer.dtsi | 7 +++++++ configs/bayleybay_defconfig | 1 + configs/chromebook_link_defconfig | 2 +- configs/chromebox_panther_defconfig | 2 +- configs/coreboot-x86_defconfig | 2 +- configs/crownbay_defconfig | 1 + configs/efi-x86_defconfig | 1 + configs/galileo_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/qemu-x86_defconfig | 1 + 27 files changed, 42 insertions(+), 42 deletions(-) create mode 100644 arch/x86/dts/tsc_timer.dtsiarch/x86/cpu/baytrail/valleyview.c +0
-3@@ -28,9 +28,6 @@ int arch_cpu_init(void)int ret;post_code (POST_CPU_INIT ); -#ifdef CONFIG_SYS_X86_TSC_TIMER -timer_set_base (rdtsc ()); -#endif ret =x86_cpu_init_f ();if (ret)arch/x86/cpu/coreboot/timestamp.c +0
-16@@ -27,28 +27,6 @@ static struct timestamp_table *ts_table __attribute__((section(".data")));void timestamp_init (void ) { -#ifdef CONFIG_SYS_X86_TSC_TIMER -uint64_t base_time; -#endif - - ts_table = lib_sysinfo.tstamp_table; -#ifdef CONFIG_SYS_X86_TSC_TIMER -/* -* If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value -* of base_time in coreboot's timestamp table as our timer base, -* otherwise TSC counter value will be used. -* -* Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS, -* the value of base_time in the timestamp table is still zero, so -* we must exclude this case too (this is currently seen on booting -* coreboot in qemu) -*/ Quoted 9 lines
arch/x86/cpu/coreboot/timestamp.c static struct timestamp_table *ts_table __attribute__((section(".data"))); · line 51
Quoted 6 lines
arch/x86/cpu/coreboot/timestamp.c +0
-6-if (ts_table && ts_table->base_time) - base_time = ts_table->base_time; -else - base_time =rdtsc (); -timer_set_base (base_time); -#endif Where does this code end up now? It seems to be deleted.
Quoted 3 lines
The TSC base was saved when TSC timer driver is probed. Please see
tsc_timer.c::tsc_timer_probe().
Thanks.
Acked-by Simon Glass <[email protected]>
PATCH 9/10 x86: tsc: Remove legacy timer codes
In reply to Bin MengNow that we have converted all x86 boards to use driver model timer, remove these legacy timer codes in the tsc driver.
Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option, as it is not needed with driver model.
Signed-off-by Bin Meng <[email protected]>
---
arch/x86/Kconfig | 20 -------------- arch/x86/cpu/qemu/Kconfig | 1 - arch/x86/cpu/quark/Kconfig | 5 ---- arch/x86/include/asm/global_data.h | 1 - arch/x86/lib/tsc_timer.c | 53 -------------------------------------- configs/coreboot-x86_defconfig | 1 - configs/efi-x86_defconfig | 1 - 7 files changed, 82 deletions(-)
arch/x86/Kconfig +0 -20
@@ -279,26 +279,6 @@ config AP_STACK_SIZE the memory used by this initialisation process. Typically 4KB is enough space. -config TSC_CALIBRATION_BYPASS - bool "Bypass Time-Stamp Counter (TSC) calibration" - default n - help - By default U-Boot automatically calibrates Time-Stamp Counter (TSC) - running frequency via Model-Specific Register (MSR) and Programmable - Interval Timer (PIT). If the calibration does not work on your board, - select this option and provide a hardcoded TSC running frequency with - CONFIG_TSC_FREQ_IN_MHZ below. - - Normally this option should be turned on in a simulation environment - like qemu. - -config TSC_FREQ_IN_MHZ - int "Time-Stamp Counter (TSC) running frequency in MHz" - depends on TSC_CALIBRATION_BYPASS - default 1000 - help - The running frequency in MHz of Time-Stamp Counter (TSC). - config HAVE_VGA_BIOS bool "Add a VGA BIOS image" help
arch/x86/cpu/qemu/Kconfig +0 -1
@@ -6,7 +6,6 @@ config QEMU bool - select TSC_CALIBRATION_BYPASS if QEMU
arch/x86/cpu/quark/Kconfig +0 -5
@@ -7,7 +7,6 @@ config INTEL_QUARK bool select HAVE_RMU - select TSC_CALIBRATION_BYPASS if INTEL_QUARK
@@ -119,8 +118,4 @@ config SYS_CAR_SIZE Space in bytes in eSRAM used as Cache-As-ARM (CAR). Note this size must not exceed eSRAM's total size. -config TSC_FREQ_IN_MHZ - int - default 400 - endif
arch/x86/include/asm/global_data.h +0 -1
@@ -54,7 +54,6 @@ struct arch_global_data {uint8_t x86_mask;uint32_t x86_device;uint64_t tsc_base;/* Initial value returned by rdtsc() */ -uint32_t tsc_mhz;/* TSC frequency in MHz */ void *new_fdt;/* Relocated FDT */ uint32_t bist;/* Built-in self test value */ enum pei_boot_mode_t pei_boot_mode;
arch/x86/lib/tsc_timer.c +0 -53
74 lines not on this page · raw message
configs/coreboot-x86_defconfig +0 -1
@@ -1,7 +1,6 @@ CONFIG_X86=y CONFIG_VENDOR_COREBOOT=y CONFIG_TARGET_COREBOOT=y -CONFIG_TSC_CALIBRATION_BYPASS=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set
configs/efi-x86_defconfig +0 -1
@@ -2,7 +2,6 @@ CONFIG_X86=y CONFIG_VENDOR_EFI=y CONFIG_DEFAULT_DEVICE_TREE="efi" CONFIG_TARGET_EFI=y -CONFIG_TSC_CALIBRATION_BYPASS=y # CONFIG_CMD_BOOTM is not set # CONFIG_CMD_NET is not set CONFIG_OF_CONTROL=y
Signature · 1 line
1.8.2.1
PATCH 9/10 x86: tsc: Remove legacy timer codes
Quoted 9 lines · Bin Meng
Now that we have converted all x86 boards to use driver model timer, remove these legacy timer codes in the tsc driver.
Note this also removes the
TSC_CALIBRATION_BYPASSKconfigoption, as it is not needed with driver model.Signed-off-by Bin Meng <[email protected]>---
Quoted 8 lines
arch/x86/Kconfig | 20 -------------- arch/x86/cpu/qemu/Kconfig | 1 - arch/x86/cpu/quark/Kconfig | 5 ---- arch/x86/include/asm/global_data.h | 1 - arch/x86/lib/tsc_timer.c | 53 -------------------------------------- configs/coreboot-x86_defconfig | 1 - configs/efi-x86_defconfig | 1 - 7 files changed, 82 deletions(-)
Acked-by Simon Glass <[email protected]>
PATCH 10/10 x86: tsc: Move tsc_timer.c to drivers/timer
In reply to Bin MengTo group all dm timer drivers together, move tsc timer to drivers/timer directory.
Signed-off-by Bin Meng <[email protected]>
---
arch/x86/lib/Makefile | 1 -
drivers/timer/Kconfig | 7 +++++++
drivers/timer/Makefile | 1 +
{arch/x86/lib => drivers/timer}/tsc_timer.c | 0
include/configs/x86-common.h | 2 --
5 files changed, 8 insertions(+), 3 deletions(-)
rename {arch/x86/lib => drivers/timer}/tsc_timer.c (100%)arch/x86/lib/Makefile +0 -1
@@ -34,7 +34,6 @@ obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o obj-y += string.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o obj-y += tables.o -obj-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_CMD_ZBOOT) += zimage.o obj-$(CONFIG_HAVE_FSP) += fsp/
drivers/timer/Kconfig +7 -0
@@ -16,4 +16,11 @@ config ALTERA_TIMER Select this to enable a timer for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config X86_TSC_TIMER + bool "x86 Time-Stamp Counter (TSC) timer support" + depends on TIMER && X86 + default y if X86 + help + Select this to enable Time-Stamp Counter (TSC) timer for x86. + endmenu
drivers/timer/Makefile +1 -0
@@ -6,3 +6,4 @@ obj-$(CONFIG_TIMER) += timer-uclass.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o +obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
drivers/timer/tsc_timer.c renamed from arch/x86/lib/tsc_timer.c +0 -0
include/configs/x86-common.h +0 -2
@@ -154,8 +154,6 @@* CPU Features */ -#define CONFIG_SYS_X86_TSC_TIMER -#define CONFIG_SYS_STACK_SIZE (32 * 1024)#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE#define CONFIG_SYS_MALLOC_LEN 0x200000
Signature · 1 line
1.8.2.1
PATCH 10/10 x86: tsc: Move tsc_timer.c to drivers/timer
Quoted 7 lines · Bin Meng
To group all dm timer drivers together, move tsc timer to
drivers/timerdirectory.Signed-off-by Bin Meng <[email protected]>---
Quoted 7 lines
arch/x86/lib/Makefile | 1 -
drivers/timer/Kconfig | 7 +++++++
drivers/timer/Makefile | 1 +
{arch/x86/lib => drivers/timer}/tsc_timer.c | 0
include/configs/x86-common.h | 2 --
5 files changed, 8 insertions(+), 3 deletions(-)
rename {arch/x86/lib => drivers/timer}/tsc_timer.c (100%)Acked-by Simon Glass <[email protected]>