SMP support for Broadcom NSP

Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's Northstar Plus CPU to the 32-bit ARM CPU device tree binding documentation file and create a new binding documentation for Northstar Plus CPU.

Signed-off-by Kapil Hali <[email protected]>

---
 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
 2 files changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +0 -0

new file mode 100644
index 0000000..8506da7

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +26 -0

+
+The secondary-boot-reg property is a u32 value that specifies the
+physical address of the register used to request the ROM holding pen
+code release a secondary CPU.
+
+Example:
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               enable-method = "brcm,bcm-nsp-smp";
+               secondary-boot-reg = <0xffff042c>;
+
+               cpu0: cpu at 0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       next-level-cache = <&L2>;
+                       reg = <0>;
+               };
+
+               cpu1: cpu at 1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       next-level-cache = <&L2>;
+                       reg = <1>;
+               };
+       };

Documentation/devicetree/bindings/arm/cpus.txt +1 -1

index 91e6e5c..6abe3f3 100644
@@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
                            "allwinner,sun8i-a23"
                            "arm,psci"
                            "brcm,brahma-b15"
+                           "brcm,bcm-nsp-smp"
                            "marvell,armada-375-smp"
                            "marvell,armada-380-smp"
                            "marvell,armada-390-smp"
--

2.1.0

Quoted 18 lines · Kapil Hali

Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's Northstar Plus CPU to the 32-bit ARM CPU device tree binding documentation file and create a new binding documentation for Northstar Plus CPU.

Signed-off-by Kapil Hali <[email protected]>

---
 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
 2 files changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +0 -0

new file mode 100644
index 0000000..8506da7

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt line 9

Quoted 9 lines

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +9 -0

@@ -0,0 +1,36 @@
+Broadcom Northstar Plus SoC CPU Enable Method
+---------------------------------------------
+This binding defines the enable method used for starting secondary
+CPUs in the following Broadcom SoCs:
+  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+The enable method is specified by defining the following required
+properties in the "cpus" device tree node:
+  - enable-method = "brcm,bcm-nsp-smp";

As I said already, this is supposed to be per cpu.

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt line 10

Quoted 1 line

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +1 -0

+  - secondary-boot-reg = <...>;

And then you might as well move this too.

Quoted 33 lines

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +26 -0

+
+The secondary-boot-reg property is a u32 value that specifies the
+physical address of the register used to request the ROM holding pen
+code release a secondary CPU.
+
+Example:
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               enable-method = "brcm,bcm-nsp-smp";
+               secondary-boot-reg = <0xffff042c>;
+
+               cpu0: cpu at 0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       next-level-cache = <&L2>;
+                       reg = <0>;
+               };
+
+               cpu1: cpu at 1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       next-level-cache = <&L2>;
+                       reg = <1>;
+               };
+       };

Documentation/devicetree/bindings/arm/cpus.txt +0 -0

index 91e6e5c..6abe3f3 100644
@@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
                            "allwinner,sun8i-a23"
                            "arm,psci"

Quoted 8 lines

Documentation/devicetree/bindings/arm/cpus.txt +1 -1

                            "brcm,brahma-b15"
+                           "brcm,bcm-nsp-smp"
                            "marvell,armada-375-smp"
                            "marvell,armada-380-smp"
                            "marvell,armada-390-smp"
--

2.1.0

Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's Northstar Plus CPU to the 32-bit ARM CPU device tree binding documentation file and create a new binding documentation for Northstar Plus CPU.

Signed-off-by Kapil Hali <[email protected]>

---
 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
 2 files changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +4 -0

new file mode 100644
index 0000000..8506da7
@@ -0,0 +1,36 @@
+Broadcom Northstar Plus SoC CPU Enable Method
+---------------------------------------------
+This binding defines the enable method used for starting secondary
+CPUs in the following Broadcom SoCs:

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +16 -0

+		secondary-boot-reg = <0xffff042c>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0>;
+		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <1>;
+		};
+	};

Documentation/devicetree/bindings/arm/cpus.txt +1 -0

index 91e6e5c..6abe3f3 100644
@@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
 			    "allwinner,sun8i-a23"
 			    "arm,psci"
 			    "brcm,brahma-b15"
+			    "brcm,bcm-nsp-smp"
 			    "marvell,armada-375-smp"
 			    "marvell,armada-380-smp"
 			    "marvell,armada-390-smp"

Le 06/11/2015 13:11, Kapil Hali a ?crit :

Quoted 30 lines

Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's Northstar Plus CPU to the 32-bit ARM CPU device tree binding documentation file and create a new binding documentation for Northstar Plus CPU.

Signed-off-by Kapil Hali <[email protected]>

---
 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
 2 files changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +12 -0

new file mode 100644
index 0000000..8506da7
@@ -0,0 +1,36 @@
+Broadcom Northstar Plus SoC CPU Enable Method
+---------------------------------------------
+This binding defines the enable method used for starting secondary
+CPUs in the following Broadcom SoCs:
+  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+The enable method is specified by defining the following required
+properties in the "cpus" device tree node:
+  - enable-method = "brcm,bcm-nsp-smp";
+  - secondary-boot-reg = <...>;
+
+The secondary-boot-reg property is a u32 value that specifies the

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt line 14

Quoted 2 lines

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +2 -0

+physical address of the register used to request the ROM holding pen
+code release a secondary CPU.

Is it really how the ROM code is implemented, as a pen holding/release mechanism (which sounds like how this was implemented previously in the kernel actually) or should this be described in a more generic way as the physical address of the register where the secondary CPUs reset vector address must be written to? Or something along these lines.

Quoted 5 lines

Is it really how the ROM code is implemented, as a pen holding/release mechanism (which sounds like how this was implemented previously in the kernel actually) or should this be described in a more generic way as the physical address of the register where the secondary CPUs reset vector address must be written to? Or something along these lines.

Why do people insist on using holding pens to bring their secondary CPUs into existence? I hope the hardware people aren't being dumb and have no way to hold in reset or power down their secondary CPUs, either of which is a vital feature for things like kexec and the like. If they do have a way to hold secondary CPUs in reset or powered down, why aren't they using that at boot instead of implementing the stupid Versatile scheme, which exists because Versatile _can't_ hold its CPUs in reset or power them down...

It's times like this that I wonder what kind of drugs the hardware SoC people are on, but I'm well aware that people contributing SMP bringup solutions are also dumb idiots who copy the Versatile scheme with very little thought... (as you can see, I'm not mincing my words here - if people want to be lazy in this regard despite this having been brought up multiple times, and the lead developers having said that the versatile pen_release stuff should not be used, they earn themselves the right to be called dumb idiots. Simple solution to avoid that title: don't be a dumb idiot by copy the Versatile SMP bring up code! It's not a sane model for any SoC sane SoC to follow.)

Is this clear enough?

Quoted 31 lines · Florian Fainelli

Le 06/11/2015 13:11, Kapil Hali a ?crit :

Quoted 30 lines

Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's Northstar Plus CPU to the 32-bit ARM CPU device tree binding documentation file and create a new binding documentation for Northstar Plus CPU.

Signed-off-by Kapil Hali <[email protected]>

---
 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
 2 files changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +12 -0

new file mode 100644
index 0000000..8506da7
@@ -0,0 +1,36 @@
+Broadcom Northstar Plus SoC CPU Enable Method
+---------------------------------------------
+This binding defines the enable method used for starting secondary
+CPUs in the following Broadcom SoCs:
+  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+The enable method is specified by defining the following required
+properties in the "cpus" device tree node:
+  - enable-method = "brcm,bcm-nsp-smp";
+  - secondary-boot-reg = <...>;
+
+The secondary-boot-reg property is a u32 value that specifies the

Quoted 8 lines

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt line 14

Quoted 2 lines

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +2 -0

+physical address of the register used to request the ROM holding pen
+code release a secondary CPU.

Is it really how the ROM code is implemented, as a pen holding/release mechanism (which sounds like how this was implemented previously in the kernel actually) or should this be described in a more generic way as the physical address of the register where the secondary CPUs reset vector address must be written to? Or something along these lines.

Why do people insist on using holding pens to bring their secondary CPUs into existence? I hope the hardware people aren't being dumb and have no way to hold in reset or power down their secondary CPUs, either of which is a vital feature for things like kexec and the like. If they do have a way to hold secondary CPUs in reset or powered down, why aren't they using that at boot instead of implementing the stupid Versatile scheme, which exists because Versatile _can't_ hold its CPUs in reset or power them down...

It's times like this that I wonder what kind of drugs the hardware SoC people are on, but I'm well aware that people contributing SMP bringup solutions are also dumb idiots who copy the Versatile scheme with very little thought... (as you can see, I'm not mincing my words here - if people want to be lazy in this regard despite this having been brought up multiple times, and the lead developers having said that the versatile pen_release stuff should not be used, they earn themselves the right to be called dumb idiots. Simple solution to avoid that title: don't be a dumb idiot by copy the Versatile SMP bring up code! It's not a sane model for any SoC sane SoC to follow.)

Is this clear enough?

Hi Russel,

It was clear the very first time itself as pointed out by you and the lead developers and hence the change was readily sent in the very next patch set. I didn't change a comment in this patch, which is misleading about the SMP enable-method used in the patch set, it is my mistake and I apologies for the same. I will change it and send the next patch set.

Also, before sending out the patch set, I had asked for a clarification about the method: https://lkml.org/lkml/2015/11/6/234

For my understanding, I am repeating my query- In case of simple method of waking up secondary core, smp_boot_secondary() will always return success indicating secondary core successfully started. I understand that in __cpu_up(), primary core waits for completion till secondary core comes online or time outs. However, is it appropriate to return successful start of secondary core without knowing if it really did?

Quoted 1 line · Kapil Hali

Hi Russel,

Wrong. Look at my name as sent in the From: and as quoted in the very next line. As far as I'm concerned (and I don't care what other people say) it's disrespectful to spell people's names incorrectly.

Quoted 5 lines

It was clear the very first time itself as pointed out by you and the lead developers and hence the change was readily sent in the very next patch set. I didn't change a comment in this patch, which is misleading about the SMP enable-method used in the patch set, it is my mistake and I apologies for the same. I will change it and send the next patch set.

Thanks.

Quoted 2 lines

Also, before sending out the patch set, I had asked for a clarification about the method: https://lkml.org/lkml/2015/11/6/234

Sorry, I don't read every single email irrespective of how it's marked. There's way too much email, and way too much mail with improperly classified recipient lists to be able to usefully sort this mail. (If you do the math, the email rate during a 12 hour working day from just linux-arm-kernel is one email every 2.5 minutes, assuming 300 emails a day. It takes way longer than that to compose a proper reply to an email - I've spent around 15 minutes on this one alone. Hence, if I'm busy, I more or less totally ignore email now, and rarely bother to "catch up" with missed emails.)

Quoted 6 lines

For my understanding, I am repeating my query- In case of simple method of waking up secondary core, smp_boot_secondary() will always return success indicating secondary core successfully started. I understand that in __cpu_up(), primary core waits for completion till secondary core comes online or time outs. However, is it appropriate to return successful start of secondary core without knowing if it really did?

Yes, because all that your smp_boot_secondary() should be doing is trying to start the core. If you encounter an error trying to do so, that's what the error return is for.

If you just set a bit somewhere to tell the hardware to release the secondary core's reset, then if you set the bit and return success, that's prefectly acceptable. The core ARM SMP code will then wait up to one second for the secondary core to become known to the kernel before declaring that the CPU failed to come online.

If it fails to appear, we assume that it will never appear - and actually at that point the system is in an unknown state: if the secondary CPU crashed during its boot, it could start scribbling into memory or touching devices in an unpredictable way: the only sane answer is to reboot the whole system to ensure that it's back to a known good state. Hence why we don't provide any cleanup at the point of a failed secondary CPU (I've been debating about tainting the kernel at that point, so we know when things have gone bad.)

Hope this helps.

Le 06/11/2015 13:11, Kapil Hali a ?crit :

Quoted 30 lines

Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's Northstar Plus CPU to the 32-bit ARM CPU device tree binding documentation file and create a new binding documentation for Northstar Plus CPU.

Signed-off-by Kapil Hali <[email protected]>

---
 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
 2 files changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +12 -0

new file mode 100644
index 0000000..8506da7
@@ -0,0 +1,36 @@
+Broadcom Northstar Plus SoC CPU Enable Method
+---------------------------------------------
+This binding defines the enable method used for starting secondary
+CPUs in the following Broadcom SoCs:
+  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+The enable method is specified by defining the following required
+properties in the "cpus" device tree node:
+  - enable-method = "brcm,bcm-nsp-smp";
+  - secondary-boot-reg = <...>;
+
+The secondary-boot-reg property is a u32 value that specifies the

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt line 14

Quoted 2 lines

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +2 -0

+physical address of the register used to request the ROM holding pen
+code release a secondary CPU.

Is it really how the ROM code is implemented, as a pen holding/release mechanism (which sounds like how this was implemented previously in the kernel actually) or should this be described in a more generic way as the physical address of the register where the secondary CPUs reset vector address must be written to? Or something along these lines.

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt line 20

Quoted 6 lines

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +6 -0

+
+Example:
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "brcm,bcm-nsp-smp";

Just a nit, but if NSP and NS are sharing the same mechanism, would not a more "NS-centric" property be more appropriate because NS came before NSP?

Quoted 21 lines

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file +16 -0

+		secondary-boot-reg = <0xffff042c>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0>;
+		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <1>;
+		};
+	};

Documentation/devicetree/bindings/arm/cpus.txt +0 -0

index 91e6e5c..6abe3f3 100644
@@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.

Documentation/devicetree/bindings/arm/cpus.txt nodes to be present and contain the properties described below. · line 197

Quoted 8 lines

Documentation/devicetree/bindings/arm/cpus.txt +1 -0

 			    "allwinner,sun8i-a23"
 			    "arm,psci"
 			    "brcm,brahma-b15"
+			    "brcm,bcm-nsp-smp"
 			    "marvell,armada-375-smp"
 			    "marvell,armada-380-smp"
 			    "marvell,armada-390-smp"

From: Jon Mason <[email protected]>

Add SMP support for Broadcom's 4708 SoCs.

Signed-off-by Jon Mason <[email protected]>

Acked-by Hauke Mehrtens <[email protected]>

Tested-by Hauke Mehrtens <[email protected]>

Signed-off-by Kapil Hali <[email protected]>

---
 arch/arm/boot/dts/bcm4708.dtsi | 2 ++
 arch/arm/mach-bcm/Kconfig      | 1 +
 arch/arm/mach-bcm/Makefile     | 3 +++
 3 files changed, 6 insertions(+)

arch/arm/mach-bcm/Kconfig +1 -0

+	select HAVE_SMP
 	help
 	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
 

Quoted 8 lines · Kapil Hali

From: Jon Mason <[email protected]>

Add SMP support for Broadcom's 4708 SoCs.

Signed-off-by Jon Mason <[email protected]>

Acked-by Hauke Mehrtens <[email protected]>

Tested-by Hauke Mehrtens <[email protected]>

Signed-off-by Kapil Hali <[email protected]>

I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.

Quoted 6 lines

---
 arch/arm/boot/dts/bcm4708.dtsi | 2 ++
 arch/arm/mach-bcm/Kconfig      | 1 +
 arch/arm/mach-bcm/Makefile     | 3 +++
 3 files changed, 6 insertions(+)

...

arch/arm/mach-bcm/Kconfig config ARCH_BCM_NSP · line 56

Quoted 6 lines

arch/arm/mach-bcm/Kconfig +0 -0

@@ -54,6 +54,7 @@ config ARCH_BCM_NSP
 config ARCH_BCM_5301X
 	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
 	select ARCH_BCM_IPROC

You activated ARM_ERRATA_764369 for NSP is this not needed for NS?

Quoted 6 lines

arch/arm/mach-bcm/Kconfig +1 -0

+	select HAVE_SMP
 	help
 	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
 

...

Quoted 21 lines · Hauke Mehrtens

Quoted 8 lines · Kapil Hali

From: Jon Mason <[email protected]>

Add SMP support for Broadcom's 4708 SoCs.

Signed-off-by Jon Mason <[email protected]>

Acked-by Hauke Mehrtens <[email protected]>

Tested-by Hauke Mehrtens <[email protected]>

Signed-off-by Kapil Hali <[email protected]>

I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.

Quoted 6 lines

---
 arch/arm/boot/dts/bcm4708.dtsi | 2 ++
 arch/arm/mach-bcm/Kconfig      | 1 +
 arch/arm/mach-bcm/Makefile     | 3 +++
 3 files changed, 6 insertions(+)

...

Quoted 8 lines

arch/arm/mach-bcm/Kconfig config ARCH_BCM_NSP · line 56

Quoted 6 lines

arch/arm/mach-bcm/Kconfig +0 -0

@@ -54,6 +54,7 @@ config ARCH_BCM_NSP
 config ARCH_BCM_5301X
 	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
 	select ARCH_BCM_IPROC

You activated ARM_ERRATA_764369 for NSP is this not needed for NS?

I'm not certain the CPU version, and without that it is difficult to know what errata's are present in the underlying hardware. My guess is that all present in NSP are present in NS (for UP and SMP). This would put it as:

        select ARM_ERRATA_754322
        select ARM_ERRATA_775420
        select ARM_ERRATA_764369 if SMP

Would you like me to have them added?

Quoted 39 lines · Jon Mason

Quoted 21 lines · Hauke Mehrtens

Quoted 8 lines · Kapil Hali

From: Jon Mason <[email protected]>

Add SMP support for Broadcom's 4708 SoCs.

Signed-off-by Jon Mason <[email protected]>

Acked-by Hauke Mehrtens <[email protected]>

Tested-by Hauke Mehrtens <[email protected]>

Signed-off-by Kapil Hali <[email protected]>

I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.

Quoted 6 lines

---
 arch/arm/boot/dts/bcm4708.dtsi | 2 ++
 arch/arm/mach-bcm/Kconfig      | 1 +
 arch/arm/mach-bcm/Makefile     | 3 +++
 3 files changed, 6 insertions(+)

...

Quoted 8 lines

arch/arm/mach-bcm/Kconfig config ARCH_BCM_NSP · line 56

Quoted 6 lines

arch/arm/mach-bcm/Kconfig +0 -0

@@ -54,6 +54,7 @@ config ARCH_BCM_NSP
 config ARCH_BCM_5301X
 	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
 	select ARCH_BCM_IPROC

You activated ARM_ERRATA_764369 for NSP is this not needed for NS?

I'm not certain the CPU version, and without that it is difficult to know what errata's are present in the underlying hardware. My guess is that all present in NSP are present in NS (for UP and SMP). This would put it as:

        select ARM_ERRATA_754322
        select ARM_ERRATA_775420
        select ARM_ERRATA_764369 if SMP

Quoted 2 lines

Would you like me to have them added?

I will send a separate patch adding all the workarounds for erratas in the CPU core and the cache controller.

Hauke

Quoted 46 lines · Hauke Mehrtens

Quoted 35 lines · Jon Mason

Quoted 21 lines · Hauke Mehrtens

Quoted 8 lines · Kapil Hali

From: Jon Mason <[email protected]>

Add SMP support for Broadcom's 4708 SoCs.

Signed-off-by Jon Mason <[email protected]>

Acked-by Hauke Mehrtens <[email protected]>

Tested-by Hauke Mehrtens <[email protected]>

Signed-off-by Kapil Hali <[email protected]>

I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.

Quoted 6 lines

---
 arch/arm/boot/dts/bcm4708.dtsi | 2 ++
 arch/arm/mach-bcm/Kconfig      | 1 +
 arch/arm/mach-bcm/Makefile     | 3 +++
 3 files changed, 6 insertions(+)

...

Quoted 8 lines

arch/arm/mach-bcm/Kconfig config ARCH_BCM_NSP · line 56

Quoted 6 lines

arch/arm/mach-bcm/Kconfig +0 -0

@@ -54,6 +54,7 @@ config ARCH_BCM_NSP
 config ARCH_BCM_5301X
 	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
 	select ARCH_BCM_IPROC

You activated ARM_ERRATA_764369 for NSP is this not needed for NS?

I'm not certain the CPU version, and without that it is difficult to know what errata's are present in the underlying hardware. My guess is that all present in NSP are present in NS (for UP and SMP). This would put it as:

Quoted 6 lines

        select ARM_ERRATA_754322
        select ARM_ERRATA_775420
        select ARM_ERRATA_764369 if SMP

Would you like me to have them added?

I will send a separate patch adding all the workarounds for erratas in the CPU core and the cache controller.

Quoted 3 lines

Hauke

Hi,

BCM4708 uses a Cortex-A9 rev r3p0 and a L2C-310 rev r3p2. For this CPU and cache controller the same workaround are needed as for NSP, if you will resend this patch, please add all of them.

Hauke

Quoted 8 lines · Kapil Hali

From: Jon Mason <[email protected]>

Add SMP support for Broadcom's 4708 SoCs.

Signed-off-by Jon Mason <[email protected]>

Acked-by Hauke Mehrtens <[email protected]>

Tested-by Hauke Mehrtens <[email protected]>

Signed-off-by Kapil Hali <[email protected]>

I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.

Quoted 6 lines

---
  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
  arch/arm/mach-bcm/Kconfig      | 1 +
  arch/arm/mach-bcm/Makefile     | 3 +++
  3 files changed, 6 insertions(+)

...

arch/arm/mach-bcm/Kconfig config ARCH_BCM_NSP · line 56

Quoted 6 lines

arch/arm/mach-bcm/Kconfig +0 -0

@@ -54,6 +54,7 @@ config ARCH_BCM_NSP
  config ARCH_BCM_5301X
  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
  	select ARCH_BCM_IPROC

You activated ARM_ERRATA_764369 for NSP is this not needed for NS?

Quoted 5 lines

arch/arm/mach-bcm/Kconfig +1 -0

+	select HAVE_SMP
  	help
  	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
 

...

Change in v3:
* Fixed patch subject from RESEND PATCH to PATCH
* Deleted arch/arm/mach-bcm/bcm_nsp.h file
* Removed inclusion of header file bcm_nsp.h in platsmp.c
* Removed unused variable 'timeout' in nsp_boot_secondary()