arm: ls1021a: merge SoC specific code in a separate file

PATCH Superseded Yuan Yao 2 participants 11 messages Nov 5, 2015 – Nov 15, 2015 Arm (32-bit)

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Yuan Yao

author

2015-11-05 10:26 UTC #0 lore raw

PATCH v2 1/5 arm: ls1021a: merge SoC specific code in a separate file

Create a soc.c file to put the code for soc special settings.

Signed-off-by Yuan Yao <[email protected]>

---
Changes in v2:
update to the lastest base.

---
 arch/arm/cpu/armv7/ls102xa/Makefile             |  1 +
 arch/arm/cpu/armv7/ls102xa/soc.c                | 66 +++++++++++++++++++++++++
 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +++++
 board/freescale/ls1021aqds/ls1021aqds.c         | 49 +-----------------
 board/freescale/ls1021atwr/ls1021atwr.c         | 42 +---------------
 5 files changed, 83 insertions(+), 87 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/ls102xa/soc.c
 create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h

arch/arm/cpu/armv7/ls102xa/Makefile +1 -0

index 2311468..0228300 100644
@@ -8,6 +8,7 @@ obj-y	+= cpu.o
 obj-y	+= clock.o
 obj-y	+= timer.o
 obj-y	+= fsl_epu.o
+obj-y	+= soc.o
 
 obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o

arch/arm/cpu/armv7/ls102xa/soc.c new file +66 -0

66 lines not on this page · raw message

arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h new file +12 -0

new file mode 100644
index 0000000..f10cb91
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_LS102XA_SOC_H
+#define __FSL_LS102XA_SOC_H
+
+unsigned int get_soc_major_rev(void);
+int arch_soc_init(void);
+#endif /* __FSL_LS102XA_SOC_H */

board/freescale/ls1021aqds/ls1021aqds.c +2 ~~-47~~

73 lines not on this page · raw message

board/freescale/ls1021atwr/ls1021atwr.c +2 ~~-40~~

66 lines not on this page · raw message

Signature · 1 line

2.1.0.27.g96db324

Yuan Yao

author

2015-11-05 10:26 UTC #1 lore raw

PATCH 2/5 arm: ls102xa: enable all the snoop signal for masters.

Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.

Signed-off-by Yuan Yao <[email protected]>

---
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 8 ++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 6 ++++++
 2 files changed, 14 insertions(+)

arch/arm/cpu/armv7/ls102xa/soc.c +8 -0

index 0fdd6d4..6036473 100644
@@ -62,5 +62,13 @@ int arch_soc_init(void)
 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 	}
 
+	/* Enable all the snoop signal for various masters */
+	out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
+				SCFG_SNPCNFGCR_DCU_RD_WR |
+				SCFG_SNPCNFGCR_SATA_RD_WR |
+				SCFG_SNPCNFGCR_USB3_RD_WR |
+				SCFG_SNPCNFGCR_DBG_RD_WR |
+				SCFG_SNPCNFGCR_EDMA_SNP);
+
 	return 0;
 }

arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +6 -0

index 09ed980..704d785 100644
@@ -150,6 +150,12 @@ struct ccsr_gur {
 #define SCFG_ETSECCMCR_GE1_CLK125	0x08000000
 #define SCFG_PIXCLKCR_PXCKEN		0x80000000
 #define SCFG_QSPI_CLKSEL		0xc0100000
+#define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
+#define SCFG_SNPCNFGCR_DCU_RD_WR	0x03000000
+#define SCFG_SNPCNFGCR_SATA_RD_WR	0x00c00000
+#define SCFG_SNPCNFGCR_USB3_RD_WR	0x00300000
+#define SCFG_SNPCNFGCR_DBG_RD_WR	0x000c0000
+#define SCFG_SNPCNFGCR_EDMA_SNP		0x00020000
 #define SCFG_ENDIANCR_LE		0x80000000
 
 /* Supplemental Configuration Unit */

Signature · 1 line

2.1.0.27.g96db324

Yuan Yao

author

2015-11-05 10:26 UTC #2 lore raw

PATCH 3/5 ls102xa: Enable snoop and DVM message requests.

In reply to Yuan Yao

Signed-off-by Yuan Yao <[email protected]>

---
 arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/ls102xa/soc.c +7 -1

index 6036473..97ba6d5 100644
@@ -40,8 +40,14 @@ int arch_soc_init(void)
 
 	/*
 	 * Enable snoop requests and DVM message requests for
-	 * Slave insterface S4 (A7 core cluster)
+	 * All the slave insterfaces.
 	 */
+	out_le32(&cci->slave[0].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+	out_le32(&cci->slave[1].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+	out_le32(&cci->slave[2].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 	out_le32(&cci->slave[4].snoop_ctrl,
 		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);

Signature · 1 line

2.1.0.27.g96db324

Yuan Yao

author

2015-11-05 10:26 UTC #3 lore raw

PATCH v2 4/5 armv7/fsl-ls102xa: Workaround for DDR erratum A008514

In reply to Yuan Yao

This is a workaround for hardware erratum.
Write the value of 63b2_0002h to EDDRTQCFG will optimal the memory controller performance.

The value: 63b2_0002h comes from the hardware team.

Signed-off-by Yuan Yao <[email protected]>

---
Changes in v2:
Rewrite the commit message to explain why and what this patch does.

---
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 10 ++++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/ls102xa/soc.c +10 -0

index 97ba6d5..b15cd60 100644
@@ -76,5 +76,15 @@ int arch_soc_init(void)
 				SCFG_SNPCNFGCR_DBG_RD_WR |
 				SCFG_SNPCNFGCR_EDMA_SNP);
 
+	/*
+	 * Memory controller require a register write before being enabled.
+	 * Affects: DDR
+	 * Register: EDDRTQCFG
+	 * Description: Memory controller performance is not optimal with
+	 *		default internal target queue register values.
+	 * Workaround: Write a value of 63b2_0002h to address: 157_020Ch.
+	 */
+	out_be32(&scfg->eddrtqcfg, 0x63b20002);
+
 	return 0;
 }

arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +1 -1

index 704d785..6b04674 100644
@@ -228,7 +228,7 @@ struct ccsr_scfg {
 	u32 scfgrevcr;
 	u32 coresrencr;
 	u32 pex2pmrdsr;
-	u32 ddrc1cr;
+	u32 eddrtqcfg;
 	u32 ddrc2cr;
 	u32 ddrc3cr;
 	u32 ddrc4cr;

Signature · 1 line

2.1.0.27.g96db324

York Sun

2015-11-05 18:05 UTC #4 lore raw

PATCH v2 4/5 armv7/fsl-ls102xa: Workaround for DDR erratum A008514

Quoted 6 lines · Yuan Yao

This is a workaround for hardware erratum.
Write the value of 63b2_0002h to EDDRTQCFG will optimal the memory controller performance.
The value: 63b2_0002h comes from the hardware team.

Quoted 8 lines

Signed-off-by Yuan Yao <[email protected]>
---
Changes in v2:
Rewrite the commit message to explain why and what this patch does.
---
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 10 ++++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

Workaround for A008514 is already implemented in DDR driver drivers/ddr/fsl/fsl_ddr_gen4.c. Please see if you can merge your workaround into it.

York

Yao Yuan

author

2015-11-09 09:30 UTC #5 lore raw

PATCH v2 4/5 armv7/fsl-ls102xa: Workaround for DDR erratum A008514

Hi york,

Is it for DDR4?
LS1021A doesn't use this file.

Best Regards,
Yuan Yao

Quoted 31 lines

-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Friday, November 06, 2015 2:05 AM
To: Yuan Yao-B46683 <[email protected]>
Cc: Wang Huan-B18965 <[email protected]>; u-boot at lists.denx.de
Subject: Re: [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514
Quoted 6 lines · Yuan Yao
This is a workaround for hardware erratum.
Write the value of 63b2_0002h to EDDRTQCFG will optimal the memory controller performance.
The value: 63b2_0002h comes from the hardware team.
Quoted 8 lines
Signed-off-by Yuan Yao <[email protected]>
---
Changes in v2:
Rewrite the commit message to explain why and what this patch does.
---
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 10 ++++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)
Workaround for A008514 is already implemented in DDR driver drivers/ddr/fsl/fsl_ddr_gen4.c. Please see if you can merge your workaround into it.
York

York Sun

2015-11-09 17:01 UTC #6 lore raw

PATCH v2 4/5 armv7/fsl-ls102xa: Workaround for DDR erratum A008514

Quoted 4 lines · On 11/09/2015 01:30 AM, Yuan Yao-B46683 wrote:

Hi york,
Is it for DDR4?
LS1021A doesn't use this file.

LS1021A support both DDR3 and DDR4. DDR4 mode uses this driver, doesn't it? My concern is if the workaround is implemented in different places, it will be harder to maintain in future versions fix this erratum. Maybe moving the workaround out of DDR driver to SoC is not a bad idea.

York

Quoted 36 lines

Best Regards,
Yuan Yao
Quoted 31 lines
-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Friday, November 06, 2015 2:05 AM
To: Yuan Yao-B46683 <[email protected]>
Cc: Wang Huan-B18965 <[email protected]>; u-boot at lists.denx.de
Subject: Re: [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514
Quoted 6 lines · Yuan Yao
This is a workaround for hardware erratum.
Write the value of 63b2_0002h to EDDRTQCFG will optimal the memory controller performance.
The value: 63b2_0002h comes from the hardware team.
Quoted 8 lines
Signed-off-by Yuan Yao <[email protected]>
---
Changes in v2:
Rewrite the commit message to explain why and what this patch does.
---
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 10 ++++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)
Workaround for A008514 is already implemented in DDR driver drivers/ddr/fsl/fsl_ddr_gen4.c. Please see if you can merge your workaround into it.
York

Yao Yuan

author

2015-11-10 13:18 UTC #7 lore raw

PATCH v2 4/5 armv7/fsl-ls102xa: Workaround for DDR erratum A008514

Thanks york,

So it seems I should moving the workaround out of DDR driver in "gen4" to SoC. I think the workaround is not just only for ddr4.
And It should be as a workaround for the SOC.

________________________________________
From: York Sun <[email protected]>
Sent: Tuesday, November 10, 2015 1:01
To: Yuan Yao-B46683
Cc: Wang Huan-B18965; u-boot at lists.denx.de
Subject: Re: [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514

Quoted 4 lines · On 11/09/2015 01:30 AM, Yuan Yao-B46683 wrote:

Hi york,
Is it for DDR4?
LS1021A doesn't use this file.

York

Quoted 36 lines

Best Regards,
Yuan Yao
Quoted 31 lines
-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Friday, November 06, 2015 2:05 AM
To: Yuan Yao-B46683 <[email protected]>
Cc: Wang Huan-B18965 <[email protected]>; u-boot at lists.denx.de
Subject: Re: [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514
Quoted 6 lines · Yuan Yao
This is a workaround for hardware erratum.
Write the value of 63b2_0002h to EDDRTQCFG will optimal the memory controller performance.
The value: 63b2_0002h comes from the hardware team.
Quoted 8 lines
Signed-off-by Yuan Yao <[email protected]>
---
Changes in v2:
Rewrite the commit message to explain why and what this patch does.
---
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 10 ++++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)
Workaround for A008514 is already implemented in DDR driver drivers/ddr/fsl/fsl_ddr_gen4.c. Please see if you can merge your workaround into it.
York

York Sun

2015-11-10 16:43 UTC #8 lore raw

PATCH v2 4/5 armv7/fsl-ls102xa: Workaround for DDR erratum A008514

Quoted 5 lines · On 11/10/2015 05:18 AM, Yuan Yao-B46683 wrote:

Thanks york,
So it seems I should moving the workaround out of DDR driver in "gen4" to SoC. I think the workaround is not just only for ddr4.
And It should be as a workaround for the SOC.

Please make the patch if you are comfortable. Please gate the code with the macro CONFIG_SYS_FSL_ERRATUM_A008514.

York

Yao Yuan

author

2015-11-15 13:19 UTC #9 lore raw

PATCH v2 4/5 armv7/fsl-ls102xa: Workaround for DDR erratum A008514

Hi York,

Thanks,
And is there any other comments for this set of patches? Or could I send v3 for review?

Best Regards,

Yuan Yao
________________________________________
From: York Sun <[email protected]>
Sent: Wednesday, November 11, 2015 0:43
To: Yuan Yao-B46683
Cc: Wang Huan-B18965; u-boot at lists.denx.de
Subject: Re: [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514

Quoted 5 lines · On 11/10/2015 05:18 AM, Yuan Yao-B46683 wrote:

Thanks york,
So it seems I should moving the workaround out of DDR driver in "gen4" to SoC. I think the workaround is not just only for ddr4.
And It should be as a workaround for the SOC.

Please make the patch if you are comfortable. Please gate the code with the macro CONFIG_SYS_FSL_ERRATUM_A008514.

York

Yuan Yao

author

2015-11-05 10:26 UTC #10 lore raw

PATCH v2 5/5 LS102XA:workaround:disable priorities within DDR

In reply to Yuan Yao

Erratum number: ERR008514
EDDRTQCFG Registers are Integration Strap values which controls performance parameters for DDR Controller.

The bit 25 is used to disable priorities within DDR since DDR are connected backwards on Rev2.0 silicon for LS1021A.

Signed-off-by Yuan Yao <[email protected]>

---
Changes in v2:
Add the Erratum number.

---
 arch/arm/cpu/armv7/ls102xa/soc.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/ls102xa/soc.c +12 -1

index b15cd60..98d4acd 100644
@@ -25,7 +25,7 @@ int arch_soc_init(void)
 {
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-	unsigned int major;
+	unsigned int major, reg;
 
 #ifdef CONFIG_FSL_QSPI
 	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);

@@ -86,5 +86,16 @@ int arch_soc_init(void)
 	 */
 	out_be32(&scfg->eddrtqcfg, 0x63b20002);
 
+	/*
+	 * EDDRTQCFG Registers are Integration Strap values which controls
+	 * performance parameters for DDR Controller.
+	 * The bit 25 is used for disable priorities within DDR.
+	 * This is a workaround because of the DDR are connected backwards
+	 * on Rev2.0.
+	 */
+	reg = in_be32(&scfg->eddrtqcfg);
+	reg |= 1 << 6;
+	out_be32(&scfg->eddrtqcfg, reg);
+
 	return 0;
 }

Signature · 1 line

2.1.0.27.g96db324