armv8: LS2080A: Rename LS2085A to reflect LS2080A

PATCH New Prabhakar Kushwaha 2 participants 10 messages Nov 9, 2015 – Nov 30, 2015

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Prabhakar Kushwaha

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2015-11-09 11:12 UTC #0 lore raw

PATCH v2 1/2 armv8: LS2080A: Rename LS2085A to reflect LS2080A

LS2080A is a prime personality of Freescale?s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by Pratiyush Mohan Srivastava <[email protected]>

Signed-off-by Prabhakar Kushwaha <[email protected]>

---
Changes for v2: Rebased on LS1043 patch set

 README                                             |  3 +
 arch/arm/Kconfig                                   | 44 +++++++----
 arch/arm/cpu/armv8/fsl-layerscape/Makefile         |  4 +-
 arch/arm/cpu/armv8/fsl-layerscape/README.lsch3     |  4 +-
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c            |  2 +-
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c            |  2 +-
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 11 +++
 .../{ls2085a_serdes.c => ls2080a_serdes.c}         |  0
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            |  2 +-
 arch/arm/cpu/armv8/fsl-layerscape/spl.c            |  4 +-
 arch/arm/dts/Makefile                              |  4 +-
 .../{fsl-ls2085a-qds.dts => fsl-ls2080a-qds.dts}   |  8 +-
 .../{fsl-ls2085a-rdb.dts => fsl-ls2080a-rdb.dts}   |  8 +-
 .../arm/dts/{fsl-ls2085a.dtsi => fsl-ls2080a.dtsi} |  4 +-
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  4 +-
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |  6 +-
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |  2 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  6 +-
 .../{ls2085a_stream_id.h => ls2080a_stream_id.h}   |  4 +-
 arch/arm/include/asm/global_data.h                 |  2 +-
 board/freescale/{ls2085a => ls2080a}/Kconfig       | 12 +--
 board/freescale/ls2080a/MAINTAINERS                |  8 ++
 board/freescale/ls2080a/Makefile                   |  8 ++
 board/freescale/{ls2085a => ls2080a}/README        |  2 +-
 board/freescale/{ls2085a => ls2080a}/ddr.c         |  3 +-
 board/freescale/{ls2085a => ls2080a}/ddr.h         |  0
 .../{ls2085a/ls2085a.c => ls2080a/ls2080a.c}       |  2 +
 board/freescale/{ls2085ardb => ls2080aqds}/Kconfig |  6 +-
 board/freescale/ls2080aqds/MAINTAINERS             |  8 ++
 .../freescale/{ls2085aqds => ls2080aqds}/Makefile  |  2 +-
 board/freescale/{ls2085aqds => ls2080aqds}/README  | 16 ++--
 board/freescale/{ls2085ardb => ls2080aqds}/ddr.c   |  5 +-
 board/freescale/{ls2085aqds => ls2080aqds}/ddr.h   |  0
 board/freescale/{ls2085aqds => ls2080aqds}/eth.c   | 92 +++++++++++-----------
 .../ls2085aqds.c => ls2080aqds/ls2080aqds.c}       |  4 +-
 .../ls2080aqds_qixis.h}                            |  0
 board/freescale/{ls2085aqds => ls2080ardb}/Kconfig |  6 +-
 board/freescale/ls2080ardb/MAINTAINERS             |  8 ++
 .../freescale/{ls2085ardb => ls2080ardb}/Makefile  |  2 +-
 board/freescale/{ls2085ardb => ls2080ardb}/README  | 12 +--
 board/freescale/{ls2085aqds => ls2080ardb}/ddr.c   |  5 +-
 board/freescale/{ls2085ardb => ls2080ardb}/ddr.h   |  0
 .../eth_ls2085rdb.c => ls2080ardb/eth_ls2080rdb.c} |  2 +-
 .../ls2085ardb.c => ls2080ardb/ls2080ardb.c}       |  4 +-
 .../ls2080ardb_qixis.h}                            |  0
 board/freescale/ls2085a/MAINTAINERS                |  8 --
 board/freescale/ls2085a/Makefile                   |  8 --
 board/freescale/ls2085aqds/MAINTAINERS             |  8 --
 board/freescale/ls2085ardb/MAINTAINERS             |  8 --
 ...ls2085a_emu_defconfig => ls2080a_emu_defconfig} |  2 +-
 ...2085a_simu_defconfig => ls2080a_simu_defconfig} |  2 +-
 .../{ls2085ardb_defconfig => ls2080aqds_defconfig} |  4 +-
 ...ds_nand_defconfig => ls2080aqds_nand_defconfig} |  2 +-
 .../{ls2085aqds_defconfig => ls2080ardb_defconfig} |  4 +-
 ...db_nand_defconfig => ls2080ardb_nand_defconfig} |  2 +-
 doc/README.fsl-trustzone-components                |  4 +-
 drivers/ddr/fsl/fsl_ddr_gen4.c                     |  4 +-
 drivers/net/fsl-mc/mc.c                            |  5 +-
 drivers/net/ldpaa_eth/Makefile                     |  2 +-
 drivers/net/ldpaa_eth/{ls2085a.c => ls2080a.c}     |  0
 drivers/pci/pcie_layerscape.c                      |  2 +-
 .../configs/{ls2085a_common.h => ls2080a_common.h} | 10 ++-
 include/configs/{ls2085a_emu.h => ls2080a_emu.h}   |  8 +-
 include/configs/{ls2085a_simu.h => ls2080a_simu.h} |  8 +-
 include/configs/{ls2085aqds.h => ls2080aqds.h}     |  4 +-
 include/configs/{ls2085ardb.h => ls2080ardb.h}     |  4 +-
 include/linux/usb/xhci-fsl.h                       |  6 +-
 67 files changed, 246 insertions(+), 190 deletions(-)
 rename arch/arm/cpu/armv8/fsl-layerscape/{ls2085a_serdes.c => ls2080a_serdes.c} (100%)
 rename arch/arm/dts/{fsl-ls2085a-qds.dts => fsl-ls2080a-qds.dts} (80%)
 rename arch/arm/dts/{fsl-ls2085a-rdb.dts => fsl-ls2080a-rdb.dts} (67%)
 rename arch/arm/dts/{fsl-ls2085a.dtsi => fsl-ls2080a.dtsi} (97%)
 rename arch/arm/include/asm/arch-fsl-layerscape/{ls2085a_stream_id.h => ls2080a_stream_id.h} (93%)
 rename board/freescale/{ls2085a => ls2080a}/Kconfig (66%)
 create mode 100644 board/freescale/ls2080a/MAINTAINERS
 create mode 100644 board/freescale/ls2080a/Makefile
 rename board/freescale/{ls2085a => ls2080a}/README (97%)
 rename board/freescale/{ls2085a => ls2080a}/ddr.c (99%)
 rename board/freescale/{ls2085a => ls2080a}/ddr.h (100%)
 rename board/freescale/{ls2085a/ls2085a.c => ls2080a/ls2080a.c} (98%)
 rename board/freescale/{ls2085ardb => ls2080aqds}/Kconfig (67%)
 create mode 100644 board/freescale/ls2080aqds/MAINTAINERS
 rename board/freescale/{ls2085aqds => ls2080aqds}/Makefile (83%)
 rename board/freescale/{ls2085aqds => ls2080aqds}/README (95%)
 rename board/freescale/{ls2085ardb => ls2080aqds}/ddr.c (98%)
 rename board/freescale/{ls2085aqds => ls2080aqds}/ddr.h (100%)
 rename board/freescale/{ls2085aqds => ls2080aqds}/eth.c (88%)
 rename board/freescale/{ls2085aqds/ls2085aqds.c => ls2080aqds/ls2080aqds.c} (98%)
 rename board/freescale/{ls2085aqds/ls2085aqds_qixis.h => ls2080aqds/ls2080aqds_qixis.h} (100%)
 rename board/freescale/{ls2085aqds => ls2080ardb}/Kconfig (67%)
 create mode 100644 board/freescale/ls2080ardb/MAINTAINERS
 rename board/freescale/{ls2085ardb => ls2080ardb}/Makefile (72%)
 rename board/freescale/{ls2085ardb => ls2080ardb}/README (94%)
 rename board/freescale/{ls2085aqds => ls2080ardb}/ddr.c (98%)
 rename board/freescale/{ls2085ardb => ls2080ardb}/ddr.h (100%)
 rename board/freescale/{ls2085ardb/eth_ls2085rdb.c => ls2080ardb/eth_ls2080rdb.c} (98%)
 rename board/freescale/{ls2085ardb/ls2085ardb.c => ls2080ardb/ls2080ardb.c} (98%)
 rename board/freescale/{ls2085ardb/ls2085ardb_qixis.h => ls2080ardb/ls2080ardb_qixis.h} (100%)
 delete mode 100644 board/freescale/ls2085a/MAINTAINERS
 delete mode 100644 board/freescale/ls2085a/Makefile
 delete mode 100644 board/freescale/ls2085aqds/MAINTAINERS
 delete mode 100644 board/freescale/ls2085ardb/MAINTAINERS
 rename configs/{ls2085a_emu_defconfig => ls2080a_emu_defconfig} (93%)
 rename configs/{ls2085a_simu_defconfig => ls2080a_simu_defconfig} (93%)
 rename configs/{ls2085ardb_defconfig => ls2080aqds_defconfig} (78%)
 rename configs/{ls2085aqds_nand_defconfig => ls2080aqds_nand_defconfig} (86%)
 rename configs/{ls2085aqds_defconfig => ls2080ardb_defconfig} (78%)
 rename configs/{ls2085ardb_nand_defconfig => ls2080ardb_nand_defconfig} (86%)
 rename drivers/net/ldpaa_eth/{ls2085a.c => ls2080a.c} (100%)
 rename include/configs/{ls2085a_common.h => ls2080a_common.h} (98%)
 rename include/configs/{ls2085a_emu.h => ls2080a_emu.h} (94%)
 rename include/configs/{ls2085a_simu.h => ls2080a_simu.h} (96%)
 rename include/configs/{ls2085aqds.h => ls2080aqds.h} (99%)
 rename include/configs/{ls2085ardb.h => ls2080ardb.h} (99%)

README +3 -0

index d18df54..28f1366 100644
@@ -611,6 +611,9 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
 		Number of controllers used for other than main memory.
 
+		CONFIG_SYS_FSL_HAS_DP_DDR
+		Defines the SoC has DP-DDR used for DPAA.
+
 		CONFIG_SYS_FSL_SEC_BE
 		Defines the SEC controller register space as Big Endian

arch/arm/Kconfig +27 ~~-17~~

72 lines not on this page · raw message

arch/arm/cpu/armv8/fsl-layerscape/Makefile +2 -2

index 6fa08c8..1beb426 100644
@@ -21,8 +21,8 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
 endif
 endif
 
-ifneq ($(CONFIG_LS2085A),)
-obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
+ifneq ($(CONFIG_LS2080A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
 else
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o

arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 +2 -2

index 1b7e698..b924134 100644
@@ -7,7 +7,7 @@
 Freescale LayerScape with Chassis Generation 3
 
 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
-for example LS2085A.
+for example LS2080A.
 
 DDR Layout
 ============

@@ -152,7 +152,7 @@ u-boot command
 nand write <rcw image in memory> 0 <size of rcw image>
 
 To form the NAND image, build u-boot with NAND config, for example,
-ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
+ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
 The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
 
 nand write <u-boot image in memory> 200000 <size of u-boot image>

arch/arm/cpu/armv8/fsl-layerscape/cpu.c +1 -1

index dbb12c2..f13c2fc 100644
@@ -438,7 +438,7 @@ int print_cpuinfo(void)
 #ifdef CONFIG_SYS_DPAA_FMAN
 	printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
 #endif
-#ifdef CONFIG_FSL_LSCH3
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	printf("     DP-DDR:   %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
 #endif
 	puts("\n");

arch/arm/cpu/armv8/fsl-layerscape/fdt.c +1 -1

index 47599c1..eafdd71 100644
@@ -141,7 +141,7 @@ void append_mmu_masters(void *blob, const char *smmu_path,
 
 /*
  * The info below summarizes how streamID partitioning works
- * for ls2085a and how it is conveyed to the OS via the device tree.
+ * for ls2080a and how it is conveyed to the OS via the device tree.
  *
  *  -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
  *     -all legacy devices get a unique ICID assigned and programmed in

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +11 -0

index 4054c3c..81cf470 100644
@@ -11,6 +11,7 @@
 #include <fsl_ifc.h>
 #include <asm/processor.h>
 #include <asm/io.h>
+#include <asm/arch-fsl-layerscape/immap_lsch3.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/soc.h>
 #include "cpu.h"

@@ -77,11 +78,15 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_systembus = sysclk;
 #ifdef CONFIG_DDR_CLK_FREQ
 	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
+#endif
 #else
 	sys_info->freq_ddrbus = sysclk;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	sys_info->freq_ddrbus2 = sysclk;
 #endif
+#endif
 
 	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &

@@ -91,9 +96,11 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
+#endif
 
 	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
 		/*

@@ -133,7 +140,9 @@ int get_clocks(void)
 	gd->cpu_clk = sys_info.freq_processor[0];
 	gd->bus_clk = sys_info.freq_systembus;
 	gd->mem_clk = sys_info.freq_ddrbus;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	gd->arch.mem2_clk = sys_info.freq_ddrbus2;
+#endif
 #if defined(CONFIG_FSL_ESDHC)
 	gd->arch.sdhc_clk = gd->bus_clk / 2;
 #endif /* defined(CONFIG_FSL_ESDHC) */

@@ -169,8 +178,10 @@ ulong get_ddr_freq(ulong ctrl_num)
 	 * DDR controller 0 & 1 are on memory complex 0
 	 * DDR controler 2 is on memory complext 1
 	 */
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (ctrl_num >= 2)
 		return gd->arch.mem2_clk;
+#endif
 
 	return gd->mem_clk;
 }

arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c renamed from arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c +0 -0

similarity index 100%
rename from arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c
rename to arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c

arch/arm/cpu/armv8/fsl-layerscape/soc.c +1 -1

index 34f9a94..54c75e2 100644
@@ -13,7 +13,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_LS2080A
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 #define PLATFORM_CYCLE_ENV_VAR	"a009635_interval_val"

arch/arm/cpu/armv8/fsl-layerscape/spl.c +2 -2

index ba551aa..a3410af 100644
@@ -48,7 +48,7 @@ void board_init_f(ulong dummy)
 	gd = &gdata;
 	/* Clear global data */
 	memset((void *)gd, 0, sizeof(gd_t));
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_LS2080A
 	arch_cpu_init();
 #endif
 #ifdef CONFIG_FSL_IFC

@@ -56,7 +56,7 @@ void board_init_f(ulong dummy)
 #endif
 	board_early_init_f();
 	timer_init();
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_LS2080A
 	env_init();
 #endif
 	get_clocks();

arch/arm/dts/Makefile +2 -2

index ddc6a05..0a4405f 100644
@@ -81,8 +81,8 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
 
 dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
 	ls1021a-twr.dtb
-dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \
-	fsl-ls2085a-rdb.dtb
+dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
+	fsl-ls2080a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
 	sun4i-a10-a1000.dtb \

arch/arm/dts/fsl-ls2080a-qds.dts renamed from arch/arm/dts/fsl-ls2085a-qds.dts +4 -4

similarity index 80%
rename from arch/arm/dts/fsl-ls2085a-qds.dts
rename to arch/arm/dts/fsl-ls2080a-qds.dts
index 4477e54..547ec27 100644
@@ -1,5 +1,5 @@
 /*
- * Freescale ls2085a QDS board device tree source
+ * Freescale ls2080a QDS board device tree source
  *
  * Copyright 2013-2015 Freescale Semiconductor, Inc.
  *

@@ -8,11 +8,11 @@
 
 /dts-v1/;
 
-#include "fsl-ls2085a.dtsi"
+#include "fsl-ls2080a.dtsi"
 
 / {
-	model = "Freescale Layerscape 2085a QDS Board";
-	compatible = "fsl,ls2085a-qds", "fsl,ls2085a";
+	model = "Freescale Layerscape 2080a QDS Board";
+	compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
 
 	aliases {
 		spi1 = &dspi;

arch/arm/dts/fsl-ls2080a-rdb.dts renamed from arch/arm/dts/fsl-ls2085a-rdb.dts +4 -4

similarity index 67%
rename from arch/arm/dts/fsl-ls2085a-rdb.dts
rename to arch/arm/dts/fsl-ls2080a-rdb.dts
index 25278df..1a1813b 100644
@@ -1,5 +1,5 @@
 /*
- * Freescale ls2085a RDB board device tree source
+ * Freescale ls2080a RDB board device tree source
  *
  * Copyright 2013-2015 Freescale Semiconductor, Inc.
  *

@@ -8,11 +8,11 @@
 
 /dts-v1/;
 
-#include "fsl-ls2085a.dtsi"
+#include "fsl-ls2080a.dtsi"
 
 / {
-	model = "Freescale Layerscape 2085a RDB Board";
-	compatible = "fsl,ls2085a-rdb", "fsl,ls2085a";
+	model = "Freescale Layerscape 2080a RDB Board";
+	compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
 
 	aliases {
 		spi1 = &dspi;

arch/arm/dts/fsl-ls2080a.dtsi renamed from arch/arm/dts/fsl-ls2085a.dtsi +2 -2

similarity index 97%
rename from arch/arm/dts/fsl-ls2085a.dtsi
rename to arch/arm/dts/fsl-ls2080a.dtsi
index 96404c5..a5c579c 100644
@@ -1,5 +1,5 @@
 /*
- * Freescale ls2085a SOC common device tree source
+ * Freescale ls2080a SOC common device tree source
  *
  * Copyright 2013-2015 Freescale Semiconductor, Inc.
  *

@@ -7,7 +7,7 @@
  */
 
 / {
-	compatible = "fsl,ls2085a";
+	compatible = "fsl,ls2080a";
 	interrupt-parent = <&gic>;
 	#address-cells = <2>;
 	#size-cells = <2>;

arch/arm/include/asm/arch-fsl-layerscape/config.h +2 -2

index c7169ab..1b700b3 100644
@@ -17,10 +17,10 @@
 #define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
 
-#if defined(CONFIG_LS2085A)
+#if defined(CONFIG_LS2080A)
 #define CONFIG_MAX_CPUS				16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
-#define CONFIG_NUM_DDR_CONTROLLERS		3
+#define CONFIG_NUM_DDR_CONTROLLERS		2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
 #define	SRDS_MAX_LANES	8
 #define CONFIG_SYS_FSL_SRDS_1

arch/arm/include/asm/arch-fsl-layerscape/cpu.h +4 -2

index 2903996..5a91dcb 100644
@@ -8,8 +8,10 @@
 #define _FSL_LAYERSCAPE_CPU_H
 
 static struct cpu_type cpu_type_list[] = {
-	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
+#ifdef CONFIG_LS2080A
 	CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+#endif
+	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
 	CPU_TYPE_ENTRY(LS2045, LS2045, 4),
 	CPU_TYPE_ENTRY(LS1043, LS1043, 4),
 };

@@ -180,7 +182,7 @@ static const struct sys_mmu_table final_mmu_table[] = {
 	  CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 	  CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_LS2080A
 	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 	  CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 #endif

arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +1 -1

index e1043b5..4787eec 100644
@@ -9,7 +9,7 @@
 
 #include <config.h>
 
-#if defined(CONFIG_LS2085A)
+#if defined(CONFIG_LS2080A)
 enum srds_prtcl {
 	NONE = 0,
 	PCIE1,

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +4 -2

index 6a70d44..134061c 100644
@@ -51,8 +51,8 @@
 #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
 #define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)
 
-#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02110000)
+#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02110000)
 
 /* TZ Address Space Controller Definitions */
 #define TZASC1_BASE			0x01100000	/* as per CCSR map. */

@@ -115,7 +115,9 @@ struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
 	unsigned long freq_systembus;
 	unsigned long freq_ddrbus;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	unsigned long freq_ddrbus2;
+#endif
 	unsigned long freq_localbus;
 	unsigned long freq_qe;
 #ifdef CONFIG_SYS_DPAA_FMAN

arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h renamed from arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h +2 -2

similarity index 93%
rename from arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h
rename to arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
index 5c94530..954104b 100644
@@ -7,7 +7,7 @@
 #ifndef __FSL_STREAM_ID_H
 #define __FSL_STREAM_ID_H
 
-/* Stream IDs on ls2085a devices are not hardwired and are
+/* Stream IDs on ls2080a devices are not hardwired and are
  * programmed by sw.  There are a limited number of stream IDs
  * available, and the partitioning of them is scenario dependent.
  * This header defines the partitioning between legacy, PCI,

@@ -17,7 +17,7 @@
  * on the specific hardware config-- e.g. perhaps not all
  * PEX controllers are in use.
  *
- * On LS2085 stream IDs are programmed in AMQ registers (32-bits) for
+ * On LS2080 stream IDs are programmed in AMQ registers (32-bits) for
  * each of the different bus masters.  The relationship between
  * the AMQ registers and stream IDs is defined in the table below:
  *          AMQ bit    streamID bit

arch/arm/include/asm/global_data.h +1 -1

index 4e3ea55..bd27281 100644
@@ -46,7 +46,7 @@ struct arch_global_data {
 	u32 omap_boot_mode;
 	u8 omap_ch_flags;
 #endif
-#ifdef CONFIG_FSL_LSCH3
+#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR)
 	unsigned long mem2_clk;
 #endif
 };

board/freescale/ls2080a/Kconfig renamed from board/freescale/ls2085a/Kconfig +6 -6

similarity index 66%
rename from board/freescale/ls2085a/Kconfig
rename to board/freescale/ls2080a/Kconfig
index 042f85b..0b938ff 100644
@@ -1,7 +1,7 @@
-if TARGET_LS2085A_EMU
+if TARGET_LS2080A_EMU
 
 config SYS_BOARD
-	default "ls2085a"
+	default "ls2080a"
 
 config SYS_VENDOR
 	default "freescale"

@@ -10,14 +10,14 @@ config SYS_SOC
 	default "fsl-layerscape"
 
 config SYS_CONFIG_NAME
-	default "ls2085a_emu"
+	default "ls2080a_emu"
 
 endif
 
-if TARGET_LS2085A_SIMU
+if TARGET_LS2080A_SIMU
 
 config SYS_BOARD
-	default "ls2085a"
+	default "ls2080a"
 
 config SYS_VENDOR
 	default "freescale"

@@ -26,6 +26,6 @@ config SYS_SOC
 	default "fsl-layerscape"
 
 config SYS_CONFIG_NAME
-	default "ls2085a_simu"
+	default "ls2080a_simu"
 
 endif

board/freescale/ls2080a/MAINTAINERS new file +8 -0

new file mode 100644
index 0000000..bb25084
@@ -0,0 +1,8 @@
+LS2080A BOARD
+M:	York Sun <[email protected]>
+S:	Maintained
+F:	board/freescale/ls2080a/
+F:	include/configs/ls2080a_emu.h
+F:	configs/ls2080a_emu_defconfig
+F:	include/configs/ls2080a_simu.h
+F:	configs/ls2080a_simu_defconfig

board/freescale/ls2080a/Makefile new file +8 -0

new file mode 100644
index 0000000..47c7c74
@@ -0,0 +1,8 @@
+#
+# Copyright 2014-15 Freescale Semiconductor
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ls2080a.o
+obj-y += ddr.o

board/freescale/ls2080a/README renamed from board/freescale/ls2085a/README +1 -1

similarity index 97%
rename from board/freescale/ls2085a/README
rename to board/freescale/ls2080a/README
index bc1d0bb..7e53f1f 100644
@@ -1,4 +1,4 @@
-Freescale ls2085a_emu
+Freescale ls2080a_emu
 
 This is a emulator target with limited peripherals.

board/freescale/ls2080a/ddr.c renamed from board/freescale/ls2085a/ddr.c +2 -1

similarity index 99%
rename from board/freescale/ls2085a/ddr.c
rename to board/freescale/ls2080a/ddr.c
index 4884fa2..47d73ef 100644
@@ -71,7 +71,7 @@ found:
 		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
 		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
 		pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
 		/* force DDR bus width to 32 bits */
 		popts->data_bus_width = 1;

@@ -79,6 +79,7 @@ found:
 		popts->burst_length = DDR_BL8;
 		popts->bstopre = 0;	/* enable auto precharge */
 	}
+#endif
 	/*
 	 * Factors to consider for half-strength driver enable:
 	 *	- number of DIMMs installed

board/freescale/ls2080a/ddr.h renamed from board/freescale/ls2085a/ddr.h +0 -0

similarity index 100%
rename from board/freescale/ls2085a/ddr.h
rename to board/freescale/ls2080a/ddr.h

board/freescale/ls2080a/ls2080a.c renamed from board/freescale/ls2085a/ls2085a.c +2 -0

similarity index 98%
rename from board/freescale/ls2085a/ls2085a.c
rename to board/freescale/ls2080a/ls2080a.c
index 27481e2..827fbf0 100644
@@ -41,11 +41,13 @@ void detail_board_ddr_info(void)
 	puts("\nDDR    ");
 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 	print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (gd->bd->bi_dram[2].size) {
 		puts("\nDP-DDR ");
 		print_size(gd->bd->bi_dram[2].size, "");
 		print_ddr_info(CONFIG_DP_DDR_CTRL);
 	}
+#endif
 }
 
 int dram_init(void)

board/freescale/ls2080aqds/Kconfig renamed from board/freescale/ls2085ardb/Kconfig +3 -3

similarity index 67%
rename from board/freescale/ls2085ardb/Kconfig
rename to board/freescale/ls2080aqds/Kconfig
index cb40db9..2f997e9 100644
@@ -1,8 +1,8 @@
 
-if TARGET_LS2085ARDB
+if TARGET_LS2080AQDS
 
 config SYS_BOARD
-	default "ls2085ardb"
+	default "ls2080aqds"
 
 config SYS_VENDOR
 	default "freescale"

@@ -11,6 +11,6 @@ config SYS_SOC
 	default "fsl-layerscape"
 
 config SYS_CONFIG_NAME
-	default "ls2085ardb"
+	default "ls2080aqds"
 
 endif

board/freescale/ls2080aqds/MAINTAINERS new file +8 -0

new file mode 100644
index 0000000..3d82482
@@ -0,0 +1,8 @@
+LS2080A BOARD
+M:	Prabhakar Kushwaha <[email protected]>
+S:	Maintained
+F:	board/freescale/ls2080aqds/
+F:	board/freescale/ls2080a/ls2080aqds.c
+F:	include/configs/ls2080aqds.h
+F:	configs/ls2080aqds_defconfig
+F:	configs/ls2080aqds_nand_defconfig

board/freescale/ls2080aqds/Makefile renamed from board/freescale/ls2085aqds/Makefile +1 -1

similarity index 83%
rename from board/freescale/ls2085aqds/Makefile
rename to board/freescale/ls2080aqds/Makefile
index da69a7d..e0da8a5 100644
@@ -4,6 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += ls2085aqds.o
+obj-y += ls2080aqds.o
 obj-y += ddr.o
 obj-y += eth.o

board/freescale/ls2080aqds/README renamed from board/freescale/ls2085aqds/README +8 -8

similarity index 95%
rename from board/freescale/ls2085aqds/README
rename to board/freescale/ls2080aqds/README
index e4a6f69..a4abb7e 100644
@@ -1,19 +1,19 @@
 Overview
 --------
-The LS2085A Development System (QDS) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2085A
-Layerscape Architecture processor. The LS2085AQDS provides validation and
-SW development platform for the Freescale LS2085A processor series, with
+The LS2080A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A
+Layerscape Architecture processor. The LS2080AQDS provides validation and
+SW development platform for the Freescale LS2080A processor series, with
 a complete debugging environment.
 
-LS2085A SoC Overview
+LS2080A SoC Overview
 ------------------
-The LS2085A integrated multicore processor combines eight ARM Cortex-A57
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
 processor cores with high-performance data path acceleration logic and network
 and peripheral bus interfaces required for networking, telecom/datacom,
 wireless infrastructure, and mil/aerospace applications.
 
-The LS2085A SoC includes the following function and features:
+The LS2080A SoC includes the following function and features:
 
  - Eight 64-bit ARM Cortex-A57 CPUs
  - 1 MB platform cache with ECC

@@ -50,7 +50,7 @@ The LS2085A SoC includes the following function and features:
  - Service processor (SP) provides pre-boot initialization and secure-boot
   capabilities
 
- LS2085AQDS board Overview
+ LS2080AQDS board Overview
  -----------------------
  - SERDES Connections, 16 lanes supporting:
       - PCI Express - 3.0

board/freescale/ls2080aqds/ddr.c renamed from board/freescale/ls2085ardb/ddr.c +4 -1

similarity index 98%
rename from board/freescale/ls2085ardb/ddr.c
rename to board/freescale/ls2080aqds/ddr.c
index 8d71ae1..ae681de 100644
@@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
 {
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
 	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
 	ulong ddr_freq;
 	int slot;

@@ -79,7 +81,7 @@ found:
 		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
 		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
 		pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
 		/* force DDR bus width to 32 bits */
 		popts->data_bus_width = 1;

@@ -114,6 +116,7 @@ found:
 		pdimm[slot].dq_mapping[16] = 0;
 		pdimm[slot].dq_mapping[17] = 0;
 	}
+#endif
 	/* To work at higher than 1333MT/s */
 	popts->half_strength_driver_enable = 0;
 	/*

board/freescale/ls2080aqds/ddr.h renamed from board/freescale/ls2085aqds/ddr.h +0 -0

similarity index 100%
rename from board/freescale/ls2085aqds/ddr.h
rename to board/freescale/ls2080aqds/ddr.h

board/freescale/ls2080aqds/eth.c renamed from board/freescale/ls2085aqds/eth.c +46 ~~-46~~

227 lines not on this page · raw message

board/freescale/ls2080aqds/ls2080aqds.c renamed from board/freescale/ls2085aqds/ls2085aqds.c +3 -1

similarity index 98%
rename from board/freescale/ls2085aqds/ls2085aqds.c
rename to board/freescale/ls2080aqds/ls2080aqds.c
index 36b059f..1f99072 100644
@@ -21,7 +21,7 @@
 #include <hwconfig.h>
 
 #include "../common/qixis.h"
-#include "ls2085aqds_qixis.h"
+#include "ls2080aqds_qixis.h"
 
 #define PIN_MUX_SEL_SDHC	0x00
 #define PIN_MUX_SEL_DSPI	0x0a

@@ -226,11 +226,13 @@ void detail_board_ddr_info(void)
 	puts("\nDDR    ");
 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 	print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (gd->bd->bi_dram[2].size) {
 		puts("\nDP-DDR ");
 		print_size(gd->bd->bi_dram[2].size, "");
 		print_ddr_info(CONFIG_DP_DDR_CTRL);
 	}
+#endif
 }
 
 int dram_init(void)

board/freescale/ls2080aqds/ls2080aqds_qixis.h renamed from board/freescale/ls2085aqds/ls2085aqds_qixis.h +0 -0

similarity index 100%
rename from board/freescale/ls2085aqds/ls2085aqds_qixis.h
rename to board/freescale/ls2080aqds/ls2080aqds_qixis.h

board/freescale/ls2080ardb/Kconfig renamed from board/freescale/ls2085aqds/Kconfig +3 -3

similarity index 67%
rename from board/freescale/ls2085aqds/Kconfig
rename to board/freescale/ls2080ardb/Kconfig
index 8d6acba..fe02575 100644
@@ -1,8 +1,8 @@
 
-if TARGET_LS2085AQDS
+if TARGET_LS2080ARDB
 
 config SYS_BOARD
-	default "ls2085aqds"
+	default "ls2080ardb"
 
 config SYS_VENDOR
 	default "freescale"

@@ -11,6 +11,6 @@ config SYS_SOC
 	default "fsl-layerscape"
 
 config SYS_CONFIG_NAME
-	default "ls2085aqds"
+	default "ls2080ardb"
 
 endif

board/freescale/ls2080ardb/MAINTAINERS new file +8 -0

new file mode 100644
index 0000000..aac8110
@@ -0,0 +1,8 @@
+LS2080A BOARD
+M:	Prabhakar Kushwaha <[email protected]>
+S:	Maintained
+F:	board/freescale/ls2080ardb/
+F:	board/freescale/ls2080a/ls2080ardb.c
+F:	include/configs/ls2080ardb.h
+F:	configs/ls2080ardb_defconfig
+F:	configs/ls2080ardb_nand_defconfig

board/freescale/ls2080ardb/Makefile renamed from board/freescale/ls2085ardb/Makefile +1 -1

similarity index 72%
rename from board/freescale/ls2085ardb/Makefile
rename to board/freescale/ls2080ardb/Makefile
index de383cc..6a52167 100644
@@ -4,5 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += ls2085ardb.o eth_ls2085rdb.o
+obj-y += ls2080ardb.o eth_ls2080rdb.o
 obj-y += ddr.o

board/freescale/ls2080ardb/README renamed from board/freescale/ls2085ardb/README +6 -6

similarity index 94%
rename from board/freescale/ls2085ardb/README
rename to board/freescale/ls2080ardb/README
index 2f18243..7fc2569 100644
@@ -1,17 +1,17 @@
 Overview
 --------
-The LS2085A Reference Design (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2085A
+The LS2080A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A
 Layerscape Architecture processor.
 
-LS2085A SoC Overview
+LS2080A SoC Overview
 ------------------
-The LS2085A integrated multicore processor combines eight ARM Cortex-A57
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
 processor cores with high-performance data path acceleration logic and network
 and peripheral bus interfaces required for networking, telecom/datacom,
 wireless infrastructure, and mil/aerospace applications.
 
-The LS2085A SoC includes the following function and features:
+The LS2080A SoC includes the following function and features:
 
  - Eight 64-bit ARM Cortex-A57 CPUs
  - 1 MB platform cache with ECC

@@ -48,7 +48,7 @@ The LS2085A SoC includes the following function and features:
  - Service processor (SP) provides pre-boot initialization and secure-boot
   capabilities
 
- LS2085ARDB board Overview
+ LS2080ARDB board Overview
  -----------------------
  - SERDES Connections, 16 lanes supporting:
       - PCI Express - 3.0

board/freescale/ls2080ardb/ddr.c renamed from board/freescale/ls2085aqds/ddr.c +4 -1

similarity index 98%
rename from board/freescale/ls2085aqds/ddr.c
rename to board/freescale/ls2080ardb/ddr.c
index 8d71ae1..ae681de 100644
@@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
 {
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
 	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
 	ulong ddr_freq;
 	int slot;

@@ -79,7 +81,7 @@ found:
 		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
 		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
 		pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
 		/* force DDR bus width to 32 bits */
 		popts->data_bus_width = 1;

@@ -114,6 +116,7 @@ found:
 		pdimm[slot].dq_mapping[16] = 0;
 		pdimm[slot].dq_mapping[17] = 0;
 	}
+#endif
 	/* To work at higher than 1333MT/s */
 	popts->half_strength_driver_enable = 0;
 	/*

board/freescale/ls2080ardb/ddr.h renamed from board/freescale/ls2085ardb/ddr.h +0 -0

similarity index 100%
rename from board/freescale/ls2085ardb/ddr.h
rename to board/freescale/ls2080ardb/ddr.h

board/freescale/ls2080ardb/eth_ls2080rdb.c renamed from board/freescale/ls2085ardb/eth_ls2085rdb.c +1 -1

similarity index 98%
rename from board/freescale/ls2085ardb/eth_ls2085rdb.c
rename to board/freescale/ls2080ardb/eth_ls2080rdb.c
index d578757..db50e4e 100644
@@ -97,7 +97,7 @@ int board_eth_init(bd_t *bis)
 
 		break;
 	default:
-		printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n",
+		printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
 		       srds_s1);
 		break;
 	}

board/freescale/ls2080ardb/ls2080ardb.c renamed from board/freescale/ls2085ardb/ls2085ardb.c +3 -1

similarity index 98%
rename from board/freescale/ls2085ardb/ls2085ardb.c
rename to board/freescale/ls2080ardb/ls2080ardb.c
index 761d7c8..2ae9d6c 100644
@@ -20,7 +20,7 @@
 #include <asm/arch/soc.h>
 
 #include "../common/qixis.h"
-#include "ls2085ardb_qixis.h"
+#include "ls2080ardb_qixis.h"
 
 #define PIN_MUX_SEL_SDHC	0x00
 #define PIN_MUX_SEL_DSPI	0x0a

@@ -192,11 +192,13 @@ void detail_board_ddr_info(void)
 	puts("\nDDR    ");
 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 	print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (gd->bd->bi_dram[2].size) {
 		puts("\nDP-DDR ");
 		print_size(gd->bd->bi_dram[2].size, "");
 		print_ddr_info(CONFIG_DP_DDR_CTRL);
 	}
+#endif
 }
 
 int dram_init(void)

board/freescale/ls2080ardb/ls2080ardb_qixis.h renamed from board/freescale/ls2085ardb/ls2085ardb_qixis.h +0 -0

similarity index 100%
rename from board/freescale/ls2085ardb/ls2085ardb_qixis.h
rename to board/freescale/ls2080ardb/ls2080ardb_qixis.h

board/freescale/ls2085a/MAINTAINERS deleted +0 -8

deleted file mode 100644
index 90b4e47..0000000
@@ -1,8 +0,0 @@
-LS2085A BOARD
-M:	York Sun <[email protected]>
-S:	Maintained
-F:	board/freescale/ls2085a/
-F:	include/configs/ls2085a_emu.h
-F:	configs/ls2085a_emu_defconfig
-F:	include/configs/ls2085a_simu.h
-F:	configs/ls2085a_simu_defconfig

board/freescale/ls2085a/Makefile deleted +0 -8

deleted file mode 100644
index 701b35c..0000000
@@ -1,8 +0,0 @@
-#
-# Copyright 2014 Freescale Semiconductor
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += ls2085a.o
-obj-y += ddr.o

board/freescale/ls2085aqds/MAINTAINERS deleted +0 -8

deleted file mode 100644
index fbed672..0000000
@@ -1,8 +0,0 @@
-LS2085A BOARD
-M:	Prabhakar Kushwaha <[email protected]>
-S:	Maintained
-F:	board/freescale/ls2085aqds/
-F:	board/freescale/ls2085a/ls2085aqds.c
-F:	include/configs/ls2085aqds.h
-F:	configs/ls2085aqds_defconfig
-F:	configs/ls2085aqds_nand_defconfig

board/freescale/ls2085ardb/MAINTAINERS deleted +0 -8

deleted file mode 100644
index d5cce40..0000000
@@ -1,8 +0,0 @@
-LS2085A BOARD
-M:	Prabhakar Kushwaha <[email protected]>
-S:	Maintained
-F:	board/freescale/ls2085ardb/
-F:	board/freescale/ls2085a/ls2085ardb.c
-F:	include/configs/ls2085ardb.h
-F:	configs/ls2085ardb_defconfig
-F:	configs/ls2085ardb_nand_defconfig

configs/ls2080a_emu_defconfig renamed from configs/ls2085a_emu_defconfig +1 -1

similarity index 93%
rename from configs/ls2085a_emu_defconfig
rename to configs/ls2080a_emu_defconfig
index 9c82e17..ebdde04 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_TARGET_LS2085A_EMU=y
+CONFIG_TARGET_LS2080A_EMU=y
 CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4"
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set

configs/ls2080a_simu_defconfig renamed from configs/ls2085a_simu_defconfig +1 -1

similarity index 93%
rename from configs/ls2085a_simu_defconfig
rename to configs/ls2080a_simu_defconfig
index 9d04218..eb8000b 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_TARGET_LS2085A_SIMU=y
+CONFIG_TARGET_LS2080A_SIMU=y
 CONFIG_SYS_EXTRA_OPTIONS="SIMU"
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set

configs/ls2080aqds_defconfig renamed from configs/ls2085ardb_defconfig +2 -2

similarity index 78%
rename from configs/ls2085ardb_defconfig
rename to configs/ls2080aqds_defconfig
index d0f16f2..afba06b 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_TARGET_LS2085ARDB=y
+CONFIG_TARGET_LS2080AQDS=y
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-rdb"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y

configs/ls2080aqds_nand_defconfig renamed from configs/ls2085aqds_nand_defconfig +1 -1

similarity index 86%
rename from configs/ls2085aqds_nand_defconfig
rename to configs/ls2080aqds_nand_defconfig
index ce2a81c..40cf883 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_TARGET_LS2085AQDS=y
+CONFIG_TARGET_LS2080AQDS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
 # CONFIG_CMD_SETEXPR is not set

configs/ls2080ardb_defconfig renamed from configs/ls2085aqds_defconfig +2 -2

similarity index 78%
rename from configs/ls2085aqds_defconfig
rename to configs/ls2080ardb_defconfig
index 78b121d..301cd7f 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_TARGET_LS2085AQDS=y
+CONFIG_TARGET_LS2080ARDB=y
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-qds"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y

configs/ls2080ardb_nand_defconfig renamed from configs/ls2085ardb_nand_defconfig +1 -1

similarity index 86%
rename from configs/ls2085ardb_nand_defconfig
rename to configs/ls2080ardb_nand_defconfig
index 25a6f71..658c9ff 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_TARGET_LS2085ARDB=y
+CONFIG_TARGET_LS2080ARDB=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
 # CONFIG_CMD_SETEXPR is not set

doc/README.fsl-trustzone-components +2 -2

index a3afd1f..e122346 100644
@@ -1,4 +1,4 @@
-Freescale ARM64 SoCs like LS2085A have ARM TrustZone components like
+Freescale ARM64 SoCs like LS2080A have ARM TrustZone components like
 TZPC-BP147 (TrustZone Protection Controller) and TZASC-400 (TrustZone
 Address Space Controller).

@@ -7,7 +7,7 @@ is left to a root-of-trust security software layer (running in EL3
 privilege mode), but still some configurations of these peripherals
 might be required while the bootloader is executing in EL3 privilege
 mode. The following sections define how to turn on these features for
-LS2085A like SoCs.
+LS2080A like SoCs.
 
 TZPC-BP147 (TrustZone Protection Controller)
 ============================================

drivers/ddr/fsl/fsl_ddr_gen4.c +2 -2

index 49e4688..eefe709 100644
@@ -107,14 +107,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		goto step2;
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_LS2080A
 	/* A008336 only applies to general DDR controllers */
 	if ((ctrl_num == 0) || (ctrl_num == 1))
 #endif
 		ddr_out32(eddrtqcr1, 0x63b30002);
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_LS2080A
 	/* A008514 only applies to DP-DDR controler */
 	if (ctrl_num == 2)
 #endif

drivers/net/fsl-mc/mc.c +4 -1

index 5168b99..e1a02d1 100644
@@ -1147,7 +1147,10 @@ static int do_fsl_mc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	switch (argv[1][0]) {
 	case 's': {
 			char sub_cmd;
-			u64 mc_fw_addr, mc_dpc_addr, aiop_fw_addr;
+			u64 mc_fw_addr, mc_dpc_addr;
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+			u64 aiop_fw_addr;
+#endif
 
 			sub_cmd = argv[2][0];
 			switch (sub_cmd) {

drivers/net/ldpaa_eth/Makefile +1 -1

index c37633f..5587aa6 100644
@@ -6,4 +6,4 @@
 
 obj-y += ldpaa_wriop.o
 obj-y += ldpaa_eth.o
-obj-$(CONFIG_LS2085A) += ls2085a.o
+obj-$(CONFIG_LS2080A) += ls2080a.o

drivers/net/ldpaa_eth/ls2080a.c renamed from drivers/net/ldpaa_eth/ls2085a.c +0 -0

similarity index 100%
rename from drivers/net/ldpaa_eth/ls2085a.c
rename to drivers/net/ldpaa_eth/ls2080a.c

drivers/pci/pcie_layerscape.c +1 -1

index 4cee038..8af6531 100644
@@ -665,7 +665,7 @@ void ft_pci_setup(void *blob, bd_t *bd)
 }
 #endif
 
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_LS2080A
 
 void pcie_set_available_streamids(void *blob, const char *pcie_path,
 				  u32 *stream_ids, int count)

include/configs/ls2080a_common.h renamed from include/configs/ls2085a_common.h +7 -3

similarity index 98%
rename from include/configs/ls2085a_common.h
rename to include/configs/ls2080a_common.h
index 0011e72..de542c2 100644
@@ -11,7 +11,7 @@
 #define CONFIG_REMAKE_ELF
 #define CONFIG_FSL_LAYERSCAPE
 #define CONFIG_FSL_LSCH3
-#define CONFIG_LS2085A
+#define CONFIG_LS2080A
 #define CONFIG_MP
 #define CONFIG_GICV3
 #define CONFIG_FSL_TZPC_BP147

@@ -20,7 +20,7 @@
 #define CONFIG_ARM_ERRATA_828024
 #define CONFIG_ARM_ERRATA_826974
 
-#include <asm/arch/ls2085a_stream_id.h>
+#include <asm/arch/ls2080a_stream_id.h>
 #include <asm/arch/config.h>
 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
 #define	CONFIG_SYS_HAS_SERDES

@@ -80,6 +80,7 @@
 #define CPU_RELEASE_ADDR		secondary_boot_func
 
 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 #define CONFIG_SYS_DP_DDR_BASE		0x6000000000ULL
 /*
  * DDR controller use 0 as the base address for binding.

@@ -88,6 +89,7 @@
 #define CONFIG_SYS_DP_DDR_BASE_PHY	0
 #define CONFIG_DP_DDR_CTRL		2
 #define CONFIG_DP_DDR_NUM_CTRLS		1
+#endif
 
 /* Generic Timer Definitions */
 /*

@@ -183,8 +185,10 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
+#ifndef CONFIG_LS2080A
 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
+#endif
 
 /*
  * Carve out a DDR region which will not be used by u-boot/Linux

@@ -205,7 +209,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_PCIE3		/* PCIE controler 3 */
 #define CONFIG_PCIE4		/* PCIE controler 4 */
 #define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
-#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
+#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
 
 #define CONFIG_SYS_PCI_64BIT

include/configs/ls2080a_emu.h renamed from include/configs/ls2085a_emu.h +5 -3

similarity index 94%
rename from include/configs/ls2085a_emu.h
rename to include/configs/ls2080a_emu.h
index 2d68e1b..6400f4f 100644
@@ -7,10 +7,10 @@
 #ifndef __LS2_EMU_H
 #define __LS2_EMU_H
 
-#include "ls2085a_common.h"
+#include "ls2080a_common.h"
 
-#define CONFIG_IDENT_STRING		" LS2085A-EMU"
-#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-EMU"
+#define CONFIG_IDENT_STRING		" LS2080A-EMU"
+#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2080A-EMU"
 
 #define CONFIG_SYS_CLK_FREQ	100000000
 #define CONFIG_DDR_CLK_FREQ	133333333

@@ -27,7 +27,9 @@
 #define CONFIG_SYS_SPD_BUS_NUM	1	/* SPD on I2C bus 1 */
 #define CONFIG_DIMM_SLOTS_PER_CTLR		1
 #define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#endif
 
 #define CONFIG_FSL_DDR_SYNC_REFRESH

include/configs/ls2080a_simu.h renamed from include/configs/ls2085a_simu.h +5 -3

similarity index 96%
rename from include/configs/ls2085a_simu.h
rename to include/configs/ls2080a_simu.h
index bd15b3d..666df80 100644
@@ -7,10 +7,10 @@
 #ifndef __LS2_SIMU_H
 #define __LS2_SIMU_H
 
-#include "ls2085a_common.h"
+#include "ls2080a_common.h"
 
-#define CONFIG_IDENT_STRING		" LS2085A-SIMU"
-#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-SIMU"
+#define CONFIG_IDENT_STRING		" LS2080A-SIMU"
+#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2080A-SIMU"
 
 #define CONFIG_SYS_CLK_FREQ	100000000
 #define CONFIG_DDR_CLK_FREQ	133333333

@@ -20,7 +20,9 @@
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR		1
 #define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#endif
 
 /* SMSC 91C111 ethernet configuration */
 #define CONFIG_SMC91111

include/configs/ls2080aqds.h renamed from include/configs/ls2085aqds.h +3 -1

similarity index 99%
rename from include/configs/ls2085aqds.h
rename to include/configs/ls2080aqds.h
index 99690ef..b8bdf62 100644
@@ -7,7 +7,7 @@
 #ifndef __LS2_QDS_H
 #define __LS2_QDS_H
 
-#include "ls2085a_common.h"
+#include "ls2080a_common.h"
 
 #define CONFIG_DISPLAY_BOARDINFO

@@ -35,7 +35,9 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
 #define CONFIG_DIMM_SLOTS_PER_CTLR		2
 #define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#endif
 #define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */
 
 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */

include/configs/ls2080ardb.h renamed from include/configs/ls2085ardb.h +3 -1

similarity index 99%
rename from include/configs/ls2085ardb.h
rename to include/configs/ls2080ardb.h
index f36253d..65d4f64 100644
@@ -7,7 +7,7 @@
 #ifndef __LS2_RDB_H
 #define __LS2_RDB_H
 
-#include "ls2085a_common.h"
+#include "ls2080a_common.h"
 
 #undef CONFIG_CONS_INDEX
 #define CONFIG_CONS_INDEX       2

@@ -37,7 +37,9 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
 #define CONFIG_DIMM_SLOTS_PER_CTLR		2
 #define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#endif
 #define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */
 
 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */

include/linux/usb/xhci-fsl.h +3 -3

index 602a413..80b7718 100644
@@ -54,9 +54,9 @@ struct fsl_xhci {
 #if defined(CONFIG_LS102XA)
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
-#elif defined(CONFIG_LS2085A)
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR
+#elif defined(CONFIG_LS2080A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
 #endif
 
 #define FSL_USB_XHCI_ADDR	{CONFIG_SYS_FSL_XHCI_USB1_ADDR, \

Signature · 1 line

1.9.1

York Sun

2015-11-10 19:10 UTC #1 lore raw

PATCH v2 1/2 armv8: LS2080A: Rename LS2085A to reflect LS2080A

Quoted 59 lines · Prabhakar Kushwaha

Signed-off-by Pratiyush Mohan Srivastava <[email protected]>

Signed-off-by Prabhakar Kushwaha <[email protected]>

---
Changes for v2: Rebased on LS1043 patch set

 README                                             |  3 +
 arch/arm/Kconfig                                   | 44 +++++++----
 arch/arm/cpu/armv8/fsl-layerscape/Makefile         |  4 +-
 arch/arm/cpu/armv8/fsl-layerscape/README.lsch3     |  4 +-
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c            |  2 +-
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c            |  2 +-
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 11 +++
 .../{ls2085a_serdes.c => ls2080a_serdes.c}         |  0
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            |  2 +-
 arch/arm/cpu/armv8/fsl-layerscape/spl.c            |  4 +-
 arch/arm/dts/Makefile                              |  4 +-
 .../{fsl-ls2085a-qds.dts => fsl-ls2080a-qds.dts}   |  8 +-
 .../{fsl-ls2085a-rdb.dts => fsl-ls2080a-rdb.dts}   |  8 +-
 .../arm/dts/{fsl-ls2085a.dtsi => fsl-ls2080a.dtsi} |  4 +-
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  4 +-
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |  6 +-
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |  2 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  6 +-
 .../{ls2085a_stream_id.h => ls2080a_stream_id.h}   |  4 +-
 arch/arm/include/asm/global_data.h                 |  2 +-
 board/freescale/{ls2085a => ls2080a}/Kconfig       | 12 +--
 board/freescale/ls2080a/MAINTAINERS                |  8 ++
 board/freescale/ls2080a/Makefile                   |  8 ++
 board/freescale/{ls2085a => ls2080a}/README        |  2 +-
 board/freescale/{ls2085a => ls2080a}/ddr.c         |  3 +-
 board/freescale/{ls2085a => ls2080a}/ddr.h         |  0
 .../{ls2085a/ls2085a.c => ls2080a/ls2080a.c}       |  2 +
 board/freescale/{ls2085ardb => ls2080aqds}/Kconfig |  6 +-
 board/freescale/ls2080aqds/MAINTAINERS             |  8 ++
 .../freescale/{ls2085aqds => ls2080aqds}/Makefile  |  2 +-
 board/freescale/{ls2085aqds => ls2080aqds}/README  | 16 ++--
 board/freescale/{ls2085ardb => ls2080aqds}/ddr.c   |  5 +-
 board/freescale/{ls2085aqds => ls2080aqds}/ddr.h   |  0
 board/freescale/{ls2085aqds => ls2080aqds}/eth.c   | 92 +++++++++++-----------
 .../ls2085aqds.c => ls2080aqds/ls2080aqds.c}       |  4 +-
 .../ls2080aqds_qixis.h}                            |  0
 board/freescale/{ls2085aqds => ls2080ardb}/Kconfig |  6 +-
 board/freescale/ls2080ardb/MAINTAINERS             |  8 ++
 .../freescale/{ls2085ardb => ls2080ardb}/Makefile  |  2 +-
 board/freescale/{ls2085ardb => ls2080ardb}/README  | 12 +--
 board/freescale/{ls2085aqds => ls2080ardb}/ddr.c   |  5 +-
 board/freescale/{ls2085ardb => ls2080ardb}/ddr.h   |  0
 .../eth_ls2085rdb.c => ls2080ardb/eth_ls2080rdb.c} |  2 +-
 .../ls2085ardb.c => ls2080ardb/ls2080ardb.c}       |  4 +-
 .../ls2080ardb_qixis.h}                            |  0
 board/freescale/ls2085a/MAINTAINERS                |  8 --
 board/freescale/ls2085a/Makefile                   |  8 --
 board/freescale/ls2085aqds/MAINTAINERS             |  8 --
 board/freescale/ls2085ardb/MAINTAINERS             |  8 --
 ...ls2085a_emu_defconfig => ls2080a_emu_defconfig} |  2 +-

Quoted 8 lines

 ...2085a_simu_defconfig => ls2080a_simu_defconfig} |  2 +-
 .../{ls2085ardb_defconfig => ls2080aqds_defconfig} |  4 +-
 ...ds_nand_defconfig => ls2080aqds_nand_defconfig} |  2 +-
 .../{ls2085aqds_defconfig => ls2080ardb_defconfig} |  4 +-
 ...db_nand_defconfig => ls2080ardb_nand_defconfig} |  2 +-
 doc/README.fsl-trustzone-components                |  4 +-
 drivers/ddr/fsl/fsl_ddr_gen4.c                     |  4 +-
 drivers/net/fsl-mc/mc.c                            |  5 +-

Prabhakar,

Are you sure you are using the correct code base? I don't even see function do_fsl_mc().

York

Kushwaha Prabhakar

author

2015-11-16 04:35 UTC #2 lore raw

PATCH v2 1/2 armv8: LS2080A: Rename LS2085A to reflect LS2080A

Hi York,

This patch set in top of my previous patches. I did to make sure it can be applied cleanly.

armv8: lsch3: Fix lane protocol parsing logic
driver: net: fsl-mc: Add create, destroy APIs in flibs
driver: net: fsl-mc: Add APIs for DPMAC objects in FLIB
armv8: ls2085aqds: Print function name during SerDes error
driver: ldpaa: Add api to return linked PHY ID of DPMAC
driver: net: fsl-mc: Increase MC command timeout
driver: net: fsl-mc: Add DPAA2 commands to manage MC
driver: net: fsl-mc: Create DPAA2 object at run-time
driver: net: ldpaa: Use DPMAC as net device
driver: net: ldpaa: Add debug information

armv8: ls2085a: Add workaround of errata A009635
driver: net: ldpaa: Fix Rx buffer alignment

Regards,
Prabhakar

Quoted 91 lines

-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Wednesday, November 11, 2015 12:40 AM
To: Kushwaha Prabhakar-B32579 <[email protected]>; u- boot at lists.denx.de
Cc: Srivastava Pratiyush-B46174 <[email protected]>
Subject: Re: [PATCH 1/2][v2] armv8: LS2080A: Rename LS2085A to reflect LS2080A

Quoted 2 lines · Prabhakar Kushwaha

LS2080A is a prime personality of Freescale?s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe

endpoint etc.

Quoted 35 lines

So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava
<[email protected]>

Signed-off-by Prabhakar Kushwaha <[email protected]>

---
Changes for v2: Rebased on LS1043 patch set

 README                                             |  3 +
 arch/arm/Kconfig                                   | 44 +++++++----
 arch/arm/cpu/armv8/fsl-layerscape/Makefile         |  4 +-
 arch/arm/cpu/armv8/fsl-layerscape/README.lsch3     |  4 +-
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c            |  2 +-
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c            |  2 +-
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 11 +++
 .../{ls2085a_serdes.c => ls2080a_serdes.c}         |  0
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            |  2 +-
 arch/arm/cpu/armv8/fsl-layerscape/spl.c            |  4 +-
 arch/arm/dts/Makefile                              |  4 +-
 .../{fsl-ls2085a-qds.dts => fsl-ls2080a-qds.dts}   |  8 +-
 .../{fsl-ls2085a-rdb.dts => fsl-ls2080a-rdb.dts}   |  8 +-
 .../arm/dts/{fsl-ls2085a.dtsi => fsl-ls2080a.dtsi} |  4 +-
arch/arm/include/asm/arch-fsl-layerscape/config.h  |  4 +-
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |  6 +-
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |  2 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  6 +-
 .../{ls2085a_stream_id.h => ls2080a_stream_id.h}   |  4 +-
 arch/arm/include/asm/global_data.h                 |  2 +-
 board/freescale/{ls2085a => ls2080a}/Kconfig       | 12 +--
 board/freescale/ls2080a/MAINTAINERS                |  8 ++
 board/freescale/ls2080a/Makefile                   |  8 ++
 board/freescale/{ls2085a => ls2080a}/README        |  2 +-
 board/freescale/{ls2085a => ls2080a}/ddr.c         |  3 +-
 board/freescale/{ls2085a => ls2080a}/ddr.h         |  0

Quoted 8 lines

 .../{ls2085a/ls2085a.c => ls2080a/ls2080a.c}       |  2 +
 board/freescale/{ls2085ardb => ls2080aqds}/Kconfig |  6 +-
 board/freescale/ls2080aqds/MAINTAINERS             |  8 ++
 .../freescale/{ls2085aqds => ls2080aqds}/Makefile  |  2 +-
board/freescale/{ls2085aqds => ls2080aqds}/README  | 16 ++--
 board/freescale/{ls2085ardb => ls2080aqds}/ddr.c   |  5 +-
 board/freescale/{ls2085aqds => ls2080aqds}/ddr.h   |  0
 board/freescale/{ls2085aqds => ls2080aqds}/eth.c   | 92 +++++++++++-----

------

Quoted 16 lines

 .../ls2085aqds.c => ls2080aqds/ls2080aqds.c}       |  4 +-
 .../ls2080aqds_qixis.h}                            |  0
 board/freescale/{ls2085aqds => ls2080ardb}/Kconfig |  6 +-
 board/freescale/ls2080ardb/MAINTAINERS             |  8 ++
 .../freescale/{ls2085ardb => ls2080ardb}/Makefile  |  2 +-
board/freescale/{ls2085ardb => ls2080ardb}/README  | 12 +--
 board/freescale/{ls2085aqds => ls2080ardb}/ddr.c   |  5 +-
 board/freescale/{ls2085ardb => ls2080ardb}/ddr.h   |  0
 .../eth_ls2085rdb.c => ls2080ardb/eth_ls2080rdb.c} |  2 +-
 .../ls2085ardb.c => ls2080ardb/ls2080ardb.c}       |  4 +-
 .../ls2080ardb_qixis.h}                            |  0
 board/freescale/ls2085a/MAINTAINERS                |  8 --
 board/freescale/ls2085a/Makefile                   |  8 --
 board/freescale/ls2085aqds/MAINTAINERS             |  8 --
 board/freescale/ls2085ardb/MAINTAINERS             |  8 --
 ...ls2085a_emu_defconfig => ls2080a_emu_defconfig} |  2 +-

Quoted 8 lines

...2085a_simu_defconfig => ls2080a_simu_defconfig} |  2 +-
.../{ls2085ardb_defconfig => ls2080aqds_defconfig} |  4 +-
...ds_nand_defconfig => ls2080aqds_nand_defconfig} |  2 +-
.../{ls2085aqds_defconfig => ls2080ardb_defconfig} |  4 +-
...db_nand_defconfig => ls2080ardb_nand_defconfig} |  2 +-
 doc/README.fsl-trustzone-components                |  4 +-
 drivers/ddr/fsl/fsl_ddr_gen4.c                     |  4 +-
 drivers/net/fsl-mc/mc.c                            |  5 +-

Prabhakar,

Are you sure you are using the correct code base? I don't even see function do_fsl_mc().

York

York Sun

2015-11-16 04:54 UTC #3 lore raw

PATCH v2 1/2 armv8: LS2080A: Rename LS2085A to reflect LS2080A

I realized this set depends on another set. Thanks.

York

Sent on a Sprint Samsung Galaxy Note? II

-------- Original message --------
From: Kushwaha Prabhakar-B32579
Date:11/15/2015 8:35 PM (GMT-08:00)
To: Sun York-R58495 , u-boot at lists.denx.de
Cc: Srivastava Pratiyush-B46174
Subject: RE: [PATCH 1/2][v2] armv8: LS2080A: Rename LS2085A to reflect LS2080A

Hi York,

This patch set in top of my previous patches. I did to make sure it can be applied cleanly.

armv8: ls2085a: Add workaround of errata A009635
driver: net: ldpaa: Fix Rx buffer alignment

Regards,
Prabhakar

Quoted 91 lines

Quoted 2 lines · Prabhakar Kushwaha

LS2080A is a prime personality of Freescale?s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe

endpoint etc.

Quoted 35 lines

So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava
<[email protected]>

Signed-off-by Prabhakar Kushwaha <[email protected]>

---
Changes for v2: Rebased on LS1043 patch set

 README                                             |  3 +
 arch/arm/Kconfig                                   | 44 +++++++----
 arch/arm/cpu/armv8/fsl-layerscape/Makefile         |  4 +-
 arch/arm/cpu/armv8/fsl-layerscape/README.lsch3     |  4 +-
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c            |  2 +-
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c            |  2 +-
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 11 +++
 .../{ls2085a_serdes.c => ls2080a_serdes.c}         |  0
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            |  2 +-
 arch/arm/cpu/armv8/fsl-layerscape/spl.c            |  4 +-
 arch/arm/dts/Makefile                              |  4 +-
 .../{fsl-ls2085a-qds.dts => fsl-ls2080a-qds.dts}   |  8 +-
 .../{fsl-ls2085a-rdb.dts => fsl-ls2080a-rdb.dts}   |  8 +-
 .../arm/dts/{fsl-ls2085a.dtsi => fsl-ls2080a.dtsi} |  4 +-
arch/arm/include/asm/arch-fsl-layerscape/config.h  |  4 +-
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |  6 +-
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |  2 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  6 +-
 .../{ls2085a_stream_id.h => ls2080a_stream_id.h}   |  4 +-
 arch/arm/include/asm/global_data.h                 |  2 +-
 board/freescale/{ls2085a => ls2080a}/Kconfig       | 12 +--
 board/freescale/ls2080a/MAINTAINERS                |  8 ++
 board/freescale/ls2080a/Makefile                   |  8 ++
 board/freescale/{ls2085a => ls2080a}/README        |  2 +-
 board/freescale/{ls2085a => ls2080a}/ddr.c         |  3 +-
 board/freescale/{ls2085a => ls2080a}/ddr.h         |  0

Quoted 8 lines

 .../{ls2085a/ls2085a.c => ls2080a/ls2080a.c}       |  2 +
 board/freescale/{ls2085ardb => ls2080aqds}/Kconfig |  6 +-
 board/freescale/ls2080aqds/MAINTAINERS             |  8 ++
 .../freescale/{ls2085aqds => ls2080aqds}/Makefile  |  2 +-
board/freescale/{ls2085aqds => ls2080aqds}/README  | 16 ++--
 board/freescale/{ls2085ardb => ls2080aqds}/ddr.c   |  5 +-
 board/freescale/{ls2085aqds => ls2080aqds}/ddr.h   |  0
 board/freescale/{ls2085aqds => ls2080aqds}/eth.c   | 92 +++++++++++-----

------

Quoted 16 lines

 .../ls2085aqds.c => ls2080aqds/ls2080aqds.c}       |  4 +-
 .../ls2080aqds_qixis.h}                            |  0
 board/freescale/{ls2085aqds => ls2080ardb}/Kconfig |  6 +-
 board/freescale/ls2080ardb/MAINTAINERS             |  8 ++
 .../freescale/{ls2085ardb => ls2080ardb}/Makefile  |  2 +-
board/freescale/{ls2085ardb => ls2080ardb}/README  | 12 +--
 board/freescale/{ls2085aqds => ls2080ardb}/ddr.c   |  5 +-
 board/freescale/{ls2085ardb => ls2080ardb}/ddr.h   |  0
 .../eth_ls2085rdb.c => ls2080ardb/eth_ls2080rdb.c} |  2 +-
 .../ls2085ardb.c => ls2080ardb/ls2080ardb.c}       |  4 +-
 .../ls2080ardb_qixis.h}                            |  0
 board/freescale/ls2085a/MAINTAINERS                |  8 --
 board/freescale/ls2085a/Makefile                   |  8 --
 board/freescale/ls2085aqds/MAINTAINERS             |  8 --
 board/freescale/ls2085ardb/MAINTAINERS             |  8 --
 ...ls2085a_emu_defconfig => ls2080a_emu_defconfig} |  2 +-

Quoted 8 lines

...2085a_simu_defconfig => ls2080a_simu_defconfig} |  2 +-
.../{ls2085ardb_defconfig => ls2080aqds_defconfig} |  4 +-
...ds_nand_defconfig => ls2080aqds_nand_defconfig} |  2 +-
.../{ls2085aqds_defconfig => ls2080ardb_defconfig} |  4 +-
...db_nand_defconfig => ls2080ardb_nand_defconfig} |  2 +-
 doc/README.fsl-trustzone-components                |  4 +-
 drivers/ddr/fsl/fsl_ddr_gen4.c                     |  4 +-
 drivers/net/fsl-mc/mc.c                            |  5 +-

Prabhakar,

Are you sure you are using the correct code base? I don't even see function do_fsl_mc().

York

York Sun

2015-11-23 19:19 UTC #4 lore raw

PATCH v2 1/2 armv8: LS2080A: Rename LS2085A to reflect LS2080A

In reply to Prabhakar Kushwaha

Quoted 8 lines · Prabhakar Kushwaha

LS2080A is a prime personality of Freescale?s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by Pratiyush Mohan Srivastava <[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>
---
Changes for v2: Rebased on LS1043 patch set

<snip>

Quoted 6 lines

arch/arm/include/asm/arch-fsl-layerscape/cpu.h +0 -0
index 2903996..5a91dcb 100644
@@ -8,8 +8,10 @@
 #define _FSL_LAYERSCAPE_CPU_H

arch/arm/include/asm/arch-fsl-layerscape/cpu.h line 17

Quoted 10 lines

arch/arm/include/asm/arch-fsl-layerscape/cpu.h +3 -1

 
 static struct cpu_type cpu_type_list[] = {
-	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
+#ifdef CONFIG_LS2080A
 	CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+#endif
+	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
 	CPU_TYPE_ENTRY(LS2045, LS2045, 4),
 	CPU_TYPE_ENTRY(LS1043, LS1043, 4),
 };

Why using ifdef here?

York

Kushwaha Prabhakar

author

2015-11-24 04:25 UTC #5 lore raw

PATCH v2 1/2 armv8: LS2080A: Rename LS2085A to reflect LS2080A

Quoted 35 lines

-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Tuesday, November 24, 2015 12:49 AM
To: Kushwaha Prabhakar-B32579 <[email protected]>; u- boot at lists.denx.de
Cc: Srivastava Pratiyush-B46174 <[email protected]>
Subject: Re: [PATCH 1/2][v2] armv8: LS2080A: Rename LS2085A to reflect LS2080A
Quoted 2 lines · Prabhakar Kushwaha
LS2080A is a prime personality of Freescale?s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe
endpoint etc.
Quoted 8 lines
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava
<[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>
---
Changes for v2: Rebased on LS1043 patch set
<snip>
Quoted 8 lines
arch/arm/include/asm/arch-fsl-layerscape/cpu.h +0 -0
index 2903996..5a91dcb 100644
@@ -8,8 +8,10 @@
 #define _FSL_LAYERSCAPE_CPU_H
 

Quoted 11 lines

arch/arm/include/asm/arch-fsl-layerscape/cpu.h line 17

Quoted 9 lines

arch/arm/include/asm/arch-fsl-layerscape/cpu.h +3 -1

 static struct cpu_type cpu_type_list[] = {
-	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
+#ifdef CONFIG_LS2080A
 	CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+#endif
+	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
 	CPU_TYPE_ENTRY(LS2045, LS2045, 4),
 	CPU_TYPE_ENTRY(LS1043, LS1043, 4),
 };

Why using ifdef here?

I am trying to reduce size of table.
Instead of adding all SoC in table only defined the required one at a time.

--prabhakar

York Sun

2015-11-24 05:44 UTC #6 lore raw

PATCH v2 1/2 armv8: LS2080A: Rename LS2085A to reflect LS2080A

Quoted 47 lines · On 11/23/2015 08:25 PM, Kushwaha Prabhakar-B32579 wrote:

Quoted 35 lines
-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Tuesday, November 24, 2015 12:49 AM
To: Kushwaha Prabhakar-B32579 <[email protected]>; u- boot at lists.denx.de
Cc: Srivastava Pratiyush-B46174 <[email protected]>
Subject: Re: [PATCH 1/2][v2] armv8: LS2080A: Rename LS2085A to reflect LS2080A
Quoted 2 lines · Prabhakar Kushwaha
LS2080A is a prime personality of Freescale?s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe
endpoint etc.
Quoted 8 lines
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava
<[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>
---
Changes for v2: Rebased on LS1043 patch set
<snip>
Quoted 8 lines
arch/arm/include/asm/arch-fsl-layerscape/cpu.h +0 -0
index 2903996..5a91dcb 100644
@@ -8,8 +8,10 @@
 #define _FSL_LAYERSCAPE_CPU_H
 
Quoted 11 lines
arch/arm/include/asm/arch-fsl-layerscape/cpu.h line 17
Quoted 9 lines
arch/arm/include/asm/arch-fsl-layerscape/cpu.h +3 -1
 static struct cpu_type cpu_type_list[] = {
-	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
+#ifdef CONFIG_LS2080A
 	CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+#endif
+	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
 	CPU_TYPE_ENTRY(LS2045, LS2045, 4),
 	CPU_TYPE_ENTRY(LS1043, LS1043, 4),
 };
Why using ifdef here?

Quoted 2 lines

I am trying to reduce size of table.
Instead of adding all SoC in table only defined the required one at a time.

I thought the plan was to support both LS2080 and LS2085 in one image built for LS2080. We have always used a complete table for cpu list. If you are flexible, I will drop the ifdef when merging this patch.

York

Kushwaha Prabhakar

author

2015-11-24 06:42 UTC #7 lore raw

PATCH v2 1/2 armv8: LS2080A: Rename LS2085A to reflect LS2080A

Quoted 60 lines

-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Tuesday, November 24, 2015 11:14 AM
To: Kushwaha Prabhakar-B32579 <[email protected]>; u- boot at lists.denx.de
Cc: Srivastava Pratiyush-B46174 <[email protected]>
Subject: Re: [PATCH 1/2][v2] armv8: LS2080A: Rename LS2085A to reflect LS2080A
Quoted 47 lines · On 11/23/2015 08:25 PM, Kushwaha Prabhakar-B32579 wrote:
Quoted 46 lines
-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Tuesday, November 24, 2015 12:49 AM
To: Kushwaha Prabhakar-B32579 <[email protected]>; u- boot at lists.denx.de
Cc: Srivastava Pratiyush-B46174 <[email protected]>
Subject: Re: [PATCH 1/2][v2] armv8: LS2080A: Rename LS2085A to reflect LS2080A
Quoted 3 lines · Prabhakar Kushwaha
LS2080A is a prime personality of Freescale?s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe
endpoint etc.
Quoted 8 lines
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava
<[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>
---
Changes for v2: Rebased on LS1043 patch set
<snip>
Quoted 6 lines
arch/arm/include/asm/arch-fsl-layerscape/cpu.h +0 -0
index 2903996..5a91dcb 100644
arch/arm/include/asm/arch-fsl-layerscape/cpu.h line 16
Quoted 10 lines
arch/arm/include/asm/arch-fsl-layerscape/cpu.h +3 -1
@@ -8,8 +8,10 @@
 #define _FSL_LAYERSCAPE_CPU_H
 
 static struct cpu_type cpu_type_list[] = {
-	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
+#ifdef CONFIG_LS2080A
 	CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+#endif
+	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
 	CPU_TYPE_ENTRY(LS2045, LS2045, 4),
 	CPU_TYPE_ENTRY(LS1043, LS1043, 4),  };
Why using ifdef here?

Quoted 7 lines

Quoted 2 lines
I am trying to reduce size of table.
Instead of adding all SoC in table only defined the required one at a time.
I thought the plan was to support both LS2080 and LS2085 in one image built for LS2080. We have always used a complete table for cpu list. If you are flexible, I will drop the ifdef when merging this patch.

Yes, we can drop the ifdef.

--prabhakar

York Sun

2015-11-25 18:51 UTC #8 lore raw

PATCH v2 1/2 armv8: LS2080A: Rename LS2085A to reflect LS2080A

Quoted 63 lines · On 11/23/2015 10:42 PM, Kushwaha Prabhakar-B32579 wrote:

Quoted 63 lines
-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Tuesday, November 24, 2015 11:14 AM
To: Kushwaha Prabhakar-B32579 <[email protected]>; u- boot at lists.denx.de
Cc: Srivastava Pratiyush-B46174 <[email protected]>
Subject: Re: [PATCH 1/2][v2] armv8: LS2080A: Rename LS2085A to reflect LS2080A
Quoted 49 lines · On 11/23/2015 08:25 PM, Kushwaha Prabhakar-B32579 wrote:
Quoted 36 lines
-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Tuesday, November 24, 2015 12:49 AM
To: Kushwaha Prabhakar-B32579 <[email protected]>; u- boot at lists.denx.de
Cc: Srivastava Pratiyush-B46174 <[email protected]>
Subject: Re: [PATCH 1/2][v2] armv8: LS2080A: Rename LS2085A to reflect LS2080A
Quoted 3 lines · Prabhakar Kushwaha
LS2080A is a prime personality of Freescale?s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe
endpoint etc.
Quoted 8 lines
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava
<[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>
---
Changes for v2: Rebased on LS1043 patch set
<snip>
Quoted 8 lines
arch/arm/include/asm/arch-fsl-layerscape/cpu.h +0 -0
index 2903996..5a91dcb 100644
@@ -8,8 +8,10 @@
 #define _FSL_LAYERSCAPE_CPU_H
 
Quoted 10 lines
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
Quoted 8 lines
arch/arm/include/asm/arch-fsl-layerscape/cpu.h +3 -1
 static struct cpu_type cpu_type_list[] = {
-	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
+#ifdef CONFIG_LS2080A
 	CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+#endif
+	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
 	CPU_TYPE_ENTRY(LS2045, LS2045, 4),
 	CPU_TYPE_ENTRY(LS1043, LS1043, 4),  };
Why using ifdef here?
I am trying to reduce size of table.
Instead of adding all SoC in table only defined the required one at a time.

Quoted 7 lines

Quoted 4 lines
I thought the plan was to support both LS2080 and LS2085 in one image built for LS2080. We have always used a complete table for cpu list. If you are flexible, I will drop the ifdef when merging this patch.
Yes, we can drop the ifdef.

Will do.

FYI, when I build the new image for ls2085aqds and run it on QDS, the SoC is "unknown (0x87011010)" with the ifdef in place. That's why I believe the ifdef shouldn't be there.

York

York Sun

2015-11-30 17:10 UTC #9 lore raw

PATCH v2 1/2 armv8: LS2080A: Rename LS2085A to reflect LS2080A

In reply to Prabhakar Kushwaha

Quoted 8 lines · Prabhakar Kushwaha

LS2080A is a prime personality of Freescale?s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by Pratiyush Mohan Srivastava <[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>
---
Changes for v2: Rebased on LS1043 patch set

Dropped #ifdef for table cpu_type_list.
Applied to fsl-qoriq master. Thanks.

York