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Make most DDR non-secure in MMU while keep a small block secure

RFC PATCH Superseded York Sun 3 participants 7 messages Nov 11, 2015 – Nov 12, 2015

Subsystems (2)
Arm (32-bit) Generic include/asm header files

v2 of 7 Superseded Latest is v7 →

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York Sun

author
#0 lore raw

v2 cover Make most DDR non-secure in MMU while keep a small block secure

This set is to change MMU tables so DDR is in non-secure mode that non-secure master such as SDHC DMA can access the data. To mix secure and non-secure MMU entries, the MMU tables themselves have to be in secure memory. A small portion memory is reserved at the end of DDR (before debug server and MC) to host secure application and the MMU tables.

This is different from existing armv7 secure_ram_addr() solution. U-boot can run in the middle of memory if the memory is large. Having security memory at the very end simplifies MMU setup.

Changes in v2:
Do not use CONFIG_SYS_MEM_TOP_HIDE mechanism Move gd->arch.secure_ram to gd->secure_ram. Change the calculation of gd->secure_ram accordingly. Chnage commit message slightly accordingly.

Changes in v1:
Initial patch.
Depends on http://patchwork.ozlabs.org/patch/540248/

York Sun (2):
Reserve secure memory
armv8: fsl-layerscape: Make DDR non secure in MMU tables

 README                                         |    8 ++
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c        |  126 ++++++++++++++++++++++--
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |   12 ++-
 board/freescale/ls2085a/ddr.c                  |   13 +++
 board/freescale/ls2085aqds/ddr.c               |   13 +++
 board/freescale/ls2085ardb/ddr.c               |   13 +++
 common/board_f.c                               |    9 ++
 common/cmd_bdinfo.c                            |    4 +
 include/asm-generic/global_data.h              |    1 +
 include/configs/ls2085a_common.h               |    6 ++
 10 files changed, 192 insertions(+), 13 deletions(-)
Signature · 1 line
1.7.9.5
author
#1 lore raw

RFC PATCH v2 1/2 Reserve secure memory

Secure memory is at the end of memory, separated and reserved from OS, tracked by gd->secure_ram. Secure memory can host MMU tables, security monitor, etc.

Signed-off-by York Sun <[email protected]>

---

Changes in v2:
Do not use CONFIG_SYS_MEM_TOP_HIDE mechanism

Changes in v1:
Initial patch.
Depends on http://patchwork.ozlabs.org/patch/540248/

 README                            |    8 ++++++++
 common/board_f.c                  |    9 +++++++++
 include/asm-generic/global_data.h |    1 +
 include/configs/ls2085a_common.h  |    6 ++++++
 4 files changed, 24 insertions(+)
README +8 -0
index ef8d437..61cbc82 100644
@@ -3881,6 +3881,14 @@ Configuration Settings:
 		Scratch address used by the alternate memory test
 		You only need to set this if address zero isn't writeable
 
+- CONFIG_SYS_MEM_RESERVE_SECURE
+		If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
+		is substracted from total RAM and won't be reported to OS.
+		This memory can be used as secure memory. A variable
+		gd->secure_ram is used to track the location. In systems
+		the RAM base is not zero, or RAM is divided into banks,
+		this variable needs to be recalcuated to get the address.
+
 - CONFIG_SYS_MEM_TOP_HIDE (PPC only):
 		If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header,
 		this specified memory area will get subtracted from the top
common/board_f.c +9 -0
index 725eb18..8061105 100644
@@ -323,6 +323,15 @@ static int setup_dest_addr(void)
 	 * Ram is setup, size stored in gd !!
 	 */
 	debug("Ram size: %08lX\n", (ulong)gd->ram_size);
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+	/* Reserve memory for secure MMU tables, and/or security monitor */
+	gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+	/*
+	 * Record secure memory location. Need recalcuate if memory splits
+	 * into banks, or the ram base is not zero.
+	 */
+	gd->secure_ram = gd->ram_size;
+#endif
 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
 	/*
 	 * Subtract specified amount of memory to hide so that it won't
include/asm-generic/global_data.h +1 -0
index d0383f3..336f3a0 100644
@@ -58,6 +58,7 @@ typedef struct global_data {
 
 	unsigned long relocaddr;	/* Start address of U-Boot in RAM */
 	phys_size_t ram_size;	/* RAM size */
+	phys_addr_t secure_ram;	/* Secure memory addr */
 	unsigned long mon_len;	/* monitor len */
 	unsigned long irq_sp;		/* irq stack pointer */
 	unsigned long start_addr_sp;	/* start_addr_stackpointer */
include/configs/ls2085a_common.h +6 -0
index 0011e72..adf132c 100644
@@ -75,6 +75,12 @@
 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2
 
 /*
+ * Reserve secure memory
+ * To be aligned with MMU block size
+ */
+#define CONFIG_SYS_MEM_RESERVE_SECURE	(2048 * 1024)	/* 2MB */
+
+/*
  * SMP Definitinos
  */
 #define CPU_RELEASE_ADDR		secondary_boot_func
Signature · 1 line
1.7.9.5
#2 lore raw

RFC PATCH v2 1/2 Reserve secure memory

Hi York,

include/asm-generic/global_data.h typedef struct global_data { · line 61

Quoted 9 lines · York Sun
include/asm-generic/global_data.h +1 -0
index d0383f3..336f3a0 100644
@@ -58,6 +58,7 @@ typedef struct global_data {
 
  	unsigned long relocaddr;	/* Start address of U-Boot in RAM */
  	phys_size_t ram_size;	/* RAM size */
+	phys_addr_t secure_ram;	/* Secure memory addr */

Shouldn't this be included only if CONFIG_SYS_MEM_RESERVE_SECURE ?

include/asm-generic/global_data.h typedef struct global_data { · line 64

Quoted 3 lines
include/asm-generic/global_data.h +0 -0
  	unsigned long mon_len;	/* monitor len */
  	unsigned long irq_sp;		/* irq stack pointer */
  	unsigned long start_addr_sp;	/* start_addr_stackpointer */

Best regards,
Thomas

author
#3 lore raw

RFC PATCH v2 1/2 Reserve secure memory

Quoted 9 lines · Thomas Chou

Hi York,

Quoted 6 lines · York Sun
include/asm-generic/global_data.h +0 -0
index d0383f3..336f3a0 100644
@@ -58,6 +58,7 @@ typedef struct global_data {
Quoted 5 lines

include/asm-generic/global_data.h typedef struct global_data { · line 61

Quoted 3 lines
include/asm-generic/global_data.h +1 -0
  	unsigned long relocaddr;	/* Start address of U-Boot in RAM */
  	phys_size_t ram_size;	/* RAM size */
+	phys_addr_t secure_ram;	/* Secure memory addr */

Shouldn't this be included only if CONFIG_SYS_MEM_RESERVE_SECURE ?

It can be. It will require checking CONFIG_SYS_MEM_RESERVE_SECURE every time this variable is used. I will add it in next version.

Thanks.

York

#4 lore raw

RFC PATCH v2 1/2 Reserve secure memory

Quoted 19 lines · York Sun
Quoted 10 lines · Thomas Chou

Hi York,

Quoted 7 lines · York Sun
include/asm renamed from include/asm-generic/global_data.h +0 -1
-generic/global_data.h

index d0383f3..336f3a0 100644

include/asm-generic/global_data.h +0 -0
@@ -58,6 +58,7 @@ typedef struct global_data {
Quoted 6 lines

include/asm-generic/global_data.h typedef struct global_data { · line 61

Quoted 4 lines
include/asm-generic/global_data.h +0 -0
  	unsigned long relocaddr;	/* Start address of U-Boot in

RAM */
phys_size_t ram_size; /* RAM size */

include/asm-generic/global_data.h +1 -0
+	phys_addr_t secure_ram;	/* Secure memory addr */

Shouldn't this be included only if CONFIG_SYS_MEM_RESERVE_SECURE ?

Quoted 2 lines

It can be. It will require checking CONFIG_SYS_MEM_RESERVE_SECURE every time this variable is used. I will add it in next version.

Why would that be better than leaving it unifdeffed?

-Scott

author
#5 lore raw

RFC PATCH v2 1/2 Reserve secure memory

Quoted 20 lines · Scott Wood
Quoted 19 lines · York Sun
Quoted 16 lines · Thomas Chou

Hi York,

include/asm-generic/global_data.h typedef struct global_data { · line 61

Quoted 11 lines · York Sun
include/asm renamed from include/asm-generic/global_data.h +0 -1
-generic/global_data.h

index d0383f3..336f3a0 100644

include/asm-generic/global_data.h +0 -0
@@ -58,6 +58,7 @@ typedef struct global_data {
 
  	unsigned long relocaddr;	/* Start address of U-Boot in

RAM */
phys_size_t ram_size; /* RAM size */

include/asm-generic/global_data.h +1 -0
+	phys_addr_t secure_ram;	/* Secure memory addr */

Shouldn't this be included only if CONFIG_SYS_MEM_RESERVE_SECURE ?

Quoted 4 lines
Quoted 2 lines

It can be. It will require checking CONFIG_SYS_MEM_RESERVE_SECURE every time this variable is used. I will add it in next version.

Why would that be better than leaving it unifdeffed?

Save a few bytes? I prefer not to use ifdef if possible, but I understand some platforms don't want to spare a few bytes.

York

author
#6 lore raw

RFC PATCH v2 2/2 armv8: fsl-layerscape: Make DDR non secure in MMU tables

In reply to York Sun

DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area.

Early MMU tables are changed to set DDR as non-secure. Before setting final MMU tables in secure DDR, existing MMU needs to be updated with a secure DDR entry. A new table is added into final MMU tables so secure memory can have 2MB granuality.

"bdinfo" command shows gd->secure_ram value.

Signed-off-by York Sun <[email protected]>

---

Changes in v2:
Move gd->arch.secure_ram to gd->secure_ram. Change the calculation of gd->secure_ram accordingly. Chnage commit message slightly accordingly.

Changes in v1: None

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c        |  126 ++++++++++++++++++++++--
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |   12 ++-
 board/freescale/ls2085a/ddr.c                  |   13 +++
 board/freescale/ls2085aqds/ddr.c               |   13 +++
 board/freescale/ls2085ardb/ddr.c               |   13 +++
 common/cmd_bdinfo.c                            |    4 +
 6 files changed, 168 insertions(+), 13 deletions(-)
arch/arm/cpu/armv8/fsl-layerscape/cpu.c +117 -9
index 9d1c70f..a372b3f 100644
@@ -207,10 +207,86 @@ static inline void early_mmu_setup(void)
 }
 
 /*
+ * Called from early mmu setup. The phys_addr needs to be in
+ * the table and aligned. This function sets the block to secure.
+ */
+static inline int fixup_early_secure_ddr(u64 *level0_table,
+					 phys_addr_t phys_addr)
+{
+	int ret = 0;
+#ifdef CONFIG_FSL_PPA_RESERVED_DRAM_SIZE
+	struct table_info table = {};
+	struct sys_mmu_table ddr_entry = {
+		0, 0, BLOCK_SIZE_L1, MT_NORMAL, PMD_SECT_OUTER_SHARE
+	};
+
+	ddr_entry.virt_addr = phys_addr;
+	ddr_entry.phys_addr = phys_addr;
+	ret = find_table(&ddr_entry, &table, level0_table);
+	if (!ret)
+		ret = set_block_entry(&ddr_entry, &table);
+#endif
+
+	return ret;
+}
+/*
+ * Called from final mmu setup. The phys_addr is new, non-existing
+ * address. A new sub table is created @level2_table_secure.
+ */
+static inline int final_secure_ddr(u64 *level0_table,
+				   u64 *level2_table_secure,
+				   phys_addr_t phys_addr)
+{
+	int ret = 0;
+#ifdef CONFIG_FSL_PPA_RESERVED_DRAM_SIZE
+	struct table_info table = {};
+	struct sys_mmu_table ddr_entry = {
+		0, 0, BLOCK_SIZE_L1, MT_NORMAL,
+		PMD_SECT_OUTER_SHARE | PMD_SECT_NS
+	};
+	u64 index;
+
+	/* Need to create a new table */
+	ddr_entry.virt_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1);
+	ddr_entry.phys_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1);
+	ret = find_table(&ddr_entry, &table, level0_table);
+	if (ret)
+		return ret;
+	index = (ddr_entry.virt_addr - table.table_base) >> SECTION_SHIFT_L1;
+	set_pgtable_table(table.ptr, index, level2_table_secure);
+	table.ptr = level2_table_secure;
+	table.table_base = ddr_entry.virt_addr;
+	table.entry_size = BLOCK_SIZE_L2;
+	ret = set_block_entry(&ddr_entry, &table);
+	if (ret) {
+		printf("MMU error: could not fill non-secure ddr block entries\n");
+		return ret;
+	}
+	ddr_entry.virt_addr = phys_addr;
+	ddr_entry.phys_addr = phys_addr;
+	ddr_entry.size = CONFIG_FSL_PPA_RESERVED_DRAM_SIZE;
+	ddr_entry.attribute = PMD_SECT_OUTER_SHARE;
+	ret = find_table(&ddr_entry, &table, level0_table);
+	if (ret) {
+		printf("MMU error: could not find secure ddr table\n");
+		return ret;
+	}
+	ret = set_block_entry(&ddr_entry, &table);
+	if (ret)
+		printf("MMU error: could not set secure ddr block entry\n");
+#endif
+
+	return ret;
+}
+
+/*
  * The final tables look similar to early tables, but different in detail.
  * These tables are in DRAM. Sub tables are added to enable cache for
  * QBMan and OCRAM.
  *
+ * Put the MMU table in secure memory if gd->secure_ram is set.
+ * OCRAM will be not used for this purpose so gd->secure_ram can't be 0.
+ *
  * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB.
  * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB.
  * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB.

@@ -224,17 +300,35 @@ static inline void early_mmu_setup(void)
 static inline void final_mmu_setup(void)
 {
 	unsigned int el, i;
-	u64 *level0_table = (u64 *)gd->arch.tlb_addr;
-	u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000);
-	u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000);
-	u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
-#ifdef CONFIG_FSL_LSCH3
-	u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
-#elif defined(CONFIG_FSL_LSCH2)
-	u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
-	u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000);
+	u64 *level0_table = gd->secure_ram ? (u64 *)gd->secure_ram
+					   : (u64 *)gd->arch.tlb_addr;
+	u64 *level1_table0 = level0_table + 512;
+	u64 *level1_table1 = level1_table0 + 512;
+	u64 *level2_table0 = level1_table1 + 512;
+	u64 *level2_table1 = level2_table0 + 512;
+#ifdef CONFIG_FSL_LSCH2
+	u64 *level2_table2 = level2_table1 + 512;
 #endif
+	u64 *level2_table_secure;
 	struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
+	u64 secure_ram = gd->secure_ram & ~(BLOCK_SIZE_L1 - 1);
+
+	/*
+	 * Modify the early MMU table to create a secure memory
+	 * to host the table
+	 */
+	if (!fixup_early_secure_ddr((u64 *)CONFIG_SYS_FSL_OCRAM_BASE,
+				    secure_ram)) {
+		flush_dcache_range(CONFIG_SYS_FSL_OCRAM_BASE,
+				   CONFIG_SYS_FSL_OCRAM_BASE + 0x5000);
+		asm volatile(
+			"tlbi vae3, %0\n"
+			"dsb sy\n"
+			"isb"
+			: : "r" (secure_ram) : "memory");
+	} else {
+		printf("MMU error: Failed to create early MMU secure DDR\n");
+	}
 
 	/* Invalidate all table entries */
 	memset(level0_table, 0, PGTABLE_SIZE);

@@ -269,6 +363,20 @@ static inline void final_mmu_setup(void)
 			       &final_mmu_table[i]);
 		}
 	}
+	/* Set the PPA memory to secure */
+	if (gd->secure_ram) {
+#ifdef CONFIG_FSL_LSCH3
+		level2_table_secure = level2_table1 + 512;
+#elif defined(CONFIG_FSL_LSCH2)
+		level2_table_secure = level2_table2 + 512;
+#endif
+		/* update tlb pointer */
+		gd->arch.tlb_addr = gd->secure_ram;
+		if (!final_secure_ddr(level0_table,
+				      level2_table_secure,
+				      gd->secure_ram))
+			gd->secure_ram |= 1;	/* set the valid flag */
+	}
 
 	/* flush new MMU table */
 	flush_dcache_range(gd->arch.tlb_addr,
arch/arm/include/asm/arch-fsl-layerscape/cpu.h +8 -4
index b4b85a8..a13a3d3 100644
@@ -129,12 +129,14 @@ static const struct sys_mmu_table early_mmu_table[] = {
 	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 	  CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
+	  PMD_SECT_OUTER_SHARE | PMD_SECT_NS},
 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
 	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
+	  PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
 #elif defined(CONFIG_FSL_LSCH2)
 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,

@@ -161,7 +163,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
+	  PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
 	{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 	  CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
 	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },

@@ -208,7 +211,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
 	  CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE,
 	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
+	  PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
 #elif defined(CONFIG_FSL_LSCH2)
 	{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 	  CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE,
board/freescale/ls2085a/ddr.c +13 -0
index 4884fa2..c68819d 100644
@@ -174,14 +174,27 @@ void dram_init_banksize(void)
 	phys_size_t dp_ddr_size;
 #endif
 
+	/*
+	 * gd->secure_ram tracks the location of secure memory.
+	 * It was set as if the memory starts from 0.
+	 * The address needs to add the offset of its bank.
+	 */
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
 		gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
 		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
 		gd->bd->bi_dram[1].size = gd->ram_size -
 					  CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+		gd->secure_ram = gd->bd->bi_dram[1].start +
+				 gd->secure_ram -
+				 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+#endif
 	} else {
 		gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+		gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
+#endif
 	}
 
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
board/freescale/ls2085aqds/ddr.c +13 -0
index 8d71ae1..c7aaf3e 100644
@@ -164,14 +164,27 @@ void dram_init_banksize(void)
 	phys_size_t dp_ddr_size;
 #endif
 
+	/*
+	 * gd->secure_ram tracks the location of secure memory.
+	 * It was set as if the memory starts from 0.
+	 * The address needs to add the offset of its bank.
+	 */
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
 		gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
 		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
 		gd->bd->bi_dram[1].size = gd->ram_size -
 					  CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+		gd->secure_ram = gd->bd->bi_dram[1].start +
+				 gd->secure_ram -
+				 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+#endif
 	} else {
 		gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+		gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
+#endif
 	}
 
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
board/freescale/ls2085ardb/ddr.c +13 -0
index 8d71ae1..c7aaf3e 100644
@@ -164,14 +164,27 @@ void dram_init_banksize(void)
 	phys_size_t dp_ddr_size;
 #endif
 
+	/*
+	 * gd->secure_ram tracks the location of secure memory.
+	 * It was set as if the memory starts from 0.
+	 * The address needs to add the offset of its bank.
+	 */
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
 		gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
 		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
 		gd->bd->bi_dram[1].size = gd->ram_size -
 					  CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+		gd->secure_ram = gd->bd->bi_dram[1].start +
+				 gd->secure_ram -
+				 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+#endif
 	} else {
 		gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+		gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
+#endif
 	}
 
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
common/cmd_bdinfo.c +4 -0
index adda55a..73530b6 100644
@@ -382,6 +382,10 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
 		print_num("-> size",	bd->bi_dram[i].size);
 	}
 
+#ifdef CONFIG_FSL_LAYERSCAPE
+	if (gd->secure_ram & 0x1)
+		print_num("Secure ram", gd->secure_ram & ~1);
+#endif
 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
 	print_eths();
 #endif
Signature · 1 line
1.7.9.5