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am43xx: Enable QUAD mode and DMA support for QSPI

PATCH New Vignesh R 3 participants 12 messages Nov 10, 2015 – Nov 17, 2015

Subsystems (2)
Arm (32-bit) SPI
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Vignesh R

author
#0 lore raw

cover am43xx: Enable QUAD mode and DMA support for QSPI

This patchset enables QUAD mode and DMA support for qspi read on am437x. This increases the througput to 4 MB/s.

Tested on am437x-sk and am437x-idk evm.

Vignesh R (2):
spi: ti_qspi: Add dummy readl for bus sync
ARM: am437xx: Enable QUAD read and EDMA support for ti_qspi

 arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 3 +++
 drivers/spi/ti_qspi.c                              | 2 ++
 include/configs/am43xx_evm.h                       | 2 ++
 3 files changed, 7 insertions(+)
Signature · 1 line
2.6.3
author
#1 lore raw

PATCH 1/2 spi: ti_qspi: Add dummy readl for bus sync

Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms.

Signed-off-by Vignesh R <[email protected]>
---
 drivers/spi/ti_qspi.c | 2 ++
 1 file changed, 2 insertions(+)
drivers/spi/ti_qspi.c +2 -0
index bd63db8a2acc..ba2da017c21a 100644
@@ -170,6 +170,8 @@ void spi_cs_deactivate(struct spi_slave *slave)
 	debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
 
 	writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
+	/* dummy readl to ensure bus sync */
+	readl(&qslave->base->cmd);
 }
 
 void spi_init(void)
Signature · 1 line
2.6.3
#2 lore raw

PATCH 1/2 spi: ti_qspi: Add dummy readl for bus sync

Quoted 7 lines · Vignesh R

Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms.

Signed-off-by Vignesh R <[email protected]>

---

Reviewed-by Mugunthan V N <[email protected]>

Regards
Mugunthan V N

#3 lore raw

PATCH 1/2 spi: ti_qspi: Add dummy readl for bus sync

In reply to Vignesh R
Quoted 15 lines · Vignesh R

Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms.

Signed-off-by Vignesh R <[email protected]>
---
 drivers/spi/ti_qspi.c | 2 ++
 1 file changed, 2 insertions(+)
drivers/spi/ti_qspi.c +0 -0
index bd63db8a2acc..ba2da017c21a 100644

drivers/spi/ti_qspi.c void spi_cs_deactivate(struct spi_slave *slave) · line 174

Quoted 5 lines
drivers/spi/ti_qspi.c +2 -0
@@ -170,6 +170,8 @@ void spi_cs_deactivate(struct spi_slave *slave)
        debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
 
        writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
+       /* dummy readl to ensure bus sync */
+       readl(&qslave->base->cmd);

Isn't effect anything for non-quad case? and dummy bytes might changed based on quad and quadio does this single dummy readl is same for those cases as well?

thanks!

Signature · 1 line
Jagan | openedev.
author
#4 lore raw

PATCH 1/2 spi: ti_qspi: Add dummy readl for bus sync

Quoted 18 lines · Jagan Teki
Quoted 17 lines · Vignesh R

Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms.

Signed-off-by Vignesh R <[email protected]>
---
 drivers/spi/ti_qspi.c | 2 ++
 1 file changed, 2 insertions(+)
drivers/spi/ti_qspi.c +0 -0
index bd63db8a2acc..ba2da017c21a 100644
@@ -170,6 +170,8 @@ void spi_cs_deactivate(struct spi_slave *slave)
        debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
Quoted 7 lines

drivers/spi/ti_qspi.c void spi_cs_deactivate(struct spi_slave *slave) · line 174

Quoted 3 lines
drivers/spi/ti_qspi.c +2 -0
        writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
+       /* dummy readl to ensure bus sync */
+       readl(&qslave->base->cmd);

Isn't effect anything for non-quad case? and dummy bytes might changed based on quad and quadio does this single dummy readl is same for those cases as well?

No, this dummy readl is not related as dummy bytes used in QUAD mode.

In ti_qspi controller, in order to end a read/write request (ie to deassert ChipSelect) invalid cmd(0x4) needs to be written to CMD field of QSPI_CMD_REG (which is done by above function) in all modes. Sometimes, this write may have been flushed out of ARM but may not have reached the QSPI IP yet (ie bus/interconnect is not flushed yet) hence ChipSelect is not deactivated. Therefore, the successive write/read operation may overlaps resulting in wrong data being read from flash. Reading back QSPI_CMD_REG makes sure that the bus/interconnect is flushed and register write is affected making sure CS is deactivated.

Signature · 2 lines
Regards
Vignesh
#5 lore raw

PATCH 1/2 spi: ti_qspi: Add dummy readl for bus sync

Quoted 31 lines · Vignesh R
Quoted 18 lines · Jagan Teki
Quoted 17 lines · Vignesh R

Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms.

Signed-off-by Vignesh R <[email protected]>
---
 drivers/spi/ti_qspi.c | 2 ++
 1 file changed, 2 insertions(+)
drivers/spi/ti_qspi.c +0 -0
index bd63db8a2acc..ba2da017c21a 100644
@@ -170,6 +170,8 @@ void spi_cs_deactivate(struct spi_slave *slave)
        debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
Quoted 7 lines

drivers/spi/ti_qspi.c void spi_cs_deactivate(struct spi_slave *slave) · line 174

Quoted 3 lines
drivers/spi/ti_qspi.c +2 -0
        writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
+       /* dummy readl to ensure bus sync */
+       readl(&qslave->base->cmd);

Isn't effect anything for non-quad case? and dummy bytes might changed based on quad and quadio does this single dummy readl is same for those cases as well?

No, this dummy readl is not related as dummy bytes used in QUAD mode.

Quoted 9 lines

In ti_qspi controller, in order to end a read/write request (ie to deassert ChipSelect) invalid cmd(0x4) needs to be written to CMD field of QSPI_CMD_REG (which is done by above function) in all modes. Sometimes, this write may have been flushed out of ARM but may not have reached the QSPI IP yet (ie bus/interconnect is not flushed yet) hence ChipSelect is not deactivated. Therefore, the successive write/read operation may overlaps resulting in wrong data being read from flash. Reading back QSPI_CMD_REG makes sure that the bus/interconnect is flushed and register write is affected making sure CS is deactivated.

Thanks for the info.

Reviewed-by Jagan Teki <[email protected]>
Signature · 1 line
Jagan.
#6 lore raw

PATCH 1/2 spi: ti_qspi: Add dummy readl for bus sync

Quoted 42 lines · Jagan Teki
Quoted 31 lines · Vignesh R
Quoted 18 lines · Jagan Teki
Quoted 17 lines · Vignesh R

Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms.

Signed-off-by Vignesh R <[email protected]>
---
 drivers/spi/ti_qspi.c | 2 ++
 1 file changed, 2 insertions(+)
drivers/spi/ti_qspi.c +0 -0
index bd63db8a2acc..ba2da017c21a 100644
@@ -170,6 +170,8 @@ void spi_cs_deactivate(struct spi_slave *slave)
        debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
Quoted 7 lines

drivers/spi/ti_qspi.c void spi_cs_deactivate(struct spi_slave *slave) · line 174

Quoted 3 lines
drivers/spi/ti_qspi.c +2 -0
        writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
+       /* dummy readl to ensure bus sync */
+       readl(&qslave->base->cmd);

Isn't effect anything for non-quad case? and dummy bytes might changed based on quad and quadio does this single dummy readl is same for those cases as well?

No, this dummy readl is not related as dummy bytes used in QUAD mode.

Quoted 9 lines

In ti_qspi controller, in order to end a read/write request (ie to deassert ChipSelect) invalid cmd(0x4) needs to be written to CMD field of QSPI_CMD_REG (which is done by above function) in all modes. Sometimes, this write may have been flushed out of ARM but may not have reached the QSPI IP yet (ie bus/interconnect is not flushed yet) hence ChipSelect is not deactivated. Therefore, the successive write/read operation may overlaps resulting in wrong data being read from flash. Reading back QSPI_CMD_REG makes sure that the bus/interconnect is flushed and register write is affected making sure CS is deactivated.

Quoted 3 lines

Thanks for the info.

Reviewed-by Jagan Teki <[email protected]>

Applied to u-boot-spi/master

thanks!

Signature · 1 line
Jagan | openedev.
author
#7 lore raw

PATCH 2/2 ARM: am43xx: Enable QUAD read and EDMA support for ti_qspi

In reply to Vignesh R

Enable TI_EDMA3 and QUAD read support for ti_qspi on am43xx, this increases read performance to 4 MB/s.

Signed-off-by Vignesh R <[email protected]>
---
 arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 3 +++
 include/configs/am43xx_evm.h                       | 2 ++
 2 files changed, 5 insertions(+)
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +3 -0
index 479893e47ea1..a7da6b5cfde6 100644
@@ -98,4 +98,7 @@
 
 #define NUM_CRYSTAL_FREQ			0x4
 
+/* EDMA3 Base Address */
+#define EDMA3_BASE				0x49000000
+
 #endif /* __AM43XX_HARDWARE_AM43XX_H */
include/configs/am43xx_evm.h +2 -0
index d93e3e7619d9..e235fd9a0e79 100644
@@ -220,6 +220,8 @@
 #define CONFIG_QSPI_SEL_GPIO                   48
 #define CONFIG_SF_DEFAULT_SPEED                48000000
 #define CONFIG_DEFAULT_SPI_MODE                SPI_MODE_3
+#define CONFIG_QSPI_QUAD_SUPPORT
+#define CONFIG_TI_EDMA3
 
 /* Enhance our eMMC support / experience. */
 #define CONFIG_CMD_GPT
Signature · 1 line
2.6.3
#10 lore raw

PATCH 2/2 ARM: am43xx: Enable QUAD read and EDMA support for ti_qspi

Quoted 11 lines · Jagan Teki
Quoted 8 lines · Mugunthan V N
Quoted 5 lines · Vignesh R

Enable TI_EDMA3 and QUAD read support for ti_qspi on am43xx, this increases read performance to 4 MB/s.

Signed-off-by Vignesh R <[email protected]>

---

Reviewed-by Mugunthan V N <[email protected]>
Reviewed-by Jagan Teki <[email protected]>

Applied to u-boot-spi/master

thanks!

Signature · 1 line
Jagan | openedev.
author
#11 lore raw

cover am43xx: Enable QUAD mode and DMA support for QSPI

In reply to Vignesh R
Quoted 5 lines · Vignesh R

This patchset enables QUAD mode and DMA support for qspi read on am437x. This increases the througput to 4 MB/s.

Tested on am437x-sk and am437x-idk evm.

Quoted 9 lines

Vignesh R (2):
spi: ti_qspi: Add dummy readl for bus sync
ARM: am437xx: Enable QUAD read and EDMA support for ti_qspi

 arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 3 +++
 drivers/spi/ti_qspi.c                              | 2 ++
 include/configs/am43xx_evm.h                       | 2 ++
 3 files changed, 7 insertions(+)

Gentle ping on the series...

Signature · 2 lines
Regards
Vignesh