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ls102x: add soc version function

PATCH New Shengzhou Liu 2 participants 3 messages Nov 19, 2015 Arm (32-bit)

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Shengzhou Liu

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#0 lore raw

PATCH 1/2 ls102x: add soc version function

Add get_svr_ver_major() and get_svr_ver_minor() helper.

Signed-off-by Shengzhou Liu <[email protected]>
---
 arch/arm/cpu/armv7/ls102xa/cpu.c                  | 14 ++++++++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  3 +++
 2 files changed, 17 insertions(+)
arch/arm/cpu/armv7/ls102xa/cpu.c +14 -0
index 14ae2a3..9253ea3 100644
@@ -209,6 +209,20 @@ void enable_caches(void)
 }
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
+u32 get_svr_ver_major(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	return SVR_MAJ(in_be32(&gur->svr));
+}
+
+u32 get_svr_ver_minor(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	return SVR_MIN(in_be32(&gur->svr));
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +3 -0
index c59c93a..4a996b8 100644
@@ -427,4 +427,7 @@ struct ccsr_ahci {
 	u32 pberr;	/* port 0/1 BIST error */
 	u32 cmds;	/* port 0/1 CMD status error */
 };
+
+u32 get_svr_ver_major(void);
+u32 get_svr_ver_minor(void);
 #endif	/* __ASM_ARCH_LS102XA_IMMAP_H_ */
Signature · 1 line
2.1.0.27.g96db324
author
#1 lore raw

PATCH 2/2 fsl/ddr: updated ddr errata-A008378 on ls102x

DDR Errata A008378 only exists on LS102x Rev1, it has been fixed on LS102x Rev2.

Signed-off-by Shengzhou Liu <[email protected]>
---
 drivers/ddr/fsl/arm_ddr_gen3.c | 11 +++++++++++
 drivers/ddr/fsl/fsl_ddr_gen4.c |  9 ++++++---
 2 files changed, 17 insertions(+), 3 deletions(-)
drivers/ddr/fsl/arm_ddr_gen3.c +11 -0
index c139da6..e059b83 100644
@@ -152,6 +152,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		}
 	}
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
+#include <asm/arch-ls102xa/immap_ls102xa.h>
+#define IS_ACC_ECC_EN(v) ((v) & 0x4)
+#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
+	if (get_svr_ver_major() < 2) {
+		if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
+		    IS_DBI(regs->ddr_sdram_cfg_3))
+			ddr_setbits32(ddr->debug[28], 0x9 << 20);
+	}
+#endif
+
 	/*
 	 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 	 * deasserted. Clocks start when any chip select is enabled and clock
drivers/ddr/fsl/fsl_ddr_gen4.c +6 -3
index 4eef047..0b0bcd2 100644
@@ -172,12 +172,15 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		}
 	}
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378
+#include <asm/arch-ls102xa/immap_ls102xa.h>
 	/* Erratum applies when accumulated ECC is used, or DBI is enabled */
 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
-	if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
-	    IS_DBI(regs->ddr_sdram_cfg_3))
-		ddr_setbits32(ddr->debug[28], 0x9 << 20);
+	if (get_svr_ver_major() < 2) {
+		if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
+		    IS_DBI(regs->ddr_sdram_cfg_3))
+			ddr_setbits32(ddr->debug[28], 0x9 << 20);
+	}
 #endif
 
 	/*
Signature · 1 line
2.1.0.27.g96db324
#2 lore raw

PATCH 2/2 fsl/ddr: updated ddr errata-A008378 on ls102x

Quoted 2 lines · Shengzhou Liu

DDR Errata A008378 only exists on LS102x Rev1, it has been fixed on LS102x Rev2.

Shengzhou,

I have different document for this erratum. We will discuss internally.

York