sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3

PATCH New Siarhei Siamashka 3 participants 4 messages Nov 20, 2015

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Arm (32-bit) Arm/Allwinner sunXi SoC support

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Siarhei Siamashka

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2015-11-20 05:07 UTC #0 lore raw

PATCH 1/1 sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3

The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz on Allwinner H3 and using PLL6 as the clock source (PLL6/3). This can be verified by reading the value of the AHB1_APB1_CFG_REG register via /dev/mem. It always reads as 0x3180 regardless of the current cpufreq operating point. So this configuration should be safe for use in U-Boot too.

PLL6 also needs to be configured before it is used as the clock source, according to the "CCU / Programming Guidelines" section of the Allwinner manual.

The current low AHB1 clock speed is limiting the USB transfer speed when booting via FEL. This patch can increase the FEL USB transfer speed from ~510 KB/s to ~950 KB/s.

Signed-off-by Siarhei Siamashka <[email protected]>

---

This is intended to be used together with the Allwinner H3 patches from Jens Kuske:

    http://lists.denx.de/pipermail/u-boot/2015-November/234589.html

Allwinner A83T is likely using the same 200MHz AHB1 setup:

    https://github.com/allwinner-zh/bootloader/blob/e5ceeca21188/basic_loader/bsp/bsp_for_a83/common/common.c#L101

I can successfully boot my A31s based tablet with 200MHz AHB1 clock speed too. And this also speeds up FEL USB transfers. However I can't check what kind of AHB1 configuration is used by the Android firmware without rooting it first, which I wouldn't do at the moment.

 arch/arm/cpu/armv7/sunxi/clock_sun6i.c        | 6 ++++--
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 7 ++++++-
 2 files changed, 10 insertions(+), 3 deletions(-)

arch/arm/cpu/armv7/sunxi/clock_sun6i.c +4 -2

index 3ab3b31..916ee48 100644
@@ -34,9 +34,11 @@ void clock_init_safe(void)
 
 	clock_set_pll1(408000000);
 
-	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
-
 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+	while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
+		;
+
+	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
 
 	writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
 	writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);

arch/arm/include/asm/arch-sunxi/clock_sun6i.h +6 -1

index 584d351..09337a1 100644
@@ -201,6 +201,7 @@ struct sunxi_ccm_reg {
 #define CCM_PLL6_CTRL_N_MASK		(0x1f << CCM_PLL6_CTRL_N_SHIFT)
 #define CCM_PLL6_CTRL_K_SHIFT		4
 #define CCM_PLL6_CTRL_K_MASK		(0x3 << CCM_PLL6_CTRL_K_SHIFT)
+#define CCM_PLL6_CTRL_LOCK		(1 << 28)
 
 #define CCM_MIPI_PLL_CTRL_M_SHIFT	0
 #define CCM_MIPI_PLL_CTRL_M_MASK	(0xf << CCM_MIPI_PLL_CTRL_M_SHIFT)

@@ -219,7 +220,11 @@ struct sunxi_ccm_reg {
 #define CCM_PLL11_CTRL_UPD		(0x1 << 30)
 #define CCM_PLL11_CTRL_EN		(0x1 << 31)
 
-#define AHB1_ABP1_DIV_DEFAULT		0x00002020
+#if defined CONFIG_MACH_SUN8I_H3
+#define AHB1_ABP1_DIV_DEFAULT		0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
+#else
+#define AHB1_ABP1_DIV_DEFAULT		0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */
+#endif
 
 #define AXI_GATE_OFFSET_DRAM		0

Signature · 1 line

2.4.10

Hans de Goede

2015-11-20 15:40 UTC #1 lore raw

PATCH 1/1 sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3

Hi,

Quoted 15 lines · Siarhei Siamashka

The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz on Allwinner H3 and using PLL6 as the clock source (PLL6/3). This can be verified by reading the value of the AHB1_APB1_CFG_REG register via /dev/mem. It always reads as 0x3180 regardless of the current cpufreq operating point. So this configuration should be safe for use in U-Boot too.
PLL6 also needs to be configured before it is used as the clock source, according to the "CCU / Programming Guidelines" section of the Allwinner manual.
The current low AHB1 clock speed is limiting the USB transfer speed when booting via FEL. This patch can increase the FEL USB transfer speed from ~510 KB/s to ~950 KB/s.

Quoted 6 lines

Signed-off-by Siarhei Siamashka <[email protected]>
---
This is intended to be used together with the Allwinner H3 patches from Jens Kuske:
     http://lists.denx.de/pipermail/u-boot/2015-November/234589.html

Thanks, I've applied this patch to my tree, and it will be part of the next pull-req.

Regards,

Hans

Quoted 57 lines

Allwinner A83T is likely using the same 200MHz AHB1 setup:

     https://github.com/allwinner-zh/bootloader/blob/e5ceeca21188/basic_loader/bsp/bsp_for_a83/common/common.c#L101

  arch/arm/cpu/armv7/sunxi/clock_sun6i.c        | 6 ++++--
  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 7 ++++++-
  2 files changed, 10 insertions(+), 3 deletions(-)

arch/arm/cpu/armv7/sunxi/clock_sun6i.c +4 -2

index 3ab3b31..916ee48 100644
@@ -34,9 +34,11 @@ void clock_init_safe(void)
 
  	clock_set_pll1(408000000);
 
-	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
-
  	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+	while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
+		;
+
+	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
 
  	writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
  	writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);

arch/arm/include/asm/arch-sunxi/clock_sun6i.h +6 -1

index 584d351..09337a1 100644
@@ -201,6 +201,7 @@ struct sunxi_ccm_reg {
  #define CCM_PLL6_CTRL_N_MASK		(0x1f << CCM_PLL6_CTRL_N_SHIFT)
  #define CCM_PLL6_CTRL_K_SHIFT		4
  #define CCM_PLL6_CTRL_K_MASK		(0x3 << CCM_PLL6_CTRL_K_SHIFT)
+#define CCM_PLL6_CTRL_LOCK		(1 << 28)
 
  #define CCM_MIPI_PLL_CTRL_M_SHIFT	0
  #define CCM_MIPI_PLL_CTRL_M_MASK	(0xf << CCM_MIPI_PLL_CTRL_M_SHIFT)

@@ -219,7 +220,11 @@ struct sunxi_ccm_reg {
  #define CCM_PLL11_CTRL_UPD		(0x1 << 30)
  #define CCM_PLL11_CTRL_EN		(0x1 << 31)
 
-#define AHB1_ABP1_DIV_DEFAULT		0x00002020
+#if defined CONFIG_MACH_SUN8I_H3
+#define AHB1_ABP1_DIV_DEFAULT		0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
+#else
+#define AHB1_ABP1_DIV_DEFAULT		0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */
+#endif
 
  #define AXI_GATE_OFFSET_DRAM		0

Chen-Yu Tsai

2015-11-20 16:04 UTC #2 lore raw

PATCH 1/1 sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3

Quoted 22 lines · Hans de Goede

Hi,
Quoted 19 lines · Siarhei Siamashka
The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz on Allwinner H3 and using PLL6 as the clock source (PLL6/3). This can be verified by reading the value of the AHB1_APB1_CFG_REG register via /dev/mem. It always reads as 0x3180 regardless of the current cpufreq operating point. So this configuration should be safe for use in U-Boot too.
PLL6 also needs to be configured before it is used as the clock source, according to the "CCU / Programming Guidelines" section of the Allwinner manual.
The current low AHB1 clock speed is limiting the USB transfer speed when booting via FEL. This patch can increase the FEL USB transfer speed from ~510 KB/s to ~950 KB/s.
Signed-off-by Siarhei Siamashka <[email protected]>
---

Quoted 7 lines

Quoted 3 lines
This is intended to be used together with the Allwinner H3 patches from Jens Kuske:
     http://lists.denx.de/pipermail/u-boot/2015-November/234589.html
Thanks, I've applied this patch to my tree, and it will be part of the next pull-req.

Can we do this for all SoCs? Starting with the ones that use clock_sun6i?

A31/A31s already are clocking AHB1 from PLL6 in Linux, albeit at 150 MHz instead of 200 MHz, since it is just reparenting, and not setting a new value for the divider or pre-divider. IIRC A23 SDK also clocks AHB1 from PLL6, but the mainline kernel hasn't adopted it. We can just drop the "#if defined CONFIG_MACH_SUN8I_H3" from clock_sun6i.h.

Also, user manuals of the earlier generation SoCs (sun[457]i) list the clock rate range for the various buses. I think we can assume the range has not changed for AHB/APB clocks. The maximum rate for these two are 276 MHz and 138 MHz, respectively.

Thanks
ChenYu

Quoted 63 lines

Quoted 62 lines

Allwinner A83T is likely using the same 200MHz AHB1 setup:

https://github.com/allwinner-zh/bootloader/blob/e5ceeca21188/basic_loader/bsp/bsp_for_a83/common/common.c#L101

  arch/arm/cpu/armv7/sunxi/clock_sun6i.c        | 6 ++++--
  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 7 ++++++-
  2 files changed, 10 insertions(+), 3 deletions(-)

arch/arm/cpu/armv7/sunxi/clock_sun6i.c +4 -2

index 3ab3b31..916ee48 100644
@@ -34,9 +34,11 @@ void clock_init_safe(void)
 
        clock_set_pll1(408000000);
 
-       writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
-
        writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+       while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
+               ;
+
+       writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
 
        writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
        writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);

arch/arm/include/asm/arch-sunxi/clock_sun6i.h +3 -1

index 584d351..09337a1 100644
@@ -201,6 +201,7 @@ struct sunxi_ccm_reg {
  #define CCM_PLL6_CTRL_N_MASK          (0x1f << CCM_PLL6_CTRL_N_SHIFT)
  #define CCM_PLL6_CTRL_K_SHIFT         4
  #define CCM_PLL6_CTRL_K_MASK          (0x3 << CCM_PLL6_CTRL_K_SHIFT)
+#define CCM_PLL6_CTRL_LOCK             (1 << 28)
 
  #define CCM_MIPI_PLL_CTRL_M_SHIFT     0
  #define CCM_MIPI_PLL_CTRL_M_MASK      (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT)

@@ -219,7 +220,11 @@ struct sunxi_ccm_reg {
  #define CCM_PLL11_CTRL_UPD            (0x1 << 30)
  #define CCM_PLL11_CTRL_EN             (0x1 << 31)
 
-#define AHB1_ABP1_DIV_DEFAULT          0x00002020
+#if defined CONFIG_MACH_SUN8I_H3
+#define AHB1_ABP1_DIV_DEFAULT          0x00003180 /*

AHB1=PLL6/3,APB1=AHB1/2 */

arch/arm/include/asm/arch-sunxi/clock_sun6i.h +2 -0

+#else
+#define AHB1_ABP1_DIV_DEFAULT          0x00002020 /* AHB1=AXI/4,

APB1=AHB1/2 */
+#endif

  #define AXI_GATE_OFFSET_DRAM          0

Hans de Goede

2015-11-20 18:31 UTC #3 lore raw

PATCH 1/1 sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3

HI,

Quoted 28 lines · Chen-Yu Tsai

Quoted 27 lines · Hans de Goede
Hi,
Quoted 22 lines · Siarhei Siamashka
The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz on Allwinner H3 and using PLL6 as the clock source (PLL6/3). This can be verified by reading the value of the AHB1_APB1_CFG_REG register via /dev/mem. It always reads as 0x3180 regardless of the current cpufreq operating point. So this configuration should be safe for use in U-Boot too.
PLL6 also needs to be configured before it is used as the clock source, according to the "CCU / Programming Guidelines" section of the Allwinner manual.
The current low AHB1 clock speed is limiting the USB transfer speed when booting via FEL. This patch can increase the FEL USB transfer speed from ~510 KB/s to ~950 KB/s.
Signed-off-by Siarhei Siamashka <[email protected]>
---
This is intended to be used together with the Allwinner H3 patches from Jens Kuske:
      http://lists.denx.de/pipermail/u-boot/2015-November/234589.html

Quoted 4 lines

Quoted 2 lines
Thanks, I've applied this patch to my tree, and it will be part of the next pull-req.
Can we do this for all SoCs? Starting with the ones that use clock_sun6i?

Sure I'm fine with that, but lets do that in a separate follow-up patch after having done some testing with it first.

Quoted 5 lines

A31/A31s already are clocking AHB1 from PLL6 in Linux, albeit at 150 MHz instead of 200 MHz, since it is just reparenting, and not setting a new value for the divider or pre-divider. IIRC A23 SDK also clocks AHB1 from PLL6, but the mainline kernel hasn't adopted it. We can just drop the "#if defined CONFIG_MACH_SUN8I_H3" from clock_sun6i.h.

I always like dropping #ifdef-s. I've added a patch for this to my u-boot sunxi-wip branch, lets let it stew a bit there before merging this upstream.

Regards,

Hans

Quoted 73 lines

Also, user manuals of the earlier generation SoCs (sun[457]i) list the clock rate range for the various buses. I think we can assume the range has not changed for AHB/APB clocks. The maximum rate for these two are 276 MHz and 138 MHz, respectively.
Thanks
ChenYu
Quoted 63 lines
Quoted 62 lines
Allwinner A83T is likely using the same 200MHz AHB1 setup:
https://github.com/allwinner-zh/bootloader/blob/e5ceeca21188/basic_loader/bsp/bsp_for_a83/common/common.c#L101
I can successfully boot my A31s based tablet with 200MHz AHB1 clock speed too. And this also speeds up FEL USB transfers. However I can't check what kind of AHB1 configuration is used by the Android firmware without rooting it first, which I wouldn't do at the moment.
   arch/arm/cpu/armv7/sunxi/clock_sun6i.c        | 6 ++++--
   arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 7 ++++++-
   2 files changed, 10 insertions(+), 3 deletions(-)
arch/arm/cpu/armv7/sunxi/clock_sun6i.c +4 -2
index 3ab3b31..916ee48 100644
@@ -34,9 +34,11 @@ void clock_init_safe(void)
 
         clock_set_pll1(408000000);
 
-       writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
-
         writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+       while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
+               ;
+
+       writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
 
         writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
         writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
arch/arm/include/asm/arch-sunxi/clock_sun6i.h +3 -1
index 584d351..09337a1 100644
@@ -201,6 +201,7 @@ struct sunxi_ccm_reg {
   #define CCM_PLL6_CTRL_N_MASK          (0x1f << CCM_PLL6_CTRL_N_SHIFT)
   #define CCM_PLL6_CTRL_K_SHIFT         4
   #define CCM_PLL6_CTRL_K_MASK          (0x3 << CCM_PLL6_CTRL_K_SHIFT)
+#define CCM_PLL6_CTRL_LOCK             (1 << 28)
 
   #define CCM_MIPI_PLL_CTRL_M_SHIFT     0
   #define CCM_MIPI_PLL_CTRL_M_MASK      (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT)
@@ -219,7 +220,11 @@ struct sunxi_ccm_reg {
   #define CCM_PLL11_CTRL_UPD            (0x1 << 30)
   #define CCM_PLL11_CTRL_EN             (0x1 << 31)
 
-#define AHB1_ABP1_DIV_DEFAULT          0x00002020
+#if defined CONFIG_MACH_SUN8I_H3
+#define AHB1_ABP1_DIV_DEFAULT          0x00003180 /*
AHB1=PLL6/3,APB1=AHB1/2 */
arch/arm/include/asm/arch-sunxi/clock_sun6i.h +2 -0
+#else
+#define AHB1_ABP1_DIV_DEFAULT          0x00002020 /* AHB1=AXI/4,
APB1=AHB1/2 */
+#endif
   #define AXI_GATE_OFFSET_DRAM          0