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irqchip: lpc32xx: add LPC32xx irqchip driver

PATCH In review Vladimir Zapolskiy 5 participants 21 messages Nov 20, 2015 – Apr 5, 2016

Subsystems (5)
Device tree bindings Arm (32-bit) Arm sub-architectures irqchip drivers +1 more subsystems
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Vladimir Zapolskiy

author maintainer
#0 lore raw

cover irqchip: lpc32xx: add LPC32xx irqchip driver

The change adds wakeup controller platform driver and irqchip driver for NXP LPC32xx boards.

The changeset has dependencies on the recent updates to LPC32xx DTS:
* http://permalink.gmane.org/gmane.linux.ports.arm.kernel/456304
* Recent LPC32xx CCF series (no link at the moment)

Vladimir Zapolskiy (10):
dt-bindings: create arm/nxp folder and move LPC32xx SoC description to it
dt-bindings: nxp: add description of wakeup controller on LPC32xx
dt-bindings: interrupt-controllers: add description of SIC1 and SIC2
arm: lpc32xx: add wakeup platform driver
arm: dts: lpc32xx: assign interrupt types
arm: dts: lpc32xx: add description of IC wakeup controllers
arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC
irqchip: add LPC32xx interrupt controller driver
irqchip: lpc32xx: add option to wakeup from an interrupt
arm: dts: lpc32xx: enable SIC1 and SIC2 by default

 Documentation/devicetree/bindings/arm/lpc32xx.txt  |   8 -
 .../devicetree/bindings/arm/nxp/lpc32xx.txt        |   8 +
 .../bindings/arm/nxp/nxp,lpc3220-wakeup.txt        |  41 +++
 .../interrupt-controller/nxp,lpc3220-mic.txt       |  99 +++++--
 arch/arm/Kconfig                                   |   2 +
 arch/arm/boot/dts/lpc32xx.dtsi                     | 139 ++++++---
 arch/arm/mach-lpc32xx/Makefile                     |   4 +-
 arch/arm/mach-lpc32xx/include/mach/wakeup.h        |  21 ++
 arch/arm/mach-lpc32xx/phy3250.c                    |   1 -
 arch/arm/mach-lpc32xx/wakeup.c                     | 144 +++++++++
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-lpc32xx.c                      | 326 +++++++++++++++++++++
 12 files changed, 723 insertions(+), 71 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/lpc32xx.txt
 create mode 100644 Documentation/devicetree/bindings/arm/nxp/lpc32xx.txt
 create mode 100644 Documentation/devicetree/bindings/arm/nxp/nxp,lpc3220-wakeup.txt
 create mode 100644 arch/arm/mach-lpc32xx/include/mach/wakeup.h
 create mode 100644 arch/arm/mach-lpc32xx/wakeup.c
 create mode 100644 drivers/irqchip/irq-lpc32xx.c
Signature · 1 line
2.1.4
author maintainer
#1 lore raw

PATCH 1/10 dt-bindings: create arm/nxp folder and move LPC32xx SoC description to it

Create a separate folder for device tree bindings of NXP SoCs devices, and move lpc32xx.txt to it.

Signed-off-by Vladimir Zapolskiy <[email protected]>
---
 Documentation/devicetree/bindings/arm/lpc32xx.txt     | 8 --------
 Documentation/devicetree/bindings/arm/nxp/lpc32xx.txt | 8 ++++++++
 2 files changed, 8 insertions(+), 8 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/lpc32xx.txt
 create mode 100644 Documentation/devicetree/bindings/arm/nxp/lpc32xx.txt
Documentation/devicetree/bindings/arm/lpc32xx.txt deleted +0 -8
deleted file mode 100644
index 56ec8dd..0000000
@@ -1,8 +0,0 @@
-NXP LPC32xx Platforms Device Tree Bindings
-------------------------------------------
-
-Boards with the NXP LPC32xx SoC shall have the following properties:
-
-Required root node property:
-
-compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250"
Documentation/devicetree/bindings/arm/nxp/lpc32xx.txt new file +8 -0
new file mode 100644
index 0000000..56ec8dd
@@ -0,0 +1,8 @@
+NXP LPC32xx Platforms Device Tree Bindings
+------------------------------------------
+
+Boards with the NXP LPC32xx SoC shall have the following properties:
+
+Required root node property:
+
+compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250"
Signature · 1 line
2.1.4
maintainer
#2 lore raw

PATCH 1/10 dt-bindings: create arm/nxp folder and move LPC32xx SoC description to it

Quoted 7 lines · Vladimir Zapolskiy

Create a separate folder for device tree bindings of NXP SoCs devices, and move lpc32xx.txt to it.

Signed-off-by Vladimir Zapolskiy <[email protected]>
---
 Documentation/devicetree/bindings/arm/lpc32xx.txt     | 8 --------
 Documentation/devicetree/bindings/arm/nxp/lpc32xx.txt | 8 ++++++++

This one is short, but use git-format-patch -M option in the future.

Acked-by Rob Herring <[email protected]>
Quoted 35 lines
 2 files changed, 8 insertions(+), 8 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/lpc32xx.txt
 create mode 100644 Documentation/devicetree/bindings/arm/nxp/lpc32xx.txt
Documentation/devicetree/bindings/arm/lpc32xx.txt deleted +0 -8
deleted file mode 100644
index 56ec8dd..0000000
@@ -1,8 +0,0 @@
-NXP LPC32xx Platforms Device Tree Bindings
-------------------------------------------
-
-Boards with the NXP LPC32xx SoC shall have the following properties:
-
-Required root node property:
-
-compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250"
Documentation/devicetree/bindings/arm/nxp/lpc32xx.txt new file +8 -0
new file mode 100644
index 0000000..56ec8dd
@@ -0,0 +1,8 @@
+NXP LPC32xx Platforms Device Tree Bindings
+------------------------------------------
+
+Boards with the NXP LPC32xx SoC shall have the following properties:
+
+Required root node property:
+
+compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250"
Signature · 1 line
2.1.4
author maintainer
#3 lore raw

PATCH 2/10 dt-bindings: nxp: add description of wakeup controller on LPC32xx

In reply to Vladimir Zapolskiy

NXP LPC32xx has three wakeup controllers of two types, this descriptions defines DT bindings of wakeup controllers connected to MIC, SIC1 and SIC2 interrupt controllers.

Signed-off-by Vladimir Zapolskiy <[email protected]>
---
 .../bindings/arm/nxp/nxp,lpc3220-wakeup.txt        | 41 ++++++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/nxp/nxp,lpc3220-wakeup.txt
Documentation/devicetree/bindings/arm/nxp/nxp,lpc3220-wakeup.txt new file +41 -0
new file mode 100644
index 0000000..803728f
@@ -0,0 +1,41 @@
+NXP LPC32xx Wakeup Controller
+
+Required properties:
+- compatible: should be "nxp,lpc3220-wakeup"
+- reg:  should contain wakeup controller registers location and length
+- #wakeup-cells: must be 2, the first cell describes wakeup source on
+  the controller, the second cell is a hardware interrupt number on IC.
+
+Examples:
+
+	/* System Control Block */
+	scb {
+		compatible = "simple-bus";
+		ranges = <0x0 0x040004000 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		wakeup_int: wakeup-controller at 20 {
+			compatible = "nxp,lpc3220-wakeup";
+			reg = <0x20 0x10>;
+			#wakeup-cells = <2>;
+		};
+
+		wakeup_pin: wakeup-controller at 30 {
+			compatible = "nxp,lpc3220-wakeup";
+			reg = <0x30 0x10>;
+			#wakeup-cells = <2>;
+		};
+	};
+
+	/* Main Interrupt Controller */
+	mic: interrupt-controller at 40008000 {
+		compatible = "nxp,lpc3220-mic";
+		reg = <0x40008000 0x4000>;
+		interrupt-controller;
+		interrupt-controller-name = "mic";
+		#interrupt-cells = <2>;
+
+		wakeup-sources = <&wakeup_int 7 29>,
+				 <&wakeup_int 25 27>;
+	};
Signature · 1 line
2.1.4
maintainer
#4 lore raw

PATCH 2/10 dt-bindings: nxp: add description of wakeup controller on LPC32xx

Quoted 16 lines · Vladimir Zapolskiy

NXP LPC32xx has three wakeup controllers of two types, this descriptions defines DT bindings of wakeup controllers connected to MIC, SIC1 and SIC2 interrupt controllers.

Signed-off-by Vladimir Zapolskiy <[email protected]>
---
 .../bindings/arm/nxp/nxp,lpc3220-wakeup.txt        | 41 ++++++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/nxp/nxp,lpc3220-wakeup.txt
Documentation/devicetree/bindings/arm/nxp/nxp,lpc3220-wakeup.txt new file +0 -0
new file mode 100644
index 0000000..803728f

Documentation/devicetree/bindings/arm/nxp/nxp,lpc3220-wakeup.txt line 7

Quoted 7 lines
Documentation/devicetree/bindings/arm/nxp/nxp,lpc3220-wakeup.txt new file +7 -0
@@ -0,0 +1,41 @@
+NXP LPC32xx Wakeup Controller
+
+Required properties:
+- compatible: should be "nxp,lpc3220-wakeup"
+- reg:  should contain wakeup controller registers location and length
+- #wakeup-cells: must be 2, the first cell describes wakeup source on
+  the controller, the second cell is a hardware interrupt number on IC.

This probably needs to be done differently. For one, we already have a common property "wakeup-source" with different meaning.

Marc, Is there an example of using stacked irqdomain and mapping of irq numbers to wakeup numbers?

Rob

Quoted 37 lines
Documentation/devicetree/bindings/arm/nxp/nxp,lpc3220-wakeup.txt new file +34 -0
+
+Examples:
+
+	/* System Control Block */
+	scb {
+		compatible = "simple-bus";
+		ranges = <0x0 0x040004000 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		wakeup_int: wakeup-controller at 20 {
+			compatible = "nxp,lpc3220-wakeup";
+			reg = <0x20 0x10>;
+			#wakeup-cells = <2>;
+		};
+
+		wakeup_pin: wakeup-controller at 30 {
+			compatible = "nxp,lpc3220-wakeup";
+			reg = <0x30 0x10>;
+			#wakeup-cells = <2>;
+		};
+	};
+
+	/* Main Interrupt Controller */
+	mic: interrupt-controller at 40008000 {
+		compatible = "nxp,lpc3220-mic";
+		reg = <0x40008000 0x4000>;
+		interrupt-controller;
+		interrupt-controller-name = "mic";
+		#interrupt-cells = <2>;
+
+		wakeup-sources = <&wakeup_int 7 29>,
+				 <&wakeup_int 25 27>;
+	};
Signature · 1 line
2.1.4
author maintainer
#5 lore raw

PATCH 3/10 dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

In reply to Vladimir Zapolskiy

NXP LPC32xx has three interrupt controllers, namely root Main Interrupt Controller (MIC) and two supplementary Sub Interrupt Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2 are connected to MIC.

Also the change describes two additional optional properties:
* interrupt-controller-name - human readable name of an interrupt controller,
* wakeup-sources - list of mappings between a hardware interrupt and its correspondent wakeup source to exit CPU STOP mode.

Signed-off-by Vladimir Zapolskiy <[email protected]>
---
 .../interrupt-controller/nxp,lpc3220-mic.txt       | 99 ++++++++++++++++------
 1 file changed, 75 insertions(+), 24 deletions(-)
Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt +75 -24
index 539adca..99e41ca 100644
@@ -1,38 +1,89 @@
-* NXP LPC32xx Main Interrupt Controller
-  (MIC, including SIC1 and SIC2 secondary controllers)
+* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
 
 Required properties:
-- compatible: Should be "nxp,lpc3220-mic"
-- interrupt-controller: Identifies the node as an interrupt controller.
-- interrupt-parent: Empty for the interrupt controller itself
-- #interrupt-cells: The number of cells to define the interrupts. Should be 2.
-  The first cell is the IRQ number
-  The second cell is used to specify mode:
-      1 = low-to-high edge triggered
-      2 = high-to-low edge triggered
-      4 = active high level-sensitive
-      8 = active low level-sensitive
-      Default for internal sources should be set to 4 (active high).
-- reg: Should contain MIC registers location and length
+- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
+- reg: should contain IC registers location and length
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: the number of cells to define an interrupt, should be 2.
+  The first cell is the IRQ number, the second cell is used to specify
+  one of the supported modes:
+      IRQ_TYPE_EDGE_RISING = low-to-high edge triggered
+      IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered
+      IRQ_TYPE_LEVEL_HIGH = active high level-sensitive
+      IRQ_TYPE_LEVEL_LOW = active low level-sensitive
+      Default for internal sources should be set to IRQ_TYPE_LEVEL_HIGH.
+
+Optional properties:
+- interrupt-parent: empty for MIC interrupt controller, link to parent
+  MIC interrupt controller for SIC1 and SIC2
+- interrupts: empty for MIC interrupt controller, cascaded MIC
+  hardware interrupts for SIC1 and SIC2
+- interrupt-controller-name: readable interrupt controller name
+- wakeup-sources: mapping of interrupts handled by the controller and
+  which may serve as a wakeup source.
 
 Examples:
-	/*
-	 * MIC
-	 */
+
+	/* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
 	mic: interrupt-controller at 40008000 {
 		compatible = "nxp,lpc3220-mic";
+		reg = <0x40008000 0x4000>;
+		interrupt-controller;
+		interrupt-controller-name = "mic";
+		#interrupt-cells = <2>;
+
+		wakeup-sources = <&wakeup_int 7 29>,
+				 <&wakeup_int 25 27>;
+	};
+
+	sic1: interrupt-controller at 4000C000 {
+		compatible = "nxp,lpc3220-sic";
+		reg = <0x4000C000 0x4000>;
+		interrupt-controller;
+		interrupt-controller-name = "sic1";
+		#interrupt-cells = <2>;
+
+		interrupt-parent = <&mic>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+			     <30 IRQ_TYPE_LEVEL_LOW>;
+
+		wakeup-sources = <&wakeup_int 16 22>, <&wakeup_int 19 26>,
+				 <&wakeup_int 20 25>, <&wakeup_int 21 31>,
+				 <&wakeup_int 24 20>, <&wakeup_int 29 8>,
+				 <&wakeup_int 30 6>, <&wakeup_int 31 7>,
+				 <&wakeup_pin 25 4>;
+	};
+
+	sic2: interrupt-controller at 40010000 {
+		compatible = "nxp,lpc3220-sic";
+		reg = <0x40010000 0x4000>;
 		interrupt-controller;
-		interrupt-parent;
+		interrupt-controller-name = "sic2";
 		#interrupt-cells = <2>;
-		reg = <0x40008000 0xC000>;
+
+		interrupt-parent = <&mic>;
+		interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+			     <31 IRQ_TYPE_LEVEL_LOW>;
+
+		wakeup-sources = <&wakeup_int 0 0>, <&wakeup_int 1 1>,
+				 <&wakeup_int 2 2>, <&wakeup_int 3 3>,
+				 <&wakeup_int 4 4>, <&wakeup_int 5 5>,
+				 <&wakeup_int 6 8>, <&wakeup_pin 3 9>,
+				 <&wakeup_pin 4 10>, <&wakeup_pin 5 11>,
+				 <&wakeup_pin 6 6>, <&wakeup_pin 7 15>,
+				 <&wakeup_pin 8 20>, <&wakeup_pin 9 31>,
+				 <&wakeup_pin 10 22>, <&wakeup_pin 11 23>,
+				 <&wakeup_pin 12 24>, <&wakeup_pin 13 25>,
+				 <&wakeup_pin 14 26>, <&wakeup_pin 15 27>,
+				 <&wakeup_pin 16 27>, <&wakeup_pin 18 18>,
+				 <&wakeup_pin 23 7>, <&wakeup_pin 26 19>,
+				 <&wakeup_pin 30 12>;
 	};
 
-	/*
-	 * ADC
-	 */
+	/* ADC */
 	adc at 40048000 {
 		compatible = "nxp,lpc3220-adc";
 		reg = <0x40048000 0x1000>;
-		interrupt-parent = <&mic>;
-		interrupts = <39 4>;
+		interrupt-parent = <&sic1>;
+		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 	};
Signature · 1 line
2.1.4
maintainer
#6 lore raw

PATCH 3/10 dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

Quoted 8 lines · Vladimir Zapolskiy

NXP LPC32xx has three interrupt controllers, namely root Main Interrupt Controller (MIC) and two supplementary Sub Interrupt Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2 are connected to MIC.

Also the change describes two additional optional properties:
* interrupt-controller-name - human readable name of an interrupt controller,

Why? compatible is human readable. If you don't like that, then put the string in the driver.

Quoted 2 lines

* wakeup-sources - list of mappings between a hardware interrupt and its correspondent wakeup source to exit CPU STOP mode.

This needs further discussion as I mentioned.

The rest looks fine.

Rob

Quoted 126 lines
Signed-off-by Vladimir Zapolskiy <[email protected]>
---
 .../interrupt-controller/nxp,lpc3220-mic.txt       | 99 ++++++++++++++++------
 1 file changed, 75 insertions(+), 24 deletions(-)
Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt +75 -24
index 539adca..99e41ca 100644
@@ -1,38 +1,89 @@
-* NXP LPC32xx Main Interrupt Controller
-  (MIC, including SIC1 and SIC2 secondary controllers)
+* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
 
 Required properties:
-- compatible: Should be "nxp,lpc3220-mic"
-- interrupt-controller: Identifies the node as an interrupt controller.
-- interrupt-parent: Empty for the interrupt controller itself
-- #interrupt-cells: The number of cells to define the interrupts. Should be 2.
-  The first cell is the IRQ number
-  The second cell is used to specify mode:
-      1 = low-to-high edge triggered
-      2 = high-to-low edge triggered
-      4 = active high level-sensitive
-      8 = active low level-sensitive
-      Default for internal sources should be set to 4 (active high).
-- reg: Should contain MIC registers location and length
+- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
+- reg: should contain IC registers location and length
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: the number of cells to define an interrupt, should be 2.
+  The first cell is the IRQ number, the second cell is used to specify
+  one of the supported modes:
+      IRQ_TYPE_EDGE_RISING = low-to-high edge triggered
+      IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered
+      IRQ_TYPE_LEVEL_HIGH = active high level-sensitive
+      IRQ_TYPE_LEVEL_LOW = active low level-sensitive
+      Default for internal sources should be set to IRQ_TYPE_LEVEL_HIGH.
+
+Optional properties:
+- interrupt-parent: empty for MIC interrupt controller, link to parent
+  MIC interrupt controller for SIC1 and SIC2
+- interrupts: empty for MIC interrupt controller, cascaded MIC
+  hardware interrupts for SIC1 and SIC2
+- interrupt-controller-name: readable interrupt controller name
+- wakeup-sources: mapping of interrupts handled by the controller and
+  which may serve as a wakeup source.
 
 Examples:
-	/*
-	 * MIC
-	 */
+
+	/* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
 	mic: interrupt-controller at 40008000 {
 		compatible = "nxp,lpc3220-mic";
+		reg = <0x40008000 0x4000>;
+		interrupt-controller;
+		interrupt-controller-name = "mic";
+		#interrupt-cells = <2>;
+
+		wakeup-sources = <&wakeup_int 7 29>,
+				 <&wakeup_int 25 27>;
+	};
+
+	sic1: interrupt-controller at 4000C000 {
+		compatible = "nxp,lpc3220-sic";
+		reg = <0x4000C000 0x4000>;
+		interrupt-controller;
+		interrupt-controller-name = "sic1";
+		#interrupt-cells = <2>;
+
+		interrupt-parent = <&mic>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+			     <30 IRQ_TYPE_LEVEL_LOW>;
+
+		wakeup-sources = <&wakeup_int 16 22>, <&wakeup_int 19 26>,
+				 <&wakeup_int 20 25>, <&wakeup_int 21 31>,
+				 <&wakeup_int 24 20>, <&wakeup_int 29 8>,
+				 <&wakeup_int 30 6>, <&wakeup_int 31 7>,
+				 <&wakeup_pin 25 4>;
+	};
+
+	sic2: interrupt-controller at 40010000 {
+		compatible = "nxp,lpc3220-sic";
+		reg = <0x40010000 0x4000>;
 		interrupt-controller;
-		interrupt-parent;
+		interrupt-controller-name = "sic2";
 		#interrupt-cells = <2>;
-		reg = <0x40008000 0xC000>;
+
+		interrupt-parent = <&mic>;
+		interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+			     <31 IRQ_TYPE_LEVEL_LOW>;
+
+		wakeup-sources = <&wakeup_int 0 0>, <&wakeup_int 1 1>,
+				 <&wakeup_int 2 2>, <&wakeup_int 3 3>,
+				 <&wakeup_int 4 4>, <&wakeup_int 5 5>,
+				 <&wakeup_int 6 8>, <&wakeup_pin 3 9>,
+				 <&wakeup_pin 4 10>, <&wakeup_pin 5 11>,
+				 <&wakeup_pin 6 6>, <&wakeup_pin 7 15>,
+				 <&wakeup_pin 8 20>, <&wakeup_pin 9 31>,
+				 <&wakeup_pin 10 22>, <&wakeup_pin 11 23>,
+				 <&wakeup_pin 12 24>, <&wakeup_pin 13 25>,
+				 <&wakeup_pin 14 26>, <&wakeup_pin 15 27>,
+				 <&wakeup_pin 16 27>, <&wakeup_pin 18 18>,
+				 <&wakeup_pin 23 7>, <&wakeup_pin 26 19>,
+				 <&wakeup_pin 30 12>;
 	};
 
-	/*
-	 * ADC
-	 */
+	/* ADC */
 	adc at 40048000 {
 		compatible = "nxp,lpc3220-adc";
 		reg = <0x40048000 0x1000>;
-		interrupt-parent = <&mic>;
-		interrupts = <39 4>;
+		interrupt-parent = <&sic1>;
+		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 	};
Signature · 1 line
2.1.4
author maintainer
#7 lore raw

PATCH 3/10 dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

Hi Rob,

Quoted 6 lines · Rob Herring
Quoted 5 lines · Vladimir Zapolskiy

NXP LPC32xx has three interrupt controllers, namely root Main Interrupt Controller (MIC) and two supplementary Sub Interrupt Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2 are connected to MIC.

Quoted 6 lines
Quoted 3 lines

Also the change describes two additional optional properties:
* interrupt-controller-name - human readable name of an interrupt controller,

Why? compatible is human readable. If you don't like that, then put the string in the driver.

in runtime I'd like to differentiate various IRQ chips by name. Here for example I have one compatible "*-sic" and two actual IRQ chips SIC1 and SIC2. If I read /proc/interrupts or /sys/kernel/debug/irq_domain_mapping I would prefer to visualize interrupts from SIC1 and SIC2.

I understand that this property is not hardware specific, but there are plenty of similar properties like "label" etc. Probably renaming of the property may help?

Quoted 4 lines
Quoted 2 lines

* wakeup-sources - list of mappings between a hardware interrupt and its correspondent wakeup source to exit CPU STOP mode.

This needs further discussion as I mentioned.

Ok.

Quoted 2 lines

The rest looks fine.

Thanks for review.

--
Best wishes,
Vladimir

#8 lore raw

PATCH 3/10 dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

Quoted 16 lines · Vladimir Zapolskiy

Hi Rob,

Quoted 6 lines · Rob Herring
Quoted 5 lines · Vladimir Zapolskiy

NXP LPC32xx has three interrupt controllers, namely root Main Interrupt Controller (MIC) and two supplementary Sub Interrupt Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2 are connected to MIC.

Quoted 6 lines
Quoted 3 lines

Also the change describes two additional optional properties:
* interrupt-controller-name - human readable name of an interrupt controller,

Why? compatible is human readable. If you don't like that, then put the string in the driver.

Quoted 8 lines

in runtime I'd like to differentiate various IRQ chips by name. Here for example I have one compatible "*-sic" and two actual IRQ chips SIC1 and SIC2. If I read /proc/interrupts or /sys/kernel/debug/irq_domain_mapping I would prefer to visualize interrupts from SIC1 and SIC2.

I understand that this property is not hardware specific, but there are plenty of similar properties like "label" etc. Probably renaming of the property may help?

You can always generate the name based on the probing order or the address.

Thanks,

	M.
Signature · 1 line
Jazz is not dead. It just smells funny...
author maintainer
#9 lore raw

PATCH 3/10 dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

Hi Marc,

Quoted 22 lines · Marc Zyngier
Quoted 21 lines · Vladimir Zapolskiy

Hi Rob,

Quoted 6 lines · Rob Herring
Quoted 5 lines · Vladimir Zapolskiy

NXP LPC32xx has three interrupt controllers, namely root Main Interrupt Controller (MIC) and two supplementary Sub Interrupt Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2 are connected to MIC.

Quoted 6 lines
Quoted 3 lines

Also the change describes two additional optional properties:
* interrupt-controller-name - human readable name of an interrupt controller,

Why? compatible is human readable. If you don't like that, then put the string in the driver.

in runtime I'd like to differentiate various IRQ chips by name. Here for example I have one compatible "*-sic" and two actual IRQ chips SIC1 and SIC2. If I read /proc/interrupts or /sys/kernel/debug/irq_domain_mapping I would prefer to visualize interrupts from SIC1 and SIC2.

Quoted 5 lines
Quoted 3 lines

I understand that this property is not hardware specific, but there are plenty of similar properties like "label" etc. Probably renaming of the property may help?

You can always generate the name based on the probing order or the address.

But the probing order is not guaranteed in general.

It might be confusing, if the spec operates with strictly defined SIC1 and SIC2 names, and in runtime the names of interrupt controllers are swapped.

Another option might be to introduce different compatibles, but I think optional label/name property is better.

--
With best wishes,
Vladimir

author maintainer
#10 lore raw

PATCH 4/10 arm: lpc32xx: add wakeup platform driver

In reply to Vladimir Zapolskiy

NXP LPC32xx has three wakeup controllers of two types, this change adds support of two wakeup controllers connected to MIC, SIC1 and SIC2 interrupt controllers, which may propagate interrupt wakeup source status to one of the wakeup controllers. Wakeup controllers are found as subdevices of System Control Block with offsets 0x20 and 0x30.

The change does not add support of P01 wakeup controller, which may define Port0 and Port1 I/O pins as wakeup sources.

Signed-off-by Vladimir Zapolskiy <[email protected]>
---
 arch/arm/mach-lpc32xx/Makefile              |   2 +-
 arch/arm/mach-lpc32xx/include/mach/wakeup.h |  21 ++++
 arch/arm/mach-lpc32xx/wakeup.c              | 144 ++++++++++++++++++++++++++++
 3 files changed, 166 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-lpc32xx/include/mach/wakeup.h
 create mode 100644 arch/arm/mach-lpc32xx/wakeup.c
arch/arm/mach-lpc32xx/Makefile +1 -1
index c70709a..b1023c0 100644
@@ -3,5 +3,5 @@
 #
 
 obj-y	:= irq.o common.o serial.o
-obj-y	+= pm.o suspend.o
+obj-y	+= pm.o suspend.o wakeup.o
 obj-y	+= phy3250.o
arch/arm/mach-lpc32xx/include/mach/wakeup.h new file +21 -0
new file mode 100644
index 0000000..2c6c5fa
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2015 Vladimir Zapolskiy <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __LPC32XX_WAKEUP_H
+#define __LPC32XX_WAKEUP_H
+
+struct wakeup_controller;
+
+void lpc32xx_wakeup_clear(struct wakeup_controller *wuc, u32 bit);
+void lpc32xx_wakeup_set_edge(struct wakeup_controller *wuc, u32 bit, bool val);
+void lpc32xx_wakeup_enable(struct wakeup_controller *wuc, u32 bit, bool on);
+
+#endif
arch/arm/mach-lpc32xx/wakeup.c new file +144 -0

144 lines not on this page · raw message

Signature · 1 line
2.1.4
author maintainer
#11 lore raw

PATCH 5/10 arm: dts: lpc32xx: assign interrupt types

In reply to Vladimir Zapolskiy

LPC32xx interrupt controller has two cells, instead of zero specify proper irq types for all consumers.

Signed-off-by Vladimir Zapolskiy <[email protected]>
---
 arch/arm/boot/dts/lpc32xx.dtsi | 63 +++++++++++++++++++++++-------------------
 1 file changed, 34 insertions(+), 29 deletions(-)
arch/arm/boot/dts/lpc32xx.dtsi +34 -29
index f396343..fbf1984b 100644
@@ -14,6 +14,7 @@
 #include "skeleton.dtsi"
 
 #include <dt-bindings/clock/lpc32xx-clock.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	compatible = "nxp,lpc3220";

@@ -66,7 +67,7 @@
 		mlc: flash at 200a8000 {
 			compatible = "nxp,lpc3220-mlc";
 			reg = <0x200a8000 0x11000>;
-			interrupts = <11 0>;
+			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk LPC32XX_CLK_MLC>;
 			status = "disabled";
 		};

@@ -74,7 +75,7 @@
 		dma: dma at 31000000 {
 			compatible = "arm,pl080", "arm,primecell";
 			reg = <0x31000000 0x1000>;
-			interrupts = <0x1c 0>;
+			interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk LPC32XX_CLK_DMA>;
 			clock-names = "apb_pclk";
 		};

@@ -91,7 +92,7 @@
 			ohci: ohci at 0 {
 				compatible = "nxp,ohci-nxp", "usb-ohci";
 				reg = <0x0 0x300>;
-				interrupts = <0x3b 0>;
+				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
 				status = "disabled";
 			};

@@ -99,7 +100,10 @@
 			usbd: usbd at 0 {
 				compatible = "nxp,lpc3220-udc";
 				reg = <0x0 0x300>;
-				interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
+				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>,
+					     <62 IRQ_TYPE_LEVEL_HIGH>,
+					     <60 IRQ_TYPE_LEVEL_HIGH>,
+					     <58 IRQ_TYPE_LEVEL_LOW>;
 				clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
 				status = "disabled";
 			};

@@ -107,7 +111,7 @@
 			i2cusb: i2c at 300 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x300 0x100>;
-				interrupts = <0x3f 0>;
+				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
 				#address-cells = <1>;
 				#size-cells = <0>;

@@ -124,7 +128,7 @@
 		clcd: clcd at 31040000 {
 			compatible = "arm,pl110", "arm,primecell";
 			reg = <0x31040000 0x1000>;
-			interrupts = <0x0e 0>;
+			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk LPC32XX_CLK_LCD>;
 			clock-names = "apb_pclk";
 			status = "disabled";

@@ -133,7 +137,7 @@
 		mac: ethernet at 31060000 {
 			compatible = "nxp,lpc-eth";
 			reg = <0x31060000 0x1000>;
-			interrupts = <0x1d 0>;
+			interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk LPC32XX_CLK_MAC>;
 		};
 

@@ -161,7 +165,7 @@
 			ssp0: ssp at 20084000 {
 				compatible = "arm,pl022", "arm,primecell";
 				reg = <0x20084000 0x1000>;
-				interrupts = <0x14 0>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_SSP0>;
 				clock-names = "apb_pclk";
 			};

@@ -174,7 +178,7 @@
 			ssp1: ssp at 2008c000 {
 				compatible = "arm,pl022", "arm,primecell";
 				reg = <0x2008c000 0x1000>;
-				interrupts = <0x15 0>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_SSP1>;
 				clock-names = "apb_pclk";
 			};

@@ -192,7 +196,8 @@
 			sd: sd at 20098000 {
 				compatible = "arm,pl18x", "arm,primecell";
 				reg = <0x20098000 0x1000>;
-				interrupts = <0x0f 0>, <0x0d 0>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+					     <13 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_SD>;
 				clock-names = "apb_pclk";
 				status = "disabled";

@@ -208,7 +213,7 @@
 				/* actually, ns16550a w/ 64 byte fifos! */
 				compatible = "nxp,lpc3220-uart";
 				reg = <0x40090000 0x1000>;
-				interrupts = <9 0>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
 				clocks = <&clk LPC32XX_CLK_UART5>;
 				status = "disabled";

@@ -217,7 +222,7 @@
 			uart3: serial at 40080000 {
 				compatible = "nxp,lpc3220-uart";
 				reg = <0x40080000 0x1000>;
-				interrupts = <7 0>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
 				clocks = <&clk LPC32XX_CLK_UART3>;
 				status = "disabled";

@@ -226,7 +231,7 @@
 			uart4: serial at 40088000 {
 				compatible = "nxp,lpc3220-uart";
 				reg = <0x40088000 0x1000>;
-				interrupts = <8 0>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
 				clocks = <&clk LPC32XX_CLK_UART4>;
 				status = "disabled";

@@ -235,7 +240,7 @@
 			uart6: serial at 40098000 {
 				compatible = "nxp,lpc3220-uart";
 				reg = <0x40098000 0x1000>;
-				interrupts = <10 0>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
 				clocks = <&clk LPC32XX_CLK_UART6>;
 				status = "disabled";

@@ -244,7 +249,7 @@
 			i2c1: i2c at 400A0000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A0000 0x100>;
-				interrupts = <0x33 0>;
+				interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;

@@ -254,7 +259,7 @@
 			i2c2: i2c at 400A8000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A8000 0x100>;
-				interrupts = <0x32 0>;
+				interrupts = <50 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;

@@ -308,28 +313,28 @@
 			uart1: serial at 40014000 {
 				compatible = "nxp,lpc3220-hsuart";
 				reg = <0x40014000 0x1000>;
-				interrupts = <26 0>;
+				interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			uart2: serial at 40018000 {
 				compatible = "nxp,lpc3220-hsuart";
 				reg = <0x40018000 0x1000>;
-				interrupts = <25 0>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			uart7: serial at 4001c000 {
 				compatible = "nxp,lpc3220-hsuart";
 				reg = <0x4001c000 0x1000>;
-				interrupts = <24 0>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			rtc: rtc at 40024000 {
 				compatible = "nxp,lpc3220-rtc";
 				reg = <0x40024000 0x1000>;
-				interrupts = <0x34 0>;
+				interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_RTC>;
 			};
 

@@ -343,7 +348,7 @@
 			timer4: timer at 4002C000 {
 				compatible = "nxp,lpc3220-timer";
 				reg = <0x4002C000 0x1000>;
-				interrupts = <0x3 0>;
+				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 				clocks = <&clk LPC32XX_CLK_TIMER4>;
 				clock-names = "timerclk";
 				status = "disabled";

@@ -352,7 +357,7 @@
 			timer5: timer at 40030000 {
 				compatible = "nxp,lpc3220-timer";
 				reg = <0x40030000 0x1000>;
-				interrupts = <0x4 0>;
+				interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 				clocks = <&clk LPC32XX_CLK_TIMER5>;
 				clock-names = "timerclk";
 				status = "disabled";

@@ -369,7 +374,7 @@
 				reg = <0x40044000 0x1000>;
 				clocks = <&clk LPC32XX_CLK_TIMER0>;
 				clock-names = "timerclk";
-				interrupts = <0x10 0>;
+				interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
 			};
 
 			/*

@@ -382,7 +387,7 @@
 			adc: adc at 40048000 {
 				compatible = "nxp,lpc3220-adc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <0x27 0>;
+				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};

@@ -390,7 +395,7 @@
 			tsc: tsc at 40048000 {
 				compatible = "nxp,lpc3220-tsc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <0x27 0>;
+				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};

@@ -398,7 +403,7 @@
 			timer1: timer at 4004C000 {
 				compatible = "nxp,lpc3220-timer";
 				reg = <0x4004C000 0x1000>;
-				interrupts = <0x11 0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
 				clocks = <&clk LPC32XX_CLK_TIMER1>;
 				clock-names = "timerclk";
 			};

@@ -406,14 +411,14 @@
 			key: key at 40050000 {
 				compatible = "nxp,lpc3220-key";
 				reg = <0x40050000 0x1000>;
-				interrupts = <54 0>;
+				interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			timer2: timer at 40058000 {
 				compatible = "nxp,lpc3220-timer";
 				reg = <0x40058000 0x1000>;
-				interrupts = <0x12 0>;
+				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 				clocks = <&clk LPC32XX_CLK_TIMER2>;
 				clock-names = "timerclk";
 				status = "disabled";

@@ -436,7 +441,7 @@
 			timer3: timer at 40060000 {
 				compatible = "nxp,lpc3220-timer";
 				reg = <0x40060000 0x1000>;
-				interrupts = <0x13 0>;
+				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 				clocks = <&clk LPC32XX_CLK_TIMER3>;
 				clock-names = "timerclk";
 				status = "disabled";
Signature · 1 line
2.1.4
author maintainer
#12 lore raw

PATCH 6/10 arm: dts: lpc32xx: add description of IC wakeup controllers

In reply to Vladimir Zapolskiy

The change adds System Control Block simple bus device tree node and populates it with two first subdevices, wakeup controllers connected to LPC32xx interrupt controllers MIC, SIC1 and SIC2.

The change also assigns a name to MIC controller and set its wakeup sources.

Signed-off-by Vladimir Zapolskiy <[email protected]>
---
 arch/arm/boot/dts/lpc32xx.dtsi | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)
arch/arm/boot/dts/lpc32xx.dtsi +17 -1
index fbf1984b..b2735dd 100644
@@ -295,6 +295,18 @@
 					clocks = <&xtal_32k>, <&xtal>;
 					clock-names = "xtal_32k", "xtal";
 				};
+
+				wakeup_int: wakeup-controller at 20 {
+					compatible = "nxp,lpc3220-wakeup";
+					reg = <0x20 0x10>;
+					#wakeup-cells = <2>;
+				};
+
+				wakeup_pin: wakeup-controller at 30 {
+					compatible = "nxp,lpc3220-wakeup";
+					reg = <0x30 0x10>;
+					#wakeup-cells = <2>;
+				};
 			};
 
 			/*

@@ -305,9 +317,13 @@
 			 */
 			mic: interrupt-controller at 40008000 {
 				compatible = "nxp,lpc3220-mic";
-				interrupt-controller;
 				reg = <0x40008000 0xC000>;
+				interrupt-controller;
+				interrupt-controller-name = "mic";
 				#interrupt-cells = <2>;
+
+				wakeup-sources = <&wakeup_int 7 29>,
+						 <&wakeup_int 25 27>;
 			};
 
 			uart1: serial at 40014000 {
Signature · 1 line
2.1.4
author maintainer
#13 lore raw

PATCH 7/10 arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

In reply to Vladimir Zapolskiy

The change adds separate device nodes for SIC1 and SIC2 interrupt controllers and reparents all defined SIC1 and SIC2 interrupt producers to the correspondent interrupt controller, this is needed to perform switching to a new LPC32xx MIC/SIC interrupt controller driver.

At the moment SIC1 and SIC2 are disabled by default, this has some excuses:
* legacy LPC32xx interrupt controller driver is broken since commit 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which requires a private interrupt handler, otherwise any SIC1 generated interrupt (mapped to MIC hwirq 0) breaks the kernel with the message "unexpected IRQ trap at vector 00",
* due to the problem described above restriction of access to SIC1 interrupts may be even considered as helpful, now at least the kernel can be successfully booted, but with some not hooked peripherals (ADC/touchscreen, I2C, RTC and USB),
* the change is transitional before switching to a new LPC32xx IC driver.

Signed-off-by Vladimir Zapolskiy <[email protected]>
---
 arch/arm/boot/dts/lpc32xx.dtsi | 86 +++++++++++++++++++++++++++++++++---------
 1 file changed, 68 insertions(+), 18 deletions(-)
arch/arm/boot/dts/lpc32xx.dtsi +68 -18
index b2735dd..8dda6e7 100644
@@ -92,7 +92,8 @@
 			ohci: ohci at 0 {
 				compatible = "nxp,ohci-nxp", "usb-ohci";
 				reg = <0x0 0x300>;
-				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
 				status = "disabled";
 			};

@@ -100,10 +101,11 @@
 			usbd: usbd at 0 {
 				compatible = "nxp,lpc3220-udc";
 				reg = <0x0 0x300>;
-				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>,
-					     <62 IRQ_TYPE_LEVEL_HIGH>,
-					     <60 IRQ_TYPE_LEVEL_HIGH>,
-					     <58 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
+					     <30 IRQ_TYPE_LEVEL_HIGH>,
+					     <28 IRQ_TYPE_LEVEL_HIGH>,
+					     <26 IRQ_TYPE_LEVEL_LOW>;
 				clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
 				status = "disabled";
 			};

@@ -111,7 +113,8 @@
 			i2cusb: i2c at 300 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x300 0x100>;
-				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
 				#address-cells = <1>;
 				#size-cells = <0>;

@@ -249,7 +252,8 @@
 			i2c1: i2c at 400A0000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A0000 0x100>;
-				interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;

@@ -259,7 +263,8 @@
 			i2c2: i2c at 400A8000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A8000 0x100>;
-				interrupts = <50 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;

@@ -309,15 +314,9 @@
 				};
 			};
 
-			/*
-			 * MIC Interrupt controller includes:
-			 *   MIC @40008000
-			 *   SIC1 @4000C000
-			 *   SIC2 @40010000
-			 */
 			mic: interrupt-controller at 40008000 {
 				compatible = "nxp,lpc3220-mic";
-				reg = <0x40008000 0xC000>;
+				reg = <0x40008000 0x4000>;
 				interrupt-controller;
 				interrupt-controller-name = "mic";
 				#interrupt-cells = <2>;

@@ -326,6 +325,54 @@
 						 <&wakeup_int 25 27>;
 			};
 
+			sic1: interrupt-controller at 4000C000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x4000C000 0x4000>;
+				interrupt-controller;
+				interrupt-controller-name = "sic1";
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+					     <30 IRQ_TYPE_LEVEL_LOW>;
+
+				wakeup-sources = <&wakeup_int 16 22>, <&wakeup_int 19 26>,
+						 <&wakeup_int 20 25>, <&wakeup_int 21 31>,
+						 <&wakeup_int 24 20>, <&wakeup_int 29 8>,
+						 <&wakeup_int 30 6>, <&wakeup_int 31 7>,
+						 <&wakeup_pin 25 4>;
+
+				status = "disabled";
+			};
+
+			sic2: interrupt-controller at 40010000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x40010000 0x4000>;
+				interrupt-controller;
+				interrupt-controller-name = "sic2";
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+					     <31 IRQ_TYPE_LEVEL_LOW>;
+
+				wakeup-sources = <&wakeup_int 0 0>, <&wakeup_int 1 1>,
+						 <&wakeup_int 2 2>, <&wakeup_int 3 3>,
+						 <&wakeup_int 4 4>, <&wakeup_int 5 5>,
+						 <&wakeup_int 6 8>, <&wakeup_pin 3 9>,
+						 <&wakeup_pin 4 10>, <&wakeup_pin 5 11>,
+						 <&wakeup_pin 6 6>, <&wakeup_pin 7 15>,
+						 <&wakeup_pin 8 20>, <&wakeup_pin 9 31>,
+						 <&wakeup_pin 10 22>, <&wakeup_pin 11 23>,
+						 <&wakeup_pin 12 24>, <&wakeup_pin 13 25>,
+						 <&wakeup_pin 14 26>, <&wakeup_pin 15 27>,
+						 <&wakeup_pin 16 28>, <&wakeup_pin 18 18>,
+						 <&wakeup_pin 23 7>, <&wakeup_pin 26 19>,
+						 <&wakeup_pin 30 12>;
+
+				status = "disabled";
+			};
+
 			uart1: serial at 40014000 {
 				compatible = "nxp,lpc3220-hsuart";
 				reg = <0x40014000 0x1000>;

@@ -350,7 +397,8 @@
 			rtc: rtc at 40024000 {
 				compatible = "nxp,lpc3220-rtc";
 				reg = <0x40024000 0x1000>;
-				interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_RTC>;
 			};
 

@@ -403,7 +451,8 @@
 			adc: adc at 40048000 {
 				compatible = "nxp,lpc3220-adc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};

@@ -411,7 +460,8 @@
 			tsc: tsc at 40048000 {
 				compatible = "nxp,lpc3220-tsc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
Signature · 1 line
2.1.4
author maintainer
#14 lore raw

PATCH 8/10 irqchip: add LPC32xx interrupt controller driver

In reply to Vladimir Zapolskiy

The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2 interrupt controllers.

This is a list of new features in comparison to the legacy driver:
* irq types are taken from device tree settings, no more need to hardcode them,
* old driver is based on irq_domain_add_legacy, which causes problems with handling MIC hardware interrupt 0 produced by SIC1,
* there is one driver for MIC, SIC1 and SIC2, no more need to handle them separately, e.g. have two separate handlers for SIC1 and SIC2,
* the driver does not have any dependencies on hardcoded register offsets,
* the driver is much simpler for comprehension and more maintainable,
* SPARSE_IRQS option is supported.

The change disables compilation of a legacy driver found at arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate commit.

Signed-off-by Vladimir Zapolskiy <[email protected]>
---
 arch/arm/Kconfig                |   2 +
 arch/arm/mach-lpc32xx/Makefile  |   2 +-
 arch/arm/mach-lpc32xx/phy3250.c |   1 -
 drivers/irqchip/Makefile        |   1 +
 drivers/irqchip/irq-lpc32xx.c   | 227 ++++++++++++++++++++++++++++++++++++++++
 5 files changed, 231 insertions(+), 2 deletions(-)
 create mode 100644 drivers/irqchip/irq-lpc32xx.c
arch/arm/Kconfig +2 -0
index 5cc11f1..1f2c03f 100644
@@ -597,6 +597,8 @@ config ARCH_LPC32XX
 	select CPU_ARM926T
 	select GENERIC_CLOCKEVENTS
 	select HAVE_IDE
+	select MULTI_IRQ_HANDLER
+	select SPARSE_IRQ
 	select USE_OF
 	help
 	  Support for the NXP LPC32XX family of processors
arch/arm/mach-lpc32xx/Makefile +1 -1
index b1023c0..2a28f645 100644
@@ -2,6 +2,6 @@
 # Makefile for the linux kernel.
 #
 
-obj-y	:= irq.o common.o serial.o
+obj-y	:= common.o serial.o
 obj-y	+= pm.o suspend.o wakeup.o
 obj-y	+= phy3250.o
arch/arm/mach-lpc32xx/phy3250.c +0 -1
index 60f3392..92e8574 100644
@@ -259,7 +259,6 @@ static const char *const lpc32xx_dt_compat[] __initconst = {
 DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
 	.atag_offset	= 0x100,
 	.map_io		= lpc32xx_map_io,
-	.init_irq	= lpc32xx_init_irq,
 	.init_machine	= lpc3250_machine_init,
 	.dt_compat	= lpc32xx_dt_compat,
 	.restart	= lpc23xx_restart,
drivers/irqchip/Makefile +1 -0
index 177f78f..21008a6 100644
@@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
 obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2836.o
 obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o
 obj-$(CONFIG_ARCH_HIP04)		+= irq-hip04.o
+obj-$(CONFIG_ARCH_LPC32XX)		+= irq-lpc32xx.o
 obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
 obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
 obj-$(CONFIG_IRQ_MXS)			+= irq-mxs.o
drivers/irqchip/irq-lpc32xx.c new file +227 -0

227 lines not on this page · raw message

Signature · 1 line
2.1.4
#15 lore raw

PATCH 8/10 irqchip: add LPC32xx interrupt controller driver

Quoted 116 lines · Vladimir Zapolskiy

The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2 interrupt controllers.

This is a list of new features in comparison to the legacy driver:
* irq types are taken from device tree settings, no more need to hardcode them,
* old driver is based on irq_domain_add_legacy, which causes problems with handling MIC hardware interrupt 0 produced by SIC1,
* there is one driver for MIC, SIC1 and SIC2, no more need to handle them separately, e.g. have two separate handlers for SIC1 and SIC2,
* the driver does not have any dependencies on hardcoded register offsets,
* the driver is much simpler for comprehension and more maintainable,
* SPARSE_IRQS option is supported.

The change disables compilation of a legacy driver found at arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate commit.

Signed-off-by Vladimir Zapolskiy <[email protected]>
---
 arch/arm/Kconfig                |   2 +
 arch/arm/mach-lpc32xx/Makefile  |   2 +-
 arch/arm/mach-lpc32xx/phy3250.c |   1 -
 drivers/irqchip/Makefile        |   1 +
 drivers/irqchip/irq-lpc32xx.c   | 227 ++++++++++++++++++++++++++++++++++++++++
 5 files changed, 231 insertions(+), 2 deletions(-)
 create mode 100644 drivers/irqchip/irq-lpc32xx.c
arch/arm/Kconfig +2 -0
index 5cc11f1..1f2c03f 100644
@@ -597,6 +597,8 @@ config ARCH_LPC32XX
 	select CPU_ARM926T
 	select GENERIC_CLOCKEVENTS
 	select HAVE_IDE
+	select MULTI_IRQ_HANDLER
+	select SPARSE_IRQ
 	select USE_OF
 	help
 	  Support for the NXP LPC32XX family of processors
arch/arm/mach-lpc32xx/Makefile +1 -1
index b1023c0..2a28f645 100644
@@ -2,6 +2,6 @@
 # Makefile for the linux kernel.
 #
 
-obj-y	:= irq.o common.o serial.o
+obj-y	:= common.o serial.o
 obj-y	+= pm.o suspend.o wakeup.o
 obj-y	+= phy3250.o
arch/arm/mach-lpc32xx/phy3250.c +0 -1
index 60f3392..92e8574 100644
@@ -259,7 +259,6 @@ static const char *const lpc32xx_dt_compat[] __initconst = {
 DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
 	.atag_offset	= 0x100,
 	.map_io		= lpc32xx_map_io,
-	.init_irq	= lpc32xx_init_irq,
 	.init_machine	= lpc3250_machine_init,
 	.dt_compat	= lpc32xx_dt_compat,
 	.restart	= lpc23xx_restart,
drivers/irqchip/Makefile +1 -0
index 177f78f..21008a6 100644
@@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
 obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2836.o
 obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o
 obj-$(CONFIG_ARCH_HIP04)		+= irq-hip04.o
+obj-$(CONFIG_ARCH_LPC32XX)		+= irq-lpc32xx.o
 obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
 obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
 obj-$(CONFIG_IRQ_MXS)			+= irq-mxs.o
drivers/irqchip/irq-lpc32xx.c new file +32 -0
new file mode 100644
index 0000000..fcf281b
@@ -0,0 +1,227 @@
+/*
+ * Copyright 2015 Vladimir Zapolskiy <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <asm/exception.h>
+
+#define LPC32XX_INTC_MASK		0x00
+#define LPC32XX_INTC_RAW		0x04
+#define LPC32XX_INTC_STAT		0x08
+#define LPC32XX_INTC_POL		0x0C
+#define LPC32XX_INTC_TYPE		0x10
+#define LPC32XX_INTC_FIQ		0x14
+
+#define IRQS_PER_CONTROLLER		32
+
+struct lpc32xx_irq_chip {

drivers/irqchip/irq-lpc32xx.c line 42

Quoted 10 lines
drivers/irqchip/irq-lpc32xx.c new file +10 -0
+	void __iomem *base;
+	struct irq_domain *domain;
+	struct irq_chip chip;
+};
+
+static struct lpc32xx_irq_chip *lpc32xx_mic_data;
+
+static inline u32 lpc32xx_ic_read(struct irq_domain *id, u32 reg)
+{
+	struct lpc32xx_irq_chip *ic = (struct lpc32xx_irq_chip *)id->host_data;

Nit: No need for a cast.

Also, it is a bit weird to use the domain as the anchor for your chip-specific data. You end up following two pointers to get to it in most cases (irq_data -> domain -> chip), which could be avoided by using irq_data->chip_data.

drivers/irqchip/irq-lpc32xx.c line 44

Quoted 2 lines
drivers/irqchip/irq-lpc32xx.c new file +2 -0
+
+	return readl(ic->base + reg);

You should be able to use *_relaxed accessors.

Quoted 83 lines
drivers/irqchip/irq-lpc32xx.c new file +83 -0
+}
+
+static inline void lpc32xx_ic_write(struct irq_domain *id, u32 reg, u32 val)
+{
+	struct lpc32xx_irq_chip *ic = (struct lpc32xx_irq_chip *)id->host_data;
+
+	writel(val, ic->base + reg);
+}
+
+static void lpc32xx_irq_mask(struct irq_data *d)
+{
+	u32 val, mask = BIT(d->hwirq);
+
+	val = lpc32xx_ic_read(d->domain, LPC32XX_INTC_MASK) & ~mask;
+	lpc32xx_ic_write(d->domain, LPC32XX_INTC_MASK, val);
+}
+
+static void lpc32xx_irq_unmask(struct irq_data *d)
+{
+	u32 val, mask = BIT(d->hwirq);
+
+	val = lpc32xx_ic_read(d->domain, LPC32XX_INTC_MASK) | mask;
+	lpc32xx_ic_write(d->domain, LPC32XX_INTC_MASK, val);
+}
+
+static void lpc32xx_irq_ack(struct irq_data *d)
+{
+	u32 mask = BIT(d->hwirq);
+
+	lpc32xx_ic_write(d->domain, LPC32XX_INTC_RAW, mask);
+}
+
+static int lpc32xx_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	struct irq_domain *domain = d->domain;
+	u32 val, mask = BIT(d->hwirq);
+	bool high, edge;
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		edge = true;
+		high = true;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		edge = true;
+		high = false;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		edge = false;
+		high = true;
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		edge = false;
+		high = false;
+		break;
+	default:
+		pr_info("unsupported irq type %d\n", type);
+		return -EINVAL;
+	}
+
+	irqd_set_trigger_type(d, type);
+
+	val = lpc32xx_ic_read(domain, LPC32XX_INTC_POL);
+	if (high)
+		val |= mask;
+	else
+		val &= ~mask;
+	lpc32xx_ic_write(domain, LPC32XX_INTC_POL, val);
+
+	val = lpc32xx_ic_read(domain, LPC32XX_INTC_TYPE);
+	if (edge) {
+		val |= mask;
+		irq_set_handler_locked(d, handle_edge_irq);
+	} else {
+		val &= ~mask;
+		irq_set_handler_locked(d, handle_level_irq);
+	}
+	lpc32xx_ic_write(domain, LPC32XX_INTC_TYPE, val);
+
+	return 0;
+}
+
+static void __exception_irq_entry lpc32xx_handle_irq(struct pt_regs *regs)

drivers/irqchip/irq-lpc32xx.c line 137

Quoted 10 lines
drivers/irqchip/irq-lpc32xx.c new file +10 -0
+{
+	u32 hwirq;
+
+	do {
+		hwirq = lpc32xx_ic_read(lpc32xx_mic_data->domain,
+					LPC32XX_INTC_STAT);
+		if (hwirq)
+			handle_domain_irq(lpc32xx_mic_data->domain,
+					  ffs(hwirq) - 1, regs);
+	} while (hwirq);

If you imagine a case where you have multiple interrupts pending, you only handle a single interrupt, and go back reading the status register, which is going to be expensive.

You may want to handle all the interrupts described in your status before looping again.

Quoted 4 lines
drivers/irqchip/irq-lpc32xx.c new file +4 -0
+}
+
+static void lpc32xx_sic_handler(struct irq_desc *desc)
+{

drivers/irqchip/irq-lpc32xx.c line 151

Quoted 10 lines
drivers/irqchip/irq-lpc32xx.c new file +10 -0
+	struct lpc32xx_irq_chip *ic = irq_desc_get_handler_data(desc);
+	struct irq_domain *domain = ic->domain;
+	u32 hwirq;
+
+	do {
+		hwirq = lpc32xx_ic_read(domain, LPC32XX_INTC_STAT);
+		if (hwirq)
+			generic_handle_irq(irq_find_mapping(domain,
+							    ffs(hwirq) - 1));
+	} while (hwirq);

Same here. Also, you're missing chained_irq_enter/exit.

drivers/irqchip/irq-lpc32xx.c line 162

Quoted 11 lines
drivers/irqchip/irq-lpc32xx.c new file +11 -0
+}
+
+static int lpc32xx_irq_domain_map(struct irq_domain *id, unsigned int virq,
+				  irq_hw_number_t hw)
+{
+	struct lpc32xx_irq_chip *ic = (struct lpc32xx_irq_chip *)id->host_data;
+
+	irq_set_chip_and_handler(virq, &ic->chip, handle_level_irq);
+	irq_set_status_flags(virq, IRQ_LEVEL);
+	irq_set_noprobe(virq);
+

This is where you should populate the irq_data chip_data field.

Quoted 56 lines
drivers/irqchip/irq-lpc32xx.c new file +55 -0
+	return 0;
+}
+
+static void lpc32xx_irq_domain_unmap(struct irq_domain *id, unsigned int virq)
+{
+	irq_set_chip_and_handler(virq, NULL, NULL);
+}
+
+static const struct irq_domain_ops lpc32xx_irq_domain_ops = {
+	.map    = lpc32xx_irq_domain_map,
+	.unmap	= lpc32xx_irq_domain_unmap,
+	.xlate  = irq_domain_xlate_twocell,
+};
+
+static int __init lpc32xx_of_ic_init(struct device_node *node,
+				     struct device_node *parent)
+{
+	int parent_irq, i;
+	struct lpc32xx_irq_chip *irqc;
+
+	irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
+	if (!irqc)
+		return -ENOMEM;
+
+	irqc->chip.irq_ack = lpc32xx_irq_ack;
+	irqc->chip.irq_mask = lpc32xx_irq_mask;
+	irqc->chip.irq_unmask = lpc32xx_irq_unmask;
+	irqc->chip.irq_set_type = lpc32xx_irq_set_type;
+	irqc->chip.name = of_get_property(node, "interrupt-controller-name",
+					  NULL);
+
+	irqc->base = of_iomap(node, 0);
+	if (!irqc->base) {
+		pr_err("%s: unable to map registers\n", node->full_name);
+		return -EINVAL;
+	}
+
+	irqc->domain = irq_domain_add_linear(node, IRQS_PER_CONTROLLER,
+					     &lpc32xx_irq_domain_ops, irqc);
+	if (!irqc->domain) {
+		pr_err("unable to add irq domain\n");
+		iounmap(irqc->base);
+		return -ENODEV;
+	}
+
+	for (i = 0; i < of_irq_count(node); i++) {
+		parent_irq = irq_of_parse_and_map(node, i);
+		if (parent_irq)
+			irq_set_chained_handler_and_data(parent_irq,
+						 lpc32xx_sic_handler, irqc);
+	}
+
+	if (of_device_is_compatible(node, "nxp,lpc3220-mic")) {
+		lpc32xx_mic_data = irqc;
+		set_handle_irq(lpc32xx_handle_irq);

drivers/irqchip/irq-lpc32xx.c line 227

Quoted 10 lines
drivers/irqchip/irq-lpc32xx.c new file +10 -0
+	}
+
+	lpc32xx_ic_write(irqc->domain, LPC32XX_INTC_MASK, 0x00);
+	lpc32xx_ic_write(irqc->domain, LPC32XX_INTC_POL, 0x00);
+	lpc32xx_ic_write(irqc->domain, LPC32XX_INTC_TYPE, 0x00);
+
+	return 0;
+}
+IRQCHIP_DECLARE(nxp_lpc32xx_mic, "nxp,lpc3220-mic", lpc32xx_of_ic_init);
+IRQCHIP_DECLARE(nxp_lpc32xx_sic, "nxp,lpc3220-sic", lpc32xx_of_ic_init);

Thanks,

	M.
Signature · 1 line
Jazz is not dead. It just smells funny...
author maintainer
#16 lore raw

PATCH 9/10 irqchip: lpc32xx: add option to wakeup from an interrupt

In reply to Vladimir Zapolskiy

The change allows to set wakeup interrupts on client side.

Now all LPC32xx irq chips have assigned irq_set_wake callback, which is rerouted to some platform specific wakeup controller.

Mapping between particular interrupts and wakeup sources is taken from interrupt controller device tree node.

It is worth to mention that during initialization wakeup controller driver may appear after initialization of interrupt controller driver, this situation is correctly handled.

Signed-off-by Vladimir Zapolskiy <[email protected]>
---
 drivers/irqchip/irq-lpc32xx.c | 103 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 101 insertions(+), 2 deletions(-)
drivers/irqchip/irq-lpc32xx.c +101 -2
index fcf281b..e0f50da 100644
@@ -19,6 +19,7 @@
 #include <linux/of_platform.h>
 #include <linux/slab.h>
 #include <asm/exception.h>
+#include <mach/wakeup.h>
 
 #define LPC32XX_INTC_MASK		0x00
 #define LPC32XX_INTC_RAW		0x04

@@ -27,16 +28,53 @@
 #define LPC32XX_INTC_TYPE		0x10
 #define LPC32XX_INTC_FIQ		0x14
 
+struct irq_to_wakeup {
+	/*
+	 * wakeup controller driver initialization may be deferred,
+	 * get its platform driver in runtime by device node
+	 */
+	struct wakeup_controller *wakeup;
+	struct device_node *wakeup_node;
+	u32 bit;
+};
+
 #define IRQS_PER_CONTROLLER		32
 
 struct lpc32xx_irq_chip {
 	void __iomem *base;
 	struct irq_domain *domain;
 	struct irq_chip chip;
+	struct irq_to_wakeup i2w[IRQS_PER_CONTROLLER];
 };
 
 static struct lpc32xx_irq_chip *lpc32xx_mic_data;
 
+static struct wakeup_controller *get_wakeup_bit(struct irq_data *d, u32 *bit)
+{
+	struct irq_domain *id = d->domain;
+	struct lpc32xx_irq_chip *ic = (struct lpc32xx_irq_chip *)id->host_data;
+	struct irq_to_wakeup *i2w = &ic->i2w[d->hwirq];
+	struct platform_device *wakeup;
+
+	if (!i2w->wakeup_node)
+		return NULL;
+
+	if (!i2w->wakeup) {
+		pr_debug("searching wakeup device for interrupt %u\n",
+				 irq_find_mapping(id, d->hwirq));
+		wakeup = of_find_device_by_node(i2w->wakeup_node);
+		if (wakeup) {
+			i2w->wakeup = platform_get_drvdata(wakeup);
+			of_node_put(i2w->wakeup_node);
+		}
+	}
+
+	if (i2w->wakeup)
+		*bit = i2w->bit;
+
+	return i2w->wakeup;
+}
+
 static inline u32 lpc32xx_ic_read(struct irq_domain *id, u32 reg)
 {
 	struct lpc32xx_irq_chip *ic = (struct lpc32xx_irq_chip *)id->host_data;

@@ -77,8 +115,9 @@ static void lpc32xx_irq_ack(struct irq_data *d)
 static int lpc32xx_irq_set_type(struct irq_data *d, unsigned int type)
 {
 	struct irq_domain *domain = d->domain;
-	u32 val, mask = BIT(d->hwirq);
+	u32 bit, val, mask = BIT(d->hwirq);
 	bool high, edge;
+	struct wakeup_controller *wuc;
 
 	switch (type) {
 	case IRQ_TYPE_EDGE_RISING:

@@ -121,6 +160,24 @@ static int lpc32xx_irq_set_type(struct irq_data *d, unsigned int type)
 	}
 	lpc32xx_ic_write(domain, LPC32XX_INTC_TYPE, val);
 
+	wuc = get_wakeup_bit(d, &bit);
+	if (wuc)
+		lpc32xx_wakeup_set_edge(wuc, bit, high);
+
+	return 0;
+}
+
+static int lpc32xx_irq_set_wake(struct irq_data *d, unsigned int state)
+{
+	struct wakeup_controller *wuc;
+	u32 bit;
+
+	wuc = get_wakeup_bit(d, &bit);
+	if (wuc)
+		lpc32xx_wakeup_enable(wuc, bit, state);
+	else
+		return -ENODEV;
+
 	return 0;
 }
 

@@ -174,11 +231,42 @@ static const struct irq_domain_ops lpc32xx_irq_domain_ops = {
 	.xlate  = irq_domain_xlate_twocell,
 };
 
+static void __init of_node_to_wakeup(struct irq_to_wakeup *i2w,
+				     struct of_phandle_args *args)
+{
+	struct platform_device *wakeup;
+	int wakeup_cells = 0;
+	u32 hwirq;
+
+	if (!of_device_is_available(args->np))
+		return;
+
+	of_property_read_u32(args->np, "#wakeup-cells", &wakeup_cells);
+	if (wakeup_cells != 2) {
+		pr_info("%s: unsupported format of wakeup data, got %d\n",
+			args->np->full_name, wakeup_cells);
+		return;
+	}
+
+	hwirq = args->args[1];
+
+	wakeup = of_find_device_by_node(args->np);
+	if (wakeup) {
+		i2w[hwirq].wakeup = platform_get_drvdata(wakeup);
+	} else {
+		i2w[hwirq].wakeup_node = args->np;
+		of_node_get(i2w[hwirq].wakeup_node);
+	}
+
+	i2w[hwirq].bit = args->args[0];
+}
+
 static int __init lpc32xx_of_ic_init(struct device_node *node,
 				     struct device_node *parent)
 {
-	int parent_irq, i;
+	int parent_irq, i, ret;
 	struct lpc32xx_irq_chip *irqc;
+	struct of_phandle_args args;
 
 	irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
 	if (!irqc)

@@ -188,9 +276,20 @@ static int __init lpc32xx_of_ic_init(struct device_node *node,
 	irqc->chip.irq_mask = lpc32xx_irq_mask;
 	irqc->chip.irq_unmask = lpc32xx_irq_unmask;
 	irqc->chip.irq_set_type = lpc32xx_irq_set_type;
+	irqc->chip.irq_set_wake = lpc32xx_irq_set_wake;
 	irqc->chip.name = of_get_property(node, "interrupt-controller-name",
 					  NULL);
 
+	for (i = 0; ; i++) {
+		ret = of_parse_phandle_with_args(node, "wakeup-sources",
+						 "#wakeup-cells", i, &args);
+		if (ret)
+			break;
+
+		of_node_to_wakeup(irqc->i2w, &args);
+		of_node_put(args.np);
+	}
+
 	irqc->base = of_iomap(node, 0);
 	if (!irqc->base) {
 		pr_err("%s: unable to map registers\n", node->full_name);
Signature · 1 line
2.1.4
author maintainer
#17 lore raw

PATCH 10/10 arm: dts: lpc32xx: enable SIC1 and SIC2 by default

In reply to Vladimir Zapolskiy

After moving to a new LPC32xx interrupt controller driver it is safe to enable SIC1 and SIC2 devices, this allows to get working ADC, RTC, I2C and USB peripheral controllers again after long period since ...

Signed-off-by Vladimir Zapolskiy <[email protected]>
---
 arch/arm/boot/dts/lpc32xx.dtsi | 4 ----
 1 file changed, 4 deletions(-)
arch/arm/boot/dts/lpc32xx.dtsi +0 -4
index 8dda6e7..603f005 100644
@@ -341,8 +341,6 @@
 						 <&wakeup_int 24 20>, <&wakeup_int 29 8>,
 						 <&wakeup_int 30 6>, <&wakeup_int 31 7>,
 						 <&wakeup_pin 25 4>;
-
-				status = "disabled";
 			};
 
 			sic2: interrupt-controller at 40010000 {

@@ -369,8 +367,6 @@
 						 <&wakeup_pin 16 28>, <&wakeup_pin 18 18>,
 						 <&wakeup_pin 23 7>, <&wakeup_pin 26 19>,
 						 <&wakeup_pin 30 12>;
-
-				status = "disabled";
 			};
 
 			uart1: serial at 40014000 {
Signature · 1 line
2.1.4
#18 lore raw
In reply to Vladimir Zapolskiy
Quoted 3 lines · Vladimir Zapolskiy

The change adds wakeup controller platform driver and irqchip driver for NXP LPC32xx boards.

Hi Vladimir,

Just to let you know that we did some testing using this changeset; I tested the change on 4.5-rc1 with patch 4 to 7, 10 & 11 from:
http://permalink.gmane.org/gmane.linux.drivers.devicetree/144671

I was able to run our software (I2C SIC1 interrupt enable) without any problem on a custom LPC32xx board.

I did not test the other SIC1 interrupt sources that were generating issue previously (i.e. breaks the kernel with the message "unexpected IRQ trap at vector 00").

We did not get any problem with the MIC interrupts we are using.

Quoted 11 lines

Vladimir Zapolskiy (10):
dt-bindings: create arm/nxp folder and move LPC32xx SoC description to it
dt-bindings: nxp: add description of wakeup controller on LPC32xx
dt-bindings: interrupt-controllers: add description of SIC1 and SIC2
arm: lpc32xx: add wakeup platform driver
arm: dts: lpc32xx: assign interrupt types
arm: dts: lpc32xx: add description of IC wakeup controllers
arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC
irqchip: add LPC32xx interrupt controller driver
irqchip: lpc32xx: add option to wakeup from an interrupt
arm: dts: lpc32xx: enable SIC1 and SIC2 by default

Sylvain Lemieux

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#19 lore raw

cover irqchip: lpc32xx: add LPC32xx irqchip driver

Hi Vladimir,

Quoted 5 lines · Sylvain Lemieux
Quoted 3 lines · Vladimir Zapolskiy

The change adds wakeup controller platform driver and irqchip driver for NXP LPC32xx boards.

Quoted 21 lines

Hi Vladimir,

Just to let you know that we did some testing using this changeset; I tested the change on 4.5-rc1 with patch 4 to 7, 10 & 11 from:
http://permalink.gmane.org/gmane.linux.drivers.devicetree/144671

I was able to run our software (I2C SIC1 interrupt enable) without any problem on a custom LPC32xx board.

Quoted 11 lines

Vladimir Zapolskiy (10):
dt-bindings: create arm/nxp folder and move LPC32xx SoC description to it
dt-bindings: nxp: add description of wakeup controller on LPC32xx
dt-bindings: interrupt-controllers: add description of SIC1 and SIC2
arm: lpc32xx: add wakeup platform driver
arm: dts: lpc32xx: assign interrupt types
arm: dts: lpc32xx: add description of IC wakeup controllers
arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC
irqchip: add LPC32xx interrupt controller driver
irqchip: lpc32xx: add option to wakeup from an interrupt
arm: dts: lpc32xx: enable SIC1 and SIC2 by default

As per the feedback you gave in the following message:
http://article.gmane.org/gmane.linux.ports.arm.kernel/483540

are you planning to send a version 2 of this patch for v4.7?

Sylvain Lemieux

Quoted 5 lines

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author maintainer
#20 lore raw

cover irqchip: lpc32xx: add LPC32xx irqchip driver

Hi Sylvain,

Quoted 30 lines · Sylvain Lemieux

Hi Vladimir,

Quoted 5 lines · Sylvain Lemieux
Quoted 3 lines · Vladimir Zapolskiy

The change adds wakeup controller platform driver and irqchip driver for NXP LPC32xx boards.

Quoted 21 lines

Hi Vladimir,

Just to let you know that we did some testing using this changeset; I tested the change on 4.5-rc1 with patch 4 to 7, 10 & 11 from:
http://permalink.gmane.org/gmane.linux.drivers.devicetree/144671

I was able to run our software (I2C SIC1 interrupt enable) without any problem on a custom LPC32xx board.

Quoted 11 lines

Vladimir Zapolskiy (10):
dt-bindings: create arm/nxp folder and move LPC32xx SoC description to it
dt-bindings: nxp: add description of wakeup controller on LPC32xx
dt-bindings: interrupt-controllers: add description of SIC1 and SIC2
arm: lpc32xx: add wakeup platform driver
arm: dts: lpc32xx: assign interrupt types
arm: dts: lpc32xx: add description of IC wakeup controllers
arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC
irqchip: add LPC32xx interrupt controller driver
irqchip: lpc32xx: add option to wakeup from an interrupt
arm: dts: lpc32xx: enable SIC1 and SIC2 by default

Quoted 5 lines

As per the feedback you gave in the following message:
http://article.gmane.org/gmane.linux.ports.arm.kernel/483540

are you planning to send a version 2 of this patch for v4.7?

definitely, I plan to find enough time this week to rebase and submit v2. FWIW 2 changes from the series are found in v4.6.

--
With best wishes,
Vladimir