arm: dts: lpc32xx: updates to LPC32xx SoC and boards
Subsystems (10)
Vladimir Zapolskiy
maintainerv2 cover arm: dts: lpc32xx: updates to LPC32xx SoC and boards
The change improves description of NXP LPC32xx hardware, among important changes it adds standard timers and external memory controller nodes, splits PWM device node into two,
Changes from v1 to v2:
- removed v1 2/5 "arm: dts: lpc32xx: fix improper usage of ranges property"
- v1 4/5 "arm: dts: lpc32xx: remove unneeded cell settings from cpus" is replaced by v2 3/8 "arm: dts: lpc32xx: add reg property to cpu device node"
- new change, sets physical memory offset for EA3250 and PHY3250 v5/8
- new change, added EMC device node v2 6/8
- new change, added standard timer nodes v2 7/8
- new change, grouped USB subdevices together v2 8/8
Link to the obsolete patch series:
- http://www.spinics.net/lists/arm-kernel/msg451745.html
Vladimir Zapolskiy (8):
arm: dts: lpc32xx: change include syntax to be C preprocessor friendly
arm: dts: lpc32xx: add labels to all defined peripheral nodes
arm: dts: lpc32xx: add reg property to cpu device node
arm: dts: lpc32xx: add device node for the second pwm controller
arm: dts: ea3250/phy3250: specify phys memory offset for lpc32xx boards
arm: dts: lpc32xx: add external memory controller device node
arm: dts: lpc32xx: add device nodes for standard timers
arm: dts: lpc32xx: move USB controller subdevices into own device node
arch/arm/boot/dts/ea3250.dts | 41 +++++------- arch/arm/boot/dts/lpc32xx.dtsi | 142 ++++++++++++++++++++++++++++++----------- arch/arm/boot/dts/phy3250.dts | 41 +++++------- 3 files changed, 139 insertions(+), 85 deletions(-)
Signature · 1 line
2.1.4
Vladimir Zapolskiy
maintainerPATCH v2 1/8 arm: dts: lpc32xx: change include syntax to be C preprocessor friendly
The change replaces /include/ to #include in lpc32xx.dtsi and derivatives, it is required, if C preprocessor is intended to be used over dtsi/dts files, otherwise errors like one below are generated:
Error: ea3250.dts:15.1-9 syntax error
FATAL ERROR: Unable to parse input tree
---
Changes from v1 to v2:
- none
arch/arm/boot/dts/ea3250.dts | 2 +- arch/arm/boot/dts/lpc32xx.dtsi | 2 +- arch/arm/boot/dts/phy3250.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/boot/dts/ea3250.dts +1 -1
@@ -12,7 +12,7 @@ */ /dts-v1/; -/include/ "lpc32xx.dtsi" +#include "lpc32xx.dtsi" / { model = "Embedded Artists LPC3250 board based on NXP LPC3250";
arch/arm/boot/dts/lpc32xx.dtsi +1 -1
@@ -11,7 +11,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { compatible = "nxp,lpc3220";
arch/arm/boot/dts/phy3250.dts +1 -1
@@ -12,7 +12,7 @@ */ /dts-v1/; -/include/ "lpc32xx.dtsi" +#include "lpc32xx.dtsi" / { model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
Signature · 1 line
2.1.4
Vladimir Zapolskiy
maintainerPATCH v2 2/8 arm: dts: lpc32xx: add labels to all defined peripheral nodes
In reply to Vladimir ZapolskiyTo simplify writing of dts files for all lpc32xx.dtsi users who adjust device node properties, add labels to all defined peripheral device nodes in lpc32xx.dtsi.
---
Changes from v1 to v2:
- none
arch/arm/boot/dts/lpc32xx.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)
arch/arm/boot/dts/lpc32xx.dtsi +10 -10
@@ -49,7 +49,7 @@ status = "disabled"; }; - dma at 31000000 { + dma: dma at 31000000 { compatible = "arm,pl080", "arm,primecell"; reg = <0x31000000 0x1000>; interrupts = <0x1c 0>;
@@ -58,21 +58,21 @@ /* * Enable either ohci or usbd (gadget)! */ - ohci at 31020000 { + ohci: ohci at 31020000 { compatible = "nxp,ohci-nxp", "usb-ohci"; reg = <0x31020000 0x300>; interrupts = <0x3b 0>; status = "disabled"; }; - usbd at 31020000 { + usbd: usbd at 31020000 { compatible = "nxp,lpc3220-udc"; reg = <0x31020000 0x300>; interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; status = "disabled"; }; - clcd at 31040000 { + clcd: clcd at 31040000 { compatible = "arm,pl110", "arm,primecell"; reg = <0x31040000 0x1000>; interrupts = <0x0e 0>;
@@ -118,7 +118,7 @@ reg = <0x20094000 0x1000>; }; - sd at 20098000 { + sd: sd at 20098000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x20098000 0x1000>; interrupts = <0x0f 0>, <0x0d 0>;
@@ -243,7 +243,7 @@ status = "disabled"; }; - rtc at 40024000 { + rtc: rtc at 40024000 { compatible = "nxp,lpc3220-rtc"; reg = <0x40024000 0x1000>; interrupts = <0x34 0>;
@@ -256,7 +256,7 @@ #gpio-cells = <3>; /* bank, pin, flags */ }; - watchdog at 4003C000 { + watchdog: watchdog at 4003C000 { compatible = "nxp,pnx4008-wdt"; reg = <0x4003C000 0x1000>; };
@@ -268,21 +268,21 @@ * them */ - adc at 40048000 { + adc: adc at 40048000 { compatible = "nxp,lpc3220-adc"; reg = <0x40048000 0x1000>; interrupts = <0x27 0>; status = "disabled"; }; - tsc at 40048000 { + tsc: tsc at 40048000 { compatible = "nxp,lpc3220-tsc"; reg = <0x40048000 0x1000>; interrupts = <0x27 0>; status = "disabled"; }; - key at 40050000 { + key: key at 40050000 { compatible = "nxp,lpc3220-key"; reg = <0x40050000 0x1000>; interrupts = <54 0>;
Signature · 1 line
2.1.4
Vladimir Zapolskiy
maintainerPATCH v2 3/8 arm: dts: lpc32xx: add reg property to cpu device node
In reply to Vladimir ZapolskiyAccording to device tree bindings for ARM cpus cpu node must contain a reg property for enumeration scheme.
The change adds reg = <0x0> indicating that the processor does not have CPU identification register and updates cell settings.
---
Changes from v1 to v2:
- new change, replaced v1 4/5 "arm: dts: lpc32xx: remove unneeded cell settings from cpus"
arch/arm/boot/dts/lpc32xx.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
arch/arm/boot/dts/lpc32xx.dtsi +3 -2
@@ -18,12 +18,13 @@ interrupt-parent = <&mic>; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu at 0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0x0>; }; };
Signature · 1 line
2.1.4
Vladimir Zapolskiy
maintainerPATCH v2 4/8 arm: dts: lpc32xx: add device node for the second pwm controller
In reply to Vladimir ZapolskiyLPC32xx SoCs have two independent PWM controllers, they have different clock parents, clock gates and even slightly different controls, each of these two PWM controllers has one output channel. Due to almost similar controls arranged in a row it is incorrectly assumed that there is one PWM controller with two channels, fix this problem in lpc32xx.dtsi, which at the moment prevents separate configuration of different clock parents and gates for both PWM controllers.
---
Changes from v1 to v2:
- none
arch/arm/boot/dts/lpc32xx.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
arch/arm/boot/dts/lpc32xx.dtsi +8 -2
@@ -290,9 +290,15 @@ status = "disabled"; }; - pwm: pwm at 4005C000 { + pwm1: pwm at 4005C000 { compatible = "nxp,lpc3220-pwm"; - reg = <0x4005C000 0x8>; + reg = <0x4005C000 0x4>; + status = "disabled"; + }; + + pwm2: pwm at 4005C004 { + compatible = "nxp,lpc3220-pwm"; + reg = <0x4005C004 0x4>; status = "disabled"; }; };
Signature · 1 line
2.1.4
Vladimir Zapolskiy
maintainerPATCH v2 5/8 arm: dts: ea3250/phy3250: specify phys memory offset for lpc32xx boards
In reply to Vladimir ZapolskiyIn case if SDRAM memory region is not populated by a bootloader, provide this value in device trees for EA3250 and PHY3250 boards.
---
Changes from v1 to v2:
- none, new change
arch/arm/boot/dts/ea3250.dts | 2 +- arch/arm/boot/dts/phy3250.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/boot/dts/ea3250.dts +1 -1
@@ -22,7 +22,7 @@ memory { device_type = "memory"; - reg = <0 0x4000000>; + reg = <0x80000000 0x4000000>; }; ahb {
arch/arm/boot/dts/phy3250.dts +1 -1
@@ -22,7 +22,7 @@ memory { device_type = "memory"; - reg = <0 0x4000000>; + reg = <0x80000000 0x4000000>; }; ahb {
Signature · 1 line
2.1.4
Vladimir Zapolskiy
maintainerPATCH v2 6/8 arm: dts: lpc32xx: add external memory controller device node
In reply to Vladimir ZapolskiyThe change adds a description of ARM PrimeCell PL175 memory controller, which is found on NXP LPC32xx SoCs.
The controller supports up to 4 static memory devices mapped to 0xE000 0000 - 0xE3FF FFFF physical memory area.
---
Changes from v1 to v2:
- none, new change
arch/arm/boot/dts/lpc32xx.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)
arch/arm/boot/dts/lpc32xx.dtsi +15 -1
@@ -32,7 +32,8 @@ #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - ranges = <0x20000000 0x20000000 0x30000000>; + ranges = <0x20000000 0x20000000 0x30000000>, + <0xe0000000 0xe0000000 0x04000000>; /* * Enable either SLC or MLC
@@ -86,6 +87,19 @@ interrupts = <0x1d 0>; }; + emc: memory-controller at 31080000 { + compatible = "arm,pl175", "arm,primecell"; + reg = <0x31080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xe0000000 0x01000000>, + <1 0xe1000000 0x01000000>, + <2 0xe2000000 0x01000000>, + <3 0xe3000000 0x01000000>; + status = "disabled"; + }; + apb { #address-cells = <1>; #size-cells = <1>;
Signature · 1 line
2.1.4
Vladimir Zapolskiy
maintainerPATCH v2 7/8 arm: dts: lpc32xx: add device nodes for standard timers
In reply to Vladimir ZapolskiyFrom: Vladimir Zapolskiy <[email protected]>
NXP LPC32xx SoCs have 6 standard timers, add device nodes to describe them.
---
Changes from v1 to v2:
- none, new change
arch/arm/boot/dts/lpc32xx.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+)
arch/arm/boot/dts/lpc32xx.dtsi +40 -0
@@ -271,11 +271,31 @@ #gpio-cells = <3>; /* bank, pin, flags */ }; + timer4: timer at 4002C000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x4002C000 0x1000>; + interrupts = <0x3 0>; + status = "disabled"; + }; + + timer5: timer at 40030000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40030000 0x1000>; + interrupts = <0x4 0>; + status = "disabled"; + }; + watchdog: watchdog at 4003C000 { compatible = "nxp,pnx4008-wdt"; reg = <0x4003C000 0x1000>; }; + timer0: timer at 40044000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40044000 0x1000>; + interrupts = <0x10 0>; + }; + /* * TSC vs. ADC: Since those two share the same * hardware, you need to choose from one of the
@@ -297,6 +317,12 @@ status = "disabled"; }; + timer1: timer at 4004C000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x4004C000 0x1000>; + interrupts = <0x11 0>; + }; + key: key at 40050000 { compatible = "nxp,lpc3220-key"; reg = <0x40050000 0x1000>;
@@ -304,6 +330,13 @@ status = "disabled"; }; + timer2: timer at 40058000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40058000 0x1000>; + interrupts = <0x12 0>; + status = "disabled"; + }; + pwm1: pwm at 4005C000 { compatible = "nxp,lpc3220-pwm"; reg = <0x4005C000 0x4>;
@@ -315,6 +348,13 @@ reg = <0x4005C004 0x4>; status = "disabled"; }; + + timer3: timer at 40060000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40060000 0x1000>; + interrupts = <0x13 0>; + status = "disabled"; + }; }; }; };
Signature · 1 line
2.1.4
Vladimir Zapolskiy
maintainerPATCH v3 7/8 arm: dts: lpc32xx: add device nodes for standard timers
NXP LPC32xx SoCs have 6 standard timers, add device nodes to describe them.
---
Changes from v2 to v3:
- corrected email address in "from" field
Changes from v1 to v2:
- none, new change
arch/arm/boot/dts/lpc32xx.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+)
arch/arm/boot/dts/lpc32xx.dtsi +40 -0
@@ -271,11 +271,31 @@ #gpio-cells = <3>; /* bank, pin, flags */ }; + timer4: timer at 4002C000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x4002C000 0x1000>; + interrupts = <0x3 0>; + status = "disabled"; + }; + + timer5: timer at 40030000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40030000 0x1000>; + interrupts = <0x4 0>; + status = "disabled"; + }; + watchdog: watchdog at 4003C000 { compatible = "nxp,pnx4008-wdt"; reg = <0x4003C000 0x1000>; }; + timer0: timer at 40044000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40044000 0x1000>; + interrupts = <0x10 0>; + }; + /* * TSC vs. ADC: Since those two share the same * hardware, you need to choose from one of the
@@ -297,6 +317,12 @@ status = "disabled"; }; + timer1: timer at 4004C000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x4004C000 0x1000>; + interrupts = <0x11 0>; + }; + key: key at 40050000 { compatible = "nxp,lpc3220-key"; reg = <0x40050000 0x1000>;
@@ -304,6 +330,13 @@ status = "disabled"; }; + timer2: timer at 40058000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40058000 0x1000>; + interrupts = <0x12 0>; + status = "disabled"; + }; + pwm1: pwm at 4005C000 { compatible = "nxp,lpc3220-pwm"; reg = <0x4005C000 0x4>;
@@ -315,6 +348,13 @@ reg = <0x4005C004 0x4>; status = "disabled"; }; + + timer3: timer at 40060000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40060000 0x1000>; + interrupts = <0x13 0>; + status = "disabled"; + }; }; }; };
Signature · 1 line
2.1.4
Vladimir Zapolskiy
maintainerPATCH v2 8/8 arm: dts: lpc32xx: move USB controller subdevices into own device node
In reply to Vladimir ZapolskiyNXP LPC32xx SoC has one USB OTG controller, which is supposed to work with an external phy (default is NXP ISP1301).
Practically the USB controller contains 5 subdevices:
- host controller 0x3102 0000 -- 0x3102 00FF
- OTG controller 0x3102 0100 -- 0x3102 01FF
- device controller 0x3102 0200 -- 0x3102 02FF
- I2C controller 0x3102 0300 -- 0x3102 03FF
- clock controller 0x3102 0F00 -- 0x3102 0FFF
The USB controller can be considered as a "bus", because the subdevices above are relatively independent, for example I2C controller is the same as other two general purpose I2C controllers found on SoC.
The change is not intended to modify any logic, but it rearranges existing device nodes, in future it is planned to add a USB clock controller device node into the same group.
---
Changes from v1 to v2:
- none, new change
arch/arm/boot/dts/ea3250.dts | 37 ++++++++++++----------------- arch/arm/boot/dts/lpc32xx.dtsi | 53 ++++++++++++++++++++++++------------------ arch/arm/boot/dts/phy3250.dts | 37 ++++++++++++----------------- 3 files changed, 60 insertions(+), 67 deletions(-)
arch/arm/boot/dts/ea3250.dts +15 -22
@@ -31,19 +31,6 @@ use-iram; }; - /* Here, choose exactly one from: ohci, usbd */ - ohci at 31020000 { - transceiver = <&isp1301>; - status = "okay"; - }; - -/* - usbd at 31020000 { - transceiver = <&isp1301>; - status = "okay"; - }; -*/ - /* 128MB Flash via SLC NAND controller */ slc: flash at 20020000 { status = "okay";
@@ -130,15 +117,6 @@ clock-frequency = <100000>; }; - i2cusb: i2c at 31020300 { - clock-frequency = <100000>; - - isp1301: usb-transceiver at 2d { - compatible = "nxp,isp1301"; - reg = <0x2d>; - }; - }; - sd at 20098000 { wp-gpios = <&pca9532 5 0>; cd-gpios = <&pca9532 4 0>;
@@ -279,3 +257,18 @@ }; }; }; + +/* Here, choose exactly one from: ohci, usbd */ +&ohci /* &usbd */ { + transceiver = <&isp1301>; + status = "okay"; +}; + +&i2cusb { + clock-frequency = <100000>; + + isp1301: usb-transceiver at 2d { + compatible = "nxp,isp1301"; + reg = <0x2d>; + }; +};
arch/arm/boot/dts/lpc32xx.dtsi +30 -23
66 lines not on this page · raw message
arch/arm/boot/dts/phy3250.dts +15 -22
@@ -31,19 +31,6 @@ use-iram; }; - /* Here, choose exactly one from: ohci, usbd */ - ohci at 31020000 { - transceiver = <&isp1301>; - status = "okay"; - }; - -/* - usbd at 31020000 { - transceiver = <&isp1301>; - status = "okay"; - }; -*/ - clcd at 31040000 { status = "okay"; };
@@ -123,15 +110,6 @@ clock-frequency = <100000>; }; - i2cusb: i2c at 31020300 { - clock-frequency = <100000>; - - isp1301: usb-transceiver at 2c { - compatible = "nxp,isp1301"; - reg = <0x2c>; - }; - }; - ssp0: ssp at 20084000 { #address-cells = <1>; #size-cells = <0>;
@@ -200,3 +178,18 @@ }; }; }; + +/* Here, choose exactly one from: ohci, usbd */ +&ohci /* &usbd */ { + transceiver = <&isp1301>; + status = "okay"; +}; + +&i2cusb { + clock-frequency = <100000>; + + isp1301: usb-transceiver at 2c { + compatible = "nxp,isp1301"; + reg = <0x2c>; + }; +};
Signature · 1 line
2.1.4
Rob Herring
maintainerPATCH v2 8/8 arm: dts: lpc32xx: move USB controller subdevices into own device node
Quoted 9 lines · Vladimir Zapolskiy
NXP LPC32xx SoC has one USB OTG controller, which is supposed to work with an external phy (default is NXP ISP1301).
Practically the USB controller contains 5 subdevices:
- host controller0x31020000 --0x310200FF
- OTG controller0x31020100 --0x310201FF
- device controller0x31020200 --0x310202FF
- I2C controller0x31020300 --0x310203FF
- clock controller0x31020F00 --0x31020FFF
[...]
Quoted 23 lines
arch/arm/boot/dts/lpc32xx.dtsi +8
-14- /* - * Enable either ohci or usbd (gadget)! - */ - ohci: ohci at 31020000 { - compatible = "nxp,ohci-nxp", "usb-ohci"; - reg = <0x31020000 0x300>; - interrupts = <0x3b 0>; - status = "disabled"; - }; + usb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0x31020000 0x00001000>; - usbd: usbd at 31020000 { - compatible = "nxp,lpc3220-udc"; - reg = <0x31020000 0x300>; - interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; - status = "disabled"; + /* + * Enable either ohci or usbd (gadget)! + */
arch/arm/boot/dts/lpc32xx.dtsi line 78
Quoted 10 lines
arch/arm/boot/dts/lpc32xx.dtsi +10
-0+ ohci: ohci at 0 { + compatible = "nxp,ohci-nxp", "usb-ohci"; + reg = <0x0 0x300>; + interrupts = <0x3b 0>; + status = "disabled"; + }; + + usbd: usbd at 0 { + compatible = "nxp,lpc3220-udc"; + reg = <0x0 0x300>;
Not a result of this change, but you are overlapping addresses. Please don't do that. It causes problems adding device resources into the resource tree (i.e. request_resource).
Rob
Vladimir Zapolskiy
maintainerPATCH v2 8/8 arm: dts: lpc32xx: move USB controller subdevices into own device node
Quoted 47 lines · Rob Herring
Quoted 9 lines · Vladimir Zapolskiy
NXP LPC32xx SoC has one USB OTG controller, which is supposed to work with an external phy (default is NXP ISP1301).
Practically the USB controller contains 5 subdevices:
- host controller0x31020000 --0x310200FF
- OTG controller0x31020100 --0x310201FF
- device controller0x31020200 --0x310202FF
- I2C controller0x31020300 --0x310203FF
- clock controller0x31020F00 --0x31020FFF[...]
Quoted 23 lines
arch/arm/boot/dts/lpc32xx.dtsi +8
-14- /* - * Enable either ohci or usbd (gadget)! - */ - ohci: ohci at 31020000 { - compatible = "nxp,ohci-nxp", "usb-ohci"; - reg = <0x31020000 0x300>; - interrupts = <0x3b 0>; - status = "disabled"; - }; + usb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0x31020000 0x00001000>; - usbd: usbd at 31020000 { - compatible = "nxp,lpc3220-udc"; - reg = <0x31020000 0x300>; - interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; - status = "disabled"; + /* + * Enable either ohci or usbd (gadget)! + */arch/arm/boot/dts/lpc32xx.dtsi line 78
Quoted 10 lines
arch/arm/boot/dts/lpc32xx.dtsi +10
-0+ ohci: ohci at 0 { + compatible = "nxp,ohci-nxp", "usb-ohci"; + reg = <0x0 0x300>; + interrupts = <0x3b 0>; + status = "disabled"; + }; + + usbd: usbd at 0 { + compatible = "nxp,lpc3220-udc"; + reg = <0x0 0x300>;
Quoted 4 lines
Not a result of this change, but you are overlapping addresses. Please don't do that. It causes problems adding device resources into the resource tree (i.e.
request_resource).
As you noticed this is legacy code, it will be corrected after fixing USB host and device drivers, and this is in long term plans. USB changes require at least CCF and IRQ chip changes applied.
--
With best wishes,
Vladimir
v2 cover arm: dts: lpc32xx: updates to LPC32xx SoC and boards
In reply to Vladimir ZapolskiyQuoted 4 lines · On Sunday 18 October 2015 00:35:49 Vladimir Zapolskiy wrote:
The change improves description of NXP LPC32xx hardware, among important changes it adds standard timers and external memory controller nodes, splits PWM device node into two,
Quoted 8 lines
Changes from v1 to v2:
- removed v1 2/5 "arm: dts: lpc32xx: fix improper usage of ranges property"
- v1 4/5 "arm: dts: lpc32xx: remove unneeded cell settings from cpus" is replaced by v2 3/8 "arm: dts: lpc32xx: add reg property to cpu device node"
- new change, sets physical memory offset for EA3250 and PHY3250 v5/8
- new change, added EMC device node v2 6/8
- new change, added standard timer nodes v2 7/8
- new change, grouped USB subdevices together v2 8/8
Looks ok to me. Who should pick them up? I haven't seen pull requests from Roland in a while. If he's still interested in the port, I think it would be best if he could create a branch here.
If not, we can pick them up directly this time into arm-soc, but then we should find a new maintainer.
Arnd
Vladimir Zapolskiy
maintainerv2 cover arm: dts: lpc32xx: updates to LPC32xx SoC and boards
Hi Arnd,
Quoted 14 lines · Arnd Bergmann
Quoted 4 lines · On Sunday 18 October 2015 00:35:49 Vladimir Zapolskiy wrote:
The change improves description of NXP LPC32xx hardware, among important changes it adds standard timers and external memory controller nodes, splits PWM device node into two,
Quoted 8 lines
Changes from v1 to v2:
- removed v1 2/5 "arm: dts: lpc32xx: fix improper usage of ranges property"
- v1 4/5 "arm: dts: lpc32xx: remove unneeded cell settings from cpus" is replaced by v2 3/8 "arm: dts: lpc32xx: add reg property to cpu device node"
- new change, sets physical memory offset for EA3250 and PHY3250 v5/8
- new change, added EMC device node v2 6/8
- new change, added standard timer nodes v2 7/8
- new change, grouped USB subdevices together v2 8/8
Quoted 3 lines
Looks ok to me. Who should pick them up? I haven't seen pull requests from Roland in a while. If he's still interested in the port, I think it would be best if he could create a branch here.
I still don't see a reply from Roland, if possible please apply the patches to arm-soc this time.
Quoted 3 lines
If not, we can pick them up directly this time into arm-soc, but then we should find a new maintainer.
I have some interest in LPC32xx SoC, I know the SoC very well (authored LPC32xx support in U-boot) and there are more patches in my queue, if there is no objection from anyone, I would be happy to become a maintainer of the platform.
--
With best wishes,
Vladimir
Vladimir Zapolskiy
maintainerv2 cover arm: dts: lpc32xx: updates to LPC32xx SoC and boards
In reply to Arnd BergmannHi Arnd,
Quoted 14 lines · Arnd Bergmann
Quoted 4 lines · On Sunday 18 October 2015 00:35:49 Vladimir Zapolskiy wrote:
The change improves description of NXP LPC32xx hardware, among important changes it adds standard timers and external memory controller nodes, splits PWM device node into two,
Quoted 8 lines
Changes from v1 to v2:
- removed v1 2/5 "arm: dts: lpc32xx: fix improper usage of ranges property"
- v1 4/5 "arm: dts: lpc32xx: remove unneeded cell settings from cpus" is replaced by v2 3/8 "arm: dts: lpc32xx: add reg property to cpu device node"
- new change, sets physical memory offset for EA3250 and PHY3250 v5/8
- new change, added EMC device node v2 6/8
- new change, added standard timer nodes v2 7/8
- new change, grouped USB subdevices together v2 8/8
Quoted 8 lines
Looks ok to me. Who should pick them up? I haven't seen pull requests from Roland in a while. If he's still interested in the port, I think it would be best if he could create a branch here.
If not, we can pick them up directly this time into arm-soc, but then we should find a new maintainer.
Arnd
please pick this series up for v4.3, if it is still possible.
Thank you.
--
With best wishes,
Vladimir
Vladimir Zapolskiy
maintainerv2 cover arm: dts: lpc32xx: updates to LPC32xx SoC and boards
Hello Arnd,
Quoted 21 lines · Vladimir Zapolskiy
Hi Arnd,
Quoted 18 lines · Arnd Bergmann
Quoted 4 lines · On Sunday 18 October 2015 00:35:49 Vladimir Zapolskiy wrote:
The change improves description of NXP LPC32xx hardware, among important changes it adds standard timers and external memory controller nodes, splits PWM device node into two,
Quoted 8 lines
Changes from v1 to v2:
- removed v1 2/5 "arm: dts: lpc32xx: fix improper usage of ranges property"
- v1 4/5 "arm: dts: lpc32xx: remove unneeded cell settings from cpus" is replaced by v2 3/8 "arm: dts: lpc32xx: add reg property to cpu device node"
- new change, sets physical memory offset for EA3250 and PHY3250 v5/8
- new change, added EMC device node v2 6/8
- new change, added standard timer nodes v2 7/8
- new change, grouped USB subdevices together v2 8/8Looks ok to me. Who should pick them up? I haven't seen pull requests from Roland in a while. If he's still interested in the port, I think it would be best if he could create a branch here.
Quoted 9 lines
Quoted 4 lines
If not, we can pick them up directly this time into arm-soc, but then we should find a new maintainer.
Arnd
please pick this series up for v4.3, if it is still possible.
Thank you.
in connection to previous discussion started here [1] I want to ask your opinion, does it make sense to support non-DT LPC32xx platforms (by the way there is no such platforms in vanilla)?
In particular I'd like to remove legacy platform data support and clean-up mach-lpc32xx, e.g. remove duplicated timer driver etc.
At the moment I've completed development and tested:
* common clock framework driver (no review comments from maintainers so far),
* irqchip driver (SPARSE_IRQ is supported),
* as a dependency to IRQ changes I developed a wakeup controller driver,
* as a dependency to IRQ changes GPIO driver is rewritten -- at the moment it strictly depends on hwirq plus its current version breaks board boot in v4.4, see [2].
In general the platform is broken since commit 76ba59f8366 ("genirq: Add irq_domain-aware core IRQ handler"), dated Aug 26 2014 (!), because the platform is based on legacy irq domain and hwirq 0 is actively exploited -- this is a cascaded irq to one of the sub-irq controllers.
All done work allows to remove thousands of LoCs and make LPC32xx boot and work again at the price of discontinued legacy DTB to new kernel compatibility (for example due to missed clocks properties etc.) and removed platform_data hooks.
I can continue to improve LPC32xx platform, but I believe I need some kind of approval from ARM maintainers to convince clk/irqchip/gpio maintainers to accept my work. What would be your opinion on this subject?
[1] http://www.spinics.net/lists/arm-kernel/msg452447.html
[2] https://www.mail-archive.com/linux-gpio at vger.kernel.org/msg11028.html
--
With best wishes,
Vladimir
v2 cover arm: dts: lpc32xx: updates to LPC32xx SoC and boards
Quoted 20 lines · On Friday 13 November 2015 22:20:26 Vladimir Zapolskiy wrote:
Quoted 19 lines · Vladimir Zapolskiy
Quoted 18 lines · Arnd Bergmann
Quoted 4 lines · On Sunday 18 October 2015 00:35:49 Vladimir Zapolskiy wrote:
The change improves description of NXP LPC32xx hardware, among important changes it adds standard timers and external memory controller nodes, splits PWM device node into two,
Quoted 8 lines
Changes from v1 to v2:
- removed v1 2/5 "arm: dts: lpc32xx: fix improper usage of ranges property"
- v1 4/5 "arm: dts: lpc32xx: remove unneeded cell settings from cpus" is replaced by v2 3/8 "arm: dts: lpc32xx: add reg property to cpu device node"
- new change, sets physical memory offset for EA3250 and PHY3250 v5/8
- new change, added EMC device node v2 6/8
- new change, added standard timer nodes v2 7/8
- new change, grouped USB subdevices together v2 8/8Looks ok to me. Who should pick them up? I haven't seen pull requests from Roland in a while. If he's still interested in the port, I think it would be best if he could create a branch here.
Quoted 5 lines
Quoted 5 lines
Quoted 3 lines
If not, we can pick them up directly this time into arm-soc, but then we should find a new maintainer.
please pick this series up for v4.3, if it is still possible.
Hi Vladimir,
Sorry for missing this for the merge window. We sometimes don't see stuff for inclusion when it doesn't get sent to arm at kernel.org.
That alias is for all arm-soc maintainers combined, and this time I happened to hand over to Olof who did the merges at the end of the cycle.
Please rebase your patches on top of v4.4-rc1 next week and send them again.
Quoted 3 lines
in connection to previous discussion started here [1] I want to ask your opinion, does it make sense to support non-DT LPC32xx platforms (by the way there is no such platforms in vanilla)?
No, we have made it rather clear in the past that we would not do that.
lpc32xx was one of the earliest platforms to move to devicetree a few years ago, but a lot of the details were not worked out at the time, and the cleanups stagnated at some point, so lpc32xx is in a rather unique intermediate state now.
Quoted 2 lines
In particular I'd like to remove legacy platform data support and clean-up mach-lpc32xx, e.g. remove duplicated timer driver etc.
That would be great.
Quoted 9 lines
At the moment I've completed development and tested:
* common clock framework driver (no review comments from maintainers so far),
* irqchip driver (SPARSE_IRQis supported),
* as a dependency to IRQ changes I developed a wakeup controller driver,
* as a dependency to IRQ changes GPIO driver is rewritten -- at the moment it strictly depends on hwirq plus its current version breaks board boot in v4.4, see [2].
Quoted 4 lines
In general the platform is broken since commit
76ba59f8366("genirq: Add irq_domain-aware core IRQ handler"), dated Aug 26 2014 (!), because the platform is based on legacy irq domain and hwirq 0 is actively exploited -- this is a cascaded irq to one of the sub-irq controllers.
Ok, thanks for letting us know. We should of course fix this and perhaps backport the fix to stable kernels, but more importantly it means that nobody has noticed the breakage for a while and that gives us some more freedom to change things now.
Quoted 4 lines
All done work allows to remove thousands of LoCs and make LPC32xx boot and work again at the price of discontinued legacy DTB to new kernel compatibility (for example due to missed clocks properties etc.) and removed
platform_datahooks.
sounds good.
Quoted 6 lines
I can continue to improve LPC32xx platform, but I believe I need some kind of approval from ARM maintainers to convince clk/irqchip/gpio maintainers to accept my work. What would be your opinion on this subject?
[1] http://www.spinics.net/lists/arm-kernel/msg452447.html
[2] https://www.mail-archive.com/linux-gpio at vger.kernel.org/msg11028.html
I don't see any problem here whatsoever. Please go on cleaning up the platform and send patches for review. We'll try to get them merged soon.
Obviously the new DT bindings need to be reviewed properly and for the subsystems we also need to make sure the drivers are sane, but that is the same as for any other platform.
I have in the past tried to do some cleanup towards multiplatform support, see my patch below for anything that you might find useful. It's rather hackish and most of the changes I did there are probably obsoleted by a better change that you have already done, but there might be one or two things that you missed.
Arnd
----
Quoted 1 line
From
1b46ec69e0f94e1d49cbfa3816f7fe8854d0a304Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <[email protected]>
Date: Wed, 14 Oct 2015 15:52:53 +0200
Subject: [PATCH] experimental lpc32xx multiplatform cleanup
arch/arm/Kconfig +2 -0
@@ -498,6 +498,8 @@ config ARCH_LPC32XX select CPU_ARM926T select GENERIC_CLOCKEVENTS select HAVE_IDE + select MULTI_IRQ_HANDLER + select SPARSE_IRQ select USE_OF help Support for the NXP LPC32XX family of processors
arch/arm/mach-lpc32xx/Makefile +1 -1
@@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := timer.o irq.o common.o serial.o clock.o +obj-y := timer.o irq.o common.o serial.o clock.o gpio.o obj-y += pm.o suspend.o obj-y += phy3250.o
arch/arm/mach-lpc32xx/board.h renamed from arch/arm/mach-lpc32xx/include/mach/board.h +0 -0
arch/arm/mach-lpc32xx/clock.c +2 -2
@@ -94,8 +94,8 @@#include <linux/amba/clcd.h> #include <linux/clkdev.h> -#include <mach/hardware.h> -#include <mach/platform.h> +#include "hardware.h" +#include "platform.h" #include "clock.h" #include "common.h"
arch/arm/mach-lpc32xx/common.c +2 -2
@@ -28,8 +28,8 @@#include <asm/mach/map.h> #include <asm/system_info.h> -#include <mach/hardware.h> -#include <mach/platform.h> +#include "hardware.h" +#include "platform.h" #include "common.h" /*
arch/arm/mach-lpc32xx/common.h +1 -1
@@ -19,7 +19,7 @@#ifndef __LPC32XX_COMMON_H#define __LPC32XX_COMMON_H -#include <mach/board.h> +#include "board.h" #include <linux/platform_device.h> #include <linux/reboot.h>
arch/arm/mach-lpc32xx/gpio.c renamed from drivers/gpio/gpio-lpc32xx.c +3 -3
@@ -27,9 +27,9 @@#include <linux/module.h> #include <linux/platform_data/gpio-lpc32xx.h> -#include <mach/hardware.h> -#include <mach/platform.h> -#include <mach/irqs.h> +#include "hardware.h" +#include "platform.h" +#include "irqs.h" #define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
arch/arm/mach-lpc32xx/hardware.h renamed from arch/arm/mach-lpc32xx/include/mach/hardware.h +0 -0
arch/arm/mach-lpc32xx/include/mach/entry-macro.S deleted +0 -37
@@ -1,37 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/include/mach/entry-macro.S - * - * Author: Kevin Wells <[email protected]> - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mach/hardware.h> -#include <mach/platform.h> - -#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8 - - .macro get_irqnr_preamble, base, tmp - ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE) - .endm - -/* - * Return IRQ number in irqnr. Also return processor Z flag status in CPSR - * as set if an interrupt is pending. - */ - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS] - clz \irqnr, \irqstat - rsb \irqnr, \irqnr, #31 - teq \irqstat, #0 - .endm
arch/arm/mach-lpc32xx/include/mach/uncompress.h +2 -2
@@ -21,8 +21,8 @@#include <linux/io.h> -#include <mach/hardware.h> -#include <mach/platform.h> +#define LPC32XX_UART5_BASE 0x40090000 +/* * Uncompress output is hardcoded to standard UART 5
arch/arm/mach-lpc32xx/irq.c +20 -4
@@ -28,9 +28,11 @@#include <linux/irqdomain.h> #include <linux/module.h> -#include <mach/irqs.h> -#include <mach/hardware.h> -#include <mach/platform.h> +#include <asm/exception.h> + +#include "irqs.h" +#include "hardware.h" +#include "platform.h" #include "common.h" /*
@@ -81,7 +83,7 @@ struct lpc32xx_event_info {/* * Maps an IRQ number to and event mask and register */ -static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS ] = { +static const struct lpc32xx_event_info lpc32xx_events[LPC32XX_LEGACY_IRQS ] = { [IRQ_LPC32XX_GPI_08 ] = { .event_group = &lpc32xx_event_pin_regs, .mask =LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT ,
@@ -370,6 +372,19 @@ static struct irq_chip lpc32xx_irq_chip = { .irq_set_wake = lpc32xx_irq_wake }; +static void __exception_irq_entry lpc32xx_mic_handler(struct pt_regs *regs) +{ +unsigned long ints =__raw_readl (LPC32XX_INTC_STAT (LPC32XX_MIC_BASE )); + +while (ints) { +int irqno =fls (ints) -1 ; + + ints &= ~(1 << irqno); + +handle_IRQ (irqno, regs); + } +} +static void lpc32xx_sic1_handler (struct irq_desc *desc) {unsigned long ints =__raw_readl (LPC32XX_INTC_STAT (LPC32XX_SIC1_BASE ));
@@ -400,6 +415,7 @@ static int __init __lpc32xx_mic_of_init(struct device_node *node, struct device_node *parent) { lpc32xx_mic_np = node; +set_handle_irq (lpc32xx_mic_handler);return 0 ; }
arch/arm/mach-lpc32xx/irqs.h renamed from arch/arm/mach-lpc32xx/include/mach/irqs.h +1 -1
@@ -112,6 +112,6 @@#define IRQ_LPC32XX_GPI_06 LPC32XX_SIC2_IRQ(28)#define IRQ_LPC32XX_SYSCLK LPC32XX_SIC2_IRQ(31) -#define NR_IRQS 96 +#define LPC32XX_LEGACY_IRQS 96#endif
arch/arm/mach-lpc32xx/phy3250.c +5 -3
@@ -42,10 +42,11 @@#include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <mach/hardware.h> -#include <mach/platform.h> -#include <mach/board.h> +#include "hardware.h" +#include "platform.h" +#include "board.h" #include "common.h" +#include "irqs.h" /* * Mapped GPIOLIB GPIOs
@@ -258,6 +259,7 @@ static const char *const lpc32xx_dt_compat[] __initconst = {DT_MACHINE_START (LPC32XX_DT ,"LPC32XX SoC (Flattened Device Tree)" ) .atag_offset = 0x100, + .nr_irqs = LPC32XX_LEGACY_IRQS, .map_io = lpc32xx_map_io, .init_irq = lpc32xx_init_irq, .init_time = lpc32xx_timer_init,
arch/arm/mach-lpc32xx/platform.h renamed from arch/arm/mach-lpc32xx/include/mach/platform.h +0 -0
arch/arm/mach-lpc32xx/pm.c +2 -2
@@ -70,8 +70,8 @@#include <asm/cacheflush.h> -#include <mach/hardware.h> -#include <mach/platform.h> +#include "hardware.h" +#include "platform.h" #include "common.h" #include "clock.h"
arch/arm/mach-lpc32xx/serial.c +2 -2
@@ -25,8 +25,8 @@#include <linux/clk.h> #include <linux/io.h> -#include <mach/hardware.h> -#include <mach/platform.h> +#include "hardware.h" +#include "platform.h" #include "common.h" #define LPC32XX_SUART_FIFO_SIZE 64
arch/arm/mach-lpc32xx/suspend.S +2 -2
@@ -11,8 +11,8 @@ */ #include <linux/linkage.h> #include <asm/assembler.h> -#include <mach/platform.h> -#include <mach/hardware.h> +#include "platform.h" +#include "hardware.h" /* Using named register defines makes the code easier to follow */ #define WORK1_REG r0
arch/arm/mach-lpc32xx/timer.c +3 -2
@@ -27,9 +27,10 @@#include <asm/mach/time.h> -#include <mach/hardware.h> -#include <mach/platform.h> +#include "hardware.h" +#include "platform.h" #include "common.h" +#include "irqs.h" static int lpc32xx_clkevt_next_event (unsigned long delta,struct clock_event_device *dev)
drivers/gpio/Makefile +0 -1
@@ -50,7 +50,6 @@ obj-$(CONFIG_GPIO_INTEL_MID) += gpio-intel-mid.o obj-$(CONFIG_GPIO_LOONGSON) += gpio-loongson.o obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o -obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o obj-$(CONFIG_GPIO_MAX730X) += gpio-max730x.o obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
drivers/net/ethernet/nxp/lpc_eth.c +11 -3
@@ -44,9 +44,6 @@#include <linux/types.h> #include <linux/io.h> -#include <mach/board.h> -#include <mach/platform.h> -#include <mach/hardware.h> #define MODNAME "lpc-eth"#define DRV_VERSION "1.00"
@@ -1312,9 +1309,12 @@ static int lpc_eth_drv_probe(struct platform_device *pdev)struct phy_device *phydev;dma_addr_t dma_handle;int irq, ret; +#if 0 u32 tmp;/* Setup network interface for RMII or MII mode */ + FIXME:use pinctrl + tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK ;if (lpc_phy_interface_mode (&pdev->dev) ==PHY_INTERFACE_MODE_MII )
@@ -1322,6 +1322,7 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) else tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;__raw_writel (tmp,LPC32XX_CLKPWR_MACCLK_CTRL ); +#endif /* Get platform resources */ res =platform_get_resource (pdev,IORESOURCE_MEM ,0 );
@@ -1387,6 +1388,8 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) pldat->dma_buff_base_v =0 ;if (use_iram_for_net (&pldat->pdev->dev)) { +#if 0 +/* FIXME: get iram from DT */ dma_handle =LPC32XX_IRAM_BASE ;if (pldat->dma_buff_size <=lpc32xx_return_iram_size ()) pldat->dma_buff_base_v =
@@ -1394,6 +1397,7 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) else netdev_err(ndev, "IRAM not big enough for net buffers, using SDRAM instead.\n"); +#endif }if (pldat->dma_buff_base_v ==0 ) {
@@ -1483,11 +1487,13 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) err_out_unregister_netdev:unregister_netdev (ndev); err_out_dma_unmap: +#if 0 if (!use_iram_for_net (&pldat->pdev->dev) || pldat->dma_buff_size >lpc32xx_return_iram_size ())dma_free_coherent (&pldat->pdev->dev, pldat->dma_buff_size, pldat->dma_buff_base_v, pldat->dma_buff_base_p); +#endif err_out_free_irq:free_irq (ndev->irq, ndev); err_out_iounmap:
@@ -1509,11 +1515,13 @@ static int lpc_eth_drv_remove(struct platform_device *pdev)unregister_netdev (ndev); +#if 0 if (!use_iram_for_net (&pldat->pdev->dev) || pldat->dma_buff_size >lpc32xx_return_iram_size ())dma_free_coherent (&pldat->pdev->dev, pldat->dma_buff_size, pldat->dma_buff_base_v, pldat->dma_buff_base_p); +#endif free_irq (ndev->irq, ndev);iounmap (pldat->net_base);mdiobus_unregister (pldat->mii_bus);
drivers/tty/serial/lpc32xx_hs.c +5 -3
@@ -34,8 +34,6 @@#include <linux/irq.h> #include <linux/gpio.h> #include <linux/of.h> -#include <mach/platform.h> -#include <mach/hardware.h> /* * High Speed UART register offsets
@@ -447,9 +445,9 @@ static void serial_lpc32xx_break_ctl(struct uart_port *port,/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */ static void lpc32xx_loopback_set (resource_size_t mapbase,int state) { +#if 0 int bit;u32 tmp; -switch (mapbase) {case LPC32XX_HS_UART1_BASE : bit =0 ;
@@ -471,6 +469,7 @@ static void lpc32xx_loopback_set(resource_size_t mapbase, int state) else tmp &= ~(1 << bit);writel (tmp,LPC32XX_UARTCTL_CLOOP ); +#endif }/* port->lock is not held. */
@@ -700,7 +699,10 @@ static int serial_hs_lpc32xx_probe(struct platform_device *pdev) p->port.irq = ret; p->port.iotype =UPIO_MEM32 ; +#if 0 +/* FIXME: use clk_get_rate() */ p->port.uartclk =LPC32XX_MAIN_OSC_FREQ ; +#endif p->port.regshift =2 ; p->port.flags =UPF_BOOT_AUTOCONF |UPF_FIXED_PORT |UPF_IOREMAP ; p->port.dev = &pdev->dev;
drivers/usb/gadget/udc/lpc32xx_udc.c +11 -5
@@ -52,13 +52,9 @@#include <linux/usb/isp1301.h> #include <asm/byteorder.h> -#include <mach/hardware.h> #include <linux/io.h> #include <asm/irq.h> -#include <mach/platform.h> -#include <mach/irqs.h> -#include <mach/board.h> #ifdef CONFIG_USB_GADGET_DEBUG_FILES #include <linux/debugfs.h> #include <linux/seq_file.h>
@@ -652,8 +648,11 @@ static void isp1301_udc_configure(struct lpc32xx_udc *udc)i2c_smbus_write_byte_data (udc->isp1301_i2c_client,ISP1301_I2C_INTERRUPT_RISING ,INT_VBUS_VLD ); +#if 0 +/* FIXME: use clock interface */ /* Enable usb_need_clk clock after transceiver is initialized */ writel ((readl (USB_CTRL ) |USB_DEV_NEED_CLK_EN ),USB_CTRL ); +#endif dev_info (udc->dev,"ISP1301 Vendor ID : 0x%04x\n" ,i2c_smbus_read_word_data (udc->isp1301_i2c_client,0x00 ));
@@ -997,9 +996,11 @@ static void udc_clk_set(struct lpc32xx_udc *udc, int enable)/* 48MHz PLL up */ clk_enable (udc->usb_pll_clk); +#if 0 /* Enable the USB device clock */ writel (readl (USB_CTRL ) |USB_DEV_NEED_CLK_EN ,USB_CTRL ); +#endif clk_enable (udc->usb_otg_clk); }else {
@@ -1013,10 +1014,11 @@ static void udc_clk_set(struct lpc32xx_udc *udc, int enable)/* 48MHz PLL dpwn */ clk_disable (udc->usb_pll_clk); +#if 0 /* Disable the USB device clock */ writel (readl (USB_CTRL ) & ~USB_DEV_NEED_CLK_EN ,USB_CTRL ); - +#endif clk_disable (udc->usb_otg_clk); } }
@@ -3138,8 +3140,10 @@ static int lpc32xx_udc_probe(struct platform_device *pdev) goto io_map_fail; } +#if 0 /* Enable AHB slave USB clock, needed for further USB clock control */ writel (USB_SLAVE_HCLK_EN | (1 <<19 ),USB_CTRL ); +#endif /* Get required clocks */ udc->usb_pll_clk =clk_get (&pdev->dev,"ck_pll5" );
@@ -3174,7 +3178,9 @@ static int lpc32xx_udc_probe(struct platform_device *pdev) goto pll_set_fail; } +#if 0 writel (readl (USB_CTRL ) |USB_DEV_NEED_CLK_EN ,USB_CTRL ); +#endif /* Enable USB device clock */ retval =clk_enable (udc->usb_slv_clk);
drivers/usb/host/ohci-nxp.c +13 -5
@@ -33,13 +33,10 @@#include "ohci.h" -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/io.h> -#include <mach/platform.h> -#include <mach/irqs.h> - +#if 0 #define USB_CONFIG_BASE 0x31020000#define PWRMAN_BASE 0x40004000
@@ -52,6 +49,7 @@#define PAD_CONTROL_LAST_DRIVEN (1 << 19)#define USB_OTG_STAT_CONTROL IO_ADDRESS(USB_CONFIG_BASE + 0x110) +#endif /* USB_OTG_STAT_CONTROL bit defines */ #define TRANSPARENT_I2C_EN (1 << 7)
@@ -117,8 +115,10 @@ static void isp1301_configure_lpc32xx(void)i2c_smbus_write_byte_data (isp1301_i2c_client,ISP1301_I2C_INTERRUPT_RISING |ISP1301_I2C_REG_CLEAR_ADDR , ~0 ); +#if 0 /* Enable usb_need_clk clock after transceiver is initialized */ __raw_writel (__raw_readl (USB_CTRL ) |USB_HOST_NEED_CLK_EN ,USB_CTRL ); +#endif printk (KERN_INFO "ISP1301 Vendor ID : 0x%04x\n" ,i2c_smbus_read_word_data (isp1301_i2c_client,0x00 ));
@@ -148,17 +148,21 @@ static inline void isp1301_vbus_off(void)static void ohci_nxp_start_hc (void ) { +#if 0 unsigned long tmp =__raw_readl (USB_OTG_STAT_CONTROL ) |HOST_EN ;__raw_writel (tmp,USB_OTG_STAT_CONTROL ); +#endif isp1301_vbus_on (); }static void ohci_nxp_stop_hc (void ) { -unsigned long tmp;isp1301_vbus_off (); +#if 0 +unsigned long tmp; tmp =__raw_readl (USB_OTG_STAT_CONTROL ) & ~HOST_EN ;__raw_writel (tmp,USB_OTG_STAT_CONTROL ); +#endif }static int ohci_hcd_nxp_probe (struct platform_device *pdev)
@@ -192,8 +196,10 @@ static int ohci_hcd_nxp_probe(struct platform_device *pdev) goto fail_disable; } +#if 0 /* Enable AHB slave USB clock, needed for further USB clock control */ __raw_writel (USB_SLAVE_HCLK_EN |PAD_CONTROL_LAST_DRIVEN ,USB_CTRL ); +#endif /* Enable USB PLL */ usb_pll_clk =devm_clk_get (&pdev->dev,"ck_pll5" );
@@ -237,7 +243,9 @@ static int ohci_hcd_nxp_probe(struct platform_device *pdev) goto fail_otg; } +#if 0 __raw_writel (__raw_readl (USB_CTRL ) |USB_HOST_NEED_CLK_EN ,USB_CTRL ); +#endif ret =clk_prepare_enable (usb_otg_clk);if (ret <0 ) {
drivers/watchdog/pnx4008_wdt.c +0 -1
@@ -31,7 +31,6 @@#include <linux/slab.h> #include <linux/err.h> #include <linux/of.h> -#include <mach/hardware.h> /* WatchDog Timer - Chapter 23 Page 207 */