Skip to contentSkip to conversation

eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

PATCH New Yuanzheng Li 4 participants 7 messages Nov 25, 2015 – Mar 22, 2016 Network drivers

lore
Share & tools
lore

Yuanzheng Li

author
#0 lore raw

PATCH 1/1 eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

The TBI_ANA register is configurated with the wrong value 0x4001, refer to QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual. It set the reserved areas, bit 1 and bit 11 to bit 15 in big endian, which should be cleared. But the normal functions of the auto-negotiation, e.g. Pause and Full Duplex, do not be set.

There is no problem in the p2041rdb board, because the ppc is connected directly with the phy chip which support auto-negotiation by default in SGMII interface. But the link problem will occur when it is connected with a switch chip like BCM5389, the switch chip disable auto-negotiation by default, and the ppc also disable auto-negotiation, then there is no link between them.

So use the vlue TBIANA_SETTINGS to enable the ppc's auto-negotiation.

Signed-off-by Yuanzheng Li <[email protected]>
Cc York Sun <[email protected]>
---
 drivers/net/fm/eth.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/net/fm/eth.c +1 -1
index eb8e936..78c0988 100644
@@ -81,7 +81,7 @@ qsgmii_loop:
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON,
 			TBICON_CLK_SELECT);
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA,
-			TBIANA_SGMII_ACK);
+			TBIANA_SETTINGS);
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
 			TBI_CR, TBICR_SETTINGS);
 #endif
Signature · 1 line
1.7.8
#1 lore raw

PATCH 1/1 eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

+ Experts

Quoted 27 lines · Yuanzheng Li

The TBI_ANA register is configurated with the wrong value 0x4001, refer to QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual. It set the reserved areas, bit 1 and bit 11 to bit 15 in big endian, which should be cleared. But the normal functions of the auto-negotiation, e.g. Pause and Full Duplex, do not be set.

There is no problem in the p2041rdb board, because the ppc is connected directly with the phy chip which support auto-negotiation by default in SGMII interface. But the link problem will occur when it is connected with a switch chip like BCM5389, the switch chip disable auto-negotiation by default, and the ppc also disable auto-negotiation, then there is no link between them.

So use the vlue TBIANA_SETTINGS to enable the ppc's auto-negotiation.

Signed-off-by Yuanzheng Li <[email protected]>
Cc York Sun <[email protected]>
---
 drivers/net/fm/eth.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/net/fm/eth.c +0 -0
index eb8e936..78c0988 100644

drivers/net/fm/eth.c qsgmii_loop: · line 87

Quoted 8 lines
drivers/net/fm/eth.c +1 -1
@@ -81,7 +81,7 @@ qsgmii_loop:
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON,
 			TBICON_CLK_SELECT);
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA,
-			TBIANA_SGMII_ACK);
+			TBIANA_SETTINGS);
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
 			TBI_CR, TBICR_SETTINGS);
 #endif

Yuanzheng,

After your change, TBIANA_SGMII_ACK is not used and should be removed.

Shaohui and Codrin,

Please comment.

York

#2 lore raw

PATCH 1/1 eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

Quoted 8 lines

-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Thursday, November 26, 2015 1:03 AM
To: Xie Shaohui-B21989; Ciubotariu Codrin Constantin-B43658
Cc: Yuanzheng Li; u-boot at lists.denx.de; Liu Dave-R63238
Subject: Re: [PATCH] eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

Quoted 9 lines

+ Experts

Quoted 2 lines · Yuanzheng Li

The TBI_ANA register is configurated with the wrong value 0x4001, refer to QorIQ Data Path Acceleration Architecture (DPAA) Reference

Manual.

Quoted 3 lines

It set the reserved areas, bit 1 and bit 11 to bit 15 in big endian, which should be cleared. But the normal functions of the auto-negotiation, e.g. Pause and Full Duplex, do not be set.

[S.H] The value 0x4001 is so special, as mentioned, it does not match the DPAA RM, So I dig some docs and found AN3869, in which the 0x4001 is the desired one to write to TBI_ANA for SGMII.

Quoted 7 lines
Quoted 7 lines

There is no problem in the p2041rdb board, because the ppc is connected directly with the phy chip which support auto-negotiation by default in SGMII interface. But the link problem will occur when it is connected with a switch chip like BCM5389, the switch chip disable auto-negotiation by default, and the ppc also disable auto-negotiation, then there is no link between them.

[S.H] This seems a phyless connection. If BCM5389 disables AN, then PPC should Also disable AN by setting TBI_CR.

Quoted 2 lines
Quoted 2 lines

So use the vlue TBIANA_SETTINGS to enable the ppc's auto-negotiation.

[S.H] The TBI_ANA is " AN Advertisement Register ", it does not enable/disable AN. A proper way should be to distinguish the phy and phyless connections and configure The TBI registers accordingly.

Thanks,
Shaohui

Quoted 31 lines
Quoted 13 lines
Signed-off-by Yuanzheng Li <[email protected]>
Cc York Sun <[email protected]>
---
 drivers/net/fm/eth.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/net/fm/eth.c index renamed from drivers/net/fm/eth.c +0 -0

eb8e936..78c0988 100644

drivers/net/fm/eth.c qsgmii_loop: · line 87

Quoted 8 lines
drivers/net/fm/eth.c +1 -1
@@ -81,7 +81,7 @@ qsgmii_loop:
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON,
 			TBICON_CLK_SELECT);
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA,
-			TBIANA_SGMII_ACK);
+			TBIANA_SETTINGS);
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
 			TBI_CR, TBICR_SETTINGS);
 #endif

Yuanzheng,

After your change, TBIANA_SGMII_ACK is not used and should be removed.

Shaohui and Codrin,

Please comment.

York

author
#3 lore raw

PATCH 1/1 eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

The value TBIANA_SETTINGS is also work on the p2041rdb board, so it can work on the both phy and phyless connections.

Quoted 72 lines · Shaohui Xie
Quoted 8 lines

-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Thursday, November 26, 2015 1:03 AM
To: Xie Shaohui-B21989; Ciubotariu Codrin Constantin-B43658
Cc: Yuanzheng Li; u-boot at lists.denx.de; Liu Dave-R63238
Subject: Re: [PATCH] eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

Quoted 9 lines

+ Experts

Quoted 2 lines · Yuanzheng Li

The TBI_ANA register is configurated with the wrong value 0x4001, refer to QorIQ Data Path Acceleration Architecture (DPAA) Reference

Manual.

Quoted 3 lines

It set the reserved areas, bit 1 and bit 11 to bit 15 in big endian, which should be cleared. But the normal functions of the auto-negotiation, e.g. Pause and Full Duplex, do not be set.

[S.H] The value 0x4001 is so special, as mentioned, it does not match the DPAA RM, So I dig some docs and found AN3869, in which the 0x4001 is the desired one to write to TBI_ANA for SGMII.

Quoted 7 lines
Quoted 7 lines

There is no problem in the p2041rdb board, because the ppc is connected directly with the phy chip which support auto-negotiation by default in SGMII interface. But the link problem will occur when it is connected with a switch chip like BCM5389, the switch chip disable auto-negotiation by default, and the ppc also disable auto-negotiation, then there is no link between them.

[S.H] This seems a phyless connection. If BCM5389 disables AN, then PPC should Also disable AN by setting TBI_CR.

Quoted 2 lines
Quoted 2 lines

So use the vlue TBIANA_SETTINGS to enable the ppc's auto-negotiation.

[S.H] The TBI_ANA is " AN Advertisement Register ", it does not enable/disable AN. A proper way should be to distinguish the phy and phyless connections and configure The TBI registers accordingly.

Thanks,
Shaohui

Quoted 31 lines
Quoted 13 lines
Signed-off-by Yuanzheng Li <[email protected]>
Cc York Sun <[email protected]>
---
 drivers/net/fm/eth.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/net/fm/eth.c index renamed from drivers/net/fm/eth.c +0 -0

eb8e936..78c0988 100644

drivers/net/fm/eth.c qsgmii_loop: · line 87

Quoted 8 lines
drivers/net/fm/eth.c +1 -1
@@ -81,7 +81,7 @@ qsgmii_loop:
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON,
 			TBICON_CLK_SELECT);
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA,
-			TBIANA_SGMII_ACK);
+			TBIANA_SETTINGS);
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
 			TBI_CR, TBICR_SETTINGS);
 #endif

Yuanzheng,

After your change, TBIANA_SGMII_ACK is not used and should be removed.

Shaohui and Codrin,

Please comment.

York

#4 lore raw

PATCH 1/1 eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

Shaohui,

Please comment/confirm.

York

Quoted 82 lines · ???

The value TBIANA_SETTINGS is also work on the p2041rdb board, so it can work on the both phy and phyless connections.

Quoted 71 lines · Shaohui Xie
Quoted 8 lines

-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Thursday, November 26, 2015 1:03 AM
To: Xie Shaohui-B21989; Ciubotariu Codrin Constantin-B43658
Cc: Yuanzheng Li; u-boot at lists.denx.de; Liu Dave-R63238
Subject: Re: [PATCH] eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

Quoted 9 lines

+ Experts

Quoted 2 lines · Yuanzheng Li

The TBI_ANA register is configurated with the wrong value 0x4001, refer to QorIQ Data Path Acceleration Architecture (DPAA) Reference

Manual.

Quoted 3 lines

It set the reserved areas, bit 1 and bit 11 to bit 15 in big endian, which should be cleared. But the normal functions of the auto-negotiation, e.g. Pause and Full Duplex, do not be set.

[S.H] The value 0x4001 is so special, as mentioned, it does not match the DPAA RM, So I dig some docs and found AN3869, in which the 0x4001 is the desired one to write to TBI_ANA for SGMII.

Quoted 7 lines
Quoted 7 lines

There is no problem in the p2041rdb board, because the ppc is connected directly with the phy chip which support auto-negotiation by default in SGMII interface. But the link problem will occur when it is connected with a switch chip like BCM5389, the switch chip disable auto-negotiation by default, and the ppc also disable auto-negotiation, then there is no link between them.

[S.H] This seems a phyless connection. If BCM5389 disables AN, then PPC should Also disable AN by setting TBI_CR.

Quoted 2 lines
Quoted 2 lines

So use the vlue TBIANA_SETTINGS to enable the ppc's auto-negotiation.

[S.H] The TBI_ANA is " AN Advertisement Register ", it does not enable/disable AN. A proper way should be to distinguish the phy and phyless connections and configure The TBI registers accordingly.

Thanks,
Shaohui

Quoted 31 lines
Quoted 13 lines
Signed-off-by Yuanzheng Li <[email protected]>
Cc York Sun <[email protected]>
---
 drivers/net/fm/eth.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/net/fm/eth.c index renamed from drivers/net/fm/eth.c +0 -0

eb8e936..78c0988 100644

drivers/net/fm/eth.c qsgmii_loop: · line 87

Quoted 8 lines
drivers/net/fm/eth.c +1 -1
@@ -81,7 +81,7 @@ qsgmii_loop:
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON,
 			TBICON_CLK_SELECT);
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA,
-			TBIANA_SGMII_ACK);
+			TBIANA_SETTINGS);
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
 			TBI_CR, TBICR_SETTINGS);
 #endif

Yuanzheng,

After your change, TBIANA_SGMII_ACK is not used and should be removed.

Shaohui and Codrin,

Please comment.

York

#5 lore raw

PATCH 1/1 eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

Hi,

As mentioned, the value 0x4001 is the desired one in AN3869 for SGMII setting, quoted as below:
" Program TBI ANA = 0x4001 (SGMII) or 0x01A0 (1000BASE-X). "

I think the AN3869 should be followed, change SGMII setting just because it worked on P2041rdb is not a good reason.

To distinguish SGMII from other connections should be the way to program TBI ANA, This is also follow the AN3869.

Best Regards,
Shaohui Xie

Quoted 104 lines

-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Monday, December 14, 2015 11:55 AM
To: ???; Xie Shaohui-B21989
Cc: Ciubotariu Codrin Constantin-B43658; u-boot at lists.denx.de; Liu Dave- R63238
Subject: Re: [PATCH] eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

Shaohui,

Please comment/confirm.

York

Quoted 5 lines · ???

The value TBIANA_SETTINGS is also work on the p2041rdb board, so it can work on the both phy and phyless connections.

Quoted 30 lines
Quoted 29 lines · Shaohui Xie
Quoted 8 lines

-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Thursday, November 26, 2015 1:03 AM
To: Xie Shaohui-B21989; Ciubotariu Codrin Constantin-B43658
Cc: Yuanzheng Li; u-boot at lists.denx.de; Liu Dave-R63238
Subject: Re: [PATCH] eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

Quoted 10 lines

+ Experts

Quoted 3 lines · Yuanzheng Li

The TBI_ANA register is configurated with the wrong value 0x4001, refer to QorIQ Data Path Acceleration Architecture (DPAA) Reference

Manual.

Quoted 3 lines

It set the reserved areas, bit 1 and bit 11 to bit 15 in big endian, which should be cleared. But the normal functions of the auto-negotiation, e.g. Pause and Full Duplex, do not be set.

[S.H] The value 0x4001 is so special, as mentioned, it does not match the DPAA RM, So I dig some docs and found AN3869, in which the 0x4001 is the desired one to write to TBI_ANA for SGMII.

Quoted 7 lines
Quoted 7 lines

There is no problem in the p2041rdb board, because the ppc is connected directly with the phy chip which support auto-negotiation by default in SGMII interface. But the link problem will occur when it is connected with a switch chip like BCM5389, the switch chip disable auto-negotiation by default, and the ppc also disable auto-negotiation, then there is no link

between them.

Quoted 5 lines
Quoted 5 lines

[S.H] This seems a phyless connection. If BCM5389 disables AN, then PPC should Also disable AN by setting TBI_CR.

Quoted 2 lines
Quoted 2 lines

So use the vlue TBIANA_SETTINGS to enable the ppc's auto-

negotiation.

Quoted 1 line
Quoted 1 line

[S.H] The TBI_ANA is " AN Advertisement Register ", it does not

enable/disable AN.

Quoted 13 lines
Quoted 13 lines

A proper way should be to distinguish the phy and phyless connections and configure The TBI registers accordingly.

Thanks,
Shaohui

Quoted 7 lines
Quoted 7 lines
Signed-off-by Yuanzheng Li <[email protected]>
Cc York Sun <[email protected]>
---
 drivers/net/fm/eth.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
Quoted 6 lines
Quoted 6 lines
Quoted 6 lines

drivers/net/fm/eth.c qsgmii_loop: · line 81

Quoted 6 lines
drivers/net/fm/eth.c index renamed from drivers/net/fm/eth.c +0 -0

eb8e936..78c0988 100644

drivers/net/fm/eth.c +0 -0
@@ -81,7 +81,7 @@ qsgmii_loop:
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,

TBI_TBICON,

Quoted 2 lines
Quoted 2 lines
Quoted 2 lines

drivers/net/fm/eth.c qsgmii_loop: · line 85

Quoted 2 lines
drivers/net/fm/eth.c +0 -0
 			TBICON_CLK_SELECT);
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,

TBI_ANA,

Quoted 21 lines
Quoted 16 lines
Quoted 16 lines

drivers/net/fm/eth.c qsgmii_loop: · line 87

Quoted 6 lines
drivers/net/fm/eth.c +1 -1
-			TBIANA_SGMII_ACK);
+			TBIANA_SETTINGS);
 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
 			TBI_CR, TBICR_SETTINGS);
 #endif

Yuanzheng,

After your change, TBIANA_SGMII_ACK is not used and should be removed.

Shaohui and Codrin,

Please comment.

York

#6 lore raw

PATCH 1/1 eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

Quoted 6 lines · On 12/13/2015 11:07 PM, Xie Shaohui-B21989 wrote:

Hi,

As mentioned, the value 0x4001 is the desired one in AN3869 for SGMII setting, quoted as below:
" Program TBI ANA = 0x4001 (SGMII) or 0x01A0 (1000BASE-X). "

Quoted 10 lines

I think the AN3869 should be followed, change SGMII setting just because it worked on P2041rdb is not a good reason.

To distinguish SGMII from other connections should be the way to program TBI ANA, This is also follow the AN3869.

Best Regards,
Shaohui Xie

Looks like this patch is dead. I will mark is NA.

York