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arm: ls1021a: merge SoC specific code in a separate file

PATCH New Yuan Yao 2 participants 7 messages Nov 26, 2015 – Nov 30, 2015 Arm (32-bit)

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Yuan Yao

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#0 lore raw

PATCH 1/5 arm: ls1021a: merge SoC specific code in a separate file

Create a soc.c file to put the code for soc special settings.

Signed-off-by Yuan Yao <[email protected]>
---
 arch/arm/cpu/armv7/ls102xa/Makefile             |  1 +
 arch/arm/cpu/armv7/ls102xa/soc.c                | 66 +++++++++++++++++++++++++
 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +++++
 board/freescale/ls1021aqds/ls1021aqds.c         | 49 +-----------------
 board/freescale/ls1021atwr/ls1021atwr.c         | 42 +---------------
 5 files changed, 83 insertions(+), 87 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/ls102xa/soc.c
 create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
arch/arm/cpu/armv7/ls102xa/Makefile +1 -0
index 2311468..0228300 100644
@@ -8,6 +8,7 @@ obj-y	+= cpu.o
 obj-y	+= clock.o
 obj-y	+= timer.o
 obj-y	+= fsl_epu.o
+obj-y	+= soc.o
 
 obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
arch/arm/cpu/armv7/ls102xa/soc.c new file +66 -0

66 lines not on this page · raw message

arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h new file +12 -0
new file mode 100644
index 0000000..f10cb91
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_LS102XA_SOC_H
+#define __FSL_LS102XA_SOC_H
+
+unsigned int get_soc_major_rev(void);
+int arch_soc_init(void);
+#endif /* __FSL_LS102XA_SOC_H */
board/freescale/ls1021aqds/ls1021aqds.c +2 -47

73 lines not on this page · raw message

board/freescale/ls1021atwr/ls1021atwr.c +2 -40

66 lines not on this page · raw message

Signature · 1 line
2.1.0.27.g96db324
author
#1 lore raw

PATCH 2/5 arm: ls102xa: enable all the snoop signal for masters.

Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.

Signed-off-by Yuan Yao <[email protected]>
---
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 8 ++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 6 ++++++
 2 files changed, 14 insertions(+)
arch/arm/cpu/armv7/ls102xa/soc.c +8 -0
index 0fdd6d4..6036473 100644
@@ -62,5 +62,13 @@ int arch_soc_init(void)
 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 	}
 
+	/* Enable all the snoop signal for various masters */
+	out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
+				SCFG_SNPCNFGCR_DCU_RD_WR |
+				SCFG_SNPCNFGCR_SATA_RD_WR |
+				SCFG_SNPCNFGCR_USB3_RD_WR |
+				SCFG_SNPCNFGCR_DBG_RD_WR |
+				SCFG_SNPCNFGCR_EDMA_SNP);
+
 	return 0;
 }
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +6 -0
index 1bcdf04..0527576 100644
@@ -150,6 +150,12 @@ struct ccsr_gur {
 #define SCFG_ETSECCMCR_GE1_CLK125	0x08000000
 #define SCFG_PIXCLKCR_PXCKEN		0x80000000
 #define SCFG_QSPI_CLKSEL		0xc0100000
+#define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
+#define SCFG_SNPCNFGCR_DCU_RD_WR	0x03000000
+#define SCFG_SNPCNFGCR_SATA_RD_WR	0x00c00000
+#define SCFG_SNPCNFGCR_USB3_RD_WR	0x00300000
+#define SCFG_SNPCNFGCR_DBG_RD_WR	0x000c0000
+#define SCFG_SNPCNFGCR_EDMA_SNP		0x00020000
 #define SCFG_ENDIANCR_LE		0x80000000
 
 /* Supplemental Configuration Unit */
Signature · 1 line
2.1.0.27.g96db324
author
#2 lore raw

PATCH 3/5 ls102xa: Enable snoop and DVM message requests.

In reply to Yuan Yao
Signed-off-by Yuan Yao <[email protected]>
---
 arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/ls102xa/soc.c +7 -1
index 6036473..97ba6d5 100644
@@ -40,8 +40,14 @@ int arch_soc_init(void)
 
 	/*
 	 * Enable snoop requests and DVM message requests for
-	 * Slave insterface S4 (A7 core cluster)
+	 * All the slave insterfaces.
 	 */
+	out_le32(&cci->slave[0].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+	out_le32(&cci->slave[1].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+	out_le32(&cci->slave[2].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 	out_le32(&cci->slave[4].snoop_ctrl,
 		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
Signature · 1 line
2.1.0.27.g96db324
author
#3 lore raw

PATCH v2 4/5 armv7/fsl-ls102xa: Workaround for DDR erratum A008514

In reply to Yuan Yao

This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the memory controller performance.

The value: 63b2_0042h comes from the hardware team.

Signed-off-by Yuan Yao <[email protected]>

---
Changed in v2:
squash both of the two patches into one patch to set EDDRTQCF.

---
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 10 ++++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/ls102xa/soc.c +10 -0
index 97ba6d5..79ae883 100644
@@ -76,5 +76,15 @@ int arch_soc_init(void)
 				SCFG_SNPCNFGCR_DBG_RD_WR |
 				SCFG_SNPCNFGCR_EDMA_SNP);
 
+	/*
+	 * Memory controller require a register write before being enabled.
+	 * Affects: DDR
+	 * Register: EDDRTQCFG
+	 * Description: Memory controller performance is not optimal with
+	 *		default internal target queue register values.
+	 * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
+	 */
+	out_be32(&scfg->eddrtqcfg, 0x63b20042);
+
 	return 0;
 }
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +1 -1
index 0527576..c584c9f 100644
@@ -228,7 +228,7 @@ struct ccsr_scfg {
 	u32 scfgrevcr;
 	u32 coresrencr;
 	u32 pex2pmrdsr;
-	u32 ddrc1cr;
+	u32 eddrtqcfg;
 	u32 ddrc2cr;
 	u32 ddrc3cr;
 	u32 ddrc4cr;
Signature · 1 line
2.1.0.27.g96db324
author
#4 lore raw

PATCH 5/5 move the erratum_a008336_a008514 from general ddr file to soc file

In reply to Yuan Yao

Both of the erratum:A008336 and A008514 are not apply to all the soc like:LS1021A, LS1043A.
So it seems better to move those erratum codes form the general ddr file to the private soc file.

Signed-off-by Yuan Yao <[email protected]>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37 +++++++++++++++++++++++++++++++++
 drivers/ddr/fsl/fsl_ddr_gen4.c          | 34 ------------------------------
 2 files changed, 37 insertions(+), 34 deletions(-)
arch/arm/cpu/armv8/fsl-layerscape/soc.c +37 -0
index 8896b70..738b113 100644
@@ -14,6 +14,41 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+/*
+ * This erratum requires setting a value to eddrtqcr1 to
+ * optimal the DDR performance.
+ */
+static void erratum_a008336(void)
+{
+	u32 *eddrtqcr1;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
+#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
+	out_le32(eddrtqcr1, 0x63b30002);
+#endif
+#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
+	out_le32(eddrtqcr1, 0x63b30002);
+#endif
+#endif
+}
+
+/*
+ * This erratum requires a register write before being Memory
+ * controller 3 being enabled.
+ */
+static void erratum_a008514(void)
+{
+	u32 *eddrtqcr1;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
+#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
+	out_le32(eddrtqcr1, 0x63b20002);
+#endif
+#endif
+}
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 #define PLATFORM_CYCLE_ENV_VAR	"a009635_interval_val"
 

@@ -118,6 +153,8 @@ void fsl_lsch3_early_init_f(void)
 	erratum_rcw_src();
 	init_early_memctl_regs();	/* tighten IFC timing */
 	erratum_a009203();
+	erratum_a008514();
+	erratum_a008336();
 }
 
 #elif defined(CONFIG_LS1043A)
drivers/ddr/fsl/fsl_ddr_gen4.c +0 -34
index 50f4671..d7cbf34 100644
@@ -48,10 +48,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	u32 temp_sdram_cfg;
 	u32 total_gb_size_per_controller;
 	int timeout;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-	u32 *eddrtqcr1;
-#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 	u32 temp32, mr6;
 	u32 vref_seq1[3] = {0x80, 0x96, 0x16};	/* for range 1 */

@@ -69,36 +65,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	switch (ctrl_num) {
 	case 0:
 		ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
-#endif
 		break;
 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
 	case 1:
 		ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
-#endif
 		break;
 #endif
 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
 	case 2:
 		ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
-#endif
 		break;
 #endif
 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
 	case 3:
 		ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800;
-#endif
 		break;
 #endif
 	default:

@@ -109,20 +89,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	if (step == 2)
 		goto step2;
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
-	/* A008336 only applies to general DDR controllers */
-	if ((ctrl_num == 0) || (ctrl_num == 1))
-#endif
-		ddr_out32(eddrtqcr1, 0x63b30002);
-#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
-	/* A008514 only applies to DP-DDR controler */
-	if (ctrl_num == 2)
-#endif
-		ddr_out32(eddrtqcr1, 0x63b20002);
-#endif
 	if (regs->ddr_eor)
 		ddr_out32(&ddr->eor, regs->ddr_eor);
Signature · 1 line
2.1.0.27.g96db324
#5 lore raw

PATCH 5/5 move the erratum_a008336_a008514 from general ddr file to soc file

Hi Yuan

Quoted 2 lines · Yuan Yao

Both of the erratum:A008336 and A008514 are not apply to all the soc like:LS1021A, LS1043A.

nitpick : perhaps you could reword the commit message to make
it a bit more clear. A suggestion :

"As the errata A008336 and A008514 do not apply to all LS series
SoCs (such as LS1021A, LS1043A) we move them to an soc specific file"

arch/arm/cpu/armv8/fsl-layerscape/soc.c

Quoted 13 lines

So it seems better to move those erratum codes form the general ddr file to the private soc file.

Signed-off-by Yuan Yao <[email protected]>
---
  arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37 +++++++++++++++++++++++++++++++++
  drivers/ddr/fsl/fsl_ddr_gen4.c          | 34 ------------------------------
  2 files changed, 37 insertions(+), 34 deletions(-)
arch/arm/cpu/armv8/fsl-layerscape/soc.c +0 -0
index 8896b70..738b113 100644

Not exactly related to this patch but at this point we have :

armv7/ls102xa
armv8/fsl-layerscape

I think ls102x is also considered a layerscape SoC
and this is potentially confusing. Perhaps in another patch we can come up with better naming.

Regards
Sinan Akman

Quoted 125 lines
arch/arm/cpu/armv8/fsl-layerscape/soc.c +37 -0
@@ -14,6 +14,41 @@
  DECLARE_GLOBAL_DATA_PTR;
 
  #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+/*
+ * This erratum requires setting a value to eddrtqcr1 to
+ * optimal the DDR performance.
+ */
+static void erratum_a008336(void)
+{
+	u32 *eddrtqcr1;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
+#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
+	out_le32(eddrtqcr1, 0x63b30002);
+#endif
+#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
+	out_le32(eddrtqcr1, 0x63b30002);
+#endif
+#endif
+}
+
+/*
+ * This erratum requires a register write before being Memory
+ * controller 3 being enabled.
+ */
+static void erratum_a008514(void)
+{
+	u32 *eddrtqcr1;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
+#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
+	out_le32(eddrtqcr1, 0x63b20002);
+#endif
+#endif
+}
  #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
  #define PLATFORM_CYCLE_ENV_VAR	"a009635_interval_val"
 

@@ -118,6 +153,8 @@ void fsl_lsch3_early_init_f(void)
  	erratum_rcw_src();
  	init_early_memctl_regs();	/* tighten IFC timing */
  	erratum_a009203();
+	erratum_a008514();
+	erratum_a008336();
  }
 
  #elif defined(CONFIG_LS1043A)
drivers/ddr/fsl/fsl_ddr_gen4.c +0 -34
index 50f4671..d7cbf34 100644
@@ -48,10 +48,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  	u32 temp_sdram_cfg;
  	u32 total_gb_size_per_controller;
  	int timeout;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-	u32 *eddrtqcr1;
-#endif
  #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  	u32 temp32, mr6;
  	u32 vref_seq1[3] = {0x80, 0x96, 0x16};	/* for range 1 */

@@ -69,36 +65,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  	switch (ctrl_num) {
  	case 0:
  		ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
-#endif
  		break;
  #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  	case 1:
  		ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
-#endif
  		break;
  #endif
  #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  	case 2:
  		ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
-#endif
  		break;
  #endif
  #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  	case 3:
  		ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800;
-#endif
  		break;
  #endif
  	default:

@@ -109,20 +89,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  	if (step == 2)
  		goto step2;
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
-	/* A008336 only applies to general DDR controllers */
-	if ((ctrl_num == 0) || (ctrl_num == 1))
-#endif
-		ddr_out32(eddrtqcr1, 0x63b30002);
-#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
-	/* A008514 only applies to DP-DDR controler */
-	if (ctrl_num == 2)
-#endif
-		ddr_out32(eddrtqcr1, 0x63b20002);
-#endif
  	if (regs->ddr_eor)
  		ddr_out32(&ddr->eor, regs->ddr_eor);
author
#6 lore raw

PATCH 5/5 move the erratum_a008336_a008514 from general ddr file to soc file

Hi Sinan Akman,

Thanks for your review, I will update my commit message in the next version.

Best Regards,

Yuan Yao

On 27/11/2015 12:04 AM, Sinan Akman wrote:
Hi Yuan

Quoted 2 lines · Yuan Yao

Both of the erratum:A008336 and A008514 are not apply to all the soc like:LS1021A, LS1043A.

nitpick : perhaps you could reword the commit message to make it a bit more clear. A suggestion :

"As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file"

arch/arm/cpu/armv8/fsl-layerscape/soc.c

Quoted 14 lines

So it seems better to move those erratum codes form the general ddr file to the private soc file.

Signed-off-by Yuan Yao <[email protected]>
---
  arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37 +++++++++++++++++++++++++++++++++
  drivers/ddr/fsl/fsl_ddr_gen4.c          | 34 ------------------------------
  2 files changed, 37 insertions(+), 34 deletions(-)
arch/arm/cpu/armv8/fsl-layerscape/soc.c +0 -0
index 8896b70..738b113 100644

Not exactly related to this patch but at this point we have :

armv7/ls102xa
armv8/fsl-layerscape

I think ls102x is also considered a layerscape SoC and this is potentially confusing. Perhaps in another patch we can come up with better naming.

Regards
Sinan Akman

Quoted 125 lines
arch/arm/cpu/armv8/fsl-layerscape/soc.c +37 -0
@@ -14,6 +14,41 @@
  DECLARE_GLOBAL_DATA_PTR;
 
  #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+/*
+ * This erratum requires setting a value to eddrtqcr1 to
+ * optimal the DDR performance.
+ */
+static void erratum_a008336(void)
+{
+	u32 *eddrtqcr1;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 #ifdef 
+CONFIG_SYS_FSL_DCSR_DDR_ADDR
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
+	out_le32(eddrtqcr1, 0x63b30002);
+#endif
+#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
+	out_le32(eddrtqcr1, 0x63b30002);
+#endif
+#endif
+}
+
+/*
+ * This erratum requires a register write before being Memory
+ * controller 3 being enabled.
+ */
+static void erratum_a008514(void)
+{
+	u32 *eddrtqcr1;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 #ifdef 
+CONFIG_SYS_FSL_DCSR_DDR2_ADDR
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
+	out_le32(eddrtqcr1, 0x63b20002);
+#endif
+#endif
+}
  #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
  #define PLATFORM_CYCLE_ENV_VAR	"a009635_interval_val"
 

@@ -118,6 +153,8 @@ void fsl_lsch3_early_init_f(void)
  	erratum_rcw_src();
  	init_early_memctl_regs();	/* tighten IFC timing */
  	erratum_a009203();
+	erratum_a008514();
+	erratum_a008336();
  }
 
  #elif defined(CONFIG_LS1043A)
(quoted diff) +0 -0

b/drivers/ddr/fsl/fsl_ddr_gen4.c index 50f4671..d7cbf34 100644

drivers/ddr/fsl/fsl_ddr_gen4.c +0 -13
@@ -48,10 +48,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  	u32 temp_sdram_cfg;
  	u32 total_gb_size_per_controller;
  	int timeout;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-	u32 *eddrtqcr1;
-#endif
  #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  	u32 temp32, mr6;
  	u32 vref_seq1[3] = {0x80, 0x96, 0x16};	/* for range 1 */

@@ -69,36 +65,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  	switch (ctrl_num) {
  	case 0:
  		ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; -#if 
 defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
-#endif
  		break;
  #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  	case 1:
  		ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; -#if 
 defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
-#endif
  		break;
  #endif
  #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  	case 2:
  		ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; -#if 
 defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
-#endif
  		break;
  #endif
  #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  	case 3:
  		ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; -#if

defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \

drivers/ddr/fsl/fsl_ddr_gen4.c +0 -15
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800;
-#endif
  		break;
  #endif
  	default:

@@ -109,20 +89,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  	if (step == 2)
  		goto step2;
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 -#if defined(CONFIG_LS2080A) || 
 defined(CONFIG_LS2085A)
-	/* A008336 only applies to general DDR controllers */
-	if ((ctrl_num == 0) || (ctrl_num == 1))
-#endif
-		ddr_out32(eddrtqcr1, 0x63b30002);
-#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 -#if defined(CONFIG_LS2080A) || 
 defined(CONFIG_LS2085A)
-	/* A008514 only applies to DP-DDR controler */
-	if (ctrl_num == 2)
-#endif
-		ddr_out32(eddrtqcr1, 0x63b20002);
-#endif
  	if (regs->ddr_eor)
  		ddr_out32(&ddr->eor, regs->ddr_eor);