Bring up rk3036 uboot

some rockchip soc will not include lib/timer.c in SPL stage, so implement timer driver for some soc can use us delay function in SPL.

Signed-off-by Lin Huang <[email protected]>

Acked-by Simon Glass <[email protected]>

---
Changes in v1: None
Changes in v2:
- add udelay function
Changes in v3:
- fix some coding style
Changes in v4: None
Changes in v5: None

 arch/arm/include/asm/arch-rockchip/timer.h | 22 ++++++++++++++
 arch/arm/mach-rockchip/Makefile            |  1 +
 arch/arm/mach-rockchip/board-spl.c         | 21 ++-----------
 arch/arm/mach-rockchip/rk_timer.c          | 48 ++++++++++++++++++++++++++++++
 include/configs/rk3288_common.h            |  3 +-
 5 files changed, 75 insertions(+), 20 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h
 create mode 100644 arch/arm/mach-rockchip/rk_timer.c

arch/arm/include/asm/arch-rockchip/timer.h new file +0 -0

new file mode 100644
index 0000000..59444d4

arch/arm/include/asm/arch-rockchip/timer.h new file +11 -0

+       unsigned int timer_load_count1;
+       unsigned int timer_curr_value0;
+       unsigned int timer_curr_value1;
+       unsigned int timer_ctrl_reg;
+       unsigned int timer_int_status;
+};
+
+void rockchip_timer_init(void);
+void rockchip_udelay(unsigned int us);
+
+#endif

arch/arm/mach-rockchip/Makefile +1 -0

index 5a4e383..abe03a8 100644
@@ -10,4 +10,5 @@ else
 obj-y += board.o
 endif
 obj-y += common.o
+obj-y += rk_timer.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/

arch/arm/mach-rockchip/board-spl.c +2 -19

index 28c3949..0426adf 100644
@@ -18,6 +18,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/periph.h>
 #include <asm/arch/sdram.h>
+#include <asm/arch/timer.h>
 #include <dm/pinctrl.h>
 #include <dm/root.h>
 #include <dm/test.h>

@@ -110,24 +111,6 @@ static void configure_l2ctlr(void)
        write_l2ctlr(l2ctlr);
 }
 
-struct rk3288_timer {
-       u32 timer_load_count0;
-       u32 timer_load_count1;
-       u32 timer_curr_value0;
-       u32 timer_curr_value1;
-       u32 timer_ctrl_reg;
-       u32 timer_int_status;
-};
-
-void init_timer(void)
-{
-       struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE;
-
-       writel(0xffffffff, &timer7_ptr->timer_load_count0);
-       writel(0xffffffff, &timer7_ptr->timer_load_count1);
-       writel(1, &timer7_ptr->timer_ctrl_reg);
-}
-
 static int configure_emmc(struct udevice *pinctrl)
 {
        struct gpio_desc desc;

@@ -197,7 +180,7 @@ void board_init_f(ulong dummy)
                hang();
        }
 
-       init_timer();
+       rockchip_timer_init();
        configure_l2ctlr();
 
        ret = uclass_get_device(UCLASS_CLK, 0, &dev);

arch/arm/mach-rockchip/rk_timer.c new file +14 -0

new file mode 100644
index 0000000..ae693c0
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <asm/arch/timer.h>
+#include <asm/io.h>
+#include <common.h>
+#include <linux/types.h>
+
+struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE;
+
+static uint64_t rockchip_get_ticks(void)

arch/arm/mach-rockchip/rk_timer.c new file +13 -0

+       tmp = rockchip_get_ticks() + usec_to_tick(us);
+
+       /* loop till event */
+       while (rockchip_get_ticks() < tmp+1)
+               ;
+}
+
+void rockchip_timer_init(void)
+{
+       writel(0xffffffff, &timer_ptr->timer_load_count0);
+       writel(0xffffffff, &timer_ptr->timer_load_count1);
+       writel(1, &timer_ptr->timer_ctrl_reg);
+}

include/configs/rk3288_common.h +0 -0

index 36408b9..cdea6cb 100644

include/configs/rk3288_common.h +1 -1

+#define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
 
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
--

1.9.1

Quoted 32 lines · Lin Huang

some rockchip soc will not include lib/timer.c in SPL stage, so implement timer driver for some soc can use us delay function in SPL.

Signed-off-by Lin Huang <[email protected]>

Acked-by Simon Glass <[email protected]>

---
Changes in v1: None
Changes in v2:
- add udelay function
Changes in v3:
- fix some coding style
Changes in v4: None
Changes in v5: None

  arch/arm/include/asm/arch-rockchip/timer.h | 22 ++++++++++++++
  arch/arm/mach-rockchip/Makefile            |  1 +
  arch/arm/mach-rockchip/board-spl.c         | 21 ++-----------
  arch/arm/mach-rockchip/rk_timer.c          | 48 ++++++++++++++++++++++++++++++
  include/configs/rk3288_common.h            |  3 +-
  5 files changed, 75 insertions(+), 20 deletions(-)

create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h create mode 100644 arch/arm/mach-rockchip/rk_timer.c

arch/arm/include/asm/arch-rockchip/timer.h new file +3 -0

new file mode 100644
index 0000000..59444d4
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *

arch/arm/include/asm/arch-rockchip/timer.h line 10

Quoted 7 lines

arch/arm/include/asm/arch-rockchip/timer.h new file +7 -0

+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_TIMER_H
+#define __ASM_ARCH_TIMER_H
+
+struct rk_timer {

question: should these use sized integer type?

arch/arm/include/asm/arch-rockchip/timer.h line 11

Quoted 1 line

arch/arm/include/asm/arch-rockchip/timer.h new file +1 -0

+       unsigned int timer_load_count0;

nit: it may be clearer to use _l / _h suffix instead of 0 / 1

Quoted 92 lines

arch/arm/include/asm/arch-rockchip/timer.h new file +11 -0

+       unsigned int timer_load_count1;
+       unsigned int timer_curr_value0;
+       unsigned int timer_curr_value1;
+       unsigned int timer_ctrl_reg;
+       unsigned int timer_int_status;
+};
+
+void rockchip_timer_init(void);
+void rockchip_udelay(unsigned int us);
+
+#endif

arch/arm/mach-rockchip/Makefile +1 -0

index 5a4e383..abe03a8 100644
@@ -10,4 +10,5 @@ else
  obj-y += board.o
  endif
  obj-y += common.o
+obj-y += rk_timer.o
  obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/

arch/arm/mach-rockchip/board-spl.c +2 -19

index 28c3949..0426adf 100644
@@ -18,6 +18,7 @@
  #include <asm/arch/hardware.h>
  #include <asm/arch/periph.h>
  #include <asm/arch/sdram.h>
+#include <asm/arch/timer.h>
  #include <dm/pinctrl.h>
  #include <dm/root.h>
  #include <dm/test.h>

@@ -110,24 +111,6 @@ static void configure_l2ctlr(void)
         write_l2ctlr(l2ctlr);
  }
 
-struct rk3288_timer {
-       u32 timer_load_count0;
-       u32 timer_load_count1;
-       u32 timer_curr_value0;
-       u32 timer_curr_value1;
-       u32 timer_ctrl_reg;
-       u32 timer_int_status;
-};
-
-void init_timer(void)
-{
-       struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE;
-
-       writel(0xffffffff, &timer7_ptr->timer_load_count0);
-       writel(0xffffffff, &timer7_ptr->timer_load_count1);
-       writel(1, &timer7_ptr->timer_ctrl_reg);
-}
-
  static int configure_emmc(struct udevice *pinctrl)
  {
         struct gpio_desc desc;

@@ -197,7 +180,7 @@ void board_init_f(ulong dummy)
                 hang();
         }
 
-       init_timer();
+       rockchip_timer_init();
         configure_l2ctlr();
 
         ret = uclass_get_device(UCLASS_CLK, 0, &dev);

arch/arm/mach-rockchip/rk_timer.c new file +18 -0

new file mode 100644
index 0000000..ae693c0
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <asm/arch/timer.h>
+#include <asm/io.h>
+#include <common.h>
+#include <linux/types.h>
+
+struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE;
+
+static uint64_t rockchip_get_ticks(void)
+{
+       uint64_t timebase_h, timebase_l;
+
+       timebase_l = readl(&timer_ptr->timer_curr_value0);

arch/arm/mach-rockchip/rk_timer.c line 24

Quoted 6 lines

arch/arm/mach-rockchip/rk_timer.c new file +6 -0

+       timebase_h = readl(&timer_ptr->timer_curr_value1);
+
+       return timebase_h << 32 | timebase_l;
+}
+
+static unsigned int usec_to_tick(unsigned long usec)

should probably use 'uint64_t' for 'tick' and the return value, and use 'unsigned int' for 'usec'

arch/arm/mach-rockchip/rk_timer.c line 31

Quoted 8 lines

arch/arm/mach-rockchip/rk_timer.c new file +7 -0

+{
+       unsigned int tick = usec;
+       tick *= CONFIG_SYS_TIMER_RATE / (1000 * 1000);
+       return tick;
+}
+
+void rockchip_udelay(unsigned int us)

nit: perhaps use 'usec' instead of 'us' for consistency with usec_to_tick

arch/arm/mach-rockchip/rk_timer.c line 35

Quoted 5 lines

arch/arm/mach-rockchip/rk_timer.c new file +4 -0

+{
+       uint64_t tmp;
+
+       /* get current timestamp */

nit: the comment is kind of misleadning as 'tmp' isn't the current timestamp

Quoted 20 lines

arch/arm/mach-rockchip/rk_timer.c new file +13 -0

+       tmp = rockchip_get_ticks() + usec_to_tick(us);
+
+       /* loop till event */
+       while (rockchip_get_ticks() < tmp+1)
+               ;
+}
+
+void rockchip_timer_init(void)
+{
+       writel(0xffffffff, &timer_ptr->timer_load_count0);
+       writel(0xffffffff, &timer_ptr->timer_load_count1);
+       writel(1, &timer_ptr->timer_ctrl_reg);
+}

include/configs/rk3288_common.h +0 -0

index 36408b9..cdea6cb 100644
@@ -23,7 +23,8 @@
  #define CONFIG_DISPLAY_BOARDINFO
 

include/configs/rk3288_common.h line 26

Quoted 3 lines

include/configs/rk3288_common.h +1 -1

  #define CONFIG_SYS_TIMER_RATE          (24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_COUNTER       (TIMER7_BASE + 8)
+#define        CONFIG_SYS_TIMER_BASE           0xff810020 /* TIMER7 */

nit: the code around it seems to use a space instead of a tab after #define

Quoted 8 lines

include/configs/rk3288_common.h +1 -1

+#define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
 
  #define CONFIG_SPL_FRAMEWORK
  #define CONFIG_SPL_LIBCOMMON_SUPPORT
--

1.9.1

Add SPL Kconfig for REGMAP and SYSCON, so REGMAP and SYSCON can remove from SPL stage.

Signed-off-by Lin Huang <[email protected]>

---
Changes in v1: None
Changes in v2: None
Changes in v3:
- fix compile error
Changes in v4: None
Changes in v5: None

 configs/chromebook_jerry_defconfig |  2 ++
 configs/firefly-rk3288_defconfig   |  2 ++
 configs/sandbox_defconfig          |  2 ++
 drivers/core/Kconfig               | 19 +++++++++++++++++++
 drivers/core/Makefile              |  4 ++--
 5 files changed, 27 insertions(+), 2 deletions(-)

GRF is the gereral register file. Add header files with register definitions.

Signed-off-by Lin Huang <[email protected]>

Acked-by Simon Glass <[email protected]>

---
Changes in v1:
- clean copyright announcement
Changes in v2:
- move some macro to grf_rk3036.h
Changes in v3: None
Changes in v4: None
Changes in v5: None

 arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 ++++++++++++++++++++++++
 1 file changed, 493 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3036.h

arch/arm/include/asm/arch-rockchip/grf_rk3036.h new file +2 -0

new file mode 100644
index 0000000..72d133c
@@ -0,0 +1,493 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd

arch/arm/include/asm/arch-rockchip/grf_rk3036.h new file +481 -1

+       unsigned int gpio0a_iomux;
+       unsigned int gpio0b_iomux;
+       unsigned int gpio0c_iomux;
+       unsigned int gpio0d_iomux;
+
+       unsigned int gpio1a_iomux;
+       unsigned int gpio1b_iomux;
+       unsigned int gpio1c_iomux;
+       unsigned int gpio1d_iomux;
+
+       unsigned int gpio2a_iomux;
+       unsigned int gpio2b_iomux;
+       unsigned int gpio2c_iomux;
+       unsigned int gpio2d_iomux;
+
+       unsigned int reserved2[0x0a];
+       unsigned int gpiods;
+       unsigned int reserved3[0x05];
+       unsigned int gpio0l_pull;
+       unsigned int gpio0h_pull;
+       unsigned int gpio1l_pull;
+       unsigned int gpio1h_pull;
+       unsigned int gpio2l_pull;
+       unsigned int gpio2h_pull;
+       unsigned int reserved4[4];
+       unsigned int soc_con0;
+       unsigned int soc_con1;
+       unsigned int soc_con2;
+       unsigned int soc_status0;
+       unsigned int reserved5;
+       unsigned int soc_con3;
+       unsigned int reserved6;
+       unsigned int dmac_con0;
+       unsigned int dmac_con1;
+       unsigned int dmac_con2;
+       unsigned int reserved7[5];
+       unsigned int uoc0_con5;
+       unsigned int reserved8[4];
+       unsigned int uoc1_con4;
+       unsigned int uoc1_con5;
+       unsigned int reserved9;
+       unsigned int ddrc_stat;
+       unsigned int uoc_con6;
+       unsigned int soc_status1;
+       unsigned int cpu_con0;
+       unsigned int cpu_con1;
+       unsigned int cpu_con2;
+       unsigned int cpu_con3;
+       unsigned int reserved10;
+       unsigned int reserved11;
+       unsigned int cpu_status0;
+       unsigned int cpu_status1;
+       unsigned int os_reg[8];
+       unsigned int reserved12[6];
+       unsigned int dll_con[4];
+       unsigned int dll_status[4];
+       unsigned int dfi_wrnum;
+       unsigned int dfi_rdnum;
+       unsigned int dfi_actnum;
+       unsigned int dfi_timerval;
+       unsigned int nfi_fifo[4];
+       unsigned int reserved13[0x10];
+       unsigned int usbphy0_con[8];
+       unsigned int usbphy1_con[8];
+       unsigned int reserved14[0x10];
+       unsigned int chip_tag;
+       unsigned int sdmmc_det_cnt;
+};
+check_member(rk3036_grf, sdmmc_det_cnt, 0x304);
+
+/* GRF_GPIO0A_IOMUX */
+enum {
+       GPIO0A3_SHIFT           = 6,
+       GPIO0A3_MASK            = 1,
+       GPIO0A3_GPIO            = 0,
+       GPIO0A3_I2C1_SDA,
+
+       GPIO0A2_SHIFT           = 4,
+       GPIO0A2_MASK            = 1,
+       GPIO0A2_GPIO            = 0,
+       GPIO0A2_I2C1_SCL,
+
+       GPIO0A1_SHIFT           = 2,
+       GPIO0A1_MASK            = 3,
+       GPIO0A1_GPIO            = 0,
+       GPIO0A1_I2C0_SDA,
+       GPIO0A1_PWM2,
+
+       GPIO0A0_SHIFT           = 0,
+       GPIO0A0_MASK            = 3,
+       GPIO0A0_GPIO            = 0,
+       GPIO0A0_I2C0_SCL,
+       GPIO0A0_PWM1,
+
+};
+
+/* GRF_GPIO0B_IOMUX */
+enum {
+       GPIO0B6_SHIFT           = 12,
+       GPIO0B6_MASK            = 3,
+       GPIO0B6_GPIO            = 0,
+       GPIO0B6_MMC1_D3,
+       GPIO0B6_I2S1_SCLK,
+
+       GPIO0B5_SHIFT           = 10,
+       GPIO0B5_MASK            = 3,
+       GPIO0B5_GPIO            = 0,
+       GPIO0B5_MMC1_D2,
+       GPIO0B5_I2S1_SDI,
+
+       GPIO0B4_SHIFT           = 8,
+       GPIO0B4_MASK            = 3,
+       GPIO0B4_GPIO            = 0,
+       GPIO0B4_MMC1_D1,
+       GPIO0B4_I2S1_LRCKTX,
+
+       GPIO0B3_SHIFT           = 6,
+       GPIO0B3_MASK            = 3,
+       GPIO0B3_GPIO            = 0,
+       GPIO0B3_MMC1_D0,
+       GPIO0B3_I2S1_LRCKRX,
+
+       GPIO0B1_SHIFT           = 2,
+       GPIO0B1_MASK            = 3,
+       GPIO0B1_GPIO            = 0,
+       GPIO0B1_MMC1_CLKOUT,
+       GPIO0B1_I2S1_MCLK,
+
+       GPIO0B0_SHIFT           = 0,
+       GPIO0B0_MASK            = 3,
+       GPIO0B0_GPIO            = 0,
+       GPIO0B0_MMC1_CMD,
+       GPIO0B0_I2S1_SDO,
+};
+
+/* GRF_GPIO0C_IOMUX */
+enum {
+       GPIO0C4_SHIFT           = 8,
+       GPIO0C4_MASK            = 1,
+       GPIO0C4_GPIO            = 0,
+       GPIO0C4_DRIVE_VBUS,
+
+       GPIO0C3_SHIFT           = 6,
+       GPIO0C3_MASK            = 1,
+       GPIO0C3_GPIO            = 0,
+       GPIO0C3_UART0_CTSN,
+
+       GPIO0C2_SHIFT           = 4,
+       GPIO0C2_MASK            = 1,
+       GPIO0C2_GPIO            = 0,
+       GPIO0C2_UART0_RTSN,
+
+       GPIO0C1_SHIFT           = 2,
+       GPIO0C1_MASK            = 1,
+       GPIO0C1_GPIO            = 0,
+       GPIO0C1_UART0_SIN,
+
+
+       GPIO0C0_SHIFT           = 0,
+       GPIO0C0_MASK            = 1,
+       GPIO0C0_GPIO            = 0,
+       GPIO0C0_UART0_SOUT,
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+       GPIO0D4_SHIFT           = 8,
+       GPIO0D4_MASK            = 1,
+       GPIO0D4_GPIO            = 0,
+       GPIO0D4_SPDIF,
+
+       GPIO0D3_SHIFT           = 6,
+       GPIO0D3_MASK            = 1,
+       GPIO0D3_GPIO            = 0,
+       GPIO0D3_PWM3,
+
+       GPIO0D2_SHIFT           = 4,
+       GPIO0D2_MASK            = 1,
+       GPIO0D2_GPIO            = 0,
+       GPIO0D2_PWM0,
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+       GPIO1A5_SHIFT           = 10,
+       GPIO1A5_MASK            = 1,
+       GPIO1A5_GPIO            = 0,
+       GPIO1A5_I2S_SDI,
+
+       GPIO1A4_SHIFT           = 8,
+       GPIO1A4_MASK            = 1,
+       GPIO1A4_GPIO            = 0,
+       GPIO1A4_I2S_SD0,
+
+       GPIO1A3_SHIFT           = 6,
+       GPIO1A3_MASK            = 1,
+       GPIO1A3_GPIO            = 0,
+       GPIO1A3_I2S_LRCKTX,
+
+       GPIO1A2_SHIFT           = 4,
+       GPIO1A2_MASK            = 6,
+       GPIO1A2_GPIO            = 0,
+       GPIO1A2_I2S_LRCKRX,
+       GPIO1A2_I2S_PWM1_0,
+
+       GPIO1A1_SHIFT           = 2,
+       GPIO1A1_MASK            = 1,
+       GPIO1A1_GPIO            = 0,
+       GPIO1A1_I2S_SCLK,
+
+       GPIO1A0_SHIFT           = 0,
+       GPIO1A0_MASK            = 1,
+       GPIO1A0_GPIO            = 0,
+       GPIO1A0_I2S_MCLK,
+
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+       GPIO1B7_SHIFT           = 14,
+       GPIO1B7_MASK            = 1,
+       GPIO1B7_GPIO            = 0,
+       GPIO1B7_MMC0_CMD,
+
+       GPIO1B3_SHIFT           = 6,
+       GPIO1B3_MASK            = 1,
+       GPIO1B3_GPIO            = 0,
+       GPIO1B3_HDMI_HPD,
+
+       GPIO1B2_SHIFT           = 4,
+       GPIO1B2_MASK            = 1,
+       GPIO1B2_GPIO            = 0,
+       GPIO1B2_HDMI_SCL,
+
+       GPIO1B1_SHIFT           = 2,
+       GPIO1B1_MASK            = 1,
+       GPIO1B1_GPIO            = 0,
+       GPIO1B1_HDMI_SDA,
+
+       GPIO1B0_SHIFT           = 0,
+       GPIO1B0_MASK            = 1,
+       GPIO1B0_GPIO            = 0,
+       GPIO1B0_HDMI_CEC,
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+       GPIO1C5_SHIFT           = 10,
+       GPIO1C5_MASK            = 3,
+       GPIO1C5_GPIO            = 0,
+       GPIO1C5_MMC0_D3,
+       GPIO1C5_JTAG_TMS,
+
+       GPIO1C4_SHIFT           = 8,
+       GPIO1C4_MASK            = 3,
+       GPIO1C4_GPIO            = 0,
+       GPIO1C4_MMC0_D2,
+       GPIO1C4_JTAG_TCK,
+
+       GPIO1C3_SHIFT           = 6,
+       GPIO1C3_MASK            = 3,
+       GPIO1C3_GPIO            = 0,
+       GPIO1C3_MMC0_D1,
+       GPIO1C3_UART2_SOUT,
+
+       GPIO1C2_SHIFT           = 4,
+       GPIO1C2_MASK            = 3,
+       GPIO1C2_GPIO            = 0,
+       GPIO1C2_MMC0_D0,
+       GPIO1C2_UART2_SIN,
+
+       GPIO1C1_SHIFT           = 2,
+       GPIO1C1_MASK            = 1,
+       GPIO1C1_GPIO            = 0,
+       GPIO1C1_MMC0_DETN,
+
+       GPIO1C0_SHIFT           = 0,
+       GPIO1C0_MASK            = 1,
+       GPIO1C0_GPIO            = 0,
+       GPIO1C0_MMC0_CLKOUT,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+       GPIO1D7_SHIFT           = 14,
+       GPIO1D7_MASK            = 3,
+       GPIO1D7_GPIO            = 0,
+       GPIO1D7_NAND_D7,
+       GPIO1D7_EMMC_D7,
+       GPIO1D7_SPI_CSN1,
+
+       GPIO1D6_SHIFT           = 12,
+       GPIO1D6_MASK            = 3,
+       GPIO1D6_GPIO            = 0,
+       GPIO1D6_NAND_D6,
+       GPIO1D6_EMMC_D6,
+       GPIO1D6_SPI_CSN0,
+
+       GPIO1D5_SHIFT           = 10,
+       GPIO1D5_MASK            = 3,
+       GPIO1D5_GPIO            = 0,
+       GPIO1D5_NAND_D5,
+       GPIO1D5_EMMC_D5,
+       GPIO1D5_SPI_TXD,
+
+       GPIO1D4_SHIFT           = 8,
+       GPIO1D4_MASK            = 3,
+       GPIO1D4_GPIO            = 0,
+       GPIO1D4_NAND_D4,
+       GPIO1D4_EMMC_D4,
+       GPIO1D4_SPI_RXD,
+
+       GPIO1D3_SHIFT           = 6,
+       GPIO1D3_MASK            = 3,
+       GPIO1D3_GPIO            = 0,
+       GPIO1D3_NAND_D3,
+       GPIO1D3_EMMC_D3,
+       GPIO1D3_SFC_SIO3,
+
+       GPIO1D2_SHIFT           = 4,
+       GPIO1D2_MASK            = 3,
+       GPIO1D2_GPIO            = 0,
+       GPIO1D2_NAND_D2,
+       GPIO1D2_EMMC_D2,
+       GPIO1D2_SFC_SIO2,
+
+       GPIO1D1_SHIFT           = 2,
+       GPIO1D1_MASK            = 3,
+       GPIO1D1_GPIO            = 0,
+       GPIO1D1_NAND_D1,
+       GPIO1D1_EMMC_D1,
+       GPIO1D1_SFC_SIO1,
+
+       GPIO1D0_SHIFT           = 0,
+       GPIO1D0_MASK            = 3,
+       GPIO1D0_GPIO            = 0,
+       GPIO1D0_NAND_D0,
+       GPIO1D0_EMMC_D0,
+       GPIO1D0_SFC_SIO0,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+       GPIO2A7_SHIFT           = 14,
+       GPIO2A7_MASK            = 1,
+       GPIO2A7_GPIO            = 0,
+       GPIO2A7_TESTCLK_OUT,
+
+       GPIO2A6_SHIFT           = 12,
+       GPIO2A6_MASK            = 1,
+       GPIO2A6_GPIO            = 0,
+       GPIO2A6_NAND_CS0,
+
+       GPIO2A4_SHIFT           = 8,
+       GPIO2A4_MASK            = 3,
+       GPIO2A4_GPIO            = 0,
+       GPIO2A4_NAND_RDY,
+       GPIO2A4_EMMC_CMD,
+       GPIO2A3_SFC_CLK,
+
+       GPIO2A3_SHIFT           = 6,
+       GPIO2A3_MASK            = 3,
+       GPIO2A3_GPIO            = 0,
+       GPIO2A3_NAND_RDN,
+       GPIO2A4_SFC_CSN1,
+
+       GPIO2A2_SHIFT           = 4,
+       GPIO2A2_MASK            = 3,
+       GPIO2A2_GPIO            = 0,
+       GPIO2A2_NAND_WRN,
+       GPIO2A4_SFC_CSN0,
+
+       GPIO2A1_SHIFT           = 2,
+       GPIO2A1_MASK            = 3,
+       GPIO2A1_GPIO            = 0,
+       GPIO2A1_NAND_CLE,
+       GPIO2A1_EMMC_CLKOUT,
+
+       GPIO2A0_SHIFT           = 0,
+       GPIO2A0_MASK            = 3,
+       GPIO2A0_GPIO            = 0,
+       GPIO2A0_NAND_ALE,
+       GPIO2A0_SPI_CLK,
+};
+
+/* GRF_GPIO2B_IOMUX */
+enum {
+       GPIO2B7_SHIFT           = 14,
+       GPIO2B7_MASK            = 1,
+       GPIO2B7_GPIO            = 0,
+       GPIO2B7_MAC_RXER,
+
+       GPIO2B6_SHIFT           = 12,
+       GPIO2B6_MASK            = 3,
+       GPIO2B6_GPIO            = 0,
+       GPIO2B6_MAC_CLKOUT,
+       GPIO2B6_MAC_CLKIN,
+
+       GPIO2B5_SHIFT           = 10,
+       GPIO2B5_MASK            = 1,
+       GPIO2B5_GPIO            = 0,
+       GPIO2B5_MAC_TXEN,
+
+       GPIO2B4_SHIFT           = 8,
+       GPIO2B4_MASK            = 1,
+       GPIO2B4_GPIO            = 0,
+       GPIO2B4_MAC_MDIO,
+
+       GPIO2B2_SHIFT           = 4,
+       GPIO2B2_MASK            = 1,
+       GPIO2B2_GPIO            = 0,
+       GPIO2B2_MAC_CRS,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+       GPIO2C7_SHIFT           = 14,
+       GPIO2C7_MASK            = 3,
+       GPIO2C7_GPIO            = 0,
+       GPIO2C7_UART1_SOUT,
+       GPIO2C7_TESTCLK_OUT1,
+
+       GPIO2C6_SHIFT           = 12,
+       GPIO2C6_MASK            = 1,
+       GPIO2C6_GPIO            = 0,
+       GPIO2C6_UART1_SIN,
+
+       GPIO2C5_SHIFT           = 10,
+       GPIO2C5_MASK            = 1,
+       GPIO2C5_GPIO            = 0,
+       GPIO2C5_I2C2_SCL,
+
+       GPIO2C4_SHIFT           = 8,
+       GPIO2C4_MASK            = 1,
+       GPIO2C4_GPIO            = 0,
+       GPIO2C4_I2C2_SDA,
+
+       GPIO2C3_SHIFT           = 6,
+       GPIO2C3_MASK            = 1,
+       GPIO2C3_GPIO            = 0,
+       GPIO2C3_MAC_TXD0,
+
+       GPIO2C2_SHIFT           = 4,
+       GPIO2C2_MASK            = 1,
+       GPIO2C2_GPIO            = 0,
+       GPIO2C2_MAC_TXD1,
+
+       GPIO2C1_SHIFT           = 2,
+       GPIO2C1_MASK            = 1,
+       GPIO2C1_GPIO            = 0,
+       GPIO2C1_MAC_RXD0,
+
+       GPIO2C0_SHIFT           = 0,
+       GPIO2C0_MASK            = 1,
+       GPIO2C0_GPIO            = 0,
+       GPIO2C0_MAC_RXD1,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+       GPIO2D6_SHIFT           = 12,
+       GPIO2D6_MASK            = 1,
+       GPIO2D6_GPIO            = 0,
+       GPIO2D6_I2S_SDO1,
+
+       GPIO2D5_SHIFT           = 10,
+       GPIO2D5_MASK            = 1,
+       GPIO2D5_GPIO            = 0,
+       GPIO2D5_I2S_SDO2,
+
+       GPIO2D4_SHIFT           = 8,
+       GPIO2D4_MASK            = 1,
+       GPIO2D4_GPIO            = 0,
+       GPIO2D4_I2S_SDO3,
+
+       GPIO2D1_SHIFT           = 2,
+       GPIO2D1_MASK            = 1,
+       GPIO2D1_GPIO            = 0,
+       GPIO2D1_MAC_MDC,
+};
+#endif
--

1.9.1

Add a driver which support pin multiplexing setup for rk3036

Signed-off-by Lin Huang <[email protected]>

Acked-by Simon Glass <[email protected]>

---
Changes in v1:
- clean copyright announcement
Changes in v2: None
Changes in v3:
- fix some coding style error
Changes in v4: None
Changes in v5: None

 drivers/pinctrl/Kconfig                   |  18 ++
 drivers/pinctrl/rockchip/Makefile         |   1 +
 drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++++++++++++++++++++++++
 3 files changed, 295 insertions(+)
 create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c

drivers/pinctrl/Kconfig +0 -0

index 3b6e3b7..6495313 100644
@@ -114,6 +114,24 @@ config ROCKCHIP_PINCTRL
 	  definitions and pin control functions for each available multiplex
 	  function.
 

drivers/pinctrl/Kconfig +8 -0

+	bool "Rockchip pin control driver"
+	depends on DM
+	help
+	  Support pin multiplexing control on Rockchip SoCs. The driver is
+	  controlled by a device tree node which contains both the GPIO
+	  definitions and pin control functions for each available multiplex
+	  function.
+
 config PINCTRL_SANDBOX
 	bool "Sandbox pinctrl driver"
 	depends on SANDBOX

Hi Lin,

El 10/11/15 a las 07:24, Lin Huang escribi?:

Quoted 27 lines

Add a driver which support pin multiplexing setup for rk3036

Signed-off-by Lin Huang <[email protected]>

Acked-by Simon Glass <[email protected]>

---
Changes in v1:
- clean copyright announcement
Changes in v2: None
Changes in v3:
- fix some coding style error
Changes in v4: None
Changes in v5: None

  drivers/pinctrl/Kconfig                   |  18 ++
  drivers/pinctrl/rockchip/Makefile         |   1 +
  drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++++++++++++++++++++++++
  3 files changed, 295 insertions(+)

create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c

drivers/pinctrl/Kconfig +0 -0

index 3b6e3b7..6495313 100644
@@ -114,6 +114,24 @@ config ROCKCHIP_PINCTRL
  	  definitions and pin control functions for each available multiplex
  	  function.
 

drivers/pinctrl/Kconfig config ROCKCHIP_PINCTRL · line 126

Quoted 10 lines

drivers/pinctrl/Kconfig +10 -0

+config ROCKCHIP_3036_PINCTRL
+	bool "Rockchip rk3036 pin control driver"
+	depends on DM
+	help
+	  Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is
+	  controlled by a device tree node which contains both the GPIO
+	  definitions and pin control functions for each available multiplex
+	  function.
+
+config ROCKCHIP_PINCTRL

You're duplicating ROCKCHIP_PINCTRL entry here.

Quoted 12 lines

drivers/pinctrl/Kconfig +8 -0

+	bool "Rockchip pin control driver"
+	depends on DM
+	help
+	  Support pin multiplexing control on Rockchip SoCs. The driver is
+	  controlled by a device tree node which contains both the GPIO
+	  definitions and pin control functions for each available multiplex
+	  function.
+
  config PINCTRL_SANDBOX
  	bool "Sandbox pinctrl driver"
  	depends on SANDBOX

[...]

some soc(rk3036 etc) use dw_mmc but do not have internal dma, so we implement fifo mode to read and write data.

Signed-off-by Lin Huang <[email protected]>

---
 drivers/mmc/dw_mmc.c | 81 +++++++++++++++++++++++++++++++++++++++++++---------
 include/dwmmc.h      |  5 ++++
 2 files changed, 72 insertions(+), 14 deletions(-)

drivers/mmc/dw_mmc.c +23 -9

index 26d34ae..18be055 100644
@@ -118,6 +118,8 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
        u32 mask, ctrl;
        ulong start = get_timer(0);
        struct bounce_buffer bbstate;
+       unsigned int fifo_len, fifo_depth, size;
+       unsigned int *buf = NULL;
 
        while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
                if (get_timer(start) > timeout) {

@@ -129,17 +131,28 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
        dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
 
        if (data) {
-               if (data->flags == MMC_DATA_READ) {
-                       bounce_buffer_start(&bbstate, (void*)data->dest,
-                                           data->blocksize *
-                                           data->blocks, GEN_BB_WRITE);
+               if (host->fifo_mode) {
+                       if (data->flags == MMC_DATA_READ)
+                               buf = (unsigned int *)data->dest;
+                       else
+                               buf = (unsigned int *)data->src;
+                       dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
+                       dwmci_writel(host, DWMCI_BYTCNT,
+                                    data->blocksize * data->blocks);
+                       dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
                } else {
-                       bounce_buffer_start(&bbstate, (void*)data->src,
-                                           data->blocksize *
-                                           data->blocks, GEN_BB_READ);
+                       if (data->flags == MMC_DATA_READ) {
+                               bounce_buffer_start(&bbstate, (void*)data->dest,
+                                               data->blocksize *
+                                               data->blocks, GEN_BB_WRITE);
+                       } else {
+                               bounce_buffer_start(&bbstate, (void*)data->src,
+                                               data->blocksize *
+                                               data->blocks, GEN_BB_READ);
+                       }
+                       dwmci_prepare_data(host, data, cur_idmac,
+                                          bbstate.bounce_buffer);
                }
-               dwmci_prepare_data(host, data, cur_idmac,
-                                  bbstate.bounce_buffer);
        }
 
        dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);

@@ -215,6 +228,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
        if (data) {
                start = get_timer(0);
                timeout = 240000;
+               size = data->blocksize * data->blocks / 4;
                for (;;) {
                        mask = dwmci_readl(host, DWMCI_RINTSTS);
                        /* Error during data transfer. */

drivers/mmc/dw_mmc.c +29 -5

+                               }
+                       } else if (data->flags == MMC_DATA_WRITE &&
+                                  host->fifo_mode) {
+                               fifo_depth = (((host->fifoth_val &
+                                               RX_WMARK_MASK) >>
+                                               RX_WMARK_SHIFT) + 1) * 2;
+                               if ((dwmci_readl(host, DWMCI_RINTSTS) &&
+                                    DWMCI_INTMSK_TXDR) && size) {
+                                       fifo_len = dwmci_readl(host,
+                                                       DWMCI_STATUS);
+                                       fifo_len = fifo_depth -
+                                               ((fifo_len >> DWMCI_FIFO_SHIFT)
+                                               & DWMCI_FIFO_MASK);
+                                       for (i = 0; i < fifo_len; i++)
+                                               dwmci_writel(host, DWMCI_DATA,
+                                                            *buf++);
+                                       dwmci_writel(host, DWMCI_RINTSTS,
+                                                    DWMCI_INTMSK_TXDR);
+                                       size = size > fifo_len ?
+                                                       (size - fifo_len) : 0;
+                               }
+                       }
+
                        /* Data arrived correctly. */
                        if (mask & DWMCI_INTMSK_DTO) {
                                ret = 0;

@@ -241,11 +293,12 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 
                dwmci_writel(host, DWMCI_RINTSTS, mask);
 
-               ctrl = dwmci_readl(host, DWMCI_CTRL);
-               ctrl &= ~(DWMCI_DMA_EN);
-               dwmci_writel(host, DWMCI_CTRL, ctrl);
-
-               bounce_buffer_stop(&bbstate);
+               if (!host->fifo_mode) {
+                       ctrl = dwmci_readl(host, DWMCI_CTRL);
+                       ctrl &= ~(DWMCI_DMA_EN);
+                       dwmci_writel(host, DWMCI_CTRL, ctrl);
+                       bounce_buffer_stop(&bbstate);
+               }
        }
 
        udelay(100);

include/dwmmc.h +2 -0

index 25cf42c..8d26e5e 100644
@@ -105,6 +105,8 @@
 
 /* Status Register */
 #define DWMCI_BUSY             (1 << 9)
+#define DWMCI_FIFO_MASK                0x1ff
+#define DWMCI_FIFO_SHIFT       17
 
 /* FIFOTH Register */
 #define MSIZE(x)               ((x) << 28)

include/dwmmc.h +0 -1

 };
 
 struct dwmci_idmac {
--

1.9.1

rk3036 mmc do not have internal dma, so we use fifo mode when read and write data, we get the fifo mode and fifo depth property from dts, pass to dw_mmc driver.

Signed-off-by Lin Huang <[email protected]>

---
 arch/arm/dts/rk3036.dtsi      |  1 +
 drivers/mmc/rockchip_dw_mmc.c | 28 ++++++++++++++++++++++------
 2 files changed, 23 insertions(+), 6 deletions(-)

arch/arm/dts/rk3036.dtsi +1 -0

index 0daae1e..ecf5416 100644
@@ -257,6 +257,7 @@
                cap-mmc-highspeed;
                mmc-ddr-1_8v;
                disable-wp;
+               fifo-mode;
                non-removable;
                num-slots = <1>;
                default-sample-phase = <158>;

drivers/mmc/rockchip_dw_mmc.c +0 -0

index f11c8e0..616e0bb 100644

drivers/mmc/rockchip_dw_mmc.c +0 -1

        priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
        if (IS_ERR(priv->grf))

@@ -71,10 +74,23 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
        if (ret)
                return ret;
 
-       ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,

drivers/mmc/rockchip_dw_mmc.c +2 -1

+
+       ret = add_dwmci(host, minmax[1], minmax[0]);
        if (ret)
                return ret;
 
--

1.9.1

add early uart driver so we can print debug message in SPL stage

Signed-off-by Lin Huang <[email protected]>

---
Changes in v1: None
Changes in v2: None
Changes in v3:
- pass uart base address to rk_uart_init() function Changes in v4: None
Changes in v5: None

 arch/arm/include/asm/arch-rockchip/uart.h | 44 ++++++++++++++++++++++++
 arch/arm/mach-rockchip/Makefile           |  1 +
 arch/arm/mach-rockchip/rk_early_print.c   | 56 +++++++++++++++++++++++++++++++
 3 files changed, 101 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rockchip/uart.h
 create mode 100644 arch/arm/mach-rockchip/rk_early_print.c

arch/arm/include/asm/arch-rockchip/uart.h new file +44 -0

new file mode 100644
index 0000000..ea86ce6
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_UART_H
+#define __ASM_ARCH_UART_H
+struct rk_uart {
+       unsigned int rbr; /* Receive buffer register. */
+       unsigned int ier; /* Interrupt enable register. */
+       unsigned int fcr; /* FIFO control register. */
+       unsigned int lcr; /* Line control register. */
+       unsigned int mcr; /* Modem control register. */
+       unsigned int lsr; /* Line status register. */
+       unsigned int msr; /* Modem status register. */
+       unsigned int scr;
+       unsigned int reserved1[(0x30 - 0x20) / 4];
+       unsigned int srbr[(0x70 - 0x30) / 4];
+       unsigned int far;
+       unsigned int tfr;
+       unsigned int rfw;
+       unsigned int usr;
+       unsigned int tfl;
+       unsigned int rfl;
+       unsigned int srr;
+       unsigned int srts;
+       unsigned int sbcr;
+       unsigned int sdmam;
+       unsigned int sfe;
+       unsigned int srt;
+       unsigned int stet;
+       unsigned int htx;
+       unsigned int dmasa;
+       unsigned int reserver2[(0xf4 - 0xac) / 4];
+       unsigned int cpr;
+       unsigned int ucv;
+       unsigned int ctr;
+};
+
+void rk_uart_init(void *base);
+void print_hex(unsigned int n);
+void print(char *s);
+#endif

arch/arm/mach-rockchip/Makefile +1 -0

index 902235b..a29675d 100644
@@ -10,5 +10,6 @@ else
 obj-y += board.o
 endif
 obj-y += rk_timer.o
+obj-y += rk_early_print.o
 obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/

arch/arm/mach-rockchip/rk_early_print.c new file +45 -0

new file mode 100644
index 0000000..c63ebd5
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/uart.h>
+#include <common.h>
+
+static struct rk_uart *uart_ptr;
+
+static void uart_wrtie_byte(char byte)
+{
+       writel(byte, &uart_ptr->rbr);
+       while (!(readl(&uart_ptr->lsr) & 0x40))
+               ;
+}
+
+void print(char *s)
+{
+       while (*s) {
+               if (*s == '\n')
+                       uart_wrtie_byte('\r');
+           uart_wrtie_byte(*s);
+           s++;
+       }
+}
+
+void print_hex(unsigned int n)
+{
+       int i;
+       int temp;
+
+       uart_wrtie_byte('0');
+       uart_wrtie_byte('x');
+
+       for (i = 8; i > 0; i--) {
+               temp = (n >> (i - 1) * 4) & 0x0f;
+               if (temp < 10)
+                       uart_wrtie_byte((char)(temp + '0'));
+               else
+                       uart_wrtie_byte((char)(temp - 10 + 'a'));
+       }
+       uart_wrtie_byte('\n');

arch/arm/mach-rockchip/rk_early_print.c new file +1 -1

+}
--

1.9.1