armv8: ls2085a: Add support of LS2085A SoC
Subsystems (4)
PATCH v2 2/2 armv8: ls2085a: Add support of LS2085A SoC
Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.
Signed-off-by Pratiyush Mohan Srivastava <[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>
---
Changes for v2: Rebased on LS1043 patch set
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 8 ++++++--
arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 5 +++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 4 ++--
arch/arm/include/asm/arch-fsl-layerscape/config.h | 8 +++++++-
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +++-
arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +-
configs/ls2080a_emu_defconfig | 2 +-
configs/ls2080a_simu_defconfig | 2 +-
configs/ls2080aqds_defconfig | 2 +-
configs/ls2080aqds_nand_defconfig | 2 +-
configs/ls2080ardb_defconfig | 2 +-
configs/ls2080ardb_nand_defconfig | 2 +-
configs/{ls2080a_emu_defconfig => ls2085a_emu_defconfig} | 2 +-
configs/{ls2080a_simu_defconfig => ls2085a_simu_defconfig} | 2 +-
configs/{ls2080aqds_defconfig => ls2085aqds_defconfig} | 2 +-
configs/{ls2080aqds_nand_defconfig => ls2085aqds_nand_defconfig} | 2 +-
configs/{ls2080ardb_defconfig => ls2085ardb_defconfig} | 2 +-
configs/{ls2080ardb_nand_defconfig => ls2085ardb_nand_defconfig} | 2 +-
drivers/ddr/fsl/fsl_ddr_gen4.c | 4 ++--
drivers/net/ldpaa_eth/Makefile | 1 +
drivers/pci/pcie_layerscape.c | 2 +-
include/configs/ls2080a_common.h | 9 +++++++--
include/configs/ls2080a_emu.h | 7 +++++++
include/configs/ls2080a_simu.h | 7 +++++++
include/linux/usb/xhci-fsl.h | 2 +-
26 files changed, 63 insertions(+), 26 deletions(-)
copy configs/{ls2080a_emu_defconfig => ls2085a_emu_defconfig} (87%)
copy configs/{ls2080a_simu_defconfig => ls2085a_simu_defconfig} (90%)
copy configs/{ls2080aqds_defconfig => ls2085aqds_defconfig} (86%)
copy configs/{ls2080aqds_nand_defconfig => ls2085aqds_nand_defconfig} (73%)
copy configs/{ls2080ardb_defconfig => ls2085ardb_defconfig} (86%)
copy configs/{ls2080ardb_nand_defconfig => ls2085ardb_nand_defconfig} (73%)arch/arm/cpu/armv8/fsl-layerscape/Makefile +6 -2
@@ -23,8 +23,12 @@ endif ifneq ($(CONFIG_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o -else +endif + +ifneq ($(CONFIG_LS2085A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o +endif + ifneq ($(CONFIG_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o endif -endif
arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c +5 -0
@@ -28,7 +28,12 @@ static struct serdes_config serdes1_cfg_tbl[] = { SGMII1 } }, {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, +#ifdef CONFIG_LS2080A + {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } }, +#endif +#ifdef CONFIG_LS2085A {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, +#endif {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A,
arch/arm/cpu/armv8/fsl-layerscape/soc.c +1 -1
@@ -13,7 +13,7 @@DECLARE_GLOBAL_DATA_PTR ; -#ifdef CONFIG_LS2080A +#if defined(CONFIG_LS2080A ) || defined(CONFIG_LS2085A )#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
arch/arm/cpu/armv8/fsl-layerscape/spl.c +2 -2
@@ -48,7 +48,7 @@ void board_init_f(ulong dummy) gd = &gdata;/* Clear global data */ memset ((void *)gd,0 ,sizeof (gd_t)); -#ifdef CONFIG_LS2080A +#if defined(CONFIG_LS2080A ) || defined(CONFIG_LS2085A )arch_cpu_init ();#endif #ifdef CONFIG_FSL_IFC
@@ -56,7 +56,7 @@ void board_init_f(ulong dummy)#endif board_early_init_f ();timer_init (); -#ifdef CONFIG_LS2080A +#if defined(CONFIG_LS2080A ) || defined(CONFIG_LS2085A )env_init ();#endif get_clocks ();
arch/arm/include/asm/arch-fsl-layerscape/config.h +7 -1
@@ -17,10 +17,16 @@#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 -#if defined(CONFIG_LS2080A ) +#if defined(CONFIG_LS2080A ) || defined(CONFIG_LS2085A )#define CONFIG_MAX_CPUS 16#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#ifdef CONFIG_LS2080A #define CONFIG_NUM_DDR_CONTROLLERS 2 +#endif +#ifdef CONFIG_LS2085A +#define CONFIG_NUM_DDR_CONTROLLERS 3 +#define CONFIG_SYS_FSL_HAS_DP_DDR +#endif #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }#define SRDS_MAX_LANES 8#define CONFIG_SYS_FSL_SRDS_1
arch/arm/include/asm/arch-fsl-layerscape/cpu.h +3 -1
@@ -11,8 +11,10 @@ static struct cpu_type cpu_type_list[] = {#ifdef CONFIG_LS2080A CPU_TYPE_ENTRY(LS2080, LS2080, 8),#endif +#ifdef CONFIG_LS2085A CPU_TYPE_ENTRY (LS2085 ,LS2085 ,8 ),CPU_TYPE_ENTRY (LS2045 ,LS2045 ,4 ), +#endif CPU_TYPE_ENTRY(LS1043, LS1043, 4), };
@@ -182,7 +184,7 @@ static const struct sys_mmu_table final_mmu_table[] = { CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, -#ifdef CONFIG_LS2080A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, #endif
arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +1 -1
@@ -9,7 +9,7 @@#include <config.h> -#if defined(CONFIG_LS2080A ) +#if defined(CONFIG_LS2080A ) || defined(CONFIG_LS2085A )enum srds_prtcl {NONE =0 , PCIE1,
configs/ls2080a_emu_defconfig +1 -1
@@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080A_EMU=y -CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A" # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set
configs/ls2080a_simu_defconfig +1 -1
@@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080A_SIMU=y -CONFIG_SYS_EXTRA_OPTIONS="SIMU" +CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A" # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set
configs/ls2080aqds_defconfig +1 -1
@@ -4,7 +4,7 @@ CONFIG_TARGET_LS2080AQDS=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y
configs/ls2080aqds_nand_defconfig +1 -1
@@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080AQDS=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y
configs/ls2080ardb_defconfig +1 -1
@@ -4,7 +4,7 @@ CONFIG_TARGET_LS2080ARDB=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y
configs/ls2080ardb_nand_defconfig +1 -1
@@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080ARDB=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y
configs/ls2085a_emu_defconfig renamed from configs/ls2080a_emu_defconfig +1 -1
@@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080A_EMU=y -CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2085A" # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set
configs/ls2085a_simu_defconfig renamed from configs/ls2080a_simu_defconfig +1 -1
@@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080A_SIMU=y -CONFIG_SYS_EXTRA_OPTIONS="SIMU" +CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2085A" # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set
configs/ls2085aqds_defconfig renamed from configs/ls2080aqds_defconfig +1 -1
@@ -4,7 +4,7 @@ CONFIG_TARGET_LS2080AQDS=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y
configs/ls2085aqds_nand_defconfig renamed from configs/ls2080aqds_nand_defconfig +1 -1
@@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080AQDS=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A" # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y
configs/ls2085ardb_defconfig renamed from configs/ls2080ardb_defconfig +1 -1
@@ -4,7 +4,7 @@ CONFIG_TARGET_LS2080ARDB=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y
configs/ls2085ardb_nand_defconfig renamed from configs/ls2080ardb_nand_defconfig +1 -1
@@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080ARDB=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A" # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y
drivers/ddr/fsl/fsl_ddr_gen4.c +2 -2
@@ -107,14 +107,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, goto step2; #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 -#ifdef CONFIG_LS2080A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) /* A008336 only applies to general DDR controllers */ if ((ctrl_num == 0) || (ctrl_num == 1)) #endif ddr_out32(eddrtqcr1, 0x63b30002); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 -#ifdef CONFIG_LS2080A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) /* A008514 only applies to DP-DDR controler */ if (ctrl_num == 2) #endif
drivers/net/ldpaa_eth/Makefile +1 -0
@@ -7,3 +7,4 @@ obj-y += ldpaa_wriop.o obj-y += ldpaa_eth.o obj-$(CONFIG_LS2080A) += ls2080a.o +obj-$(CONFIG_LS2085A) += ls2080a.o
drivers/pci/pcie_layerscape.c +1 -1
@@ -665,7 +665,7 @@ void ft_pci_setup(void *blob, bd_t *bd) }#endif -#ifdef CONFIG_LS2080A +#if defined(CONFIG_LS2080A ) || defined(CONFIG_LS2085A )void pcie_set_available_streamids (void *blob,const char *pcie_path,u32 *stream_ids,int count)
include/configs/ls2080a_common.h +7 -2
@@ -11,7 +11,6 @@#define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE #define CONFIG_FSL_LSCH3 -#define CONFIG_LS2080A #define CONFIG_MP #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147
@@ -185,7 +184,7 @@ unsigned long long get_qixis_addr(void);#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -#ifndef CONFIG_LS2080A +#ifdef CONFIG_LS2085A #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000#endif
@@ -209,7 +208,13 @@ unsigned long long get_qixis_addr(void);#define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE4 /* PCIE controler 4 */ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#ifdef CONFIG_LS2080A #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" +#endif + +#ifdef CONFIG_LS2085A +#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie" +#endif #define CONFIG_SYS_PCI_64BIT
include/configs/ls2080a_emu.h +7 -0
@@ -9,8 +9,15 @@#include "ls2080a_common.h" +#ifdef CONFIG_LS2080A #define CONFIG_IDENT_STRING " LS2080A-EMU"#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-EMU" +#endif + +#ifdef CONFIG_LS2085A +#define CONFIG_IDENT_STRING " LS2085A-EMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" +#endif #define CONFIG_SYS_CLK_FREQ 100000000#define CONFIG_DDR_CLK_FREQ 133333333
include/configs/ls2080a_simu.h +7 -0
@@ -9,8 +9,15 @@#include "ls2080a_common.h" +#ifdef CONFIG_LS2080A #define CONFIG_IDENT_STRING " LS2080A-SIMU"#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-SIMU" +#endif + +#ifdef CONFIG_LS2085A +#define CONFIG_IDENT_STRING " LS2085A-SIMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU" +#endif #define CONFIG_SYS_CLK_FREQ 100000000#define CONFIG_DDR_CLK_FREQ 133333333
include/linux/usb/xhci-fsl.h +1 -1
@@ -54,7 +54,7 @@ struct fsl_xhci {#if defined(CONFIG_LS102XA )#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 -#elif defined(CONFIG_LS2080A ) +#elif defined(CONFIG_LS2080A ) || defined(CONFIG_LS2085A )#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR#endif
Signature · 1 line
1.9.1
PATCH v2 2/2 armv8: ls2085a: Add support of LS2085A SoC
Quoted 9 lines · Prabhakar Kushwaha
Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.Signed-off-by Pratiyush Mohan Srivastava <[email protected]>Signed-off-by Prabhakar Kushwaha <[email protected]>---
Changes for v2: Rebased on LS1043 patch set
Dropped #ifdef in cpu.h.
Applied to fsl-qoriq master. Thanks.
York