add LS1043AQDS platform support

PATCH New Gong Qianyu 2 participants 15 messages Nov 11, 2015 – Nov 30, 2015

Subsystems (3)

Arm (32-bit) USB PCI

lore

Share & tools

lore

Gong Qianyu

author

2015-11-11 09:58 UTC #0 lore raw

v4 cover add LS1043AQDS platform support

Hi all,

Here are the main changes for V4 patchset. LS1043ARDB MAINTAINERS has already been updated in U-Boot. So remove that patch in V4 patchset.

- Update the code base.
- Use #ifndef CONFIG_LS102XA instead of #ifdef CONFIG_FSL_LAYERSCAPE for PCIe patch.
- Fix vid support for LS1043AQDS.
- Remove RAW_TIMING definition for DDR3.
- Remove LS1043AQDS_MDIO_10GC related code because LS1043AQDS board has no phy for it.

[Patch V4 1/7] pci/layerscape: add support for LS1043A PCIe LUT [Patch V4 2/7] armv8/fsl-layerscape: Remove reference to gdata [Patch V4 3/7] armv8/ls1043ardb: dts: add dtb support [Patch V4 4/7] armv8/ls1043aqds: add LS1043AQDS board support [Patch V4 5/7] armv8/ls1043aqds: dts: add dtb support [Patch V4 6/7] armv8/ls1043ardb: add DSPI support [Patch V4 7/7] armv8/ls1043ardb: add USB support

Gong Qianyu

author

2015-11-11 09:58 UTC #1 lore raw

PATCH v4 1/7 pci/layerscape: add support for LS1043A PCIe LUT register access

From: Mingkai Hu <[email protected]>

The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register.

Signed-off-by Mingkai Hu <[email protected]>

Signed-off-by Gong Qianyu <[email protected]>

---
V4:
- Use #ifndef CONFIG_LS102XA instead of #ifdef CONFIG_FSL_LAYERSCAPE.
V3:
- No change.
V2:
- Fix compile errors for ls1021a.

 arch/arm/include/asm/arch-fsl-layerscape/config.h      |  2 ++
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h |  4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h |  4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h         |  8 ++++++++
 drivers/pci/pcie_layerscape.c                          | 14 +++++++-------
 5 files changed, 25 insertions(+), 7 deletions(-)

arch/arm/include/asm/arch-fsl-layerscape/config.h +2 -0

index 87bb937..fe361da 100644
@@ -44,6 +44,7 @@
 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
 #define CONFIG_SYS_FSL_ESDHC_LE
 #define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
 
 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN

@@ -113,6 +114,7 @@
 #define CONFIG_SYS_FSL_WDOG_BE
 #define CONFIG_SYS_FSL_DSPI_BE
 #define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_PEX_LUT_BE
 
 #define QE_MURAM_SIZE		0x6000UL
 #define MAX_QE_RISC		1

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +4 -0

index d941437..f52815d 100644
@@ -60,6 +60,10 @@
 #define CONFIG_SYS_PCIE1_PHYS_ADDR		0x4000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
+/* LUT registers */
+#define PCIE_LUT_BASE				0x10000
+#define PCIE_LUT_LCTRL0				0x7F8
+#define PCIE_LUT_DBG				0x7FC
 
 /* TZ Address Space Controller Definitions */
 #define TZASC1_BASE			0x01100000	/* as per CCSR map. */

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +4 -0

index 6a70d44..e700af0 100644
@@ -78,6 +78,10 @@
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
 #define CONFIG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
+/* LUT registers */
+#define PCIE_LUT_BASE				0x80000
+#define PCIE_LUT_LCTRL0				0x7F8
+#define PCIE_LUT_DBG				0x7FC
 
 /* Device Configuration */
 #define DCFG_BASE		0x01e00000

arch/arm/include/asm/arch-fsl-layerscape/soc.h +8 -0

index 5ed456e..8691906 100644
@@ -23,6 +23,14 @@
 #define scfg_out32(a, v)   out_be32(a, v)
 #endif
 
+#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
+#define pex_lut_in32(a)       in_le32(a)
+#define pex_lut_out32(a, v)   out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
+#define pex_lut_in32(a)       in_be32(a)
+#define pex_lut_out32(a, v)   out_be32(a, v)
+#endif
+
 struct cpu_type {
 	char name[15];
 	u32 soc_ver;

drivers/pci/pcie_layerscape.c +7 -7

index 4cee038..43e3dc4 100644
@@ -11,8 +11,9 @@
 #include <asm/io.h>
 #include <errno.h>
 #include <malloc.h>
-#ifdef CONFIG_FSL_LAYERSCAPE
+#ifndef CONFIG_LS102XA
 #include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
 #endif
 
 #ifndef CONFIG_SYS_PCI_MEMORY_BUS

@@ -57,11 +58,6 @@
 #define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
 #define PCIE_ATU_UPPER_TARGET		0x91C
 
-/* LUT registers */
-#define PCIE_LUT_BASE		0x80000
-#define PCIE_LUT_LCTRL0		0x7F8
-#define PCIE_LUT_DBG		0x7FC
-
 #define PCIE_DBI_RO_WR_EN	0x8bc
 
 #define PCIE_LINK_CAP		0x7c

@@ -162,7 +158,7 @@ static int ls_pcie_link_state(struct ls_pcie *pcie)
 {
 	u32 state;
 
-	state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
+	state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
 		LTSSM_STATE_MASK;
 	if (state < LTSSM_PCIE_L0) {
 		debug("....PCIe link error. LTSSM=0x%02x.\n", state);

@@ -466,16 +462,20 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
 
 		for (pf = 0; pf < PCIE_PF_NUM; pf++) {
 			for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
+#ifndef CONFIG_LS102XA
 				writel(PCIE_LCTRL0_VAL(pf, vf),
 				       pcie->dbi + PCIE_LUT_BASE +
 				       PCIE_LUT_LCTRL0);
+#endif
 				ls_pcie_ep_setup_bars(pcie->dbi);
 				ls_pcie_ep_setup_atu(pcie, info);
 			}
 		}
 
 		/* Disable CFG2 */
+#ifndef CONFIG_LS102XA
 		writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
+#endif
 	} else {
 		ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
 		ls_pcie_ep_setup_atu(pcie, info);

Signature · 1 line

2.1.0.27.g96db324

York Sun

Applied

2015-11-30 17:13 UTC #2 lore raw

PATCH v4 1/7 pci/layerscape: add support for LS1043A PCIe LUT register access

Quoted 17 lines · Gong Qianyu

From: Mingkai Hu <[email protected]>
The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register.
Signed-off-by Mingkai Hu <[email protected]>
Signed-off-by Gong Qianyu <[email protected]>
---
V4:
- Use #ifndef CONFIG_LS102XA instead of #ifdef CONFIG_FSL_LAYERSCAPE.
V3:
- No change.
V2:
- Fix compile errors for ls1021a.

Quoted 6 lines

 arch/arm/include/asm/arch-fsl-layerscape/config.h      |  2 ++
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h |  4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h |  4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h         |  8 ++++++++
 drivers/pci/pcie_layerscape.c                          | 14 +++++++-------
 5 files changed, 25 insertions(+), 7 deletions(-)

Applied to fsl-qoriq master. Thanks.

York

Gong Qianyu

author

2015-11-11 09:58 UTC #3 lore raw

PATCH v4 2/7 armv8/fsl-layerscape: Remove reference to gdata

In reply to Gong Qianyu

The global_data pointer (gd) has been set earlier in crt0_64.S. So there's no need to assign it again. Remove gdata since it is going away in U-Boot.

Signed-off-by Gong Qianyu <[email protected]>

---
V4:
- No change.
V3:
- New Patch.
- Fix dead code.

 arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 --
 1 file changed, 2 deletions(-)

arch/arm/cpu/armv8/fsl-layerscape/spl.c +0 -2

index ba551aa..e53ed9a 100644
@@ -44,8 +44,6 @@ u32 spl_boot_mode(void)
 #ifdef CONFIG_SPL_BUILD
 void board_init_f(ulong dummy)
 {
-	/* Set global data pointer */
-	gd = &gdata;
 	/* Clear global data */
 	memset((void *)gd, 0, sizeof(gd_t));
 #ifdef CONFIG_LS2085A

Signature · 1 line

2.1.0.27.g96db324

York Sun

Applied

2015-11-30 17:13 UTC #4 lore raw

PATCH v4 2/7 armv8/fsl-layerscape: Remove reference to gdata

Quoted 12 lines · Gong Qianyu

The global_data pointer (gd) has been set earlier in crt0_64.S. So there's no need to assign it again. Remove gdata since it is going away in U-Boot.
Signed-off-by Gong Qianyu <[email protected]>
---
V4:
- No change.
V3:
- New Patch.
- Fix dead code.

Quoted 2 lines

 arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 --
 1 file changed, 2 deletions(-)

Applied to fsl-qoriq master. Thanks.

York

Gong Qianyu

author

2015-11-11 09:58 UTC #5 lore raw

PATCH v4 3/7 armv8/ls1043ardb: dts: add dtb support

In reply to Gong Qianyu

Reuse dts files from ls1043a linux kernel. Some parts in dts files may not be needed by U-Boot.

Signed-off-by Gong Qianyu <[email protected]>

---
V4:
- No change.
V3:
- Modified the dts file according to ls1043a upstreaming linux kernel.
V2:
- New Patch.

 arch/arm/dts/Makefile            |   1 +
 arch/arm/dts/fsl-ls1043a-rdb.dts |  84 ++++++++++++++++++++
 arch/arm/dts/fsl-ls1043a.dtsi    | 160 +++++++++++++++++++++++++++++++++++++++
 configs/ls1043ardb_defconfig     |   2 +
 4 files changed, 247 insertions(+)

arch/arm/dts/Makefile +1 -0

index 9542fff..7e12f01 100644
@@ -89,6 +89,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
 	ls1021a-twr.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \
 	fsl-ls2085a-rdb.dtb
+dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
 	sun4i-a10-a1000.dtb \

arch/arm/dts/fsl-ls1043a-rdb.dts new file +84 -0

84 lines not on this page · raw message

arch/arm/dts/fsl-ls1043a.dtsi new file +160 -0

160 lines not on this page · raw message

configs/ls1043ardb_defconfig +2 -0

index ae84d2e..f77fbbf 100644
@@ -2,3 +2,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043ARDB=y
 CONFIG_FSL_LAYERSCAPE=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_OF_CONTROL=y

Signature · 1 line

2.1.0.27.g96db324

York Sun

Applied

2015-11-30 17:14 UTC #6 lore raw

PATCH v4 3/7 armv8/ls1043ardb: dts: add dtb support

Quoted 12 lines · Gong Qianyu

Reuse dts files from ls1043a linux kernel. Some parts in dts files may not be needed by U-Boot.
Signed-off-by Gong Qianyu <[email protected]>
---
V4:
- No change.
V3:
- Modified the dts file according to ls1043a upstreaming linux kernel.
V2:
- New Patch.

Quoted 5 lines

 arch/arm/dts/Makefile            |   1 +
 arch/arm/dts/fsl-ls1043a-rdb.dts |  84 ++++++++++++++++++++
 arch/arm/dts/fsl-ls1043a.dtsi    | 160 +++++++++++++++++++++++++++++++++++++++
 configs/ls1043ardb_defconfig     |   2 +
 4 files changed, 247 insertions(+)

Applied to fsl-qoriq master. Thanks.

York

Gong Qianyu

author

2015-11-11 09:58 UTC #7 lore raw

PATCH v4 4/7 armv8/ls1043aqds: add LS1043AQDS board support

In reply to Gong Qianyu

From: Shaohui Xie <[email protected]>

LS1043AQDS Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 DIMM
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card

Ethernet:
* Two RGMII ports
* XFI 10G port
* SGMII
* QSGMII with 4x 1G ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console

Signed-off-by Shaohui Xie <[email protected]>

Signed-off-by Mingkai Hu <[email protected]>

Signed-off-by Hou Zhiqiang <[email protected]>

Signed-off-by Gong Qianyu <[email protected]>

---
V4:
- Fix vid macros in config file and add vid support.
- Remove RAW_TIMING definition for DDR3.
- Remove LS1043AQDS_MDIO_10GC related code because LS1043AQDS has no phy for it.
V3:
- Update the commit message.
- Remove #ifdef in fdt.h.
- Rename ls1043aqds_sdcard_defconfig to ls1043aqds_sdcard_ifc_defconfig.
V2:
- No change.

 arch/arm/Kconfig                                   |   9 +
 arch/arm/include/asm/arch-fsl-layerscape/fdt.h     |   1 +
 board/freescale/common/vid.c                       |  22 +
 board/freescale/ls1043aqds/Kconfig                 |  15 +
 board/freescale/ls1043aqds/MAINTAINERS             |   9 +
 board/freescale/ls1043aqds/Makefile                |   9 +
 board/freescale/ls1043aqds/README                  |  96 ++++
 board/freescale/ls1043aqds/ddr.c                   | 131 ++++++
 board/freescale/ls1043aqds/ddr.h                   |  60 +++
 board/freescale/ls1043aqds/eth.c                   | 492 +++++++++++++++++++++
 board/freescale/ls1043aqds/ls1043aqds.c            | 333 ++++++++++++++
 board/freescale/ls1043aqds/ls1043aqds_pbi.cfg      |  14 +
 board/freescale/ls1043aqds/ls1043aqds_qixis.h      |  39 ++
 board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg |   7 +
 .../freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg |   8 +
 configs/ls1043aqds_defconfig                       |   3 +
 configs/ls1043aqds_nand_defconfig                  |   4 +
 configs/ls1043aqds_nor_ddr3_defconfig              |   2 +
 configs/ls1043aqds_sdcard_ifc_defconfig            |   4 +
 include/configs/ls1043aqds.h                       | 387 ++++++++++++++++
 20 files changed, 1645 insertions(+)

arch/arm/Kconfig +9 -0

index 0d756cb..267dd2a 100644
@@ -634,6 +634,14 @@ config TARGET_LS1021ATWR
 	select CPU_V7
 	select SUPPORT_SPL
 
+config TARGET_LS1043AQDS
+	bool "Support ls1043aqds"
+	select ARM64
+	select ARMV8_MULTIENTRY
+	select SUPPORT_SPL
+	help
+	  Support for Freescale LS1043AQDS platform.
+
 config TARGET_LS1043ARDB
 	bool "Support ls1043ardb"
 	select ARM64

@@ -758,6 +766,7 @@ source "board/freescale/ls2085aqds/Kconfig"
 source "board/freescale/ls2085ardb/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
+source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"

arch/arm/include/asm/arch-fsl-layerscape/fdt.h +1 -0

index 4da73ab..099563e 100644
@@ -11,4 +11,5 @@ void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt);
 void append_mmu_masters(void *blob, const char *smmu_path,
 			const char *master_name, u32 *stream_ids, int count);
 void fdt_fixup_smmu_pcie(void *blob);
+void fdt_fixup_board_enet(void *fdt);
 #endif	/* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */

board/freescale/common/vid.c +22 -0

index 6b8af14..f1bed51 100644
@@ -7,7 +7,12 @@
 #include <common.h>
 #include <command.h>
 #include <i2c.h>
+#include <asm/io.h>
+#ifdef CONFIG_LS1043A
+#include <asm/arch/immap_lsch2.h>
+#else
 #include <asm/immap_85xx.h>
+#endif
 #include "vid.h"
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -240,7 +245,11 @@ static int set_voltage_to_IR(int i2caddress, int vdd)
 	 * SoC before converting into an IR VID value
 	 */
 	vdd += board_vdd_drop_compensation();
+#ifdef CONFIG_LS1043A
+	vid = DIV_ROUND_UP(vdd - 265, 5);
+#else
 	vid = DIV_ROUND_UP(vdd - 245, 5);
+#endif
 
 	ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
 			1, (void *)&vid, sizeof(vid));

@@ -276,8 +285,12 @@ static int set_voltage(int i2caddress, int vdd)
 int adjust_vdd(ulong vdd_override)
 {
 	int re_enable = disable_interrupts();
+#ifdef CONFIG_LS1043A
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#else
 	ccsr_gur_t __iomem *gur =
 		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
 	u32 fusesr;
 	u8 vid;
 	int vdd_target, vdd_current, vdd_last;

@@ -352,12 +365,21 @@ int adjust_vdd(ulong vdd_override)
 	 * | T |          |         |                 |         |
 	 * ------------------------------------------------------
 	 */
+#ifdef CONFIG_LS1043A
+	vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
+		FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
+	if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
+		vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
+			FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
+	}
+#else
 	vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
 		FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
 	if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) {
 		vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
 			FSL_CORENET_DCFG_FUSESR_VID_MASK;
 	}
+#endif
 	vdd_target = vdd[vid];
 
 	/* check override variable for overriding VDD */

board/freescale/ls1043aqds/Kconfig new file +15 -0

new file mode 100644
index 0000000..7e27f8f
@@ -0,0 +1,15 @@
+if TARGET_LS1043AQDS
+
+config SYS_BOARD
+	default "ls1043aqds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1043aqds"
+
+endif

board/freescale/ls1043aqds/MAINTAINERS new file +9 -0

new file mode 100644
index 0000000..0c7f648
@@ -0,0 +1,9 @@
+LS1043AQDS BOARD
+M:	Mingkai Hu <[email protected]>
+S:	Maintained
+F:	board/freescale/ls1043aqds/
+F:	include/configs/ls1043aqds.h
+F:	configs/ls1043aqds_defconfig
+F:	configs/ls1043aqds_nor_ddr3_defconfig
+F:	configs/ls1043aqds_nand_defconfig
+F:	configs/ls1043aqds_sdcard_ifc_defconfig

board/freescale/ls1043aqds/Makefile new file +9 -0

new file mode 100644
index 0000000..f727bfd
@@ -0,0 +1,9 @@
+#
+# Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ddr.o
+obj-y += eth.o
+obj-y += ls1043aqds.o

board/freescale/ls1043aqds/README new file +96 -0

96 lines not on this page · raw message

board/freescale/ls1043aqds/ddr.c new file +131 -0

131 lines not on this page · raw message

board/freescale/ls1043aqds/ddr.h new file +60 -0

60 lines not on this page · raw message

board/freescale/ls1043aqds/eth.c new file +492 -0

492 lines not on this page · raw message

board/freescale/ls1043aqds/ls1043aqds.c new file +333 -0

333 lines not on this page · raw message

board/freescale/ls1043aqds/ls1043aqds_pbi.cfg new file +14 -0

new file mode 100644
index 0000000..f072274
@@ -0,0 +1,14 @@
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Alt base register
+09570158 00001000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#flush PBI data
+096100c0 000fffff

board/freescale/ls1043aqds/ls1043aqds_qixis.h new file +39 -0

new file mode 100644
index 0000000..8783be8
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xe0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+#define QIXIS_SYSCLK_64			0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100		0x0
+#define QIXIS_SDCLK1_125		0x1
+#define QIXIS_SDCLK1_165		0x2
+#define QIXIS_SDCLK1_100_SP		0x3
+
+#endif

board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg new file +7 -0

new file mode 100644
index 0000000..935ffc0
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0810000f 0c000000 00000000 00000000
+14550002 80004012 e0106000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001

board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg new file +8 -0

new file mode 100644
index 0000000..17a5dd0
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+# Enable IFC; disable QSPI
+0810000f 0c000000 00000000 00000000
+14550002 80004012 60040000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001

configs/ls1043aqds_defconfig new file +3 -0

new file mode 100644
index 0000000..ee5bea2
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y

configs/ls1043aqds_nand_defconfig new file +4 -0

new file mode 100644
index 0000000..377ca74
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y

configs/ls1043aqds_nor_ddr3_defconfig new file +2 -0

new file mode 100644
index 0000000..7b1951f
@@ -0,0 +1,2 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y

configs/ls1043aqds_sdcard_ifc_defconfig new file +4 -0

new file mode 100644
index 0000000..0fdb959
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y

include/configs/ls1043aqds.h new file +387 -0

387 lines not on this page · raw message

Signature · 1 line

2.1.0.27.g96db324

York Sun

2015-11-30 17:15 UTC #8 lore raw

PATCH v4 4/7 armv8/ls1043aqds: add LS1043AQDS board support

Quoted 54 lines · Gong Qianyu

From: Shaohui Xie <[email protected]>
LS1043AQDS Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 DIMM
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* Two RGMII ports
* XFI 10G port
* SGMII
* QSGMII with 4x 1G ports
PCIe: supports Gen 1 and Gen 2
SATA 3.0: one SATA 3.0 port
USB 3.0: two micro AB connector and one type A connector
UART: supports two UARTs up to 115200 bps for console
Signed-off-by Shaohui Xie <[email protected]>
Signed-off-by Mingkai Hu <[email protected]>
Signed-off-by Hou Zhiqiang <[email protected]>
Signed-off-by Gong Qianyu <[email protected]>
---
V4:
- Fix vid macros in config file and add vid support.
- Remove RAW_TIMING definition for DDR3.
- Remove LS1043AQDS_MDIO_10GC related code because LS1043AQDS has no phy for it.
V3:
- Update the commit message.
- Remove #ifdef in fdt.h.
- Rename ls1043aqds_sdcard_defconfig to ls1043aqds_sdcard_ifc_defconfig.
V2:
- No change.
 arch/arm/Kconfig                                   |   9 +
 arch/arm/include/asm/arch-fsl-layerscape/fdt.h     |   1 +
 board/freescale/common/vid.c                       |  22 +
 board/freescale/ls1043aqds/Kconfig                 |  15 +
 board/freescale/ls1043aqds/MAINTAINERS             |   9 +
 board/freescale/ls1043aqds/Makefile                |   9 +
 board/freescale/ls1043aqds/README                  |  96 ++++
 board/freescale/ls1043aqds/ddr.c                   | 131 ++++++
 board/freescale/ls1043aqds/ddr.h                   |  60 +++
 board/freescale/ls1043aqds/eth.c                   | 492 +++++++++++++++++++++
 board/freescale/ls1043aqds/ls1043aqds.c            | 333 ++++++++++++++
 board/freescale/ls1043aqds/ls1043aqds_pbi.cfg      |  14 +
 board/freescale/ls1043aqds/ls1043aqds_qixis.h      |  39 ++

Quoted 8 lines

 board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg |   7 +
 .../freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg |   8 +
 configs/ls1043aqds_defconfig                       |   3 +
 configs/ls1043aqds_nand_defconfig                  |   4 +
 configs/ls1043aqds_nor_ddr3_defconfig              |   2 +
 configs/ls1043aqds_sdcard_ifc_defconfig            |   4 +
 include/configs/ls1043aqds.h                       | 387 ++++++++++++++++
 20 files changed, 1645 insertions(+)

Added CONFIG_SYS_NS16550=y in defconfig files.
Applied to fsl-qoriq master. Thanks.

York

Gong Qianyu

author

2015-11-11 09:58 UTC #9 lore raw

PATCH v4 5/7 armv8/ls1043aqds: dts: add dtb support

In reply to Gong Qianyu

Reuse the dts files from ls1043a linux kernel.

Signed-off-by Gong Qianyu <[email protected]>

---
V4:
- No change.
V3:
- No change.
V2:
- New Patch.

 arch/arm/dts/Makefile            |   3 +-
 arch/arm/dts/fsl-ls1043a-qds.dts | 124 +++++++++++++++++++++++++++++++++++++++
 configs/ls1043aqds_defconfig     |   2 +
 3 files changed, 128 insertions(+), 1 deletion(-)

arch/arm/dts/Makefile +2 -1

index 7e12f01..88a500d 100644
@@ -89,7 +89,8 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
 	ls1021a-twr.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \
 	fsl-ls2085a-rdb.dtb
-dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-rdb.dtb
+dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \
+	fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
 	sun4i-a10-a1000.dtb \

arch/arm/dts/fsl-ls1043a-qds.dts new file +124 -0

124 lines not on this page · raw message

configs/ls1043aqds_defconfig +2 -0

index ee5bea2..cf163d6 100644
@@ -1,3 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
+CONFIG_OF_CONTROL=y

Signature · 1 line

2.1.0.27.g96db324

York Sun

Applied

2015-11-30 17:15 UTC #10 lore raw

PATCH v4 5/7 armv8/ls1043aqds: dts: add dtb support

Quoted 11 lines · Gong Qianyu

Reuse the dts files from ls1043a linux kernel.
Signed-off-by Gong Qianyu <[email protected]>
---
V4:
- No change.
V3:
- No change.
V2:
- New Patch.

Quoted 5 lines

 arch/arm/dts/Makefile            |   3 +-
 arch/arm/dts/fsl-ls1043a-qds.dts | 124 +++++++++++++++++++++++++++++++++++++++
 configs/ls1043aqds_defconfig     |   2 +
 3 files changed, 128 insertions(+), 1 deletion(-)

Applied to fsl-qoriq master. Thanks.

York

Gong Qianyu

author

2015-11-11 09:58 UTC #11 lore raw

PATCH v4 6/7 armv8/ls1043ardb: add DSPI support

In reply to Gong Qianyu

Use the U-Boot Driver Model. Just enable Freescale DSPI driver and set DSPI related parameters in dts file.

Signed-off-by Gong Qianyu <[email protected]>

---
V4:
- No change.
V3:
- New Patch.
- Tested on LS1043ARDB board.

 arch/arm/dts/fsl-ls1043a-rdb.dts    | 19 +++++++++++++++++++
 arch/arm/dts/fsl-ls1043a.dtsi       | 26 ++++++++++++++++++++++++++
 configs/ls1043ardb_defconfig        |  3 +++
 configs/ls1043ardb_nand_defconfig   |  5 +++++
 configs/ls1043ardb_sdcard_defconfig |  5 +++++
 include/configs/ls1043ardb.h        | 10 ++++++++++
 6 files changed, 68 insertions(+)

arch/arm/dts/fsl-ls1043a-rdb.dts +19 -0

index 17a0681..16c5c89 100644
@@ -15,6 +15,25 @@
 
 / {
 	model = "LS1043A RDB Board";
+
+        aliases {
+		spi1 = &dspi0;
+        };
+
+};
+
+&dspi0 {
+	bus-num = <0>;
+	status = "okay";
+
+	dspiflash: n25q12a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		reg = <0>;
+		spi-max-frequency = <1000000>; /* input clock */
+	};
+
 };
 
 &i2c0 {

arch/arm/dts/fsl-ls1043a.dtsi +26 -0

index 280e959..85ea81e 100644
@@ -79,6 +79,32 @@
 			clocks = <&sysclk>;
 		};
 
+		dspi0: dspi at 2100000 {
+			compatible = "fsl,vf610-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2100000 0x0 0x10000>;
+			interrupts = <0 64 0x4>;
+			clock-names = "dspi";
+			clocks = <&clockgen 4 0>;
+			num-cs = <6>;
+			big-endian;
+			status = "disabled";
+		};
+
+		dspi1: dspi at 2110000 {
+			compatible = "fsl,vf610-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2110000 0x0 0x10000>;
+			interrupts = <0 65 0x4>;
+			clock-names = "dspi";
+			clocks = <&clockgen 4 0>;
+			num-cs = <6>;
+			big-endian;
+			status = "disabled";
+		};
+
 		ifc: ifc at 1530000 {
 			compatible = "fsl,ifc", "simple-bus";
 			reg = <0x0 0x1530000 0x0 0x10000>;

configs/ls1043ardb_defconfig +3 -0

index f77fbbf..0102e0d 100644
@@ -4,3 +4,6 @@ CONFIG_TARGET_LS1043ARDB=y
 CONFIG_FSL_LAYERSCAPE=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y

configs/ls1043ardb_nand_defconfig +5 -0

index fffaca0..661cbc2 100644
@@ -2,3 +2,8 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043ARDB=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y

configs/ls1043ardb_sdcard_defconfig +5 -0

index 5fe0470..b53dd15 100644
@@ -2,3 +2,8 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043ARDB=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y

include/configs/ls1043ardb.h +10 -0

index 307d947..3fa9b3b 100644
@@ -222,6 +222,16 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
 
+/* DSPI */
+#define CONFIG_FSL_DSPI
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SF_DEFAULT_BUS		1
+#define CONFIG_SF_DEFAULT_CS		0
+#endif
+
 /*
  * Environment
  */

Signature · 1 line

2.1.0.27.g96db324

York Sun

Applied

2015-11-30 17:15 UTC #12 lore raw

PATCH v4 6/7 armv8/ls1043ardb: add DSPI support

Quoted 11 lines · Gong Qianyu

Use the U-Boot Driver Model. Just enable Freescale DSPI driver and set DSPI related parameters in dts file.
Signed-off-by Gong Qianyu <[email protected]>
---
V4:
- No change.
V3:
- New Patch.
- Tested on LS1043ARDB board.

Quoted 7 lines

 arch/arm/dts/fsl-ls1043a-rdb.dts    | 19 +++++++++++++++++++
 arch/arm/dts/fsl-ls1043a.dtsi       | 26 ++++++++++++++++++++++++++
 configs/ls1043ardb_defconfig        |  3 +++
 configs/ls1043ardb_nand_defconfig   |  5 +++++
 configs/ls1043ardb_sdcard_defconfig |  5 +++++
 include/configs/ls1043ardb.h        | 10 ++++++++++
 6 files changed, 68 insertions(+)

Applied to fsl-qoriq master. Thanks.

York

Gong Qianyu

author

2015-11-11 09:58 UTC #13 lore raw

PATCH v4 7/7 armv8/ls1043ardb: add USB support

In reply to Gong Qianyu

Add support for the third USB controller for LS1043A.

Signed-off-by Gong Qianyu <[email protected]>

---
V4:
- No change.
V3:
- New Patch. Tested on LS1043ARDB board.

 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h |  6 +++---
 board/freescale/ls1043ardb/ls1043ardb.c                | 16 ++++++++++++++++
 include/configs/ls1043ardb.h                           | 13 +++++++++++++
 include/linux/usb/xhci-fsl.h                           |  9 ++++++++-
 4 files changed, 40 insertions(+), 4 deletions(-)

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +3 -3

index f52815d..83caa91 100644
@@ -30,9 +30,9 @@
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011c0600)
 #define CONFIG_SYS_NS16550_COM3			(CONFIG_SYS_IMMR + 0x011d0500)
 #define CONFIG_SYS_NS16550_COM4			(CONFIG_SYS_IMMR + 0x011d0600)
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x01f00000)
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02000000)
-#define CONFIG_SYS_FSL_XHCI_USB3_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x01f00000)
+#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02000000)
+#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
 #define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)

board/freescale/ls1043ardb/ls1043ardb.c +16 -0

index 9032ed3..cdd50d6 100644
@@ -69,7 +69,23 @@ int dram_init(void)
 
 int board_early_init_f(void)
 {
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	u32 usb_pwrfault;
+
 	fsl_lsch2_early_init_f();
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+	out_be32(&scfg->rcwpmuxcr0, 0x3333);
+	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+	usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+			SCFG_USBPWRFAULT_USB3_SHIFT) |
+			(SCFG_USBPWRFAULT_DEDICATED <<
+			SCFG_USBPWRFAULT_USB2_SHIFT) |
+			(SCFG_USBPWRFAULT_SHARED <<
+			 SCFG_USBPWRFAULT_USB1_SHIFT);
+	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+
 	return 0;
 }

include/configs/ls1043ardb.h +13 -0

index 3fa9b3b..7d113a0 100644
@@ -278,4 +278,17 @@
 #define CONFIG_ETHPRIME			"FM1 at DTSEC3"
 #endif
 
+/* USB */
+#define CONFIG_HAS_FSL_XHCI_USB
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		3
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+#endif
+
 #endif /* __LS1043ARDB_H__ */

include/linux/usb/xhci-fsl.h +8 -1

index 602a413..b0ff129 100644
@@ -54,11 +54,18 @@ struct fsl_xhci {
 #if defined(CONFIG_LS102XA)
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
 #elif defined(CONFIG_LS2085A)
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+#elif defined(CONFIG_LS1043A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
 #endif
 
 #define FSL_USB_XHCI_ADDR	{CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
-					CONFIG_SYS_FSL_XHCI_USB2_ADDR}
+					CONFIG_SYS_FSL_XHCI_USB2_ADDR, \
+					CONFIG_SYS_FSL_XHCI_USB3_ADDR}
 #endif /* _ASM_ARCH_XHCI_FSL_H_ */

Signature · 1 line

2.1.0.27.g96db324

York Sun

Applied

2015-11-30 17:16 UTC #14 lore raw

PATCH v4 7/7 armv8/ls1043ardb: add USB support

Quoted 9 lines · Gong Qianyu

Add support for the third USB controller for LS1043A.
Signed-off-by Gong Qianyu <[email protected]>
---
V4:
- No change.
V3:
- New Patch. Tested on LS1043ARDB board.

Quoted 6 lines

 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h |  6 +++---
 board/freescale/ls1043ardb/ls1043ardb.c                | 16 ++++++++++++++++
 include/configs/ls1043ardb.h                           | 13 +++++++++++++
 include/linux/usb/xhci-fsl.h                           |  9 ++++++++-
 4 files changed, 40 insertions(+), 4 deletions(-)

Applied to fsl-qoriq master. Thanks.

York