Skip to contentSkip to conversation

armv8/layerscape: Update MMU table with execute-never bits

PATCH New Alison Wang 2 participants 2 messages Nov 5, 2015 – Nov 30, 2015 Arm (32-bit)

lore
Share & tools
lore

Alison Wang

author
#0 lore raw

PATCH 1/1 armv8/layerscape: Update MMU table with execute-never bits

For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution.

Signed-off-by York Sun <[email protected]>
Signed-off-by Alison Wang <[email protected]>
Reported-by Zhichun Hua <[email protected]>
---
 arch/arm/cpu/armv8/cache_v8.c                  |  4 +-
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c        |  2 +-
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 79 +++++++++++++++++---------
 arch/arm/include/asm/armv8/mmu.h               |  2 +-
 4 files changed, 56 insertions(+), 31 deletions(-)
arch/arm/cpu/armv8/cache_v8.c +2 -2
index b1ea822..8f3ca40 100644
@@ -13,13 +13,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 inline void set_pgtable_section(u64 *page_table, u64 index, u64 section,
-			 u64 memory_type, u64 share)
+			 u64 memory_type, u64 attribute)
 {
 	u64 value;
 
 	value = section | PMD_TYPE_SECT | PMD_SECT_AF;
 	value |= PMD_ATTRINDX(memory_type);
-	value |= share;
+	value |= attribute;
 	page_table[index] = value;
 }
arch/arm/cpu/armv8/fsl-layerscape/cpu.c +1 -1
index 0cb0afa..9d1c70f 100644
@@ -76,7 +76,7 @@ static int set_block_entry(const struct sys_mmu_table *list,
 				    index,
 				    block_addr,
 				    list->memory_type,
-				    list->share);
+				    list->attribute);
 		block_addr += block_size;
 		index++;
 	}
arch/arm/include/asm/arch-fsl-layerscape/cpu.h +52 -27

154 lines not on this page · raw message

arch/arm/include/asm/armv8/mmu.h +1 -1
index d8d9af4..2e2a3a8 100644
@@ -119,7 +119,7 @@
 
 void set_pgtable_section(u64 *page_table, u64 index,
 			 u64 section, u64 memory_type,
-			 u64 share);
+			 u64 attribute);
 void set_pgtable_table(u64 *page_table, u64 index,
 		       u64 *table_addr);
Signature · 1 line
2.1.0.27.g96db324
Applied
#1 lore raw

PATCH 1/1 armv8/layerscape: Update MMU table with execute-never bits

Quoted 7 lines · Alison Wang

For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution.

Signed-off-by York Sun <[email protected]>
Signed-off-by Alison Wang <[email protected]>
Reported-by Zhichun Hua <[email protected]>
Quoted 7 lines
---
 arch/arm/cpu/armv8/cache_v8.c                  |  4 +-
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c        |  2 +-
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 79 +++++++++++++++++---------
 arch/arm/include/asm/armv8/mmu.h               |  2 +-
 4 files changed, 56 insertions(+), 31 deletions(-)

Applied to fsl-qoriq master. Thanks.

York