arm: ls2080a: Add sata support on qds and rdb board

index 2538001..4f9489e 100644
@@ -11,6 +11,9 @@
 #include <asm/arch-fsl-lsch3/soc.h>
 #include <asm/io.h>
 #include <asm/global_data.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <ahci.h>
+#include <scsi.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -78,6 +81,39 @@ void fsl_lsch3_early_init_f(void)
 	erratum_a009203();
 }
 
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int ls2080a_sata_init(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_ahci __iomem *ahci_base;
+	u32 cfg;
+	int rc = -1;
+
+	ahci_base = (void __iomem *)CONFIG_SYS_SATA2;
+	out_le32(&ahci_base->ppcfg, AHCI_PORT_PHY_1_CFG);
+
+	ahci_base = (void __iomem *)CONFIG_SYS_SATA1;
+	out_le32(&ahci_base->ppcfg, AHCI_PORT_PHY_1_CFG);
+
+	cfg = in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+	cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+	if ((cfg != 0x41) && (cfg != 0x42) && (cfg != 0x43) &&
+	    (cfg != 0x44) && (cfg != 0x49) && (cfg != 0x4A)) {
+		printf("SATA disabled: serdes protocol doesn't support\n");
+		return rc;
+	}
+
+	rc = ahci_init((void __iomem *)CONFIG_SYS_SATA1);
+	if (rc)
+		return rc;
+
+	scsi_scan(0);
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 void board_init_f(ulong dummy)
 {

index 0733852..1616bea 100644
@@ -68,6 +68,26 @@
 #define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
 #define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02110000)
 
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1			(CONFIG_SYS_IMMR + 0x02200000)
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2			(CONFIG_SYS_IMMR + 0x02210000)
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
 /* TZ Protection Controller Definitions */
 #define TZPC_BASE				0x02200000
 #define TZPCR0SIZE_BASE				(TZPC_BASE)

index 941f99a..ce04018 100644
@@ -182,4 +182,29 @@ struct ccsr_reset {
 	u32 ip_rev1;			/* 0xbf8 */
 	u32 ip_rev2;			/* 0xbfc */
 };
+
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+	u32 res1[0xa4/4];	/* 0x0 - 0xa4 */
+	u32 pcfg;	/* port config */
+	u32 ppcfg;	/* port phy1 config */
+	u32 pp2c;	/* port phy2 config */
+	u32 pp3c;	/* port phy3 config */
+	u32 pp4c;	/* port phy4 config */
+	u32 pp5c;	/* port phy5 config */
+	u32 axicc;	/* AXI cache control */
+	u32 paxic;	/* port AXI config */
+	u32 axipc;	/* AXI PROT control */
+	u32 ptc;	/* port Trans Config */
+	u32 pts;	/* port Trans Status */
+	u32 plc;	/* port link config */
+	u32 plc1;	/* port link config1 */
+	u32 plc2;	/* port link config2 */
+	u32 pls;	/* port link status */
+	u32 pls1;	/* port link status1 */
+	u32 pcmdc;	/* port CMD config */
+	u32 ppcs;	/* port phy control status */
+	u32 pberr;	/* port 0/1 BIST error */
+	u32 cmds;	/* port 0/1 CMD status error */
+};
 #endif /* __ARCH_FSL_LSCH3_IMMAP_H */

index 9a29272..1963842 100644
@@ -23,6 +23,9 @@ struct cpu_type {
 #define SVR_SOC_VER(svr)	(((svr) >> 8) & SVR_WO_E)
 #define IS_E_PROCESSOR(svr)	(!((svr >> 8) & 0x1))
 
+#define AHCI_PORT_PHY_1_CFG    0xa003fffe
+
+int ls2080a_sata_init(void);
 void fsl_lsch3_early_init_f(void);
 void cpu_name(char *name);
 

index 8f114a5..f20bf81 100644
@@ -188,6 +188,17 @@ int config_board_mux(int ctrl_type)
 	return 0;
 }
 
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+	ls2080a_sata_init();
+#endif
+
+	return 0;
+}
+#endif
+
 int board_init(void)
 {
 	char *env_hwconfig;

index 5451b2e..036860c 100644
@@ -145,6 +145,17 @@ int config_board_mux(int ctrl_type)
 	return 0;
 }
 
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+	ls2080a_sata_init();
+#endif
+
+	return 0;
+}
+#endif
+
 int board_init(void)
 {
 	char *env_hwconfig;